iwl-power.c 13 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/slab.h>
  31. #include <linux/init.h>
  32. #include <net/mac80211.h>
  33. #include "iwl-eeprom.h"
  34. #include "iwl-dev.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-commands.h"
  38. #include "iwl-debug.h"
  39. #include "iwl-power.h"
  40. /*
  41. * Setting power level allows the card to go to sleep when not busy.
  42. *
  43. * We calculate a sleep command based on the required latency, which
  44. * we get from mac80211. In order to handle thermal throttling, we can
  45. * also use pre-defined power levels.
  46. */
  47. /*
  48. * For now, keep using power level 1 instead of automatically
  49. * adjusting ...
  50. */
  51. bool no_sleep_autoadjust = true;
  52. module_param(no_sleep_autoadjust, bool, S_IRUGO);
  53. MODULE_PARM_DESC(no_sleep_autoadjust,
  54. "don't automatically adjust sleep level "
  55. "according to maximum network latency");
  56. /*
  57. * This defines the old power levels. They are still used by default
  58. * (level 1) and for thermal throttle (levels 3 through 5)
  59. */
  60. struct iwl_power_vec_entry {
  61. struct iwl_powertable_cmd cmd;
  62. u8 no_dtim; /* number of skip dtim */
  63. };
  64. #define IWL_DTIM_RANGE_0_MAX 2
  65. #define IWL_DTIM_RANGE_1_MAX 10
  66. #define NOSLP cpu_to_le16(0), 0, 0
  67. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  68. #define TU_TO_USEC 1024
  69. #define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
  70. #define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
  71. cpu_to_le32(X1), \
  72. cpu_to_le32(X2), \
  73. cpu_to_le32(X3), \
  74. cpu_to_le32(X4)}
  75. /* default power management (not Tx power) table values */
  76. /* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
  77. /* DTIM 0 - 2 */
  78. static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
  79. {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
  80. {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
  81. {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
  82. {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
  83. {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
  84. };
  85. /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
  86. /* DTIM 3 - 10 */
  87. static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
  88. {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  89. {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
  90. {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
  91. {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
  92. {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
  93. };
  94. /* for DTIM period > IWL_DTIM_RANGE_1_MAX */
  95. /* DTIM 11 - */
  96. static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
  97. {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  98. {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  99. {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  100. {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  101. {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  102. };
  103. static void iwl_static_sleep_cmd(struct iwl_priv *priv,
  104. struct iwl_powertable_cmd *cmd,
  105. enum iwl_power_level lvl, int period)
  106. {
  107. const struct iwl_power_vec_entry *table;
  108. int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
  109. int i;
  110. u8 skip;
  111. u32 slp_itrvl;
  112. table = range_2;
  113. if (period <= IWL_DTIM_RANGE_1_MAX)
  114. table = range_1;
  115. if (period <= IWL_DTIM_RANGE_0_MAX)
  116. table = range_0;
  117. BUG_ON(lvl < 0 || lvl >= IWL_POWER_NUM);
  118. *cmd = table[lvl].cmd;
  119. if (period == 0) {
  120. skip = 0;
  121. period = 1;
  122. for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
  123. max_sleep[i] = 1;
  124. } else {
  125. skip = table[lvl].no_dtim;
  126. for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
  127. max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
  128. max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
  129. }
  130. slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
  131. /* figure out the listen interval based on dtim period and skip */
  132. if (slp_itrvl == 0xFF)
  133. cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
  134. cpu_to_le32(period * (skip + 1));
  135. slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
  136. if (slp_itrvl > period)
  137. cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
  138. cpu_to_le32((slp_itrvl / period) * period);
  139. if (skip)
  140. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  141. else
  142. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  143. if (priv->cfg->base_params->shadow_reg_enable)
  144. cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
  145. else
  146. cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
  147. if (priv->cfg->bt_params &&
  148. priv->cfg->bt_params->advanced_bt_coexist) {
  149. if (!priv->cfg->bt_params->bt_sco_disable)
  150. cmd->flags |= IWL_POWER_BT_SCO_ENA;
  151. else
  152. cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
  153. }
  154. slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
  155. if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
  156. cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
  157. cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
  158. /* enforce max sleep interval */
  159. for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
  160. if (le32_to_cpu(cmd->sleep_interval[i]) >
  161. (max_sleep[i] * period))
  162. cmd->sleep_interval[i] =
  163. cpu_to_le32(max_sleep[i] * period);
  164. if (i != (IWL_POWER_VEC_SIZE - 1)) {
  165. if (le32_to_cpu(cmd->sleep_interval[i]) >
  166. le32_to_cpu(cmd->sleep_interval[i+1]))
  167. cmd->sleep_interval[i] =
  168. cmd->sleep_interval[i+1];
  169. }
  170. }
  171. if (priv->power_data.pci_pm)
  172. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  173. else
  174. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  175. IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
  176. skip, period);
  177. IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
  178. }
  179. static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
  180. struct iwl_powertable_cmd *cmd)
  181. {
  182. memset(cmd, 0, sizeof(*cmd));
  183. if (priv->power_data.pci_pm)
  184. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  185. IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
  186. }
  187. static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
  188. struct iwl_powertable_cmd *cmd,
  189. int dynps_ms, int wakeup_period)
  190. {
  191. /*
  192. * These are the original power level 3 sleep successions. The
  193. * device may behave better with such succession and was also
  194. * only tested with that. Just like the original sleep commands,
  195. * also adjust the succession here to the wakeup_period below.
  196. * The ranges are the same as for the sleep commands, 0-2, 3-9
  197. * and >10, which is selected based on the DTIM interval for
  198. * the sleep index but here we use the wakeup period since that
  199. * is what we need to do for the latency requirements.
  200. */
  201. static const u8 slp_succ_r0[IWL_POWER_VEC_SIZE] = { 2, 2, 2, 2, 2 };
  202. static const u8 slp_succ_r1[IWL_POWER_VEC_SIZE] = { 2, 4, 6, 7, 9 };
  203. static const u8 slp_succ_r2[IWL_POWER_VEC_SIZE] = { 2, 7, 9, 9, 0xFF };
  204. const u8 *slp_succ = slp_succ_r0;
  205. int i;
  206. if (wakeup_period > IWL_DTIM_RANGE_0_MAX)
  207. slp_succ = slp_succ_r1;
  208. if (wakeup_period > IWL_DTIM_RANGE_1_MAX)
  209. slp_succ = slp_succ_r2;
  210. memset(cmd, 0, sizeof(*cmd));
  211. cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
  212. IWL_POWER_FAST_PD; /* no use seeing frames for others */
  213. if (priv->power_data.pci_pm)
  214. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  215. if (priv->cfg->base_params->shadow_reg_enable)
  216. cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
  217. else
  218. cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
  219. if (priv->cfg->bt_params &&
  220. priv->cfg->bt_params->advanced_bt_coexist) {
  221. if (!priv->cfg->bt_params->bt_sco_disable)
  222. cmd->flags |= IWL_POWER_BT_SCO_ENA;
  223. else
  224. cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
  225. }
  226. cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
  227. cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
  228. for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
  229. cmd->sleep_interval[i] =
  230. cpu_to_le32(min_t(int, slp_succ[i], wakeup_period));
  231. IWL_DEBUG_POWER(priv, "Automatic sleep command\n");
  232. }
  233. static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
  234. {
  235. IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
  236. IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
  237. IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  238. IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  239. IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  240. le32_to_cpu(cmd->sleep_interval[0]),
  241. le32_to_cpu(cmd->sleep_interval[1]),
  242. le32_to_cpu(cmd->sleep_interval[2]),
  243. le32_to_cpu(cmd->sleep_interval[3]),
  244. le32_to_cpu(cmd->sleep_interval[4]));
  245. return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD,
  246. sizeof(struct iwl_powertable_cmd), cmd);
  247. }
  248. static void iwl_power_build_cmd(struct iwl_priv *priv,
  249. struct iwl_powertable_cmd *cmd)
  250. {
  251. bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
  252. int dtimper;
  253. dtimper = priv->hw->conf.ps_dtim_period ?: 1;
  254. if (priv->cfg->base_params->broken_powersave)
  255. iwl_power_sleep_cam_cmd(priv, cmd);
  256. else if (priv->cfg->base_params->supports_idle &&
  257. priv->hw->conf.flags & IEEE80211_CONF_IDLE)
  258. iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
  259. else if (priv->cfg->ops->lib->tt_ops.lower_power_detection &&
  260. priv->cfg->ops->lib->tt_ops.tt_power_mode &&
  261. priv->cfg->ops->lib->tt_ops.lower_power_detection(priv)) {
  262. /* in thermal throttling low power state */
  263. iwl_static_sleep_cmd(priv, cmd,
  264. priv->cfg->ops->lib->tt_ops.tt_power_mode(priv), dtimper);
  265. } else if (!enabled)
  266. iwl_power_sleep_cam_cmd(priv, cmd);
  267. else if (priv->power_data.debug_sleep_level_override >= 0)
  268. iwl_static_sleep_cmd(priv, cmd,
  269. priv->power_data.debug_sleep_level_override,
  270. dtimper);
  271. else if (no_sleep_autoadjust)
  272. iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
  273. else
  274. iwl_power_fill_sleep_cmd(priv, cmd,
  275. priv->hw->conf.dynamic_ps_timeout,
  276. priv->hw->conf.max_sleep_period);
  277. }
  278. int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
  279. bool force)
  280. {
  281. int ret;
  282. bool update_chains;
  283. lockdep_assert_held(&priv->mutex);
  284. /* Don't update the RX chain when chain noise calibration is running */
  285. update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
  286. priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
  287. if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
  288. return 0;
  289. if (!iwl_is_ready_rf(priv))
  290. return -EIO;
  291. /* scan complete use sleep_power_next, need to be updated */
  292. memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
  293. if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
  294. IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
  295. return 0;
  296. }
  297. if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
  298. set_bit(STATUS_POWER_PMI, &priv->status);
  299. ret = iwl_set_power(priv, cmd);
  300. if (!ret) {
  301. if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
  302. clear_bit(STATUS_POWER_PMI, &priv->status);
  303. if (priv->cfg->ops->lib->update_chain_flags && update_chains)
  304. priv->cfg->ops->lib->update_chain_flags(priv);
  305. else if (priv->cfg->ops->lib->update_chain_flags)
  306. IWL_DEBUG_POWER(priv,
  307. "Cannot update the power, chain noise "
  308. "calibration running: %d\n",
  309. priv->chain_noise_data.state);
  310. memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
  311. } else
  312. IWL_ERR(priv, "set power fail, ret = %d", ret);
  313. return ret;
  314. }
  315. EXPORT_SYMBOL(iwl_power_set_mode);
  316. int iwl_power_update_mode(struct iwl_priv *priv, bool force)
  317. {
  318. struct iwl_powertable_cmd cmd;
  319. iwl_power_build_cmd(priv, &cmd);
  320. return iwl_power_set_mode(priv, &cmd, force);
  321. }
  322. EXPORT_SYMBOL(iwl_power_update_mode);
  323. /* initialize to default */
  324. void iwl_power_initialize(struct iwl_priv *priv)
  325. {
  326. u16 lctl = iwl_pcie_link_ctl(priv);
  327. priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
  328. priv->power_data.debug_sleep_level_override = -1;
  329. memset(&priv->power_data.sleep_cmd, 0,
  330. sizeof(priv->power_data.sleep_cmd));
  331. }
  332. EXPORT_SYMBOL(iwl_power_initialize);