ci13xxx_udc.c 74 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/platform_device.h>
  58. #include <linux/module.h>
  59. #include <linux/interrupt.h>
  60. #include <linux/io.h>
  61. #include <linux/irq.h>
  62. #include <linux/kernel.h>
  63. #include <linux/slab.h>
  64. #include <linux/pm_runtime.h>
  65. #include <linux/usb/ch9.h>
  66. #include <linux/usb/gadget.h>
  67. #include <linux/usb/otg.h>
  68. #include "ci13xxx_udc.h"
  69. /******************************************************************************
  70. * DEFINE
  71. *****************************************************************************/
  72. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* Interrupt statistics */
  91. #define ISR_MASK 0x1F
  92. static struct {
  93. u32 test;
  94. u32 ui;
  95. u32 uei;
  96. u32 pci;
  97. u32 uri;
  98. u32 sli;
  99. u32 none;
  100. struct {
  101. u32 cnt;
  102. u32 buf[ISR_MASK+1];
  103. u32 idx;
  104. } hndl;
  105. } isr_statistics;
  106. /**
  107. * ffs_nr: find first (least significant) bit set
  108. * @x: the word to search
  109. *
  110. * This function returns bit number (instead of position)
  111. */
  112. static int ffs_nr(u32 x)
  113. {
  114. int n = ffs(x);
  115. return n ? n-1 : 32;
  116. }
  117. /******************************************************************************
  118. * HW block
  119. *****************************************************************************/
  120. /* MSM specific */
  121. #define ABS_AHBBURST (0x0090UL)
  122. #define ABS_AHBMODE (0x0098UL)
  123. /* UDC register map */
  124. static uintptr_t ci_regs_nolpm[] = {
  125. [CAP_CAPLENGTH] = 0x000UL,
  126. [CAP_HCCPARAMS] = 0x008UL,
  127. [CAP_DCCPARAMS] = 0x024UL,
  128. [CAP_TESTMODE] = 0x038UL,
  129. [OP_USBCMD] = 0x000UL,
  130. [OP_USBSTS] = 0x004UL,
  131. [OP_USBINTR] = 0x008UL,
  132. [OP_DEVICEADDR] = 0x014UL,
  133. [OP_ENDPTLISTADDR] = 0x018UL,
  134. [OP_PORTSC] = 0x044UL,
  135. [OP_DEVLC] = 0x084UL,
  136. [OP_USBMODE] = 0x068UL,
  137. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  138. [OP_ENDPTPRIME] = 0x070UL,
  139. [OP_ENDPTFLUSH] = 0x074UL,
  140. [OP_ENDPTSTAT] = 0x078UL,
  141. [OP_ENDPTCOMPLETE] = 0x07CUL,
  142. [OP_ENDPTCTRL] = 0x080UL,
  143. };
  144. static uintptr_t ci_regs_lpm[] = {
  145. [CAP_CAPLENGTH] = 0x000UL,
  146. [CAP_HCCPARAMS] = 0x008UL,
  147. [CAP_DCCPARAMS] = 0x024UL,
  148. [CAP_TESTMODE] = 0x0FCUL,
  149. [OP_USBCMD] = 0x000UL,
  150. [OP_USBSTS] = 0x004UL,
  151. [OP_USBINTR] = 0x008UL,
  152. [OP_DEVICEADDR] = 0x014UL,
  153. [OP_ENDPTLISTADDR] = 0x018UL,
  154. [OP_PORTSC] = 0x044UL,
  155. [OP_DEVLC] = 0x084UL,
  156. [OP_USBMODE] = 0x0C8UL,
  157. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  158. [OP_ENDPTPRIME] = 0x0DCUL,
  159. [OP_ENDPTFLUSH] = 0x0E0UL,
  160. [OP_ENDPTSTAT] = 0x0E4UL,
  161. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  162. [OP_ENDPTCTRL] = 0x0ECUL,
  163. };
  164. static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
  165. {
  166. int i;
  167. kfree(udc->hw_bank.regmap);
  168. udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  169. GFP_KERNEL);
  170. if (!udc->hw_bank.regmap)
  171. return -ENOMEM;
  172. for (i = 0; i < OP_ENDPTCTRL; i++)
  173. udc->hw_bank.regmap[i] =
  174. (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
  175. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  176. for (; i <= OP_LAST; i++)
  177. udc->hw_bank.regmap[i] = udc->hw_bank.op +
  178. 4 * (i - OP_ENDPTCTRL) +
  179. (is_lpm
  180. ? ci_regs_lpm[OP_ENDPTCTRL]
  181. : ci_regs_nolpm[OP_ENDPTCTRL]);
  182. return 0;
  183. }
  184. /**
  185. * hw_ep_bit: calculates the bit number
  186. * @num: endpoint number
  187. * @dir: endpoint direction
  188. *
  189. * This function returns bit number
  190. */
  191. static inline int hw_ep_bit(int num, int dir)
  192. {
  193. return num + (dir ? 16 : 0);
  194. }
  195. static int ep_to_bit(struct ci13xxx *udc, int n)
  196. {
  197. int fill = 16 - udc->hw_ep_max / 2;
  198. if (n >= udc->hw_ep_max / 2)
  199. n += fill;
  200. return n;
  201. }
  202. /**
  203. * hw_read: reads from a hw register
  204. * @reg: register index
  205. * @mask: bitfield mask
  206. *
  207. * This function returns register contents
  208. */
  209. static u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
  210. {
  211. return ioread32(udc->hw_bank.regmap[reg]) & mask;
  212. }
  213. /**
  214. * hw_write: writes to a hw register
  215. * @reg: register index
  216. * @mask: bitfield mask
  217. * @data: new value
  218. */
  219. static void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask,
  220. u32 data)
  221. {
  222. if (~mask)
  223. data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
  224. | (data & mask);
  225. iowrite32(data, udc->hw_bank.regmap[reg]);
  226. }
  227. /**
  228. * hw_test_and_clear: tests & clears a hw register
  229. * @reg: register index
  230. * @mask: bitfield mask
  231. *
  232. * This function returns register contents
  233. */
  234. static u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
  235. u32 mask)
  236. {
  237. u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
  238. iowrite32(val, udc->hw_bank.regmap[reg]);
  239. return val;
  240. }
  241. /**
  242. * hw_test_and_write: tests & writes a hw register
  243. * @reg: register index
  244. * @mask: bitfield mask
  245. * @data: new value
  246. *
  247. * This function returns register contents
  248. */
  249. static u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
  250. u32 mask, u32 data)
  251. {
  252. u32 val = hw_read(udc, reg, ~0);
  253. hw_write(udc, reg, mask, data);
  254. return (val & mask) >> ffs_nr(mask);
  255. }
  256. static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
  257. uintptr_t cap_offset)
  258. {
  259. u32 reg;
  260. /* bank is a module variable */
  261. udc->hw_bank.abs = base;
  262. udc->hw_bank.cap = udc->hw_bank.abs;
  263. udc->hw_bank.cap += cap_offset;
  264. udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
  265. hw_alloc_regmap(udc, false);
  266. reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  267. ffs_nr(HCCPARAMS_LEN);
  268. udc->hw_bank.lpm = reg;
  269. hw_alloc_regmap(udc, !!reg);
  270. udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
  271. udc->hw_bank.size += OP_LAST;
  272. udc->hw_bank.size /= sizeof(u32);
  273. reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  274. ffs_nr(DCCPARAMS_DEN);
  275. udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  276. if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX)
  277. return -ENODEV;
  278. /* setup lock mode ? */
  279. /* ENDPTSETUPSTAT is '0' by default */
  280. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  281. return 0;
  282. }
  283. /**
  284. * hw_device_reset: resets chip (execute without interruption)
  285. * @base: register base address
  286. *
  287. * This function returns an error code
  288. */
  289. static int hw_device_reset(struct ci13xxx *udc)
  290. {
  291. /* should flush & stop before reset */
  292. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  293. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  294. hw_write(udc, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  295. while (hw_read(udc, OP_USBCMD, USBCMD_RST))
  296. udelay(10); /* not RTOS friendly */
  297. if (udc->udc_driver->notify_event)
  298. udc->udc_driver->notify_event(udc,
  299. CI13XXX_CONTROLLER_RESET_EVENT);
  300. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  301. hw_write(udc, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  302. /* USBMODE should be configured step by step */
  303. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  304. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  305. /* HW >= 2.3 */
  306. hw_write(udc, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  307. if (hw_read(udc, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  308. pr_err("cannot enter in device mode");
  309. pr_err("lpm = %i", udc->hw_bank.lpm);
  310. return -ENODEV;
  311. }
  312. return 0;
  313. }
  314. /**
  315. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  316. * without interruption)
  317. * @dma: 0 => disable, !0 => enable and set dma engine
  318. *
  319. * This function returns an error code
  320. */
  321. static int hw_device_state(struct ci13xxx *udc, u32 dma)
  322. {
  323. if (dma) {
  324. hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
  325. /* interrupt, error, port change, reset, sleep/suspend */
  326. hw_write(udc, OP_USBINTR, ~0,
  327. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  328. hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  329. } else {
  330. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  331. hw_write(udc, OP_USBINTR, ~0, 0);
  332. }
  333. return 0;
  334. }
  335. /**
  336. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  337. * @num: endpoint number
  338. * @dir: endpoint direction
  339. *
  340. * This function returns an error code
  341. */
  342. static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
  343. {
  344. int n = hw_ep_bit(num, dir);
  345. do {
  346. /* flush any pending transfer */
  347. hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
  348. while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
  349. cpu_relax();
  350. } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
  351. return 0;
  352. }
  353. /**
  354. * hw_ep_disable: disables endpoint (execute without interruption)
  355. * @num: endpoint number
  356. * @dir: endpoint direction
  357. *
  358. * This function returns an error code
  359. */
  360. static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
  361. {
  362. hw_ep_flush(udc, num, dir);
  363. hw_write(udc, OP_ENDPTCTRL + num,
  364. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  365. return 0;
  366. }
  367. /**
  368. * hw_ep_enable: enables endpoint (execute without interruption)
  369. * @num: endpoint number
  370. * @dir: endpoint direction
  371. * @type: endpoint type
  372. *
  373. * This function returns an error code
  374. */
  375. static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
  376. {
  377. u32 mask, data;
  378. if (dir) {
  379. mask = ENDPTCTRL_TXT; /* type */
  380. data = type << ffs_nr(mask);
  381. mask |= ENDPTCTRL_TXS; /* unstall */
  382. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  383. data |= ENDPTCTRL_TXR;
  384. mask |= ENDPTCTRL_TXE; /* enable */
  385. data |= ENDPTCTRL_TXE;
  386. } else {
  387. mask = ENDPTCTRL_RXT; /* type */
  388. data = type << ffs_nr(mask);
  389. mask |= ENDPTCTRL_RXS; /* unstall */
  390. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  391. data |= ENDPTCTRL_RXR;
  392. mask |= ENDPTCTRL_RXE; /* enable */
  393. data |= ENDPTCTRL_RXE;
  394. }
  395. hw_write(udc, OP_ENDPTCTRL + num, mask, data);
  396. return 0;
  397. }
  398. /**
  399. * hw_ep_get_halt: return endpoint halt status
  400. * @num: endpoint number
  401. * @dir: endpoint direction
  402. *
  403. * This function returns 1 if endpoint halted
  404. */
  405. static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
  406. {
  407. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  408. return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  409. }
  410. /**
  411. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  412. * interruption)
  413. * @n: endpoint number
  414. *
  415. * This function returns setup status
  416. */
  417. static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
  418. {
  419. n = ep_to_bit(udc, n);
  420. return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
  421. }
  422. /**
  423. * hw_ep_prime: primes endpoint (execute without interruption)
  424. * @num: endpoint number
  425. * @dir: endpoint direction
  426. * @is_ctrl: true if control endpoint
  427. *
  428. * This function returns an error code
  429. */
  430. static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
  431. {
  432. int n = hw_ep_bit(num, dir);
  433. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  434. return -EAGAIN;
  435. hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
  436. while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  437. cpu_relax();
  438. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  439. return -EAGAIN;
  440. /* status shoult be tested according with manual but it doesn't work */
  441. return 0;
  442. }
  443. /**
  444. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  445. * without interruption)
  446. * @num: endpoint number
  447. * @dir: endpoint direction
  448. * @value: true => stall, false => unstall
  449. *
  450. * This function returns an error code
  451. */
  452. static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
  453. {
  454. if (value != 0 && value != 1)
  455. return -EINVAL;
  456. do {
  457. enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
  458. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  459. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  460. /* data toggle - reserved for EP0 but it's in ESS */
  461. hw_write(udc, reg, mask_xs|mask_xr,
  462. value ? mask_xs : mask_xr);
  463. } while (value != hw_ep_get_halt(udc, num, dir));
  464. return 0;
  465. }
  466. /**
  467. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  468. * interruption)
  469. * @n: interrupt bit
  470. *
  471. * This function returns an error code
  472. */
  473. static int hw_intr_clear(struct ci13xxx *udc, int n)
  474. {
  475. if (n >= REG_BITS)
  476. return -EINVAL;
  477. hw_write(udc, OP_USBINTR, BIT(n), 0);
  478. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  479. return 0;
  480. }
  481. /**
  482. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  483. * interruption)
  484. * @n: interrupt bit
  485. *
  486. * This function returns an error code
  487. */
  488. static int hw_intr_force(struct ci13xxx *udc, int n)
  489. {
  490. if (n >= REG_BITS)
  491. return -EINVAL;
  492. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  493. hw_write(udc, OP_USBINTR, BIT(n), BIT(n));
  494. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  495. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, 0);
  496. return 0;
  497. }
  498. /**
  499. * hw_is_port_high_speed: test if port is high speed
  500. *
  501. * This function returns true if high speed port
  502. */
  503. static int hw_port_is_high_speed(struct ci13xxx *udc)
  504. {
  505. return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
  506. hw_read(udc, OP_PORTSC, PORTSC_HSP);
  507. }
  508. /**
  509. * hw_port_test_get: reads port test mode value
  510. *
  511. * This function returns port test mode value
  512. */
  513. static u8 hw_port_test_get(struct ci13xxx *udc)
  514. {
  515. return hw_read(udc, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  516. }
  517. /**
  518. * hw_port_test_set: writes port test mode (execute without interruption)
  519. * @mode: new value
  520. *
  521. * This function returns an error code
  522. */
  523. static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
  524. {
  525. const u8 TEST_MODE_MAX = 7;
  526. if (mode > TEST_MODE_MAX)
  527. return -EINVAL;
  528. hw_write(udc, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  529. return 0;
  530. }
  531. /**
  532. * hw_read_intr_enable: returns interrupt enable register
  533. *
  534. * This function returns register data
  535. */
  536. static u32 hw_read_intr_enable(struct ci13xxx *udc)
  537. {
  538. return hw_read(udc, OP_USBINTR, ~0);
  539. }
  540. /**
  541. * hw_read_intr_status: returns interrupt status register
  542. *
  543. * This function returns register data
  544. */
  545. static u32 hw_read_intr_status(struct ci13xxx *udc)
  546. {
  547. return hw_read(udc, OP_USBSTS, ~0);
  548. }
  549. /**
  550. * hw_register_read: reads all device registers (execute without interruption)
  551. * @buf: destination buffer
  552. * @size: buffer size
  553. *
  554. * This function returns number of registers read
  555. */
  556. static size_t hw_register_read(struct ci13xxx *udc, u32 *buf, size_t size)
  557. {
  558. unsigned i;
  559. if (size > udc->hw_bank.size)
  560. size = udc->hw_bank.size;
  561. for (i = 0; i < size; i++)
  562. buf[i] = hw_read(udc, i * sizeof(u32), ~0);
  563. return size;
  564. }
  565. /**
  566. * hw_register_write: writes to register
  567. * @addr: register address
  568. * @data: register value
  569. *
  570. * This function returns an error code
  571. */
  572. static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
  573. {
  574. /* align */
  575. addr /= sizeof(u32);
  576. if (addr >= udc->hw_bank.size)
  577. return -EINVAL;
  578. /* align */
  579. addr *= sizeof(u32);
  580. hw_write(udc, addr, ~0, data);
  581. return 0;
  582. }
  583. /**
  584. * hw_test_and_clear_complete: test & clear complete status (execute without
  585. * interruption)
  586. * @n: endpoint number
  587. *
  588. * This function returns complete status
  589. */
  590. static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
  591. {
  592. n = ep_to_bit(udc, n);
  593. return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
  594. }
  595. /**
  596. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  597. * without interruption)
  598. *
  599. * This function returns active interrutps
  600. */
  601. static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
  602. {
  603. u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
  604. hw_write(udc, OP_USBSTS, ~0, reg);
  605. return reg;
  606. }
  607. /**
  608. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  609. * interruption)
  610. *
  611. * This function returns guard value
  612. */
  613. static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
  614. {
  615. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
  616. }
  617. /**
  618. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  619. * interruption)
  620. *
  621. * This function returns guard value
  622. */
  623. static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
  624. {
  625. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  626. }
  627. /**
  628. * hw_usb_set_address: configures USB address (execute without interruption)
  629. * @value: new USB address
  630. *
  631. * This function returns an error code
  632. */
  633. static int hw_usb_set_address(struct ci13xxx *udc, u8 value)
  634. {
  635. /* advance */
  636. hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  637. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  638. return 0;
  639. }
  640. /**
  641. * hw_usb_reset: restart device after a bus reset (execute without
  642. * interruption)
  643. *
  644. * This function returns an error code
  645. */
  646. static int hw_usb_reset(struct ci13xxx *udc)
  647. {
  648. hw_usb_set_address(udc, 0);
  649. /* ESS flushes only at end?!? */
  650. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  651. /* clear setup token semaphores */
  652. hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
  653. /* clear complete status */
  654. hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
  655. /* wait until all bits cleared */
  656. while (hw_read(udc, OP_ENDPTPRIME, ~0))
  657. udelay(10); /* not RTOS friendly */
  658. /* reset all endpoints ? */
  659. /* reset internal status and wait for further instructions
  660. no need to verify the port reset status (ESS does it) */
  661. return 0;
  662. }
  663. /******************************************************************************
  664. * DBG block
  665. *****************************************************************************/
  666. /**
  667. * show_device: prints information about device capabilities and status
  668. *
  669. * Check "device.h" for details
  670. */
  671. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  672. char *buf)
  673. {
  674. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  675. struct usb_gadget *gadget = &udc->gadget;
  676. int n = 0;
  677. trace(udc->dev, "%p\n", buf);
  678. if (attr == NULL || buf == NULL) {
  679. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  680. return 0;
  681. }
  682. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  683. gadget->speed);
  684. n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed = %d\n",
  685. gadget->max_speed);
  686. /* TODO: Scheduled for removal in 3.8. */
  687. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  688. gadget_is_dualspeed(gadget));
  689. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  690. gadget->is_otg);
  691. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  692. gadget->is_a_peripheral);
  693. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  694. gadget->b_hnp_enable);
  695. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  696. gadget->a_hnp_support);
  697. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  698. gadget->a_alt_hnp_support);
  699. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  700. (gadget->name ? gadget->name : ""));
  701. return n;
  702. }
  703. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  704. /**
  705. * show_driver: prints information about attached gadget (if any)
  706. *
  707. * Check "device.h" for details
  708. */
  709. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  710. char *buf)
  711. {
  712. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  713. struct usb_gadget_driver *driver = udc->driver;
  714. int n = 0;
  715. trace(udc->dev, "%p\n", buf);
  716. if (attr == NULL || buf == NULL) {
  717. dev_err(dev, "[%s] EINVAL\n", __func__);
  718. return 0;
  719. }
  720. if (driver == NULL)
  721. return scnprintf(buf, PAGE_SIZE,
  722. "There is no gadget attached!\n");
  723. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  724. (driver->function ? driver->function : ""));
  725. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  726. driver->max_speed);
  727. return n;
  728. }
  729. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  730. /* Maximum event message length */
  731. #define DBG_DATA_MSG 64UL
  732. /* Maximum event messages */
  733. #define DBG_DATA_MAX 128UL
  734. /* Event buffer descriptor */
  735. static struct {
  736. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  737. unsigned idx; /* index */
  738. unsigned tty; /* print to console? */
  739. rwlock_t lck; /* lock */
  740. } dbg_data = {
  741. .idx = 0,
  742. .tty = 0,
  743. .lck = __RW_LOCK_UNLOCKED(lck)
  744. };
  745. /**
  746. * dbg_dec: decrements debug event index
  747. * @idx: buffer index
  748. */
  749. static void dbg_dec(unsigned *idx)
  750. {
  751. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  752. }
  753. /**
  754. * dbg_inc: increments debug event index
  755. * @idx: buffer index
  756. */
  757. static void dbg_inc(unsigned *idx)
  758. {
  759. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  760. }
  761. /**
  762. * dbg_print: prints the common part of the event
  763. * @addr: endpoint address
  764. * @name: event name
  765. * @status: status
  766. * @extra: extra information
  767. */
  768. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  769. {
  770. struct timeval tval;
  771. unsigned int stamp;
  772. unsigned long flags;
  773. write_lock_irqsave(&dbg_data.lck, flags);
  774. do_gettimeofday(&tval);
  775. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  776. stamp = stamp * 1000000 + tval.tv_usec;
  777. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  778. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  779. stamp, addr, name, status, extra);
  780. dbg_inc(&dbg_data.idx);
  781. write_unlock_irqrestore(&dbg_data.lck, flags);
  782. if (dbg_data.tty != 0)
  783. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  784. stamp, addr, name, status, extra);
  785. }
  786. /**
  787. * dbg_done: prints a DONE event
  788. * @addr: endpoint address
  789. * @td: transfer descriptor
  790. * @status: status
  791. */
  792. static void dbg_done(u8 addr, const u32 token, int status)
  793. {
  794. char msg[DBG_DATA_MSG];
  795. scnprintf(msg, sizeof(msg), "%d %02X",
  796. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  797. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  798. dbg_print(addr, "DONE", status, msg);
  799. }
  800. /**
  801. * dbg_event: prints a generic event
  802. * @addr: endpoint address
  803. * @name: event name
  804. * @status: status
  805. */
  806. static void dbg_event(u8 addr, const char *name, int status)
  807. {
  808. if (name != NULL)
  809. dbg_print(addr, name, status, "");
  810. }
  811. /*
  812. * dbg_queue: prints a QUEUE event
  813. * @addr: endpoint address
  814. * @req: USB request
  815. * @status: status
  816. */
  817. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  818. {
  819. char msg[DBG_DATA_MSG];
  820. if (req != NULL) {
  821. scnprintf(msg, sizeof(msg),
  822. "%d %d", !req->no_interrupt, req->length);
  823. dbg_print(addr, "QUEUE", status, msg);
  824. }
  825. }
  826. /**
  827. * dbg_setup: prints a SETUP event
  828. * @addr: endpoint address
  829. * @req: setup request
  830. */
  831. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  832. {
  833. char msg[DBG_DATA_MSG];
  834. if (req != NULL) {
  835. scnprintf(msg, sizeof(msg),
  836. "%02X %02X %04X %04X %d", req->bRequestType,
  837. req->bRequest, le16_to_cpu(req->wValue),
  838. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  839. dbg_print(addr, "SETUP", 0, msg);
  840. }
  841. }
  842. /**
  843. * show_events: displays the event buffer
  844. *
  845. * Check "device.h" for details
  846. */
  847. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  848. char *buf)
  849. {
  850. unsigned long flags;
  851. unsigned i, j, n = 0;
  852. trace(dev->parent, "%p\n", buf);
  853. if (attr == NULL || buf == NULL) {
  854. dev_err(dev->parent, "[%s] EINVAL\n", __func__);
  855. return 0;
  856. }
  857. read_lock_irqsave(&dbg_data.lck, flags);
  858. i = dbg_data.idx;
  859. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  860. n += strlen(dbg_data.buf[i]);
  861. if (n >= PAGE_SIZE) {
  862. n -= strlen(dbg_data.buf[i]);
  863. break;
  864. }
  865. }
  866. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  867. j += scnprintf(buf + j, PAGE_SIZE - j,
  868. "%s", dbg_data.buf[i]);
  869. read_unlock_irqrestore(&dbg_data.lck, flags);
  870. return n;
  871. }
  872. /**
  873. * store_events: configure if events are going to be also printed to console
  874. *
  875. * Check "device.h" for details
  876. */
  877. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  878. const char *buf, size_t count)
  879. {
  880. unsigned tty;
  881. trace(dev->parent, "[%s] %p, %d\n", __func__, buf, count);
  882. if (attr == NULL || buf == NULL) {
  883. dev_err(dev, "[%s] EINVAL\n", __func__);
  884. goto done;
  885. }
  886. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  887. dev_err(dev, "<1|0>: enable|disable console log\n");
  888. goto done;
  889. }
  890. dbg_data.tty = tty;
  891. dev_info(dev, "tty = %u", dbg_data.tty);
  892. done:
  893. return count;
  894. }
  895. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  896. /**
  897. * show_inters: interrupt status, enable status and historic
  898. *
  899. * Check "device.h" for details
  900. */
  901. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  902. char *buf)
  903. {
  904. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  905. unsigned long flags;
  906. u32 intr;
  907. unsigned i, j, n = 0;
  908. trace(udc->dev, "%p\n", buf);
  909. if (attr == NULL || buf == NULL) {
  910. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  911. return 0;
  912. }
  913. spin_lock_irqsave(&udc->lock, flags);
  914. n += scnprintf(buf + n, PAGE_SIZE - n,
  915. "status = %08x\n", hw_read_intr_status(udc));
  916. n += scnprintf(buf + n, PAGE_SIZE - n,
  917. "enable = %08x\n", hw_read_intr_enable(udc));
  918. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  919. isr_statistics.test);
  920. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  921. isr_statistics.ui);
  922. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  923. isr_statistics.uei);
  924. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  925. isr_statistics.pci);
  926. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  927. isr_statistics.uri);
  928. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  929. isr_statistics.sli);
  930. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  931. isr_statistics.none);
  932. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  933. isr_statistics.hndl.cnt);
  934. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  935. i &= ISR_MASK;
  936. intr = isr_statistics.hndl.buf[i];
  937. if (USBi_UI & intr)
  938. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  939. intr &= ~USBi_UI;
  940. if (USBi_UEI & intr)
  941. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  942. intr &= ~USBi_UEI;
  943. if (USBi_PCI & intr)
  944. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  945. intr &= ~USBi_PCI;
  946. if (USBi_URI & intr)
  947. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  948. intr &= ~USBi_URI;
  949. if (USBi_SLI & intr)
  950. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  951. intr &= ~USBi_SLI;
  952. if (intr)
  953. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  954. if (isr_statistics.hndl.buf[i])
  955. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  956. }
  957. spin_unlock_irqrestore(&udc->lock, flags);
  958. return n;
  959. }
  960. /**
  961. * store_inters: enable & force or disable an individual interrutps
  962. * (to be used for test purposes only)
  963. *
  964. * Check "device.h" for details
  965. */
  966. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  967. const char *buf, size_t count)
  968. {
  969. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  970. unsigned long flags;
  971. unsigned en, bit;
  972. trace(udc->dev, "%p, %d\n", buf, count);
  973. if (attr == NULL || buf == NULL) {
  974. dev_err(udc->dev, "EINVAL\n");
  975. goto done;
  976. }
  977. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  978. dev_err(udc->dev, "<1|0> <bit>: enable|disable interrupt\n");
  979. goto done;
  980. }
  981. spin_lock_irqsave(&udc->lock, flags);
  982. if (en) {
  983. if (hw_intr_force(udc, bit))
  984. dev_err(dev, "invalid bit number\n");
  985. else
  986. isr_statistics.test++;
  987. } else {
  988. if (hw_intr_clear(udc, bit))
  989. dev_err(dev, "invalid bit number\n");
  990. }
  991. spin_unlock_irqrestore(&udc->lock, flags);
  992. done:
  993. return count;
  994. }
  995. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  996. /**
  997. * show_port_test: reads port test mode
  998. *
  999. * Check "device.h" for details
  1000. */
  1001. static ssize_t show_port_test(struct device *dev,
  1002. struct device_attribute *attr, char *buf)
  1003. {
  1004. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1005. unsigned long flags;
  1006. unsigned mode;
  1007. trace(udc->dev, "%p\n", buf);
  1008. if (attr == NULL || buf == NULL) {
  1009. dev_err(udc->dev, "EINVAL\n");
  1010. return 0;
  1011. }
  1012. spin_lock_irqsave(&udc->lock, flags);
  1013. mode = hw_port_test_get(udc);
  1014. spin_unlock_irqrestore(&udc->lock, flags);
  1015. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  1016. }
  1017. /**
  1018. * store_port_test: writes port test mode
  1019. *
  1020. * Check "device.h" for details
  1021. */
  1022. static ssize_t store_port_test(struct device *dev,
  1023. struct device_attribute *attr,
  1024. const char *buf, size_t count)
  1025. {
  1026. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1027. unsigned long flags;
  1028. unsigned mode;
  1029. trace(udc->dev, "%p, %d\n", buf, count);
  1030. if (attr == NULL || buf == NULL) {
  1031. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1032. goto done;
  1033. }
  1034. if (sscanf(buf, "%u", &mode) != 1) {
  1035. dev_err(udc->dev, "<mode>: set port test mode");
  1036. goto done;
  1037. }
  1038. spin_lock_irqsave(&udc->lock, flags);
  1039. if (hw_port_test_set(udc, mode))
  1040. dev_err(udc->dev, "invalid mode\n");
  1041. spin_unlock_irqrestore(&udc->lock, flags);
  1042. done:
  1043. return count;
  1044. }
  1045. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1046. show_port_test, store_port_test);
  1047. /**
  1048. * show_qheads: DMA contents of all queue heads
  1049. *
  1050. * Check "device.h" for details
  1051. */
  1052. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1053. char *buf)
  1054. {
  1055. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1056. unsigned long flags;
  1057. unsigned i, j, n = 0;
  1058. trace(udc->dev, "%p\n", buf);
  1059. if (attr == NULL || buf == NULL) {
  1060. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1061. return 0;
  1062. }
  1063. spin_lock_irqsave(&udc->lock, flags);
  1064. for (i = 0; i < udc->hw_ep_max/2; i++) {
  1065. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1066. struct ci13xxx_ep *mEpTx =
  1067. &udc->ci13xxx_ep[i + udc->hw_ep_max/2];
  1068. n += scnprintf(buf + n, PAGE_SIZE - n,
  1069. "EP=%02i: RX=%08X TX=%08X\n",
  1070. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1071. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1072. n += scnprintf(buf + n, PAGE_SIZE - n,
  1073. " %04X: %08X %08X\n", j,
  1074. *((u32 *)mEpRx->qh.ptr + j),
  1075. *((u32 *)mEpTx->qh.ptr + j));
  1076. }
  1077. }
  1078. spin_unlock_irqrestore(&udc->lock, flags);
  1079. return n;
  1080. }
  1081. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1082. /**
  1083. * show_registers: dumps all registers
  1084. *
  1085. * Check "device.h" for details
  1086. */
  1087. #define DUMP_ENTRIES 512
  1088. static ssize_t show_registers(struct device *dev,
  1089. struct device_attribute *attr, char *buf)
  1090. {
  1091. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1092. unsigned long flags;
  1093. u32 *dump;
  1094. unsigned i, k, n = 0;
  1095. trace(udc->dev, "%p\n", buf);
  1096. if (attr == NULL || buf == NULL) {
  1097. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1098. return 0;
  1099. }
  1100. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1101. if (!dump) {
  1102. dev_err(udc->dev, "%s: out of memory\n", __func__);
  1103. return 0;
  1104. }
  1105. spin_lock_irqsave(&udc->lock, flags);
  1106. k = hw_register_read(udc, dump, DUMP_ENTRIES);
  1107. spin_unlock_irqrestore(&udc->lock, flags);
  1108. for (i = 0; i < k; i++) {
  1109. n += scnprintf(buf + n, PAGE_SIZE - n,
  1110. "reg[0x%04X] = 0x%08X\n",
  1111. i * (unsigned)sizeof(u32), dump[i]);
  1112. }
  1113. kfree(dump);
  1114. return n;
  1115. }
  1116. /**
  1117. * store_registers: writes value to register address
  1118. *
  1119. * Check "device.h" for details
  1120. */
  1121. static ssize_t store_registers(struct device *dev,
  1122. struct device_attribute *attr,
  1123. const char *buf, size_t count)
  1124. {
  1125. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1126. unsigned long addr, data, flags;
  1127. trace(udc->dev, "%p, %d\n", buf, count);
  1128. if (attr == NULL || buf == NULL) {
  1129. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1130. goto done;
  1131. }
  1132. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1133. dev_err(udc->dev,
  1134. "<addr> <data>: write data to register address\n");
  1135. goto done;
  1136. }
  1137. spin_lock_irqsave(&udc->lock, flags);
  1138. if (hw_register_write(udc, addr, data))
  1139. dev_err(udc->dev, "invalid address range\n");
  1140. spin_unlock_irqrestore(&udc->lock, flags);
  1141. done:
  1142. return count;
  1143. }
  1144. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1145. show_registers, store_registers);
  1146. /**
  1147. * show_requests: DMA contents of all requests currently queued (all endpts)
  1148. *
  1149. * Check "device.h" for details
  1150. */
  1151. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1152. char *buf)
  1153. {
  1154. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1155. unsigned long flags;
  1156. struct list_head *ptr = NULL;
  1157. struct ci13xxx_req *req = NULL;
  1158. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1159. trace(udc->dev, "%p\n", buf);
  1160. if (attr == NULL || buf == NULL) {
  1161. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1162. return 0;
  1163. }
  1164. spin_lock_irqsave(&udc->lock, flags);
  1165. for (i = 0; i < udc->hw_ep_max; i++)
  1166. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1167. {
  1168. req = list_entry(ptr, struct ci13xxx_req, queue);
  1169. n += scnprintf(buf + n, PAGE_SIZE - n,
  1170. "EP=%02i: TD=%08X %s\n",
  1171. i % udc->hw_ep_max/2, (u32)req->dma,
  1172. ((i < udc->hw_ep_max/2) ? "RX" : "TX"));
  1173. for (j = 0; j < qSize; j++)
  1174. n += scnprintf(buf + n, PAGE_SIZE - n,
  1175. " %04X: %08X\n", j,
  1176. *((u32 *)req->ptr + j));
  1177. }
  1178. spin_unlock_irqrestore(&udc->lock, flags);
  1179. return n;
  1180. }
  1181. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1182. /**
  1183. * dbg_create_files: initializes the attribute interface
  1184. * @dev: device
  1185. *
  1186. * This function returns an error code
  1187. */
  1188. __maybe_unused static int dbg_create_files(struct device *dev)
  1189. {
  1190. int retval = 0;
  1191. if (dev == NULL)
  1192. return -EINVAL;
  1193. retval = device_create_file(dev, &dev_attr_device);
  1194. if (retval)
  1195. goto done;
  1196. retval = device_create_file(dev, &dev_attr_driver);
  1197. if (retval)
  1198. goto rm_device;
  1199. retval = device_create_file(dev, &dev_attr_events);
  1200. if (retval)
  1201. goto rm_driver;
  1202. retval = device_create_file(dev, &dev_attr_inters);
  1203. if (retval)
  1204. goto rm_events;
  1205. retval = device_create_file(dev, &dev_attr_port_test);
  1206. if (retval)
  1207. goto rm_inters;
  1208. retval = device_create_file(dev, &dev_attr_qheads);
  1209. if (retval)
  1210. goto rm_port_test;
  1211. retval = device_create_file(dev, &dev_attr_registers);
  1212. if (retval)
  1213. goto rm_qheads;
  1214. retval = device_create_file(dev, &dev_attr_requests);
  1215. if (retval)
  1216. goto rm_registers;
  1217. return 0;
  1218. rm_registers:
  1219. device_remove_file(dev, &dev_attr_registers);
  1220. rm_qheads:
  1221. device_remove_file(dev, &dev_attr_qheads);
  1222. rm_port_test:
  1223. device_remove_file(dev, &dev_attr_port_test);
  1224. rm_inters:
  1225. device_remove_file(dev, &dev_attr_inters);
  1226. rm_events:
  1227. device_remove_file(dev, &dev_attr_events);
  1228. rm_driver:
  1229. device_remove_file(dev, &dev_attr_driver);
  1230. rm_device:
  1231. device_remove_file(dev, &dev_attr_device);
  1232. done:
  1233. return retval;
  1234. }
  1235. /**
  1236. * dbg_remove_files: destroys the attribute interface
  1237. * @dev: device
  1238. *
  1239. * This function returns an error code
  1240. */
  1241. __maybe_unused static int dbg_remove_files(struct device *dev)
  1242. {
  1243. if (dev == NULL)
  1244. return -EINVAL;
  1245. device_remove_file(dev, &dev_attr_requests);
  1246. device_remove_file(dev, &dev_attr_registers);
  1247. device_remove_file(dev, &dev_attr_qheads);
  1248. device_remove_file(dev, &dev_attr_port_test);
  1249. device_remove_file(dev, &dev_attr_inters);
  1250. device_remove_file(dev, &dev_attr_events);
  1251. device_remove_file(dev, &dev_attr_driver);
  1252. device_remove_file(dev, &dev_attr_device);
  1253. return 0;
  1254. }
  1255. /******************************************************************************
  1256. * UTIL block
  1257. *****************************************************************************/
  1258. /**
  1259. * _usb_addr: calculates endpoint address from direction & number
  1260. * @ep: endpoint
  1261. */
  1262. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1263. {
  1264. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1265. }
  1266. /**
  1267. * _hardware_queue: configures a request at hardware level
  1268. * @gadget: gadget
  1269. * @mEp: endpoint
  1270. *
  1271. * This function returns an error code
  1272. */
  1273. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1274. {
  1275. struct ci13xxx *udc = mEp->udc;
  1276. unsigned i;
  1277. int ret = 0;
  1278. unsigned length = mReq->req.length;
  1279. trace(udc->dev, "%p, %p", mEp, mReq);
  1280. /* don't queue twice */
  1281. if (mReq->req.status == -EALREADY)
  1282. return -EALREADY;
  1283. mReq->req.status = -EALREADY;
  1284. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1285. mReq->req.dma = \
  1286. dma_map_single(mEp->device, mReq->req.buf,
  1287. length, mEp->dir ? DMA_TO_DEVICE :
  1288. DMA_FROM_DEVICE);
  1289. if (mReq->req.dma == 0)
  1290. return -ENOMEM;
  1291. mReq->map = 1;
  1292. }
  1293. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1294. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1295. &mReq->zdma);
  1296. if (mReq->zptr == NULL) {
  1297. if (mReq->map) {
  1298. dma_unmap_single(mEp->device, mReq->req.dma,
  1299. length, mEp->dir ? DMA_TO_DEVICE :
  1300. DMA_FROM_DEVICE);
  1301. mReq->req.dma = DMA_ADDR_INVALID;
  1302. mReq->map = 0;
  1303. }
  1304. return -ENOMEM;
  1305. }
  1306. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1307. mReq->zptr->next = TD_TERMINATE;
  1308. mReq->zptr->token = TD_STATUS_ACTIVE;
  1309. if (!mReq->req.no_interrupt)
  1310. mReq->zptr->token |= TD_IOC;
  1311. }
  1312. /*
  1313. * TD configuration
  1314. * TODO - handle requests which spawns into several TDs
  1315. */
  1316. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1317. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1318. mReq->ptr->token &= TD_TOTAL_BYTES;
  1319. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1320. if (mReq->zptr) {
  1321. mReq->ptr->next = mReq->zdma;
  1322. } else {
  1323. mReq->ptr->next = TD_TERMINATE;
  1324. if (!mReq->req.no_interrupt)
  1325. mReq->ptr->token |= TD_IOC;
  1326. }
  1327. mReq->ptr->page[0] = mReq->req.dma;
  1328. for (i = 1; i < 5; i++)
  1329. mReq->ptr->page[i] =
  1330. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1331. if (!list_empty(&mEp->qh.queue)) {
  1332. struct ci13xxx_req *mReqPrev;
  1333. int n = hw_ep_bit(mEp->num, mEp->dir);
  1334. int tmp_stat;
  1335. mReqPrev = list_entry(mEp->qh.queue.prev,
  1336. struct ci13xxx_req, queue);
  1337. if (mReqPrev->zptr)
  1338. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1339. else
  1340. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1341. wmb();
  1342. if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  1343. goto done;
  1344. do {
  1345. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1346. tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
  1347. } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
  1348. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
  1349. if (tmp_stat)
  1350. goto done;
  1351. }
  1352. /* QH configuration */
  1353. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1354. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1355. mEp->qh.ptr->cap |= QH_ZLT;
  1356. wmb(); /* synchronize before ep prime */
  1357. ret = hw_ep_prime(udc, mEp->num, mEp->dir,
  1358. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1359. done:
  1360. return ret;
  1361. }
  1362. /**
  1363. * _hardware_dequeue: handles a request at hardware level
  1364. * @gadget: gadget
  1365. * @mEp: endpoint
  1366. *
  1367. * This function returns an error code
  1368. */
  1369. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1370. {
  1371. trace(mEp->udc->dev, "%p, %p", mEp, mReq);
  1372. if (mReq->req.status != -EALREADY)
  1373. return -EINVAL;
  1374. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1375. return -EBUSY;
  1376. if (mReq->zptr) {
  1377. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1378. return -EBUSY;
  1379. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1380. mReq->zptr = NULL;
  1381. }
  1382. mReq->req.status = 0;
  1383. if (mReq->map) {
  1384. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1385. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1386. mReq->req.dma = DMA_ADDR_INVALID;
  1387. mReq->map = 0;
  1388. }
  1389. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1390. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1391. mReq->req.status = -1;
  1392. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1393. mReq->req.status = -1;
  1394. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1395. mReq->req.status = -1;
  1396. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1397. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1398. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1399. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1400. return mReq->req.actual;
  1401. }
  1402. /**
  1403. * _ep_nuke: dequeues all endpoint requests
  1404. * @mEp: endpoint
  1405. *
  1406. * This function returns an error code
  1407. * Caller must hold lock
  1408. */
  1409. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1410. __releases(mEp->lock)
  1411. __acquires(mEp->lock)
  1412. {
  1413. trace(mEp->udc->dev, "%p", mEp);
  1414. if (mEp == NULL)
  1415. return -EINVAL;
  1416. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1417. while (!list_empty(&mEp->qh.queue)) {
  1418. /* pop oldest request */
  1419. struct ci13xxx_req *mReq = \
  1420. list_entry(mEp->qh.queue.next,
  1421. struct ci13xxx_req, queue);
  1422. list_del_init(&mReq->queue);
  1423. mReq->req.status = -ESHUTDOWN;
  1424. if (mReq->req.complete != NULL) {
  1425. spin_unlock(mEp->lock);
  1426. mReq->req.complete(&mEp->ep, &mReq->req);
  1427. spin_lock(mEp->lock);
  1428. }
  1429. }
  1430. return 0;
  1431. }
  1432. /**
  1433. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1434. * @gadget: gadget
  1435. *
  1436. * This function returns an error code
  1437. */
  1438. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1439. {
  1440. struct usb_ep *ep;
  1441. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1442. unsigned long flags;
  1443. trace(udc->dev, "%p", gadget);
  1444. if (gadget == NULL)
  1445. return -EINVAL;
  1446. spin_lock_irqsave(&udc->lock, flags);
  1447. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1448. udc->remote_wakeup = 0;
  1449. udc->suspended = 0;
  1450. spin_unlock_irqrestore(&udc->lock, flags);
  1451. /* flush all endpoints */
  1452. gadget_for_each_ep(ep, gadget) {
  1453. usb_ep_fifo_flush(ep);
  1454. }
  1455. usb_ep_fifo_flush(&udc->ep0out->ep);
  1456. usb_ep_fifo_flush(&udc->ep0in->ep);
  1457. if (udc->driver)
  1458. udc->driver->disconnect(gadget);
  1459. /* make sure to disable all endpoints */
  1460. gadget_for_each_ep(ep, gadget) {
  1461. usb_ep_disable(ep);
  1462. }
  1463. if (udc->status != NULL) {
  1464. usb_ep_free_request(&udc->ep0in->ep, udc->status);
  1465. udc->status = NULL;
  1466. }
  1467. return 0;
  1468. }
  1469. /******************************************************************************
  1470. * ISR block
  1471. *****************************************************************************/
  1472. /**
  1473. * isr_reset_handler: USB reset interrupt handler
  1474. * @udc: UDC device
  1475. *
  1476. * This function resets USB engine after a bus reset occurred
  1477. */
  1478. static void isr_reset_handler(struct ci13xxx *udc)
  1479. __releases(udc->lock)
  1480. __acquires(udc->lock)
  1481. {
  1482. int retval;
  1483. trace(udc->dev, "%p", udc);
  1484. dbg_event(0xFF, "BUS RST", 0);
  1485. spin_unlock(&udc->lock);
  1486. retval = _gadget_stop_activity(&udc->gadget);
  1487. if (retval)
  1488. goto done;
  1489. retval = hw_usb_reset(udc);
  1490. if (retval)
  1491. goto done;
  1492. udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
  1493. if (udc->status == NULL)
  1494. retval = -ENOMEM;
  1495. spin_lock(&udc->lock);
  1496. done:
  1497. if (retval)
  1498. dev_err(udc->dev, "error: %i\n", retval);
  1499. }
  1500. /**
  1501. * isr_get_status_complete: get_status request complete function
  1502. * @ep: endpoint
  1503. * @req: request handled
  1504. *
  1505. * Caller must release lock
  1506. */
  1507. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1508. {
  1509. trace(NULL, "%p, %p", ep, req);
  1510. if (ep == NULL || req == NULL)
  1511. return;
  1512. kfree(req->buf);
  1513. usb_ep_free_request(ep, req);
  1514. }
  1515. /**
  1516. * isr_get_status_response: get_status request response
  1517. * @udc: udc struct
  1518. * @setup: setup request packet
  1519. *
  1520. * This function returns an error code
  1521. */
  1522. static int isr_get_status_response(struct ci13xxx *udc,
  1523. struct usb_ctrlrequest *setup)
  1524. __releases(mEp->lock)
  1525. __acquires(mEp->lock)
  1526. {
  1527. struct ci13xxx_ep *mEp = udc->ep0in;
  1528. struct usb_request *req = NULL;
  1529. gfp_t gfp_flags = GFP_ATOMIC;
  1530. int dir, num, retval;
  1531. trace(udc->dev, "%p, %p", mEp, setup);
  1532. if (mEp == NULL || setup == NULL)
  1533. return -EINVAL;
  1534. spin_unlock(mEp->lock);
  1535. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1536. spin_lock(mEp->lock);
  1537. if (req == NULL)
  1538. return -ENOMEM;
  1539. req->complete = isr_get_status_complete;
  1540. req->length = 2;
  1541. req->buf = kzalloc(req->length, gfp_flags);
  1542. if (req->buf == NULL) {
  1543. retval = -ENOMEM;
  1544. goto err_free_req;
  1545. }
  1546. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1547. /* Assume that device is bus powered for now. */
  1548. *(u16 *)req->buf = udc->remote_wakeup << 1;
  1549. retval = 0;
  1550. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1551. == USB_RECIP_ENDPOINT) {
  1552. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1553. TX : RX;
  1554. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1555. *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
  1556. }
  1557. /* else do nothing; reserved for future use */
  1558. spin_unlock(mEp->lock);
  1559. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1560. spin_lock(mEp->lock);
  1561. if (retval)
  1562. goto err_free_buf;
  1563. return 0;
  1564. err_free_buf:
  1565. kfree(req->buf);
  1566. err_free_req:
  1567. spin_unlock(mEp->lock);
  1568. usb_ep_free_request(&mEp->ep, req);
  1569. spin_lock(mEp->lock);
  1570. return retval;
  1571. }
  1572. /**
  1573. * isr_setup_status_complete: setup_status request complete function
  1574. * @ep: endpoint
  1575. * @req: request handled
  1576. *
  1577. * Caller must release lock. Put the port in test mode if test mode
  1578. * feature is selected.
  1579. */
  1580. static void
  1581. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1582. {
  1583. struct ci13xxx *udc = req->context;
  1584. unsigned long flags;
  1585. trace(udc->dev, "%p, %p", ep, req);
  1586. spin_lock_irqsave(&udc->lock, flags);
  1587. if (udc->test_mode)
  1588. hw_port_test_set(udc, udc->test_mode);
  1589. spin_unlock_irqrestore(&udc->lock, flags);
  1590. }
  1591. /**
  1592. * isr_setup_status_phase: queues the status phase of a setup transation
  1593. * @udc: udc struct
  1594. *
  1595. * This function returns an error code
  1596. */
  1597. static int isr_setup_status_phase(struct ci13xxx *udc)
  1598. __releases(mEp->lock)
  1599. __acquires(mEp->lock)
  1600. {
  1601. int retval;
  1602. struct ci13xxx_ep *mEp;
  1603. trace(udc->dev, "%p", udc);
  1604. mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
  1605. udc->status->context = udc;
  1606. udc->status->complete = isr_setup_status_complete;
  1607. spin_unlock(mEp->lock);
  1608. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1609. spin_lock(mEp->lock);
  1610. return retval;
  1611. }
  1612. /**
  1613. * isr_tr_complete_low: transaction complete low level handler
  1614. * @mEp: endpoint
  1615. *
  1616. * This function returns an error code
  1617. * Caller must hold lock
  1618. */
  1619. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1620. __releases(mEp->lock)
  1621. __acquires(mEp->lock)
  1622. {
  1623. struct ci13xxx_req *mReq, *mReqTemp;
  1624. struct ci13xxx_ep *mEpTemp = mEp;
  1625. int uninitialized_var(retval);
  1626. trace(mEp->udc->dev, "%p", mEp);
  1627. if (list_empty(&mEp->qh.queue))
  1628. return -EINVAL;
  1629. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1630. queue) {
  1631. retval = _hardware_dequeue(mEp, mReq);
  1632. if (retval < 0)
  1633. break;
  1634. list_del_init(&mReq->queue);
  1635. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1636. if (mReq->req.complete != NULL) {
  1637. spin_unlock(mEp->lock);
  1638. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1639. mReq->req.length)
  1640. mEpTemp = mEp->udc->ep0in;
  1641. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1642. spin_lock(mEp->lock);
  1643. }
  1644. }
  1645. if (retval == -EBUSY)
  1646. retval = 0;
  1647. if (retval < 0)
  1648. dbg_event(_usb_addr(mEp), "DONE", retval);
  1649. return retval;
  1650. }
  1651. /**
  1652. * isr_tr_complete_handler: transaction complete interrupt handler
  1653. * @udc: UDC descriptor
  1654. *
  1655. * This function handles traffic events
  1656. */
  1657. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1658. __releases(udc->lock)
  1659. __acquires(udc->lock)
  1660. {
  1661. unsigned i;
  1662. u8 tmode = 0;
  1663. trace(udc->dev, "%p", udc);
  1664. for (i = 0; i < udc->hw_ep_max; i++) {
  1665. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1666. int type, num, dir, err = -EINVAL;
  1667. struct usb_ctrlrequest req;
  1668. if (mEp->ep.desc == NULL)
  1669. continue; /* not configured */
  1670. if (hw_test_and_clear_complete(udc, i)) {
  1671. err = isr_tr_complete_low(mEp);
  1672. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1673. if (err > 0) /* needs status phase */
  1674. err = isr_setup_status_phase(udc);
  1675. if (err < 0) {
  1676. dbg_event(_usb_addr(mEp),
  1677. "ERROR", err);
  1678. spin_unlock(&udc->lock);
  1679. if (usb_ep_set_halt(&mEp->ep))
  1680. dev_err(udc->dev,
  1681. "error: ep_set_halt\n");
  1682. spin_lock(&udc->lock);
  1683. }
  1684. }
  1685. }
  1686. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1687. !hw_test_and_clear_setup_status(udc, i))
  1688. continue;
  1689. if (i != 0) {
  1690. dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
  1691. continue;
  1692. }
  1693. /*
  1694. * Flush data and handshake transactions of previous
  1695. * setup packet.
  1696. */
  1697. _ep_nuke(udc->ep0out);
  1698. _ep_nuke(udc->ep0in);
  1699. /* read_setup_packet */
  1700. do {
  1701. hw_test_and_set_setup_guard(udc);
  1702. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1703. } while (!hw_test_and_clear_setup_guard(udc));
  1704. type = req.bRequestType;
  1705. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1706. dbg_setup(_usb_addr(mEp), &req);
  1707. switch (req.bRequest) {
  1708. case USB_REQ_CLEAR_FEATURE:
  1709. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1710. le16_to_cpu(req.wValue) ==
  1711. USB_ENDPOINT_HALT) {
  1712. if (req.wLength != 0)
  1713. break;
  1714. num = le16_to_cpu(req.wIndex);
  1715. dir = num & USB_ENDPOINT_DIR_MASK;
  1716. num &= USB_ENDPOINT_NUMBER_MASK;
  1717. if (dir) /* TX */
  1718. num += udc->hw_ep_max/2;
  1719. if (!udc->ci13xxx_ep[num].wedge) {
  1720. spin_unlock(&udc->lock);
  1721. err = usb_ep_clear_halt(
  1722. &udc->ci13xxx_ep[num].ep);
  1723. spin_lock(&udc->lock);
  1724. if (err)
  1725. break;
  1726. }
  1727. err = isr_setup_status_phase(udc);
  1728. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1729. le16_to_cpu(req.wValue) ==
  1730. USB_DEVICE_REMOTE_WAKEUP) {
  1731. if (req.wLength != 0)
  1732. break;
  1733. udc->remote_wakeup = 0;
  1734. err = isr_setup_status_phase(udc);
  1735. } else {
  1736. goto delegate;
  1737. }
  1738. break;
  1739. case USB_REQ_GET_STATUS:
  1740. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1741. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1742. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1743. goto delegate;
  1744. if (le16_to_cpu(req.wLength) != 2 ||
  1745. le16_to_cpu(req.wValue) != 0)
  1746. break;
  1747. err = isr_get_status_response(udc, &req);
  1748. break;
  1749. case USB_REQ_SET_ADDRESS:
  1750. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1751. goto delegate;
  1752. if (le16_to_cpu(req.wLength) != 0 ||
  1753. le16_to_cpu(req.wIndex) != 0)
  1754. break;
  1755. err = hw_usb_set_address(udc,
  1756. (u8)le16_to_cpu(req.wValue));
  1757. if (err)
  1758. break;
  1759. err = isr_setup_status_phase(udc);
  1760. break;
  1761. case USB_REQ_SET_FEATURE:
  1762. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1763. le16_to_cpu(req.wValue) ==
  1764. USB_ENDPOINT_HALT) {
  1765. if (req.wLength != 0)
  1766. break;
  1767. num = le16_to_cpu(req.wIndex);
  1768. dir = num & USB_ENDPOINT_DIR_MASK;
  1769. num &= USB_ENDPOINT_NUMBER_MASK;
  1770. if (dir) /* TX */
  1771. num += udc->hw_ep_max/2;
  1772. spin_unlock(&udc->lock);
  1773. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1774. spin_lock(&udc->lock);
  1775. if (!err)
  1776. isr_setup_status_phase(udc);
  1777. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1778. if (req.wLength != 0)
  1779. break;
  1780. switch (le16_to_cpu(req.wValue)) {
  1781. case USB_DEVICE_REMOTE_WAKEUP:
  1782. udc->remote_wakeup = 1;
  1783. err = isr_setup_status_phase(udc);
  1784. break;
  1785. case USB_DEVICE_TEST_MODE:
  1786. tmode = le16_to_cpu(req.wIndex) >> 8;
  1787. switch (tmode) {
  1788. case TEST_J:
  1789. case TEST_K:
  1790. case TEST_SE0_NAK:
  1791. case TEST_PACKET:
  1792. case TEST_FORCE_EN:
  1793. udc->test_mode = tmode;
  1794. err = isr_setup_status_phase(
  1795. udc);
  1796. break;
  1797. default:
  1798. break;
  1799. }
  1800. default:
  1801. goto delegate;
  1802. }
  1803. } else {
  1804. goto delegate;
  1805. }
  1806. break;
  1807. default:
  1808. delegate:
  1809. if (req.wLength == 0) /* no data phase */
  1810. udc->ep0_dir = TX;
  1811. spin_unlock(&udc->lock);
  1812. err = udc->driver->setup(&udc->gadget, &req);
  1813. spin_lock(&udc->lock);
  1814. break;
  1815. }
  1816. if (err < 0) {
  1817. dbg_event(_usb_addr(mEp), "ERROR", err);
  1818. spin_unlock(&udc->lock);
  1819. if (usb_ep_set_halt(&mEp->ep))
  1820. dev_err(udc->dev, "error: ep_set_halt\n");
  1821. spin_lock(&udc->lock);
  1822. }
  1823. }
  1824. }
  1825. /******************************************************************************
  1826. * ENDPT block
  1827. *****************************************************************************/
  1828. /**
  1829. * ep_enable: configure endpoint, making it usable
  1830. *
  1831. * Check usb_ep_enable() at "usb_gadget.h" for details
  1832. */
  1833. static int ep_enable(struct usb_ep *ep,
  1834. const struct usb_endpoint_descriptor *desc)
  1835. {
  1836. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1837. int retval = 0;
  1838. unsigned long flags;
  1839. trace(mEp->udc->dev, "%p, %p", ep, desc);
  1840. if (ep == NULL || desc == NULL)
  1841. return -EINVAL;
  1842. spin_lock_irqsave(mEp->lock, flags);
  1843. /* only internal SW should enable ctrl endpts */
  1844. mEp->ep.desc = desc;
  1845. if (!list_empty(&mEp->qh.queue))
  1846. dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
  1847. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1848. mEp->num = usb_endpoint_num(desc);
  1849. mEp->type = usb_endpoint_type(desc);
  1850. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1851. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1852. mEp->qh.ptr->cap = 0;
  1853. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1854. mEp->qh.ptr->cap |= QH_IOS;
  1855. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1856. mEp->qh.ptr->cap &= ~QH_MULT;
  1857. else
  1858. mEp->qh.ptr->cap &= ~QH_ZLT;
  1859. mEp->qh.ptr->cap |=
  1860. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1861. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1862. /*
  1863. * Enable endpoints in the HW other than ep0 as ep0
  1864. * is always enabled
  1865. */
  1866. if (mEp->num)
  1867. retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
  1868. spin_unlock_irqrestore(mEp->lock, flags);
  1869. return retval;
  1870. }
  1871. /**
  1872. * ep_disable: endpoint is no longer usable
  1873. *
  1874. * Check usb_ep_disable() at "usb_gadget.h" for details
  1875. */
  1876. static int ep_disable(struct usb_ep *ep)
  1877. {
  1878. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1879. int direction, retval = 0;
  1880. unsigned long flags;
  1881. trace(mEp->udc->dev, "%p", ep);
  1882. if (ep == NULL)
  1883. return -EINVAL;
  1884. else if (mEp->ep.desc == NULL)
  1885. return -EBUSY;
  1886. spin_lock_irqsave(mEp->lock, flags);
  1887. /* only internal SW should disable ctrl endpts */
  1888. direction = mEp->dir;
  1889. do {
  1890. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1891. retval |= _ep_nuke(mEp);
  1892. retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
  1893. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1894. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1895. } while (mEp->dir != direction);
  1896. mEp->ep.desc = NULL;
  1897. spin_unlock_irqrestore(mEp->lock, flags);
  1898. return retval;
  1899. }
  1900. /**
  1901. * ep_alloc_request: allocate a request object to use with this endpoint
  1902. *
  1903. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1904. */
  1905. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1906. {
  1907. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1908. struct ci13xxx_req *mReq = NULL;
  1909. trace(mEp->udc->dev, "%p, %i", ep, gfp_flags);
  1910. if (ep == NULL)
  1911. return NULL;
  1912. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1913. if (mReq != NULL) {
  1914. INIT_LIST_HEAD(&mReq->queue);
  1915. mReq->req.dma = DMA_ADDR_INVALID;
  1916. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1917. &mReq->dma);
  1918. if (mReq->ptr == NULL) {
  1919. kfree(mReq);
  1920. mReq = NULL;
  1921. }
  1922. }
  1923. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1924. return (mReq == NULL) ? NULL : &mReq->req;
  1925. }
  1926. /**
  1927. * ep_free_request: frees a request object
  1928. *
  1929. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1930. */
  1931. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1932. {
  1933. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1934. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1935. unsigned long flags;
  1936. trace(mEp->udc->dev, "%p, %p", ep, req);
  1937. if (ep == NULL || req == NULL) {
  1938. return;
  1939. } else if (!list_empty(&mReq->queue)) {
  1940. dev_err(mEp->udc->dev, "freeing queued request\n");
  1941. return;
  1942. }
  1943. spin_lock_irqsave(mEp->lock, flags);
  1944. if (mReq->ptr)
  1945. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1946. kfree(mReq);
  1947. dbg_event(_usb_addr(mEp), "FREE", 0);
  1948. spin_unlock_irqrestore(mEp->lock, flags);
  1949. }
  1950. /**
  1951. * ep_queue: queues (submits) an I/O request to an endpoint
  1952. *
  1953. * Check usb_ep_queue()* at usb_gadget.h" for details
  1954. */
  1955. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1956. gfp_t __maybe_unused gfp_flags)
  1957. {
  1958. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1959. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1960. struct ci13xxx *udc = mEp->udc;
  1961. int retval = 0;
  1962. unsigned long flags;
  1963. trace(mEp->udc->dev, "%p, %p, %X", ep, req, gfp_flags);
  1964. if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
  1965. return -EINVAL;
  1966. spin_lock_irqsave(mEp->lock, flags);
  1967. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1968. if (req->length)
  1969. mEp = (udc->ep0_dir == RX) ?
  1970. udc->ep0out : udc->ep0in;
  1971. if (!list_empty(&mEp->qh.queue)) {
  1972. _ep_nuke(mEp);
  1973. retval = -EOVERFLOW;
  1974. dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
  1975. _usb_addr(mEp));
  1976. }
  1977. }
  1978. /* first nuke then test link, e.g. previous status has not sent */
  1979. if (!list_empty(&mReq->queue)) {
  1980. retval = -EBUSY;
  1981. dev_err(mEp->udc->dev, "request already in queue\n");
  1982. goto done;
  1983. }
  1984. if (req->length > 4 * CI13XXX_PAGE_SIZE) {
  1985. req->length = 4 * CI13XXX_PAGE_SIZE;
  1986. retval = -EMSGSIZE;
  1987. dev_warn(mEp->udc->dev, "request length truncated\n");
  1988. }
  1989. dbg_queue(_usb_addr(mEp), req, retval);
  1990. /* push request */
  1991. mReq->req.status = -EINPROGRESS;
  1992. mReq->req.actual = 0;
  1993. retval = _hardware_enqueue(mEp, mReq);
  1994. if (retval == -EALREADY) {
  1995. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1996. retval = 0;
  1997. }
  1998. if (!retval)
  1999. list_add_tail(&mReq->queue, &mEp->qh.queue);
  2000. done:
  2001. spin_unlock_irqrestore(mEp->lock, flags);
  2002. return retval;
  2003. }
  2004. /**
  2005. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  2006. *
  2007. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  2008. */
  2009. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  2010. {
  2011. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2012. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  2013. unsigned long flags;
  2014. trace(mEp->udc->dev, "%p, %p", ep, req);
  2015. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  2016. mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
  2017. list_empty(&mEp->qh.queue))
  2018. return -EINVAL;
  2019. spin_lock_irqsave(mEp->lock, flags);
  2020. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  2021. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2022. /* pop request */
  2023. list_del_init(&mReq->queue);
  2024. if (mReq->map) {
  2025. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  2026. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  2027. mReq->req.dma = DMA_ADDR_INVALID;
  2028. mReq->map = 0;
  2029. }
  2030. req->status = -ECONNRESET;
  2031. if (mReq->req.complete != NULL) {
  2032. spin_unlock(mEp->lock);
  2033. mReq->req.complete(&mEp->ep, &mReq->req);
  2034. spin_lock(mEp->lock);
  2035. }
  2036. spin_unlock_irqrestore(mEp->lock, flags);
  2037. return 0;
  2038. }
  2039. /**
  2040. * ep_set_halt: sets the endpoint halt feature
  2041. *
  2042. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2043. */
  2044. static int ep_set_halt(struct usb_ep *ep, int value)
  2045. {
  2046. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2047. int direction, retval = 0;
  2048. unsigned long flags;
  2049. trace(mEp->udc->dev, "%p, %i", ep, value);
  2050. if (ep == NULL || mEp->ep.desc == NULL)
  2051. return -EINVAL;
  2052. spin_lock_irqsave(mEp->lock, flags);
  2053. #ifndef STALL_IN
  2054. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2055. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2056. !list_empty(&mEp->qh.queue)) {
  2057. spin_unlock_irqrestore(mEp->lock, flags);
  2058. return -EAGAIN;
  2059. }
  2060. #endif
  2061. direction = mEp->dir;
  2062. do {
  2063. dbg_event(_usb_addr(mEp), "HALT", value);
  2064. retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
  2065. if (!value)
  2066. mEp->wedge = 0;
  2067. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2068. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2069. } while (mEp->dir != direction);
  2070. spin_unlock_irqrestore(mEp->lock, flags);
  2071. return retval;
  2072. }
  2073. /**
  2074. * ep_set_wedge: sets the halt feature and ignores clear requests
  2075. *
  2076. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2077. */
  2078. static int ep_set_wedge(struct usb_ep *ep)
  2079. {
  2080. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2081. unsigned long flags;
  2082. trace(mEp->udc->dev, "%p", ep);
  2083. if (ep == NULL || mEp->ep.desc == NULL)
  2084. return -EINVAL;
  2085. spin_lock_irqsave(mEp->lock, flags);
  2086. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2087. mEp->wedge = 1;
  2088. spin_unlock_irqrestore(mEp->lock, flags);
  2089. return usb_ep_set_halt(ep);
  2090. }
  2091. /**
  2092. * ep_fifo_flush: flushes contents of a fifo
  2093. *
  2094. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2095. */
  2096. static void ep_fifo_flush(struct usb_ep *ep)
  2097. {
  2098. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2099. unsigned long flags;
  2100. trace(mEp->udc->dev, "%p", ep);
  2101. if (ep == NULL) {
  2102. dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
  2103. return;
  2104. }
  2105. spin_lock_irqsave(mEp->lock, flags);
  2106. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2107. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2108. spin_unlock_irqrestore(mEp->lock, flags);
  2109. }
  2110. /**
  2111. * Endpoint-specific part of the API to the USB controller hardware
  2112. * Check "usb_gadget.h" for details
  2113. */
  2114. static const struct usb_ep_ops usb_ep_ops = {
  2115. .enable = ep_enable,
  2116. .disable = ep_disable,
  2117. .alloc_request = ep_alloc_request,
  2118. .free_request = ep_free_request,
  2119. .queue = ep_queue,
  2120. .dequeue = ep_dequeue,
  2121. .set_halt = ep_set_halt,
  2122. .set_wedge = ep_set_wedge,
  2123. .fifo_flush = ep_fifo_flush,
  2124. };
  2125. /******************************************************************************
  2126. * GADGET block
  2127. *****************************************************************************/
  2128. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2129. {
  2130. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2131. unsigned long flags;
  2132. int gadget_ready = 0;
  2133. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2134. return -EOPNOTSUPP;
  2135. spin_lock_irqsave(&udc->lock, flags);
  2136. udc->vbus_active = is_active;
  2137. if (udc->driver)
  2138. gadget_ready = 1;
  2139. spin_unlock_irqrestore(&udc->lock, flags);
  2140. if (gadget_ready) {
  2141. if (is_active) {
  2142. pm_runtime_get_sync(&_gadget->dev);
  2143. hw_device_reset(udc);
  2144. hw_device_state(udc, udc->ep0out->qh.dma);
  2145. } else {
  2146. hw_device_state(udc, 0);
  2147. if (udc->udc_driver->notify_event)
  2148. udc->udc_driver->notify_event(udc,
  2149. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2150. _gadget_stop_activity(&udc->gadget);
  2151. pm_runtime_put_sync(&_gadget->dev);
  2152. }
  2153. }
  2154. return 0;
  2155. }
  2156. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2157. {
  2158. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2159. unsigned long flags;
  2160. int ret = 0;
  2161. trace(udc->dev, "");
  2162. spin_lock_irqsave(&udc->lock, flags);
  2163. if (!udc->remote_wakeup) {
  2164. ret = -EOPNOTSUPP;
  2165. trace(udc->dev, "remote wakeup feature is not enabled\n");
  2166. goto out;
  2167. }
  2168. if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
  2169. ret = -EINVAL;
  2170. trace(udc->dev, "port is not suspended\n");
  2171. goto out;
  2172. }
  2173. hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2174. out:
  2175. spin_unlock_irqrestore(&udc->lock, flags);
  2176. return ret;
  2177. }
  2178. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2179. {
  2180. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2181. if (udc->transceiver)
  2182. return usb_phy_set_power(udc->transceiver, mA);
  2183. return -ENOTSUPP;
  2184. }
  2185. static int ci13xxx_start(struct usb_gadget *gadget,
  2186. struct usb_gadget_driver *driver);
  2187. static int ci13xxx_stop(struct usb_gadget *gadget,
  2188. struct usb_gadget_driver *driver);
  2189. /**
  2190. * Device operations part of the API to the USB controller hardware,
  2191. * which don't involve endpoints (or i/o)
  2192. * Check "usb_gadget.h" for details
  2193. */
  2194. static const struct usb_gadget_ops usb_gadget_ops = {
  2195. .vbus_session = ci13xxx_vbus_session,
  2196. .wakeup = ci13xxx_wakeup,
  2197. .vbus_draw = ci13xxx_vbus_draw,
  2198. .udc_start = ci13xxx_start,
  2199. .udc_stop = ci13xxx_stop,
  2200. };
  2201. static int init_eps(struct ci13xxx *udc)
  2202. {
  2203. int retval = 0, i, j;
  2204. for (i = 0; i < udc->hw_ep_max/2; i++)
  2205. for (j = RX; j <= TX; j++) {
  2206. int k = i + j * udc->hw_ep_max/2;
  2207. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2208. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2209. (j == TX) ? "in" : "out");
  2210. mEp->udc = udc;
  2211. mEp->lock = &udc->lock;
  2212. mEp->device = &udc->gadget.dev;
  2213. mEp->td_pool = udc->td_pool;
  2214. mEp->ep.name = mEp->name;
  2215. mEp->ep.ops = &usb_ep_ops;
  2216. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2217. INIT_LIST_HEAD(&mEp->qh.queue);
  2218. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2219. &mEp->qh.dma);
  2220. if (mEp->qh.ptr == NULL)
  2221. retval = -ENOMEM;
  2222. else
  2223. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2224. /*
  2225. * set up shorthands for ep0 out and in endpoints,
  2226. * don't add to gadget's ep_list
  2227. */
  2228. if (i == 0) {
  2229. if (j == RX)
  2230. udc->ep0out = mEp;
  2231. else
  2232. udc->ep0in = mEp;
  2233. continue;
  2234. }
  2235. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2236. }
  2237. return retval;
  2238. }
  2239. /**
  2240. * ci13xxx_start: register a gadget driver
  2241. * @gadget: our gadget
  2242. * @driver: the driver being registered
  2243. *
  2244. * Interrupts are enabled here.
  2245. */
  2246. static int ci13xxx_start(struct usb_gadget *gadget,
  2247. struct usb_gadget_driver *driver)
  2248. {
  2249. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  2250. unsigned long flags;
  2251. int retval = -ENOMEM;
  2252. trace(udc->dev, "%p", driver);
  2253. if (driver->disconnect == NULL)
  2254. return -EINVAL;
  2255. udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
  2256. retval = usb_ep_enable(&udc->ep0out->ep);
  2257. if (retval)
  2258. return retval;
  2259. udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
  2260. retval = usb_ep_enable(&udc->ep0in->ep);
  2261. if (retval)
  2262. return retval;
  2263. spin_lock_irqsave(&udc->lock, flags);
  2264. udc->driver = driver;
  2265. pm_runtime_get_sync(&udc->gadget.dev);
  2266. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2267. if (udc->vbus_active) {
  2268. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2269. hw_device_reset(udc);
  2270. } else {
  2271. pm_runtime_put_sync(&udc->gadget.dev);
  2272. goto done;
  2273. }
  2274. }
  2275. retval = hw_device_state(udc, udc->ep0out->qh.dma);
  2276. if (retval)
  2277. pm_runtime_put_sync(&udc->gadget.dev);
  2278. done:
  2279. spin_unlock_irqrestore(&udc->lock, flags);
  2280. return retval;
  2281. }
  2282. /**
  2283. * ci13xxx_stop: unregister a gadget driver
  2284. */
  2285. static int ci13xxx_stop(struct usb_gadget *gadget,
  2286. struct usb_gadget_driver *driver)
  2287. {
  2288. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  2289. unsigned long flags;
  2290. trace(udc->dev, "%p", driver);
  2291. spin_lock_irqsave(&udc->lock, flags);
  2292. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2293. udc->vbus_active) {
  2294. hw_device_state(udc, 0);
  2295. if (udc->udc_driver->notify_event)
  2296. udc->udc_driver->notify_event(udc,
  2297. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2298. udc->driver = NULL;
  2299. spin_unlock_irqrestore(&udc->lock, flags);
  2300. _gadget_stop_activity(&udc->gadget);
  2301. spin_lock_irqsave(&udc->lock, flags);
  2302. pm_runtime_put(&udc->gadget.dev);
  2303. }
  2304. spin_unlock_irqrestore(&udc->lock, flags);
  2305. return 0;
  2306. }
  2307. /******************************************************************************
  2308. * BUS block
  2309. *****************************************************************************/
  2310. /**
  2311. * udc_irq: global interrupt handler
  2312. *
  2313. * This function returns IRQ_HANDLED if the IRQ has been handled
  2314. * It locks access to registers
  2315. */
  2316. static irqreturn_t udc_irq(int irq, void *data)
  2317. {
  2318. struct ci13xxx *udc = data;
  2319. irqreturn_t retval;
  2320. u32 intr;
  2321. trace(udc ? udc->dev : NULL, "");
  2322. if (udc == NULL) {
  2323. dev_err(udc->dev, "ENODEV");
  2324. return IRQ_HANDLED;
  2325. }
  2326. spin_lock(&udc->lock);
  2327. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2328. if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
  2329. USBMODE_CM_DEVICE) {
  2330. spin_unlock(&udc->lock);
  2331. return IRQ_NONE;
  2332. }
  2333. }
  2334. intr = hw_test_and_clear_intr_active(udc);
  2335. if (intr) {
  2336. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2337. isr_statistics.hndl.idx &= ISR_MASK;
  2338. isr_statistics.hndl.cnt++;
  2339. /* order defines priority - do NOT change it */
  2340. if (USBi_URI & intr) {
  2341. isr_statistics.uri++;
  2342. isr_reset_handler(udc);
  2343. }
  2344. if (USBi_PCI & intr) {
  2345. isr_statistics.pci++;
  2346. udc->gadget.speed = hw_port_is_high_speed(udc) ?
  2347. USB_SPEED_HIGH : USB_SPEED_FULL;
  2348. if (udc->suspended && udc->driver->resume) {
  2349. spin_unlock(&udc->lock);
  2350. udc->driver->resume(&udc->gadget);
  2351. spin_lock(&udc->lock);
  2352. udc->suspended = 0;
  2353. }
  2354. }
  2355. if (USBi_UEI & intr)
  2356. isr_statistics.uei++;
  2357. if (USBi_UI & intr) {
  2358. isr_statistics.ui++;
  2359. isr_tr_complete_handler(udc);
  2360. }
  2361. if (USBi_SLI & intr) {
  2362. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  2363. udc->driver->suspend) {
  2364. udc->suspended = 1;
  2365. spin_unlock(&udc->lock);
  2366. udc->driver->suspend(&udc->gadget);
  2367. spin_lock(&udc->lock);
  2368. }
  2369. isr_statistics.sli++;
  2370. }
  2371. retval = IRQ_HANDLED;
  2372. } else {
  2373. isr_statistics.none++;
  2374. retval = IRQ_NONE;
  2375. }
  2376. spin_unlock(&udc->lock);
  2377. return retval;
  2378. }
  2379. /**
  2380. * udc_release: driver release function
  2381. * @dev: device
  2382. *
  2383. * Currently does nothing
  2384. */
  2385. static void udc_release(struct device *dev)
  2386. {
  2387. trace(dev->parent, "%p", dev);
  2388. }
  2389. /**
  2390. * udc_probe: parent probe must call this to initialize UDC
  2391. * @dev: parent device
  2392. * @regs: registers base address
  2393. * @name: driver name
  2394. *
  2395. * This function returns an error code
  2396. * No interrupts active, the IRQ has not been requested yet
  2397. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2398. */
  2399. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2400. void __iomem *regs, struct ci13xxx **_udc)
  2401. {
  2402. struct ci13xxx *udc;
  2403. int retval = 0;
  2404. trace(dev, "%p, %p, %p", dev, regs, driver->name);
  2405. if (dev == NULL || regs == NULL || driver == NULL ||
  2406. driver->name == NULL)
  2407. return -EINVAL;
  2408. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2409. if (udc == NULL)
  2410. return -ENOMEM;
  2411. spin_lock_init(&udc->lock);
  2412. udc->regs = regs;
  2413. udc->udc_driver = driver;
  2414. udc->gadget.ops = &usb_gadget_ops;
  2415. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2416. udc->gadget.max_speed = USB_SPEED_HIGH;
  2417. udc->gadget.is_otg = 0;
  2418. udc->gadget.name = driver->name;
  2419. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2420. dev_set_name(&udc->gadget.dev, "gadget");
  2421. udc->gadget.dev.dma_mask = dev->dma_mask;
  2422. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2423. udc->gadget.dev.parent = dev;
  2424. udc->gadget.dev.release = udc_release;
  2425. udc->dev = dev;
  2426. /* alloc resources */
  2427. udc->qh_pool = dma_pool_create("ci13xxx_qh", dev,
  2428. sizeof(struct ci13xxx_qh),
  2429. 64, CI13XXX_PAGE_SIZE);
  2430. if (udc->qh_pool == NULL) {
  2431. retval = -ENOMEM;
  2432. goto free_udc;
  2433. }
  2434. udc->td_pool = dma_pool_create("ci13xxx_td", dev,
  2435. sizeof(struct ci13xxx_td),
  2436. 64, CI13XXX_PAGE_SIZE);
  2437. if (udc->td_pool == NULL) {
  2438. retval = -ENOMEM;
  2439. goto free_qh_pool;
  2440. }
  2441. retval = hw_device_init(udc, regs, driver->capoffset);
  2442. if (retval < 0)
  2443. goto free_pools;
  2444. retval = init_eps(udc);
  2445. if (retval)
  2446. goto free_pools;
  2447. udc->gadget.ep0 = &udc->ep0in->ep;
  2448. udc->transceiver = usb_get_transceiver();
  2449. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2450. if (udc->transceiver == NULL) {
  2451. retval = -ENODEV;
  2452. goto free_pools;
  2453. }
  2454. }
  2455. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2456. retval = hw_device_reset(udc);
  2457. if (retval)
  2458. goto put_transceiver;
  2459. }
  2460. retval = device_register(&udc->gadget.dev);
  2461. if (retval) {
  2462. put_device(&udc->gadget.dev);
  2463. goto put_transceiver;
  2464. }
  2465. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2466. retval = dbg_create_files(&udc->gadget.dev);
  2467. #endif
  2468. if (retval)
  2469. goto unreg_device;
  2470. if (udc->transceiver) {
  2471. retval = otg_set_peripheral(udc->transceiver->otg,
  2472. &udc->gadget);
  2473. if (retval)
  2474. goto remove_dbg;
  2475. }
  2476. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2477. if (retval)
  2478. goto remove_trans;
  2479. pm_runtime_no_callbacks(&udc->gadget.dev);
  2480. pm_runtime_enable(&udc->gadget.dev);
  2481. *_udc = udc;
  2482. return retval;
  2483. remove_trans:
  2484. if (udc->transceiver) {
  2485. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2486. usb_put_transceiver(udc->transceiver);
  2487. }
  2488. dev_err(dev, "error = %i\n", retval);
  2489. remove_dbg:
  2490. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2491. dbg_remove_files(&udc->gadget.dev);
  2492. #endif
  2493. unreg_device:
  2494. device_unregister(&udc->gadget.dev);
  2495. put_transceiver:
  2496. if (udc->transceiver)
  2497. usb_put_transceiver(udc->transceiver);
  2498. free_pools:
  2499. dma_pool_destroy(udc->td_pool);
  2500. free_qh_pool:
  2501. dma_pool_destroy(udc->qh_pool);
  2502. free_udc:
  2503. kfree(udc);
  2504. *_udc = NULL;
  2505. return retval;
  2506. }
  2507. /**
  2508. * udc_remove: parent remove must call this to remove UDC
  2509. *
  2510. * No interrupts active, the IRQ has been released
  2511. */
  2512. static void udc_remove(struct ci13xxx *udc)
  2513. {
  2514. int i;
  2515. if (udc == NULL)
  2516. return;
  2517. usb_del_gadget_udc(&udc->gadget);
  2518. for (i = 0; i < udc->hw_ep_max; i++) {
  2519. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2520. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2521. }
  2522. dma_pool_destroy(udc->td_pool);
  2523. dma_pool_destroy(udc->qh_pool);
  2524. if (udc->transceiver) {
  2525. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2526. usb_put_transceiver(udc->transceiver);
  2527. }
  2528. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2529. dbg_remove_files(&udc->gadget.dev);
  2530. #endif
  2531. device_unregister(&udc->gadget.dev);
  2532. kfree(udc->hw_bank.regmap);
  2533. kfree(udc);
  2534. }
  2535. static int __devinit ci_udc_probe(struct platform_device *pdev)
  2536. {
  2537. struct device *dev = &pdev->dev;
  2538. struct ci13xxx_udc_driver *driver = dev->platform_data;
  2539. struct ci13xxx *udc;
  2540. struct resource *res;
  2541. void __iomem *base;
  2542. int ret;
  2543. if (!driver) {
  2544. dev_err(dev, "platform data missing\n");
  2545. return -ENODEV;
  2546. }
  2547. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2548. if (!res) {
  2549. dev_err(dev, "missing resource\n");
  2550. return -ENODEV;
  2551. }
  2552. base = devm_request_and_ioremap(dev, res);
  2553. if (!res) {
  2554. dev_err(dev, "can't request and ioremap resource\n");
  2555. return -ENOMEM;
  2556. }
  2557. ret = udc_probe(driver, dev, base, &udc);
  2558. if (ret)
  2559. return ret;
  2560. udc->irq = platform_get_irq(pdev, 0);
  2561. if (udc->irq < 0) {
  2562. dev_err(dev, "missing IRQ\n");
  2563. ret = -ENODEV;
  2564. goto out;
  2565. }
  2566. platform_set_drvdata(pdev, udc);
  2567. ret = request_irq(udc->irq, udc_irq, IRQF_SHARED, driver->name, udc);
  2568. out:
  2569. if (ret)
  2570. udc_remove(udc);
  2571. return ret;
  2572. }
  2573. static int __devexit ci_udc_remove(struct platform_device *pdev)
  2574. {
  2575. struct ci13xxx *udc = platform_get_drvdata(pdev);
  2576. free_irq(udc->irq, udc);
  2577. udc_remove(udc);
  2578. return 0;
  2579. }
  2580. static struct platform_driver ci_udc_driver = {
  2581. .probe = ci_udc_probe,
  2582. .remove = __devexit_p(ci_udc_remove),
  2583. .driver = {
  2584. .name = "ci_udc",
  2585. },
  2586. };
  2587. module_platform_driver(ci_udc_driver);
  2588. MODULE_ALIAS("platform:ci_udc");
  2589. MODULE_ALIAS("platform:ci13xxx");
  2590. MODULE_LICENSE("GPL v2");
  2591. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  2592. MODULE_DESCRIPTION("ChipIdea UDC Driver");