intel_drv.h 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723
  1. /*
  2. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright (c) 2007-2008 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23. * IN THE SOFTWARE.
  24. */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27. #include <linux/i2c.h>
  28. #include <drm/i915_drm.h>
  29. #include "i915_drv.h"
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_fb_helper.h>
  33. #include <drm/drm_dp_helper.h>
  34. /**
  35. * _wait_for - magic (register) wait macro
  36. *
  37. * Does the right thing for modeset paths when run under kdgb or similar atomic
  38. * contexts. Note that it's important that we check the condition again after
  39. * having timed out, since the timeout could be due to preemption or similar and
  40. * we've never had a chance to check the condition before the timeout.
  41. */
  42. #define _wait_for(COND, MS, W) ({ \
  43. unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
  44. int ret__ = 0; \
  45. while (!(COND)) { \
  46. if (time_after(jiffies, timeout__)) { \
  47. if (!(COND)) \
  48. ret__ = -ETIMEDOUT; \
  49. break; \
  50. } \
  51. if (W && drm_can_sleep()) { \
  52. msleep(W); \
  53. } else { \
  54. cpu_relax(); \
  55. } \
  56. } \
  57. ret__; \
  58. })
  59. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  60. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  61. #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  62. DIV_ROUND_UP((US), 1000), 0)
  63. #define KHz(x) (1000*x)
  64. #define MHz(x) KHz(1000*x)
  65. /*
  66. * Display related stuff
  67. */
  68. /* store information about an Ixxx DVO */
  69. /* The i830->i865 use multiple DVOs with multiple i2cs */
  70. /* the i915, i945 have a single sDVO i2c bus - which is different */
  71. #define MAX_OUTPUTS 6
  72. /* maximum connectors per crtcs in the mode set */
  73. #define INTELFB_CONN_LIMIT 4
  74. #define INTEL_I2C_BUS_DVO 1
  75. #define INTEL_I2C_BUS_SDVO 2
  76. /* these are outputs from the chip - integrated only
  77. external chips are via DVO or SDVO output */
  78. #define INTEL_OUTPUT_UNUSED 0
  79. #define INTEL_OUTPUT_ANALOG 1
  80. #define INTEL_OUTPUT_DVO 2
  81. #define INTEL_OUTPUT_SDVO 3
  82. #define INTEL_OUTPUT_LVDS 4
  83. #define INTEL_OUTPUT_TVOUT 5
  84. #define INTEL_OUTPUT_HDMI 6
  85. #define INTEL_OUTPUT_DISPLAYPORT 7
  86. #define INTEL_OUTPUT_EDP 8
  87. #define INTEL_OUTPUT_UNKNOWN 9
  88. #define INTEL_DVO_CHIP_NONE 0
  89. #define INTEL_DVO_CHIP_LVDS 1
  90. #define INTEL_DVO_CHIP_TMDS 2
  91. #define INTEL_DVO_CHIP_TVOUT 4
  92. struct intel_framebuffer {
  93. struct drm_framebuffer base;
  94. struct drm_i915_gem_object *obj;
  95. };
  96. struct intel_fbdev {
  97. struct drm_fb_helper helper;
  98. struct intel_framebuffer ifb;
  99. struct list_head fbdev_list;
  100. struct drm_display_mode *our_mode;
  101. };
  102. struct intel_encoder {
  103. struct drm_encoder base;
  104. /*
  105. * The new crtc this encoder will be driven from. Only differs from
  106. * base->crtc while a modeset is in progress.
  107. */
  108. struct intel_crtc *new_crtc;
  109. int type;
  110. bool needs_tv_clock;
  111. /*
  112. * Intel hw has only one MUX where encoders could be clone, hence a
  113. * simple flag is enough to compute the possible_clones mask.
  114. */
  115. bool cloneable;
  116. bool connectors_active;
  117. void (*hot_plug)(struct intel_encoder *);
  118. bool (*compute_config)(struct intel_encoder *,
  119. struct intel_crtc_config *);
  120. void (*pre_pll_enable)(struct intel_encoder *);
  121. void (*pre_enable)(struct intel_encoder *);
  122. void (*enable)(struct intel_encoder *);
  123. void (*mode_set)(struct intel_encoder *intel_encoder);
  124. void (*disable)(struct intel_encoder *);
  125. void (*post_disable)(struct intel_encoder *);
  126. /* Read out the current hw state of this connector, returning true if
  127. * the encoder is active. If the encoder is enabled it also set the pipe
  128. * it is connected to in the pipe parameter. */
  129. bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  130. int crtc_mask;
  131. enum hpd_pin hpd_pin;
  132. };
  133. struct intel_panel {
  134. struct drm_display_mode *fixed_mode;
  135. int fitting_mode;
  136. };
  137. struct intel_connector {
  138. struct drm_connector base;
  139. /*
  140. * The fixed encoder this connector is connected to.
  141. */
  142. struct intel_encoder *encoder;
  143. /*
  144. * The new encoder this connector will be driven. Only differs from
  145. * encoder while a modeset is in progress.
  146. */
  147. struct intel_encoder *new_encoder;
  148. /* Reads out the current hw, returning true if the connector is enabled
  149. * and active (i.e. dpms ON state). */
  150. bool (*get_hw_state)(struct intel_connector *);
  151. /* Panel info for eDP and LVDS */
  152. struct intel_panel panel;
  153. /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  154. struct edid *edid;
  155. };
  156. struct intel_crtc_config {
  157. struct drm_display_mode requested_mode;
  158. struct drm_display_mode adjusted_mode;
  159. /* This flag must be set by the encoder's compute_config callback if it
  160. * changes the crtc timings in the mode to prevent the crtc fixup from
  161. * overwriting them. Currently only lvds needs that. */
  162. bool timings_set;
  163. /* Whether to set up the PCH/FDI. Note that we never allow sharing
  164. * between pch encoders and cpu encoders. */
  165. bool has_pch_encoder;
  166. /*
  167. * Use reduced/limited/broadcast rbg range, compressing from the full
  168. * range fed into the crtcs.
  169. */
  170. bool limited_color_range;
  171. /* DP has a bunch of special case unfortunately, so mark the pipe
  172. * accordingly. */
  173. bool has_dp_encoder;
  174. bool dither;
  175. /* Controls for the clock computation, to override various stages. */
  176. bool clock_set;
  177. /* Settings for the intel dpll used on pretty much everything but
  178. * haswell. */
  179. struct dpll {
  180. unsigned n;
  181. unsigned m1, m2;
  182. unsigned p1, p2;
  183. } dpll;
  184. int pipe_bpp;
  185. struct intel_link_m_n dp_m_n;
  186. /**
  187. * This is currently used by DP and HDMI encoders since those can have a
  188. * target pixel clock != the port link clock (which is currently stored
  189. * in adjusted_mode->clock).
  190. */
  191. int pixel_target_clock;
  192. /* Used by SDVO (and if we ever fix it, HDMI). */
  193. unsigned pixel_multiplier;
  194. };
  195. struct intel_crtc {
  196. struct drm_crtc base;
  197. enum pipe pipe;
  198. enum plane plane;
  199. enum transcoder cpu_transcoder;
  200. u8 lut_r[256], lut_g[256], lut_b[256];
  201. /*
  202. * Whether the crtc and the connected output pipeline is active. Implies
  203. * that crtc->enabled is set, i.e. the current mode configuration has
  204. * some outputs connected to this crtc.
  205. */
  206. bool active;
  207. bool eld_vld;
  208. bool primary_disabled; /* is the crtc obscured by a plane? */
  209. bool lowfreq_avail;
  210. struct intel_overlay *overlay;
  211. struct intel_unpin_work *unpin_work;
  212. int fdi_lanes;
  213. atomic_t unpin_work_count;
  214. /* Display surface base address adjustement for pageflips. Note that on
  215. * gen4+ this only adjusts up to a tile, offsets within a tile are
  216. * handled in the hw itself (with the TILEOFF register). */
  217. unsigned long dspaddr_offset;
  218. struct drm_i915_gem_object *cursor_bo;
  219. uint32_t cursor_addr;
  220. int16_t cursor_x, cursor_y;
  221. int16_t cursor_width, cursor_height;
  222. bool cursor_visible;
  223. struct intel_crtc_config config;
  224. /* We can share PLLs across outputs if the timings match */
  225. struct intel_pch_pll *pch_pll;
  226. uint32_t ddi_pll_sel;
  227. /* reset counter value when the last flip was submitted */
  228. unsigned int reset_counter;
  229. };
  230. struct intel_plane {
  231. struct drm_plane base;
  232. int plane;
  233. enum pipe pipe;
  234. struct drm_i915_gem_object *obj;
  235. bool can_scale;
  236. int max_downscale;
  237. u32 lut_r[1024], lut_g[1024], lut_b[1024];
  238. int crtc_x, crtc_y;
  239. unsigned int crtc_w, crtc_h;
  240. uint32_t src_x, src_y;
  241. uint32_t src_w, src_h;
  242. void (*update_plane)(struct drm_plane *plane,
  243. struct drm_framebuffer *fb,
  244. struct drm_i915_gem_object *obj,
  245. int crtc_x, int crtc_y,
  246. unsigned int crtc_w, unsigned int crtc_h,
  247. uint32_t x, uint32_t y,
  248. uint32_t src_w, uint32_t src_h);
  249. void (*disable_plane)(struct drm_plane *plane);
  250. int (*update_colorkey)(struct drm_plane *plane,
  251. struct drm_intel_sprite_colorkey *key);
  252. void (*get_colorkey)(struct drm_plane *plane,
  253. struct drm_intel_sprite_colorkey *key);
  254. };
  255. struct intel_watermark_params {
  256. unsigned long fifo_size;
  257. unsigned long max_wm;
  258. unsigned long default_wm;
  259. unsigned long guard_size;
  260. unsigned long cacheline_size;
  261. };
  262. struct cxsr_latency {
  263. int is_desktop;
  264. int is_ddr3;
  265. unsigned long fsb_freq;
  266. unsigned long mem_freq;
  267. unsigned long display_sr;
  268. unsigned long display_hpll_disable;
  269. unsigned long cursor_sr;
  270. unsigned long cursor_hpll_disable;
  271. };
  272. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  273. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  274. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  275. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  276. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  277. #define DIP_HEADER_SIZE 5
  278. #define DIP_TYPE_AVI 0x82
  279. #define DIP_VERSION_AVI 0x2
  280. #define DIP_LEN_AVI 13
  281. #define DIP_AVI_PR_1 0
  282. #define DIP_AVI_PR_2 1
  283. #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
  284. #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
  285. #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
  286. #define DIP_TYPE_SPD 0x83
  287. #define DIP_VERSION_SPD 0x1
  288. #define DIP_LEN_SPD 25
  289. #define DIP_SPD_UNKNOWN 0
  290. #define DIP_SPD_DSTB 0x1
  291. #define DIP_SPD_DVDP 0x2
  292. #define DIP_SPD_DVHS 0x3
  293. #define DIP_SPD_HDDVR 0x4
  294. #define DIP_SPD_DVC 0x5
  295. #define DIP_SPD_DSC 0x6
  296. #define DIP_SPD_VCD 0x7
  297. #define DIP_SPD_GAME 0x8
  298. #define DIP_SPD_PC 0x9
  299. #define DIP_SPD_BD 0xa
  300. #define DIP_SPD_SCD 0xb
  301. struct dip_infoframe {
  302. uint8_t type; /* HB0 */
  303. uint8_t ver; /* HB1 */
  304. uint8_t len; /* HB2 - body len, not including checksum */
  305. uint8_t ecc; /* Header ECC */
  306. uint8_t checksum; /* PB0 */
  307. union {
  308. struct {
  309. /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
  310. uint8_t Y_A_B_S;
  311. /* PB2 - C 7:6, M 5:4, R 3:0 */
  312. uint8_t C_M_R;
  313. /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
  314. uint8_t ITC_EC_Q_SC;
  315. /* PB4 - VIC 6:0 */
  316. uint8_t VIC;
  317. /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
  318. uint8_t YQ_CN_PR;
  319. /* PB6 to PB13 */
  320. uint16_t top_bar_end;
  321. uint16_t bottom_bar_start;
  322. uint16_t left_bar_end;
  323. uint16_t right_bar_start;
  324. } __attribute__ ((packed)) avi;
  325. struct {
  326. uint8_t vn[8];
  327. uint8_t pd[16];
  328. uint8_t sdi;
  329. } __attribute__ ((packed)) spd;
  330. uint8_t payload[27];
  331. } __attribute__ ((packed)) body;
  332. } __attribute__((packed));
  333. struct intel_hdmi {
  334. u32 hdmi_reg;
  335. int ddc_bus;
  336. uint32_t color_range;
  337. bool color_range_auto;
  338. bool has_hdmi_sink;
  339. bool has_audio;
  340. enum hdmi_force_audio force_audio;
  341. bool rgb_quant_range_selectable;
  342. void (*write_infoframe)(struct drm_encoder *encoder,
  343. struct dip_infoframe *frame);
  344. void (*set_infoframes)(struct drm_encoder *encoder,
  345. struct drm_display_mode *adjusted_mode);
  346. };
  347. #define DP_MAX_DOWNSTREAM_PORTS 0x10
  348. #define DP_LINK_CONFIGURATION_SIZE 9
  349. struct intel_dp {
  350. uint32_t output_reg;
  351. uint32_t aux_ch_ctl_reg;
  352. uint32_t DP;
  353. uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
  354. bool has_audio;
  355. enum hdmi_force_audio force_audio;
  356. uint32_t color_range;
  357. bool color_range_auto;
  358. uint8_t link_bw;
  359. uint8_t lane_count;
  360. uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  361. uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  362. struct i2c_adapter adapter;
  363. struct i2c_algo_dp_aux_data algo;
  364. bool is_pch_edp;
  365. uint8_t train_set[4];
  366. int panel_power_up_delay;
  367. int panel_power_down_delay;
  368. int panel_power_cycle_delay;
  369. int backlight_on_delay;
  370. int backlight_off_delay;
  371. struct delayed_work panel_vdd_work;
  372. bool want_panel_vdd;
  373. struct intel_connector *attached_connector;
  374. };
  375. struct intel_digital_port {
  376. struct intel_encoder base;
  377. enum port port;
  378. u32 port_reversal;
  379. struct intel_dp dp;
  380. struct intel_hdmi hdmi;
  381. };
  382. static inline struct drm_crtc *
  383. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  384. {
  385. struct drm_i915_private *dev_priv = dev->dev_private;
  386. return dev_priv->pipe_to_crtc_mapping[pipe];
  387. }
  388. static inline struct drm_crtc *
  389. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  390. {
  391. struct drm_i915_private *dev_priv = dev->dev_private;
  392. return dev_priv->plane_to_crtc_mapping[plane];
  393. }
  394. struct intel_unpin_work {
  395. struct work_struct work;
  396. struct drm_crtc *crtc;
  397. struct drm_i915_gem_object *old_fb_obj;
  398. struct drm_i915_gem_object *pending_flip_obj;
  399. struct drm_pending_vblank_event *event;
  400. atomic_t pending;
  401. #define INTEL_FLIP_INACTIVE 0
  402. #define INTEL_FLIP_PENDING 1
  403. #define INTEL_FLIP_COMPLETE 2
  404. bool enable_stall_check;
  405. };
  406. struct intel_fbc_work {
  407. struct delayed_work work;
  408. struct drm_crtc *crtc;
  409. struct drm_framebuffer *fb;
  410. int interval;
  411. };
  412. int intel_pch_rawclk(struct drm_device *dev);
  413. int intel_connector_update_modes(struct drm_connector *connector,
  414. struct edid *edid);
  415. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  416. extern void intel_attach_force_audio_property(struct drm_connector *connector);
  417. extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  418. extern void intel_crt_init(struct drm_device *dev);
  419. extern void intel_hdmi_init(struct drm_device *dev,
  420. int hdmi_reg, enum port port);
  421. extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  422. struct intel_connector *intel_connector);
  423. extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  424. extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  425. struct intel_crtc_config *pipe_config);
  426. extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
  427. extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
  428. bool is_sdvob);
  429. extern void intel_dvo_init(struct drm_device *dev);
  430. extern void intel_tv_init(struct drm_device *dev);
  431. extern void intel_mark_busy(struct drm_device *dev);
  432. extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
  433. extern void intel_mark_idle(struct drm_device *dev);
  434. extern bool intel_lvds_init(struct drm_device *dev);
  435. extern bool intel_is_dual_link_lvds(struct drm_device *dev);
  436. extern void intel_dp_init(struct drm_device *dev, int output_reg,
  437. enum port port);
  438. extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  439. struct intel_connector *intel_connector);
  440. extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
  441. extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
  442. extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  443. extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  444. extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  445. extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
  446. extern bool intel_dp_compute_config(struct intel_encoder *encoder,
  447. struct intel_crtc_config *pipe_config);
  448. extern bool intel_dpd_is_edp(struct drm_device *dev);
  449. extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
  450. extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
  451. extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
  452. extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
  453. extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  454. extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  455. extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
  456. extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
  457. extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  458. enum plane plane);
  459. /* intel_panel.c */
  460. extern int intel_panel_init(struct intel_panel *panel,
  461. struct drm_display_mode *fixed_mode);
  462. extern void intel_panel_fini(struct intel_panel *panel);
  463. extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
  464. struct drm_display_mode *adjusted_mode);
  465. extern void intel_pch_panel_fitting(struct drm_device *dev,
  466. int fitting_mode,
  467. const struct drm_display_mode *mode,
  468. struct drm_display_mode *adjusted_mode);
  469. extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
  470. extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
  471. extern int intel_panel_setup_backlight(struct drm_connector *connector);
  472. extern void intel_panel_enable_backlight(struct drm_device *dev,
  473. enum pipe pipe);
  474. extern void intel_panel_disable_backlight(struct drm_device *dev);
  475. extern void intel_panel_destroy_backlight(struct drm_device *dev);
  476. extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  477. struct intel_set_config {
  478. struct drm_encoder **save_connector_encoders;
  479. struct drm_crtc **save_encoder_crtcs;
  480. bool fb_changed;
  481. bool mode_changed;
  482. };
  483. extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  484. int x, int y, struct drm_framebuffer *old_fb);
  485. extern void intel_modeset_disable(struct drm_device *dev);
  486. extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
  487. extern void intel_crtc_load_lut(struct drm_crtc *crtc);
  488. extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
  489. extern void intel_encoder_destroy(struct drm_encoder *encoder);
  490. extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
  491. extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
  492. extern void intel_connector_dpms(struct drm_connector *, int mode);
  493. extern bool intel_connector_get_hw_state(struct intel_connector *connector);
  494. extern void intel_modeset_check_state(struct drm_device *dev);
  495. extern void intel_plane_restore(struct drm_plane *plane);
  496. static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
  497. {
  498. return to_intel_connector(connector)->encoder;
  499. }
  500. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  501. {
  502. struct intel_digital_port *intel_dig_port =
  503. container_of(encoder, struct intel_digital_port, base.base);
  504. return &intel_dig_port->dp;
  505. }
  506. static inline struct intel_digital_port *
  507. enc_to_dig_port(struct drm_encoder *encoder)
  508. {
  509. return container_of(encoder, struct intel_digital_port, base.base);
  510. }
  511. static inline struct intel_digital_port *
  512. dp_to_dig_port(struct intel_dp *intel_dp)
  513. {
  514. return container_of(intel_dp, struct intel_digital_port, dp);
  515. }
  516. static inline struct intel_digital_port *
  517. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  518. {
  519. return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  520. }
  521. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  522. struct intel_digital_port *port);
  523. extern void intel_connector_attach_encoder(struct intel_connector *connector,
  524. struct intel_encoder *encoder);
  525. extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  526. extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  527. struct drm_crtc *crtc);
  528. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  529. struct drm_file *file_priv);
  530. extern enum transcoder
  531. intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  532. enum pipe pipe);
  533. extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
  534. extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
  535. extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  536. struct intel_load_detect_pipe {
  537. struct drm_framebuffer *release_fb;
  538. bool load_detect_temp;
  539. int dpms_mode;
  540. };
  541. extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
  542. struct drm_display_mode *mode,
  543. struct intel_load_detect_pipe *old);
  544. extern void intel_release_load_detect_pipe(struct drm_connector *connector,
  545. struct intel_load_detect_pipe *old);
  546. extern void intelfb_restore(void);
  547. extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  548. u16 blue, int regno);
  549. extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  550. u16 *blue, int regno);
  551. extern void intel_enable_clock_gating(struct drm_device *dev);
  552. extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
  553. struct drm_i915_gem_object *obj,
  554. struct intel_ring_buffer *pipelined);
  555. extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
  556. extern int intel_framebuffer_init(struct drm_device *dev,
  557. struct intel_framebuffer *ifb,
  558. struct drm_mode_fb_cmd2 *mode_cmd,
  559. struct drm_i915_gem_object *obj);
  560. extern int intel_fbdev_init(struct drm_device *dev);
  561. extern void intel_fbdev_initial_config(struct drm_device *dev);
  562. extern void intel_fbdev_fini(struct drm_device *dev);
  563. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
  564. extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
  565. extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
  566. extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  567. extern void intel_setup_overlay(struct drm_device *dev);
  568. extern void intel_cleanup_overlay(struct drm_device *dev);
  569. extern int intel_overlay_switch_off(struct intel_overlay *overlay);
  570. extern int intel_overlay_put_image(struct drm_device *dev, void *data,
  571. struct drm_file *file_priv);
  572. extern int intel_overlay_attrs(struct drm_device *dev, void *data,
  573. struct drm_file *file_priv);
  574. extern void intel_fb_output_poll_changed(struct drm_device *dev);
  575. extern void intel_fb_restore_mode(struct drm_device *dev);
  576. extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  577. bool state);
  578. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  579. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  580. extern void intel_init_clock_gating(struct drm_device *dev);
  581. extern void intel_write_eld(struct drm_encoder *encoder,
  582. struct drm_display_mode *mode);
  583. extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
  584. extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  585. struct intel_link_m_n *m_n);
  586. extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  587. struct intel_link_m_n *m_n);
  588. extern void intel_prepare_ddi(struct drm_device *dev);
  589. extern void hsw_fdi_link_train(struct drm_crtc *crtc);
  590. extern void intel_ddi_init(struct drm_device *dev, enum port port);
  591. /* For use by IVB LP watermark workaround in intel_sprite.c */
  592. extern void intel_update_watermarks(struct drm_device *dev);
  593. extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  594. uint32_t sprite_width,
  595. int pixel_size);
  596. extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
  597. struct drm_display_mode *mode);
  598. extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  599. unsigned int tiling_mode,
  600. unsigned int bpp,
  601. unsigned int pitch);
  602. extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  603. struct drm_file *file_priv);
  604. extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  605. struct drm_file *file_priv);
  606. extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
  607. /* Power-related functions, located in intel_pm.c */
  608. extern void intel_init_pm(struct drm_device *dev);
  609. /* FBC */
  610. extern bool intel_fbc_enabled(struct drm_device *dev);
  611. extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
  612. extern void intel_update_fbc(struct drm_device *dev);
  613. /* IPS */
  614. extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  615. extern void intel_gpu_ips_teardown(void);
  616. extern void intel_init_power_well(struct drm_device *dev);
  617. extern void intel_set_power_well(struct drm_device *dev, bool enable);
  618. extern void intel_enable_gt_powersave(struct drm_device *dev);
  619. extern void intel_disable_gt_powersave(struct drm_device *dev);
  620. extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
  621. extern void ironlake_teardown_rc6(struct drm_device *dev);
  622. extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
  623. enum pipe *pipe);
  624. extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
  625. extern void intel_ddi_pll_init(struct drm_device *dev);
  626. extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
  627. extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  628. enum transcoder cpu_transcoder);
  629. extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  630. extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  631. extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
  632. extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
  633. extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
  634. extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  635. extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  636. extern bool
  637. intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  638. extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  639. extern void intel_display_handle_reset(struct drm_device *dev);
  640. #endif /* __INTEL_DRV_H__ */