intel_dp.c 82 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <linux/export.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_edid.h>
  34. #include "intel_drv.h"
  35. #include <drm/i915_drm.h>
  36. #include "i915_drv.h"
  37. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  38. /**
  39. * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  40. * @intel_dp: DP struct
  41. *
  42. * If a CPU or PCH DP output is attached to an eDP panel, this function
  43. * will return true, and false otherwise.
  44. */
  45. static bool is_edp(struct intel_dp *intel_dp)
  46. {
  47. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  48. return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  49. }
  50. /**
  51. * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  52. * @intel_dp: DP struct
  53. *
  54. * Returns true if the given DP struct corresponds to a PCH DP port attached
  55. * to an eDP panel, false otherwise. Helpful for determining whether we
  56. * may need FDI resources for a given DP output or not.
  57. */
  58. static bool is_pch_edp(struct intel_dp *intel_dp)
  59. {
  60. return intel_dp->is_pch_edp;
  61. }
  62. /**
  63. * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  64. * @intel_dp: DP struct
  65. *
  66. * Returns true if the given DP struct corresponds to a CPU eDP port.
  67. */
  68. static bool is_cpu_edp(struct intel_dp *intel_dp)
  69. {
  70. return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  71. }
  72. static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  73. {
  74. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  75. return intel_dig_port->base.base.dev;
  76. }
  77. static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  78. {
  79. return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  80. }
  81. /**
  82. * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  83. * @encoder: DRM encoder
  84. *
  85. * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
  86. * by intel_display.c.
  87. */
  88. bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  89. {
  90. struct intel_dp *intel_dp;
  91. if (!encoder)
  92. return false;
  93. intel_dp = enc_to_intel_dp(encoder);
  94. return is_pch_edp(intel_dp);
  95. }
  96. static void intel_dp_link_down(struct intel_dp *intel_dp);
  97. static int
  98. intel_dp_max_link_bw(struct intel_dp *intel_dp)
  99. {
  100. int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  101. switch (max_link_bw) {
  102. case DP_LINK_BW_1_62:
  103. case DP_LINK_BW_2_7:
  104. break;
  105. default:
  106. max_link_bw = DP_LINK_BW_1_62;
  107. break;
  108. }
  109. return max_link_bw;
  110. }
  111. /*
  112. * The units on the numbers in the next two are... bizarre. Examples will
  113. * make it clearer; this one parallels an example in the eDP spec.
  114. *
  115. * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  116. *
  117. * 270000 * 1 * 8 / 10 == 216000
  118. *
  119. * The actual data capacity of that configuration is 2.16Gbit/s, so the
  120. * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
  121. * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  122. * 119000. At 18bpp that's 2142000 kilobits per second.
  123. *
  124. * Thus the strange-looking division by 10 in intel_dp_link_required, to
  125. * get the result in decakilobits instead of kilobits.
  126. */
  127. static int
  128. intel_dp_link_required(int pixel_clock, int bpp)
  129. {
  130. return (pixel_clock * bpp + 9) / 10;
  131. }
  132. static int
  133. intel_dp_max_data_rate(int max_link_clock, int max_lanes)
  134. {
  135. return (max_link_clock * max_lanes * 8) / 10;
  136. }
  137. static int
  138. intel_dp_mode_valid(struct drm_connector *connector,
  139. struct drm_display_mode *mode)
  140. {
  141. struct intel_dp *intel_dp = intel_attached_dp(connector);
  142. struct intel_connector *intel_connector = to_intel_connector(connector);
  143. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  144. int target_clock = mode->clock;
  145. int max_rate, mode_rate, max_lanes, max_link_clock;
  146. if (is_edp(intel_dp) && fixed_mode) {
  147. if (mode->hdisplay > fixed_mode->hdisplay)
  148. return MODE_PANEL;
  149. if (mode->vdisplay > fixed_mode->vdisplay)
  150. return MODE_PANEL;
  151. target_clock = fixed_mode->clock;
  152. }
  153. max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
  154. max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
  155. max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
  156. mode_rate = intel_dp_link_required(target_clock, 18);
  157. if (mode_rate > max_rate)
  158. return MODE_CLOCK_HIGH;
  159. if (mode->clock < 10000)
  160. return MODE_CLOCK_LOW;
  161. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  162. return MODE_H_ILLEGAL;
  163. return MODE_OK;
  164. }
  165. static uint32_t
  166. pack_aux(uint8_t *src, int src_bytes)
  167. {
  168. int i;
  169. uint32_t v = 0;
  170. if (src_bytes > 4)
  171. src_bytes = 4;
  172. for (i = 0; i < src_bytes; i++)
  173. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  174. return v;
  175. }
  176. static void
  177. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  178. {
  179. int i;
  180. if (dst_bytes > 4)
  181. dst_bytes = 4;
  182. for (i = 0; i < dst_bytes; i++)
  183. dst[i] = src >> ((3-i) * 8);
  184. }
  185. /* hrawclock is 1/4 the FSB frequency */
  186. static int
  187. intel_hrawclk(struct drm_device *dev)
  188. {
  189. struct drm_i915_private *dev_priv = dev->dev_private;
  190. uint32_t clkcfg;
  191. /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
  192. if (IS_VALLEYVIEW(dev))
  193. return 200;
  194. clkcfg = I915_READ(CLKCFG);
  195. switch (clkcfg & CLKCFG_FSB_MASK) {
  196. case CLKCFG_FSB_400:
  197. return 100;
  198. case CLKCFG_FSB_533:
  199. return 133;
  200. case CLKCFG_FSB_667:
  201. return 166;
  202. case CLKCFG_FSB_800:
  203. return 200;
  204. case CLKCFG_FSB_1067:
  205. return 266;
  206. case CLKCFG_FSB_1333:
  207. return 333;
  208. /* these two are just a guess; one of them might be right */
  209. case CLKCFG_FSB_1600:
  210. case CLKCFG_FSB_1600_ALT:
  211. return 400;
  212. default:
  213. return 133;
  214. }
  215. }
  216. static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
  217. {
  218. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  219. struct drm_i915_private *dev_priv = dev->dev_private;
  220. u32 pp_stat_reg;
  221. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  222. return (I915_READ(pp_stat_reg) & PP_ON) != 0;
  223. }
  224. static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
  225. {
  226. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  227. struct drm_i915_private *dev_priv = dev->dev_private;
  228. u32 pp_ctrl_reg;
  229. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  230. return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
  231. }
  232. static void
  233. intel_dp_check_edp(struct intel_dp *intel_dp)
  234. {
  235. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  236. struct drm_i915_private *dev_priv = dev->dev_private;
  237. u32 pp_stat_reg, pp_ctrl_reg;
  238. if (!is_edp(intel_dp))
  239. return;
  240. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  241. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  242. if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
  243. WARN(1, "eDP powered off while attempting aux channel communication.\n");
  244. DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
  245. I915_READ(pp_stat_reg),
  246. I915_READ(pp_ctrl_reg));
  247. }
  248. }
  249. static uint32_t
  250. intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
  251. {
  252. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  253. struct drm_device *dev = intel_dig_port->base.base.dev;
  254. struct drm_i915_private *dev_priv = dev->dev_private;
  255. uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
  256. uint32_t status;
  257. bool done;
  258. #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  259. if (has_aux_irq)
  260. done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  261. msecs_to_jiffies(10));
  262. else
  263. done = wait_for_atomic(C, 10) == 0;
  264. if (!done)
  265. DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
  266. has_aux_irq);
  267. #undef C
  268. return status;
  269. }
  270. static int
  271. intel_dp_aux_ch(struct intel_dp *intel_dp,
  272. uint8_t *send, int send_bytes,
  273. uint8_t *recv, int recv_size)
  274. {
  275. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  276. struct drm_device *dev = intel_dig_port->base.base.dev;
  277. struct drm_i915_private *dev_priv = dev->dev_private;
  278. uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
  279. uint32_t ch_data = ch_ctl + 4;
  280. int i, ret, recv_bytes;
  281. uint32_t status;
  282. uint32_t aux_clock_divider;
  283. int try, precharge;
  284. bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
  285. /* dp aux is extremely sensitive to irq latency, hence request the
  286. * lowest possible wakeup latency and so prevent the cpu from going into
  287. * deep sleep states.
  288. */
  289. pm_qos_update_request(&dev_priv->pm_qos, 0);
  290. intel_dp_check_edp(intel_dp);
  291. /* The clock divider is based off the hrawclk,
  292. * and would like to run at 2MHz. So, take the
  293. * hrawclk value and divide by 2 and use that
  294. *
  295. * Note that PCH attached eDP panels should use a 125MHz input
  296. * clock divider.
  297. */
  298. if (is_cpu_edp(intel_dp)) {
  299. if (HAS_DDI(dev))
  300. aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
  301. else if (IS_VALLEYVIEW(dev))
  302. aux_clock_divider = 100;
  303. else if (IS_GEN6(dev) || IS_GEN7(dev))
  304. aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
  305. else
  306. aux_clock_divider = 225; /* eDP input clock at 450Mhz */
  307. } else if (HAS_PCH_SPLIT(dev))
  308. aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
  309. else
  310. aux_clock_divider = intel_hrawclk(dev) / 2;
  311. if (IS_GEN6(dev))
  312. precharge = 3;
  313. else
  314. precharge = 5;
  315. /* Try to wait for any previous AUX channel activity */
  316. for (try = 0; try < 3; try++) {
  317. status = I915_READ_NOTRACE(ch_ctl);
  318. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  319. break;
  320. msleep(1);
  321. }
  322. if (try == 3) {
  323. WARN(1, "dp_aux_ch not started status 0x%08x\n",
  324. I915_READ(ch_ctl));
  325. ret = -EBUSY;
  326. goto out;
  327. }
  328. /* Must try at least 3 times according to DP spec */
  329. for (try = 0; try < 5; try++) {
  330. /* Load the send data into the aux channel data registers */
  331. for (i = 0; i < send_bytes; i += 4)
  332. I915_WRITE(ch_data + i,
  333. pack_aux(send + i, send_bytes - i));
  334. /* Send the command and wait for it to complete */
  335. I915_WRITE(ch_ctl,
  336. DP_AUX_CH_CTL_SEND_BUSY |
  337. (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
  338. DP_AUX_CH_CTL_TIME_OUT_400us |
  339. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  340. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  341. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
  342. DP_AUX_CH_CTL_DONE |
  343. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  344. DP_AUX_CH_CTL_RECEIVE_ERROR);
  345. status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
  346. /* Clear done status and any errors */
  347. I915_WRITE(ch_ctl,
  348. status |
  349. DP_AUX_CH_CTL_DONE |
  350. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  351. DP_AUX_CH_CTL_RECEIVE_ERROR);
  352. if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
  353. DP_AUX_CH_CTL_RECEIVE_ERROR))
  354. continue;
  355. if (status & DP_AUX_CH_CTL_DONE)
  356. break;
  357. }
  358. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  359. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  360. ret = -EBUSY;
  361. goto out;
  362. }
  363. /* Check for timeout or receive error.
  364. * Timeouts occur when the sink is not connected
  365. */
  366. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  367. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  368. ret = -EIO;
  369. goto out;
  370. }
  371. /* Timeouts occur when the device isn't connected, so they're
  372. * "normal" -- don't fill the kernel log with these */
  373. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  374. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  375. ret = -ETIMEDOUT;
  376. goto out;
  377. }
  378. /* Unload any bytes sent back from the other side */
  379. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  380. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  381. if (recv_bytes > recv_size)
  382. recv_bytes = recv_size;
  383. for (i = 0; i < recv_bytes; i += 4)
  384. unpack_aux(I915_READ(ch_data + i),
  385. recv + i, recv_bytes - i);
  386. ret = recv_bytes;
  387. out:
  388. pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
  389. return ret;
  390. }
  391. /* Write data to the aux channel in native mode */
  392. static int
  393. intel_dp_aux_native_write(struct intel_dp *intel_dp,
  394. uint16_t address, uint8_t *send, int send_bytes)
  395. {
  396. int ret;
  397. uint8_t msg[20];
  398. int msg_bytes;
  399. uint8_t ack;
  400. intel_dp_check_edp(intel_dp);
  401. if (send_bytes > 16)
  402. return -1;
  403. msg[0] = AUX_NATIVE_WRITE << 4;
  404. msg[1] = address >> 8;
  405. msg[2] = address & 0xff;
  406. msg[3] = send_bytes - 1;
  407. memcpy(&msg[4], send, send_bytes);
  408. msg_bytes = send_bytes + 4;
  409. for (;;) {
  410. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
  411. if (ret < 0)
  412. return ret;
  413. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  414. break;
  415. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  416. udelay(100);
  417. else
  418. return -EIO;
  419. }
  420. return send_bytes;
  421. }
  422. /* Write a single byte to the aux channel in native mode */
  423. static int
  424. intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
  425. uint16_t address, uint8_t byte)
  426. {
  427. return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
  428. }
  429. /* read bytes from a native aux channel */
  430. static int
  431. intel_dp_aux_native_read(struct intel_dp *intel_dp,
  432. uint16_t address, uint8_t *recv, int recv_bytes)
  433. {
  434. uint8_t msg[4];
  435. int msg_bytes;
  436. uint8_t reply[20];
  437. int reply_bytes;
  438. uint8_t ack;
  439. int ret;
  440. intel_dp_check_edp(intel_dp);
  441. msg[0] = AUX_NATIVE_READ << 4;
  442. msg[1] = address >> 8;
  443. msg[2] = address & 0xff;
  444. msg[3] = recv_bytes - 1;
  445. msg_bytes = 4;
  446. reply_bytes = recv_bytes + 1;
  447. for (;;) {
  448. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
  449. reply, reply_bytes);
  450. if (ret == 0)
  451. return -EPROTO;
  452. if (ret < 0)
  453. return ret;
  454. ack = reply[0];
  455. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
  456. memcpy(recv, reply + 1, ret - 1);
  457. return ret - 1;
  458. }
  459. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  460. udelay(100);
  461. else
  462. return -EIO;
  463. }
  464. }
  465. static int
  466. intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  467. uint8_t write_byte, uint8_t *read_byte)
  468. {
  469. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  470. struct intel_dp *intel_dp = container_of(adapter,
  471. struct intel_dp,
  472. adapter);
  473. uint16_t address = algo_data->address;
  474. uint8_t msg[5];
  475. uint8_t reply[2];
  476. unsigned retry;
  477. int msg_bytes;
  478. int reply_bytes;
  479. int ret;
  480. intel_dp_check_edp(intel_dp);
  481. /* Set up the command byte */
  482. if (mode & MODE_I2C_READ)
  483. msg[0] = AUX_I2C_READ << 4;
  484. else
  485. msg[0] = AUX_I2C_WRITE << 4;
  486. if (!(mode & MODE_I2C_STOP))
  487. msg[0] |= AUX_I2C_MOT << 4;
  488. msg[1] = address >> 8;
  489. msg[2] = address;
  490. switch (mode) {
  491. case MODE_I2C_WRITE:
  492. msg[3] = 0;
  493. msg[4] = write_byte;
  494. msg_bytes = 5;
  495. reply_bytes = 1;
  496. break;
  497. case MODE_I2C_READ:
  498. msg[3] = 0;
  499. msg_bytes = 4;
  500. reply_bytes = 2;
  501. break;
  502. default:
  503. msg_bytes = 3;
  504. reply_bytes = 1;
  505. break;
  506. }
  507. for (retry = 0; retry < 5; retry++) {
  508. ret = intel_dp_aux_ch(intel_dp,
  509. msg, msg_bytes,
  510. reply, reply_bytes);
  511. if (ret < 0) {
  512. DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  513. return ret;
  514. }
  515. switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
  516. case AUX_NATIVE_REPLY_ACK:
  517. /* I2C-over-AUX Reply field is only valid
  518. * when paired with AUX ACK.
  519. */
  520. break;
  521. case AUX_NATIVE_REPLY_NACK:
  522. DRM_DEBUG_KMS("aux_ch native nack\n");
  523. return -EREMOTEIO;
  524. case AUX_NATIVE_REPLY_DEFER:
  525. udelay(100);
  526. continue;
  527. default:
  528. DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
  529. reply[0]);
  530. return -EREMOTEIO;
  531. }
  532. switch (reply[0] & AUX_I2C_REPLY_MASK) {
  533. case AUX_I2C_REPLY_ACK:
  534. if (mode == MODE_I2C_READ) {
  535. *read_byte = reply[1];
  536. }
  537. return reply_bytes - 1;
  538. case AUX_I2C_REPLY_NACK:
  539. DRM_DEBUG_KMS("aux_i2c nack\n");
  540. return -EREMOTEIO;
  541. case AUX_I2C_REPLY_DEFER:
  542. DRM_DEBUG_KMS("aux_i2c defer\n");
  543. udelay(100);
  544. break;
  545. default:
  546. DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
  547. return -EREMOTEIO;
  548. }
  549. }
  550. DRM_ERROR("too many retries, giving up\n");
  551. return -EREMOTEIO;
  552. }
  553. static int
  554. intel_dp_i2c_init(struct intel_dp *intel_dp,
  555. struct intel_connector *intel_connector, const char *name)
  556. {
  557. int ret;
  558. DRM_DEBUG_KMS("i2c_init %s\n", name);
  559. intel_dp->algo.running = false;
  560. intel_dp->algo.address = 0;
  561. intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
  562. memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
  563. intel_dp->adapter.owner = THIS_MODULE;
  564. intel_dp->adapter.class = I2C_CLASS_DDC;
  565. strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
  566. intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
  567. intel_dp->adapter.algo_data = &intel_dp->algo;
  568. intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
  569. ironlake_edp_panel_vdd_on(intel_dp);
  570. ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
  571. ironlake_edp_panel_vdd_off(intel_dp, false);
  572. return ret;
  573. }
  574. bool
  575. intel_dp_compute_config(struct intel_encoder *encoder,
  576. struct intel_crtc_config *pipe_config)
  577. {
  578. struct drm_device *dev = encoder->base.dev;
  579. struct drm_i915_private *dev_priv = dev->dev_private;
  580. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  581. struct drm_display_mode *mode = &pipe_config->requested_mode;
  582. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  583. struct intel_connector *intel_connector = intel_dp->attached_connector;
  584. int lane_count, clock;
  585. int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
  586. int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
  587. int bpp, mode_rate;
  588. static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
  589. int target_clock, link_avail, link_clock;
  590. if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
  591. pipe_config->has_pch_encoder = true;
  592. pipe_config->has_dp_encoder = true;
  593. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  594. intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
  595. adjusted_mode);
  596. intel_pch_panel_fitting(dev,
  597. intel_connector->panel.fitting_mode,
  598. mode, adjusted_mode);
  599. }
  600. /* We need to take the panel's fixed mode into account. */
  601. target_clock = adjusted_mode->clock;
  602. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  603. return false;
  604. DRM_DEBUG_KMS("DP link computation with max lane count %i "
  605. "max bw %02x pixel clock %iKHz\n",
  606. max_lane_count, bws[max_clock], adjusted_mode->clock);
  607. /* Walk through all bpp values. Luckily they're all nicely spaced with 2
  608. * bpc in between. */
  609. bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
  610. for (; bpp >= 6*3; bpp -= 2*3) {
  611. mode_rate = intel_dp_link_required(target_clock, bpp);
  612. for (clock = 0; clock <= max_clock; clock++) {
  613. for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
  614. link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
  615. link_avail = intel_dp_max_data_rate(link_clock,
  616. lane_count);
  617. if (mode_rate <= link_avail) {
  618. goto found;
  619. }
  620. }
  621. }
  622. }
  623. return false;
  624. found:
  625. if (intel_dp->color_range_auto) {
  626. /*
  627. * See:
  628. * CEA-861-E - 5.1 Default Encoding Parameters
  629. * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
  630. */
  631. if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
  632. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  633. else
  634. intel_dp->color_range = 0;
  635. }
  636. if (intel_dp->color_range)
  637. pipe_config->limited_color_range = true;
  638. intel_dp->link_bw = bws[clock];
  639. intel_dp->lane_count = lane_count;
  640. adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
  641. pipe_config->pixel_target_clock = target_clock;
  642. DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
  643. intel_dp->link_bw, intel_dp->lane_count,
  644. adjusted_mode->clock, bpp);
  645. DRM_DEBUG_KMS("DP link bw required %i available %i\n",
  646. mode_rate, link_avail);
  647. intel_link_compute_m_n(bpp, lane_count,
  648. target_clock, adjusted_mode->clock,
  649. &pipe_config->dp_m_n);
  650. /*
  651. * XXX: We have a strange regression where using the vbt edp bpp value
  652. * for the link bw computation results in black screens, the panel only
  653. * works when we do the computation at the usual 24bpp (but still
  654. * requires us to use 18bpp). Until that's fully debugged, stay
  655. * bug-for-bug compatible with the old code.
  656. */
  657. if (is_edp(intel_dp) && dev_priv->edp.bpp) {
  658. DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
  659. bpp, dev_priv->edp.bpp);
  660. bpp = min_t(int, bpp, dev_priv->edp.bpp);
  661. }
  662. pipe_config->pipe_bpp = bpp;
  663. return true;
  664. }
  665. void intel_dp_init_link_config(struct intel_dp *intel_dp)
  666. {
  667. memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
  668. intel_dp->link_configuration[0] = intel_dp->link_bw;
  669. intel_dp->link_configuration[1] = intel_dp->lane_count;
  670. intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
  671. /*
  672. * Check for DPCD version > 1.1 and enhanced framing support
  673. */
  674. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  675. (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
  676. intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  677. }
  678. }
  679. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  680. {
  681. struct drm_device *dev = crtc->dev;
  682. struct drm_i915_private *dev_priv = dev->dev_private;
  683. u32 dpa_ctl;
  684. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  685. dpa_ctl = I915_READ(DP_A);
  686. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  687. if (clock < 200000) {
  688. /* For a long time we've carried around a ILK-DevA w/a for the
  689. * 160MHz clock. If we're really unlucky, it's still required.
  690. */
  691. DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
  692. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  693. } else {
  694. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  695. }
  696. I915_WRITE(DP_A, dpa_ctl);
  697. POSTING_READ(DP_A);
  698. udelay(500);
  699. }
  700. static void
  701. intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
  702. struct drm_display_mode *adjusted_mode)
  703. {
  704. struct drm_device *dev = encoder->dev;
  705. struct drm_i915_private *dev_priv = dev->dev_private;
  706. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  707. struct drm_crtc *crtc = encoder->crtc;
  708. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  709. /*
  710. * There are four kinds of DP registers:
  711. *
  712. * IBX PCH
  713. * SNB CPU
  714. * IVB CPU
  715. * CPT PCH
  716. *
  717. * IBX PCH and CPU are the same for almost everything,
  718. * except that the CPU DP PLL is configured in this
  719. * register
  720. *
  721. * CPT PCH is quite different, having many bits moved
  722. * to the TRANS_DP_CTL register instead. That
  723. * configuration happens (oddly) in ironlake_pch_enable
  724. */
  725. /* Preserve the BIOS-computed detected bit. This is
  726. * supposed to be read-only.
  727. */
  728. intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
  729. /* Handle DP bits in common between all three register formats */
  730. intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  731. switch (intel_dp->lane_count) {
  732. case 1:
  733. intel_dp->DP |= DP_PORT_WIDTH_1;
  734. break;
  735. case 2:
  736. intel_dp->DP |= DP_PORT_WIDTH_2;
  737. break;
  738. case 4:
  739. intel_dp->DP |= DP_PORT_WIDTH_4;
  740. break;
  741. }
  742. if (intel_dp->has_audio) {
  743. DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
  744. pipe_name(intel_crtc->pipe));
  745. intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
  746. intel_write_eld(encoder, adjusted_mode);
  747. }
  748. intel_dp_init_link_config(intel_dp);
  749. /* Split out the IBX/CPU vs CPT settings */
  750. if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
  751. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  752. intel_dp->DP |= DP_SYNC_HS_HIGH;
  753. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  754. intel_dp->DP |= DP_SYNC_VS_HIGH;
  755. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  756. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  757. intel_dp->DP |= DP_ENHANCED_FRAMING;
  758. intel_dp->DP |= intel_crtc->pipe << 29;
  759. /* don't miss out required setting for eDP */
  760. if (adjusted_mode->clock < 200000)
  761. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  762. else
  763. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  764. } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
  765. if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
  766. intel_dp->DP |= intel_dp->color_range;
  767. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  768. intel_dp->DP |= DP_SYNC_HS_HIGH;
  769. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  770. intel_dp->DP |= DP_SYNC_VS_HIGH;
  771. intel_dp->DP |= DP_LINK_TRAIN_OFF;
  772. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  773. intel_dp->DP |= DP_ENHANCED_FRAMING;
  774. if (intel_crtc->pipe == 1)
  775. intel_dp->DP |= DP_PIPEB_SELECT;
  776. if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
  777. /* don't miss out required setting for eDP */
  778. if (adjusted_mode->clock < 200000)
  779. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  780. else
  781. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  782. }
  783. } else {
  784. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  785. }
  786. if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
  787. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  788. }
  789. #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  790. #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
  791. #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  792. #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  793. #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
  794. #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  795. static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
  796. u32 mask,
  797. u32 value)
  798. {
  799. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  800. struct drm_i915_private *dev_priv = dev->dev_private;
  801. u32 pp_stat_reg, pp_ctrl_reg;
  802. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  803. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  804. DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
  805. mask, value,
  806. I915_READ(pp_stat_reg),
  807. I915_READ(pp_ctrl_reg));
  808. if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
  809. DRM_ERROR("Panel status timeout: status %08x control %08x\n",
  810. I915_READ(pp_stat_reg),
  811. I915_READ(pp_ctrl_reg));
  812. }
  813. }
  814. static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
  815. {
  816. DRM_DEBUG_KMS("Wait for panel power on\n");
  817. ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
  818. }
  819. static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
  820. {
  821. DRM_DEBUG_KMS("Wait for panel power off time\n");
  822. ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
  823. }
  824. static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  825. {
  826. DRM_DEBUG_KMS("Wait for panel power cycle\n");
  827. ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
  828. }
  829. /* Read the current pp_control value, unlocking the register if it
  830. * is locked
  831. */
  832. static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
  833. {
  834. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  835. struct drm_i915_private *dev_priv = dev->dev_private;
  836. u32 control;
  837. u32 pp_ctrl_reg;
  838. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  839. control = I915_READ(pp_ctrl_reg);
  840. control &= ~PANEL_UNLOCK_MASK;
  841. control |= PANEL_UNLOCK_REGS;
  842. return control;
  843. }
  844. void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
  845. {
  846. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  847. struct drm_i915_private *dev_priv = dev->dev_private;
  848. u32 pp;
  849. u32 pp_stat_reg, pp_ctrl_reg;
  850. if (!is_edp(intel_dp))
  851. return;
  852. DRM_DEBUG_KMS("Turn eDP VDD on\n");
  853. WARN(intel_dp->want_panel_vdd,
  854. "eDP VDD already requested on\n");
  855. intel_dp->want_panel_vdd = true;
  856. if (ironlake_edp_have_panel_vdd(intel_dp)) {
  857. DRM_DEBUG_KMS("eDP VDD already on\n");
  858. return;
  859. }
  860. if (!ironlake_edp_have_panel_power(intel_dp))
  861. ironlake_wait_panel_power_cycle(intel_dp);
  862. pp = ironlake_get_pp_control(intel_dp);
  863. pp |= EDP_FORCE_VDD;
  864. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  865. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  866. I915_WRITE(pp_ctrl_reg, pp);
  867. POSTING_READ(pp_ctrl_reg);
  868. DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
  869. I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
  870. /*
  871. * If the panel wasn't on, delay before accessing aux channel
  872. */
  873. if (!ironlake_edp_have_panel_power(intel_dp)) {
  874. DRM_DEBUG_KMS("eDP was not running\n");
  875. msleep(intel_dp->panel_power_up_delay);
  876. }
  877. }
  878. static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
  879. {
  880. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  881. struct drm_i915_private *dev_priv = dev->dev_private;
  882. u32 pp;
  883. u32 pp_stat_reg, pp_ctrl_reg;
  884. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
  885. if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
  886. pp = ironlake_get_pp_control(intel_dp);
  887. pp &= ~EDP_FORCE_VDD;
  888. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  889. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  890. I915_WRITE(pp_ctrl_reg, pp);
  891. POSTING_READ(pp_ctrl_reg);
  892. /* Make sure sequencer is idle before allowing subsequent activity */
  893. DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
  894. I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
  895. msleep(intel_dp->panel_power_down_delay);
  896. }
  897. }
  898. static void ironlake_panel_vdd_work(struct work_struct *__work)
  899. {
  900. struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
  901. struct intel_dp, panel_vdd_work);
  902. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  903. mutex_lock(&dev->mode_config.mutex);
  904. ironlake_panel_vdd_off_sync(intel_dp);
  905. mutex_unlock(&dev->mode_config.mutex);
  906. }
  907. void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
  908. {
  909. if (!is_edp(intel_dp))
  910. return;
  911. DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
  912. WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
  913. intel_dp->want_panel_vdd = false;
  914. if (sync) {
  915. ironlake_panel_vdd_off_sync(intel_dp);
  916. } else {
  917. /*
  918. * Queue the timer to fire a long
  919. * time from now (relative to the power down delay)
  920. * to keep the panel power up across a sequence of operations
  921. */
  922. schedule_delayed_work(&intel_dp->panel_vdd_work,
  923. msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
  924. }
  925. }
  926. void ironlake_edp_panel_on(struct intel_dp *intel_dp)
  927. {
  928. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  929. struct drm_i915_private *dev_priv = dev->dev_private;
  930. u32 pp;
  931. u32 pp_ctrl_reg;
  932. if (!is_edp(intel_dp))
  933. return;
  934. DRM_DEBUG_KMS("Turn eDP power on\n");
  935. if (ironlake_edp_have_panel_power(intel_dp)) {
  936. DRM_DEBUG_KMS("eDP power already on\n");
  937. return;
  938. }
  939. ironlake_wait_panel_power_cycle(intel_dp);
  940. pp = ironlake_get_pp_control(intel_dp);
  941. if (IS_GEN5(dev)) {
  942. /* ILK workaround: disable reset around power sequence */
  943. pp &= ~PANEL_POWER_RESET;
  944. I915_WRITE(PCH_PP_CONTROL, pp);
  945. POSTING_READ(PCH_PP_CONTROL);
  946. }
  947. pp |= POWER_TARGET_ON;
  948. if (!IS_GEN5(dev))
  949. pp |= PANEL_POWER_RESET;
  950. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  951. I915_WRITE(pp_ctrl_reg, pp);
  952. POSTING_READ(pp_ctrl_reg);
  953. ironlake_wait_panel_on(intel_dp);
  954. if (IS_GEN5(dev)) {
  955. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  956. I915_WRITE(PCH_PP_CONTROL, pp);
  957. POSTING_READ(PCH_PP_CONTROL);
  958. }
  959. }
  960. void ironlake_edp_panel_off(struct intel_dp *intel_dp)
  961. {
  962. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  963. struct drm_i915_private *dev_priv = dev->dev_private;
  964. u32 pp;
  965. u32 pp_ctrl_reg;
  966. if (!is_edp(intel_dp))
  967. return;
  968. DRM_DEBUG_KMS("Turn eDP power off\n");
  969. WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
  970. pp = ironlake_get_pp_control(intel_dp);
  971. /* We need to switch off panel power _and_ force vdd, for otherwise some
  972. * panels get very unhappy and cease to work. */
  973. pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
  974. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  975. I915_WRITE(pp_ctrl_reg, pp);
  976. POSTING_READ(pp_ctrl_reg);
  977. intel_dp->want_panel_vdd = false;
  978. ironlake_wait_panel_off(intel_dp);
  979. }
  980. void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
  981. {
  982. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  983. struct drm_device *dev = intel_dig_port->base.base.dev;
  984. struct drm_i915_private *dev_priv = dev->dev_private;
  985. int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
  986. u32 pp;
  987. u32 pp_ctrl_reg;
  988. if (!is_edp(intel_dp))
  989. return;
  990. DRM_DEBUG_KMS("\n");
  991. /*
  992. * If we enable the backlight right away following a panel power
  993. * on, we may see slight flicker as the panel syncs with the eDP
  994. * link. So delay a bit to make sure the image is solid before
  995. * allowing it to appear.
  996. */
  997. msleep(intel_dp->backlight_on_delay);
  998. pp = ironlake_get_pp_control(intel_dp);
  999. pp |= EDP_BLC_ENABLE;
  1000. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  1001. I915_WRITE(pp_ctrl_reg, pp);
  1002. POSTING_READ(pp_ctrl_reg);
  1003. intel_panel_enable_backlight(dev, pipe);
  1004. }
  1005. void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
  1006. {
  1007. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1008. struct drm_i915_private *dev_priv = dev->dev_private;
  1009. u32 pp;
  1010. u32 pp_ctrl_reg;
  1011. if (!is_edp(intel_dp))
  1012. return;
  1013. intel_panel_disable_backlight(dev);
  1014. DRM_DEBUG_KMS("\n");
  1015. pp = ironlake_get_pp_control(intel_dp);
  1016. pp &= ~EDP_BLC_ENABLE;
  1017. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  1018. I915_WRITE(pp_ctrl_reg, pp);
  1019. POSTING_READ(pp_ctrl_reg);
  1020. msleep(intel_dp->backlight_off_delay);
  1021. }
  1022. static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
  1023. {
  1024. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1025. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1026. struct drm_device *dev = crtc->dev;
  1027. struct drm_i915_private *dev_priv = dev->dev_private;
  1028. u32 dpa_ctl;
  1029. assert_pipe_disabled(dev_priv,
  1030. to_intel_crtc(crtc)->pipe);
  1031. DRM_DEBUG_KMS("\n");
  1032. dpa_ctl = I915_READ(DP_A);
  1033. WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
  1034. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1035. /* We don't adjust intel_dp->DP while tearing down the link, to
  1036. * facilitate link retraining (e.g. after hotplug). Hence clear all
  1037. * enable bits here to ensure that we don't enable too much. */
  1038. intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
  1039. intel_dp->DP |= DP_PLL_ENABLE;
  1040. I915_WRITE(DP_A, intel_dp->DP);
  1041. POSTING_READ(DP_A);
  1042. udelay(200);
  1043. }
  1044. static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
  1045. {
  1046. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1047. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1048. struct drm_device *dev = crtc->dev;
  1049. struct drm_i915_private *dev_priv = dev->dev_private;
  1050. u32 dpa_ctl;
  1051. assert_pipe_disabled(dev_priv,
  1052. to_intel_crtc(crtc)->pipe);
  1053. dpa_ctl = I915_READ(DP_A);
  1054. WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
  1055. "dp pll off, should be on\n");
  1056. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1057. /* We can't rely on the value tracked for the DP register in
  1058. * intel_dp->DP because link_down must not change that (otherwise link
  1059. * re-training will fail. */
  1060. dpa_ctl &= ~DP_PLL_ENABLE;
  1061. I915_WRITE(DP_A, dpa_ctl);
  1062. POSTING_READ(DP_A);
  1063. udelay(200);
  1064. }
  1065. /* If the sink supports it, try to set the power state appropriately */
  1066. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
  1067. {
  1068. int ret, i;
  1069. /* Should have a valid DPCD by this point */
  1070. if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
  1071. return;
  1072. if (mode != DRM_MODE_DPMS_ON) {
  1073. ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
  1074. DP_SET_POWER_D3);
  1075. if (ret != 1)
  1076. DRM_DEBUG_DRIVER("failed to write sink power state\n");
  1077. } else {
  1078. /*
  1079. * When turning on, we need to retry for 1ms to give the sink
  1080. * time to wake up.
  1081. */
  1082. for (i = 0; i < 3; i++) {
  1083. ret = intel_dp_aux_native_write_1(intel_dp,
  1084. DP_SET_POWER,
  1085. DP_SET_POWER_D0);
  1086. if (ret == 1)
  1087. break;
  1088. msleep(1);
  1089. }
  1090. }
  1091. }
  1092. static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
  1093. enum pipe *pipe)
  1094. {
  1095. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1096. struct drm_device *dev = encoder->base.dev;
  1097. struct drm_i915_private *dev_priv = dev->dev_private;
  1098. u32 tmp = I915_READ(intel_dp->output_reg);
  1099. if (!(tmp & DP_PORT_EN))
  1100. return false;
  1101. if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
  1102. *pipe = PORT_TO_PIPE_CPT(tmp);
  1103. } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
  1104. *pipe = PORT_TO_PIPE(tmp);
  1105. } else {
  1106. u32 trans_sel;
  1107. u32 trans_dp;
  1108. int i;
  1109. switch (intel_dp->output_reg) {
  1110. case PCH_DP_B:
  1111. trans_sel = TRANS_DP_PORT_SEL_B;
  1112. break;
  1113. case PCH_DP_C:
  1114. trans_sel = TRANS_DP_PORT_SEL_C;
  1115. break;
  1116. case PCH_DP_D:
  1117. trans_sel = TRANS_DP_PORT_SEL_D;
  1118. break;
  1119. default:
  1120. return true;
  1121. }
  1122. for_each_pipe(i) {
  1123. trans_dp = I915_READ(TRANS_DP_CTL(i));
  1124. if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
  1125. *pipe = i;
  1126. return true;
  1127. }
  1128. }
  1129. DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
  1130. intel_dp->output_reg);
  1131. }
  1132. return true;
  1133. }
  1134. static void intel_disable_dp(struct intel_encoder *encoder)
  1135. {
  1136. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1137. /* Make sure the panel is off before trying to change the mode. But also
  1138. * ensure that we have vdd while we switch off the panel. */
  1139. ironlake_edp_panel_vdd_on(intel_dp);
  1140. ironlake_edp_backlight_off(intel_dp);
  1141. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1142. ironlake_edp_panel_off(intel_dp);
  1143. /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
  1144. if (!is_cpu_edp(intel_dp))
  1145. intel_dp_link_down(intel_dp);
  1146. }
  1147. static void intel_post_disable_dp(struct intel_encoder *encoder)
  1148. {
  1149. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1150. struct drm_device *dev = encoder->base.dev;
  1151. if (is_cpu_edp(intel_dp)) {
  1152. intel_dp_link_down(intel_dp);
  1153. if (!IS_VALLEYVIEW(dev))
  1154. ironlake_edp_pll_off(intel_dp);
  1155. }
  1156. }
  1157. static void intel_enable_dp(struct intel_encoder *encoder)
  1158. {
  1159. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1160. struct drm_device *dev = encoder->base.dev;
  1161. struct drm_i915_private *dev_priv = dev->dev_private;
  1162. uint32_t dp_reg = I915_READ(intel_dp->output_reg);
  1163. if (WARN_ON(dp_reg & DP_PORT_EN))
  1164. return;
  1165. ironlake_edp_panel_vdd_on(intel_dp);
  1166. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1167. intel_dp_start_link_train(intel_dp);
  1168. ironlake_edp_panel_on(intel_dp);
  1169. ironlake_edp_panel_vdd_off(intel_dp, true);
  1170. intel_dp_complete_link_train(intel_dp);
  1171. ironlake_edp_backlight_on(intel_dp);
  1172. }
  1173. static void intel_pre_enable_dp(struct intel_encoder *encoder)
  1174. {
  1175. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1176. struct drm_device *dev = encoder->base.dev;
  1177. if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
  1178. ironlake_edp_pll_on(intel_dp);
  1179. }
  1180. /*
  1181. * Native read with retry for link status and receiver capability reads for
  1182. * cases where the sink may still be asleep.
  1183. */
  1184. static bool
  1185. intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  1186. uint8_t *recv, int recv_bytes)
  1187. {
  1188. int ret, i;
  1189. /*
  1190. * Sinks are *supposed* to come up within 1ms from an off state,
  1191. * but we're also supposed to retry 3 times per the spec.
  1192. */
  1193. for (i = 0; i < 3; i++) {
  1194. ret = intel_dp_aux_native_read(intel_dp, address, recv,
  1195. recv_bytes);
  1196. if (ret == recv_bytes)
  1197. return true;
  1198. msleep(1);
  1199. }
  1200. return false;
  1201. }
  1202. /*
  1203. * Fetch AUX CH registers 0x202 - 0x207 which contain
  1204. * link status information
  1205. */
  1206. static bool
  1207. intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1208. {
  1209. return intel_dp_aux_native_read_retry(intel_dp,
  1210. DP_LANE0_1_STATUS,
  1211. link_status,
  1212. DP_LINK_STATUS_SIZE);
  1213. }
  1214. #if 0
  1215. static char *voltage_names[] = {
  1216. "0.4V", "0.6V", "0.8V", "1.2V"
  1217. };
  1218. static char *pre_emph_names[] = {
  1219. "0dB", "3.5dB", "6dB", "9.5dB"
  1220. };
  1221. static char *link_train_names[] = {
  1222. "pattern 1", "pattern 2", "idle", "off"
  1223. };
  1224. #endif
  1225. /*
  1226. * These are source-specific values; current Intel hardware supports
  1227. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  1228. */
  1229. static uint8_t
  1230. intel_dp_voltage_max(struct intel_dp *intel_dp)
  1231. {
  1232. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1233. if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
  1234. return DP_TRAIN_VOLTAGE_SWING_800;
  1235. else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
  1236. return DP_TRAIN_VOLTAGE_SWING_1200;
  1237. else
  1238. return DP_TRAIN_VOLTAGE_SWING_800;
  1239. }
  1240. static uint8_t
  1241. intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
  1242. {
  1243. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1244. if (HAS_DDI(dev)) {
  1245. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1246. case DP_TRAIN_VOLTAGE_SWING_400:
  1247. return DP_TRAIN_PRE_EMPHASIS_9_5;
  1248. case DP_TRAIN_VOLTAGE_SWING_600:
  1249. return DP_TRAIN_PRE_EMPHASIS_6;
  1250. case DP_TRAIN_VOLTAGE_SWING_800:
  1251. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1252. case DP_TRAIN_VOLTAGE_SWING_1200:
  1253. default:
  1254. return DP_TRAIN_PRE_EMPHASIS_0;
  1255. }
  1256. } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
  1257. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1258. case DP_TRAIN_VOLTAGE_SWING_400:
  1259. return DP_TRAIN_PRE_EMPHASIS_6;
  1260. case DP_TRAIN_VOLTAGE_SWING_600:
  1261. case DP_TRAIN_VOLTAGE_SWING_800:
  1262. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1263. default:
  1264. return DP_TRAIN_PRE_EMPHASIS_0;
  1265. }
  1266. } else {
  1267. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1268. case DP_TRAIN_VOLTAGE_SWING_400:
  1269. return DP_TRAIN_PRE_EMPHASIS_6;
  1270. case DP_TRAIN_VOLTAGE_SWING_600:
  1271. return DP_TRAIN_PRE_EMPHASIS_6;
  1272. case DP_TRAIN_VOLTAGE_SWING_800:
  1273. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1274. case DP_TRAIN_VOLTAGE_SWING_1200:
  1275. default:
  1276. return DP_TRAIN_PRE_EMPHASIS_0;
  1277. }
  1278. }
  1279. }
  1280. static void
  1281. intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1282. {
  1283. uint8_t v = 0;
  1284. uint8_t p = 0;
  1285. int lane;
  1286. uint8_t voltage_max;
  1287. uint8_t preemph_max;
  1288. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1289. uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  1290. uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  1291. if (this_v > v)
  1292. v = this_v;
  1293. if (this_p > p)
  1294. p = this_p;
  1295. }
  1296. voltage_max = intel_dp_voltage_max(intel_dp);
  1297. if (v >= voltage_max)
  1298. v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  1299. preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  1300. if (p >= preemph_max)
  1301. p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  1302. for (lane = 0; lane < 4; lane++)
  1303. intel_dp->train_set[lane] = v | p;
  1304. }
  1305. static uint32_t
  1306. intel_gen4_signal_levels(uint8_t train_set)
  1307. {
  1308. uint32_t signal_levels = 0;
  1309. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1310. case DP_TRAIN_VOLTAGE_SWING_400:
  1311. default:
  1312. signal_levels |= DP_VOLTAGE_0_4;
  1313. break;
  1314. case DP_TRAIN_VOLTAGE_SWING_600:
  1315. signal_levels |= DP_VOLTAGE_0_6;
  1316. break;
  1317. case DP_TRAIN_VOLTAGE_SWING_800:
  1318. signal_levels |= DP_VOLTAGE_0_8;
  1319. break;
  1320. case DP_TRAIN_VOLTAGE_SWING_1200:
  1321. signal_levels |= DP_VOLTAGE_1_2;
  1322. break;
  1323. }
  1324. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1325. case DP_TRAIN_PRE_EMPHASIS_0:
  1326. default:
  1327. signal_levels |= DP_PRE_EMPHASIS_0;
  1328. break;
  1329. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1330. signal_levels |= DP_PRE_EMPHASIS_3_5;
  1331. break;
  1332. case DP_TRAIN_PRE_EMPHASIS_6:
  1333. signal_levels |= DP_PRE_EMPHASIS_6;
  1334. break;
  1335. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1336. signal_levels |= DP_PRE_EMPHASIS_9_5;
  1337. break;
  1338. }
  1339. return signal_levels;
  1340. }
  1341. /* Gen6's DP voltage swing and pre-emphasis control */
  1342. static uint32_t
  1343. intel_gen6_edp_signal_levels(uint8_t train_set)
  1344. {
  1345. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1346. DP_TRAIN_PRE_EMPHASIS_MASK);
  1347. switch (signal_levels) {
  1348. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1349. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1350. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1351. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1352. return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
  1353. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1354. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1355. return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
  1356. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1357. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1358. return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
  1359. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1360. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  1361. return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
  1362. default:
  1363. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1364. "0x%x\n", signal_levels);
  1365. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1366. }
  1367. }
  1368. /* Gen7's DP voltage swing and pre-emphasis control */
  1369. static uint32_t
  1370. intel_gen7_edp_signal_levels(uint8_t train_set)
  1371. {
  1372. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1373. DP_TRAIN_PRE_EMPHASIS_MASK);
  1374. switch (signal_levels) {
  1375. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1376. return EDP_LINK_TRAIN_400MV_0DB_IVB;
  1377. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1378. return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
  1379. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1380. return EDP_LINK_TRAIN_400MV_6DB_IVB;
  1381. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1382. return EDP_LINK_TRAIN_600MV_0DB_IVB;
  1383. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1384. return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
  1385. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1386. return EDP_LINK_TRAIN_800MV_0DB_IVB;
  1387. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1388. return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
  1389. default:
  1390. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1391. "0x%x\n", signal_levels);
  1392. return EDP_LINK_TRAIN_500MV_0DB_IVB;
  1393. }
  1394. }
  1395. /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
  1396. static uint32_t
  1397. intel_hsw_signal_levels(uint8_t train_set)
  1398. {
  1399. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1400. DP_TRAIN_PRE_EMPHASIS_MASK);
  1401. switch (signal_levels) {
  1402. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1403. return DDI_BUF_EMP_400MV_0DB_HSW;
  1404. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1405. return DDI_BUF_EMP_400MV_3_5DB_HSW;
  1406. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1407. return DDI_BUF_EMP_400MV_6DB_HSW;
  1408. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
  1409. return DDI_BUF_EMP_400MV_9_5DB_HSW;
  1410. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1411. return DDI_BUF_EMP_600MV_0DB_HSW;
  1412. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1413. return DDI_BUF_EMP_600MV_3_5DB_HSW;
  1414. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1415. return DDI_BUF_EMP_600MV_6DB_HSW;
  1416. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1417. return DDI_BUF_EMP_800MV_0DB_HSW;
  1418. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1419. return DDI_BUF_EMP_800MV_3_5DB_HSW;
  1420. default:
  1421. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1422. "0x%x\n", signal_levels);
  1423. return DDI_BUF_EMP_400MV_0DB_HSW;
  1424. }
  1425. }
  1426. /* Properly updates "DP" with the correct signal levels. */
  1427. static void
  1428. intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
  1429. {
  1430. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1431. struct drm_device *dev = intel_dig_port->base.base.dev;
  1432. uint32_t signal_levels, mask;
  1433. uint8_t train_set = intel_dp->train_set[0];
  1434. if (HAS_DDI(dev)) {
  1435. signal_levels = intel_hsw_signal_levels(train_set);
  1436. mask = DDI_BUF_EMP_MASK;
  1437. } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
  1438. signal_levels = intel_gen7_edp_signal_levels(train_set);
  1439. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
  1440. } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
  1441. signal_levels = intel_gen6_edp_signal_levels(train_set);
  1442. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
  1443. } else {
  1444. signal_levels = intel_gen4_signal_levels(train_set);
  1445. mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
  1446. }
  1447. DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
  1448. *DP = (*DP & ~mask) | signal_levels;
  1449. }
  1450. static bool
  1451. intel_dp_set_link_train(struct intel_dp *intel_dp,
  1452. uint32_t dp_reg_value,
  1453. uint8_t dp_train_pat)
  1454. {
  1455. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1456. struct drm_device *dev = intel_dig_port->base.base.dev;
  1457. struct drm_i915_private *dev_priv = dev->dev_private;
  1458. enum port port = intel_dig_port->port;
  1459. int ret;
  1460. uint32_t temp;
  1461. if (HAS_DDI(dev)) {
  1462. temp = I915_READ(DP_TP_CTL(port));
  1463. if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
  1464. temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
  1465. else
  1466. temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
  1467. temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  1468. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1469. case DP_TRAINING_PATTERN_DISABLE:
  1470. if (port != PORT_A) {
  1471. temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
  1472. I915_WRITE(DP_TP_CTL(port), temp);
  1473. if (wait_for((I915_READ(DP_TP_STATUS(port)) &
  1474. DP_TP_STATUS_IDLE_DONE), 1))
  1475. DRM_ERROR("Timed out waiting for DP idle patterns\n");
  1476. temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  1477. }
  1478. temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
  1479. break;
  1480. case DP_TRAINING_PATTERN_1:
  1481. temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
  1482. break;
  1483. case DP_TRAINING_PATTERN_2:
  1484. temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
  1485. break;
  1486. case DP_TRAINING_PATTERN_3:
  1487. temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
  1488. break;
  1489. }
  1490. I915_WRITE(DP_TP_CTL(port), temp);
  1491. } else if (HAS_PCH_CPT(dev) &&
  1492. (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
  1493. dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
  1494. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1495. case DP_TRAINING_PATTERN_DISABLE:
  1496. dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
  1497. break;
  1498. case DP_TRAINING_PATTERN_1:
  1499. dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
  1500. break;
  1501. case DP_TRAINING_PATTERN_2:
  1502. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1503. break;
  1504. case DP_TRAINING_PATTERN_3:
  1505. DRM_ERROR("DP training pattern 3 not supported\n");
  1506. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1507. break;
  1508. }
  1509. } else {
  1510. dp_reg_value &= ~DP_LINK_TRAIN_MASK;
  1511. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1512. case DP_TRAINING_PATTERN_DISABLE:
  1513. dp_reg_value |= DP_LINK_TRAIN_OFF;
  1514. break;
  1515. case DP_TRAINING_PATTERN_1:
  1516. dp_reg_value |= DP_LINK_TRAIN_PAT_1;
  1517. break;
  1518. case DP_TRAINING_PATTERN_2:
  1519. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1520. break;
  1521. case DP_TRAINING_PATTERN_3:
  1522. DRM_ERROR("DP training pattern 3 not supported\n");
  1523. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1524. break;
  1525. }
  1526. }
  1527. I915_WRITE(intel_dp->output_reg, dp_reg_value);
  1528. POSTING_READ(intel_dp->output_reg);
  1529. intel_dp_aux_native_write_1(intel_dp,
  1530. DP_TRAINING_PATTERN_SET,
  1531. dp_train_pat);
  1532. if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
  1533. DP_TRAINING_PATTERN_DISABLE) {
  1534. ret = intel_dp_aux_native_write(intel_dp,
  1535. DP_TRAINING_LANE0_SET,
  1536. intel_dp->train_set,
  1537. intel_dp->lane_count);
  1538. if (ret != intel_dp->lane_count)
  1539. return false;
  1540. }
  1541. return true;
  1542. }
  1543. /* Enable corresponding port and start training pattern 1 */
  1544. void
  1545. intel_dp_start_link_train(struct intel_dp *intel_dp)
  1546. {
  1547. struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
  1548. struct drm_device *dev = encoder->dev;
  1549. int i;
  1550. uint8_t voltage;
  1551. bool clock_recovery = false;
  1552. int voltage_tries, loop_tries;
  1553. uint32_t DP = intel_dp->DP;
  1554. if (HAS_DDI(dev))
  1555. intel_ddi_prepare_link_retrain(encoder);
  1556. /* Write the link configuration data */
  1557. intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
  1558. intel_dp->link_configuration,
  1559. DP_LINK_CONFIGURATION_SIZE);
  1560. DP |= DP_PORT_EN;
  1561. memset(intel_dp->train_set, 0, 4);
  1562. voltage = 0xff;
  1563. voltage_tries = 0;
  1564. loop_tries = 0;
  1565. clock_recovery = false;
  1566. for (;;) {
  1567. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1568. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1569. intel_dp_set_signal_levels(intel_dp, &DP);
  1570. /* Set training pattern 1 */
  1571. if (!intel_dp_set_link_train(intel_dp, DP,
  1572. DP_TRAINING_PATTERN_1 |
  1573. DP_LINK_SCRAMBLING_DISABLE))
  1574. break;
  1575. drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
  1576. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1577. DRM_ERROR("failed to get link status\n");
  1578. break;
  1579. }
  1580. if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1581. DRM_DEBUG_KMS("clock recovery OK\n");
  1582. clock_recovery = true;
  1583. break;
  1584. }
  1585. /* Check to see if we've tried the max voltage */
  1586. for (i = 0; i < intel_dp->lane_count; i++)
  1587. if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  1588. break;
  1589. if (i == intel_dp->lane_count) {
  1590. ++loop_tries;
  1591. if (loop_tries == 5) {
  1592. DRM_DEBUG_KMS("too many full retries, give up\n");
  1593. break;
  1594. }
  1595. memset(intel_dp->train_set, 0, 4);
  1596. voltage_tries = 0;
  1597. continue;
  1598. }
  1599. /* Check to see if we've tried the same voltage 5 times */
  1600. if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  1601. ++voltage_tries;
  1602. if (voltage_tries == 5) {
  1603. DRM_DEBUG_KMS("too many voltage retries, give up\n");
  1604. break;
  1605. }
  1606. } else
  1607. voltage_tries = 0;
  1608. voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  1609. /* Compute new intel_dp->train_set as requested by target */
  1610. intel_get_adjust_train(intel_dp, link_status);
  1611. }
  1612. intel_dp->DP = DP;
  1613. }
  1614. void
  1615. intel_dp_complete_link_train(struct intel_dp *intel_dp)
  1616. {
  1617. bool channel_eq = false;
  1618. int tries, cr_tries;
  1619. uint32_t DP = intel_dp->DP;
  1620. /* channel equalization */
  1621. tries = 0;
  1622. cr_tries = 0;
  1623. channel_eq = false;
  1624. for (;;) {
  1625. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1626. if (cr_tries > 5) {
  1627. DRM_ERROR("failed to train DP, aborting\n");
  1628. intel_dp_link_down(intel_dp);
  1629. break;
  1630. }
  1631. intel_dp_set_signal_levels(intel_dp, &DP);
  1632. /* channel eq pattern */
  1633. if (!intel_dp_set_link_train(intel_dp, DP,
  1634. DP_TRAINING_PATTERN_2 |
  1635. DP_LINK_SCRAMBLING_DISABLE))
  1636. break;
  1637. drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
  1638. if (!intel_dp_get_link_status(intel_dp, link_status))
  1639. break;
  1640. /* Make sure clock is still ok */
  1641. if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1642. intel_dp_start_link_train(intel_dp);
  1643. cr_tries++;
  1644. continue;
  1645. }
  1646. if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  1647. channel_eq = true;
  1648. break;
  1649. }
  1650. /* Try 5 times, then try clock recovery if that fails */
  1651. if (tries > 5) {
  1652. intel_dp_link_down(intel_dp);
  1653. intel_dp_start_link_train(intel_dp);
  1654. tries = 0;
  1655. cr_tries++;
  1656. continue;
  1657. }
  1658. /* Compute new intel_dp->train_set as requested by target */
  1659. intel_get_adjust_train(intel_dp, link_status);
  1660. ++tries;
  1661. }
  1662. if (channel_eq)
  1663. DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
  1664. intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
  1665. }
  1666. static void
  1667. intel_dp_link_down(struct intel_dp *intel_dp)
  1668. {
  1669. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1670. struct drm_device *dev = intel_dig_port->base.base.dev;
  1671. struct drm_i915_private *dev_priv = dev->dev_private;
  1672. struct intel_crtc *intel_crtc =
  1673. to_intel_crtc(intel_dig_port->base.base.crtc);
  1674. uint32_t DP = intel_dp->DP;
  1675. /*
  1676. * DDI code has a strict mode set sequence and we should try to respect
  1677. * it, otherwise we might hang the machine in many different ways. So we
  1678. * really should be disabling the port only on a complete crtc_disable
  1679. * sequence. This function is just called under two conditions on DDI
  1680. * code:
  1681. * - Link train failed while doing crtc_enable, and on this case we
  1682. * really should respect the mode set sequence and wait for a
  1683. * crtc_disable.
  1684. * - Someone turned the monitor off and intel_dp_check_link_status
  1685. * called us. We don't need to disable the whole port on this case, so
  1686. * when someone turns the monitor on again,
  1687. * intel_ddi_prepare_link_retrain will take care of redoing the link
  1688. * train.
  1689. */
  1690. if (HAS_DDI(dev))
  1691. return;
  1692. if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
  1693. return;
  1694. DRM_DEBUG_KMS("\n");
  1695. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
  1696. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1697. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  1698. } else {
  1699. DP &= ~DP_LINK_TRAIN_MASK;
  1700. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  1701. }
  1702. POSTING_READ(intel_dp->output_reg);
  1703. /* We don't really know why we're doing this */
  1704. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1705. if (HAS_PCH_IBX(dev) &&
  1706. I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
  1707. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1708. /* Hardware workaround: leaving our transcoder select
  1709. * set to transcoder B while it's off will prevent the
  1710. * corresponding HDMI output on transcoder A.
  1711. *
  1712. * Combine this with another hardware workaround:
  1713. * transcoder select bit can only be cleared while the
  1714. * port is enabled.
  1715. */
  1716. DP &= ~DP_PIPEB_SELECT;
  1717. I915_WRITE(intel_dp->output_reg, DP);
  1718. /* Changes to enable or select take place the vblank
  1719. * after being written.
  1720. */
  1721. if (WARN_ON(crtc == NULL)) {
  1722. /* We should never try to disable a port without a crtc
  1723. * attached. For paranoia keep the code around for a
  1724. * bit. */
  1725. POSTING_READ(intel_dp->output_reg);
  1726. msleep(50);
  1727. } else
  1728. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1729. }
  1730. DP &= ~DP_AUDIO_OUTPUT_ENABLE;
  1731. I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
  1732. POSTING_READ(intel_dp->output_reg);
  1733. msleep(intel_dp->panel_power_down_delay);
  1734. }
  1735. static bool
  1736. intel_dp_get_dpcd(struct intel_dp *intel_dp)
  1737. {
  1738. char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
  1739. if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
  1740. sizeof(intel_dp->dpcd)) == 0)
  1741. return false; /* aux transfer failed */
  1742. hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
  1743. 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
  1744. DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
  1745. if (intel_dp->dpcd[DP_DPCD_REV] == 0)
  1746. return false; /* DPCD not present */
  1747. if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  1748. DP_DWN_STRM_PORT_PRESENT))
  1749. return true; /* native DP sink */
  1750. if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
  1751. return true; /* no per-port downstream info */
  1752. if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
  1753. intel_dp->downstream_ports,
  1754. DP_MAX_DOWNSTREAM_PORTS) == 0)
  1755. return false; /* downstream port status fetch failed */
  1756. return true;
  1757. }
  1758. static void
  1759. intel_dp_probe_oui(struct intel_dp *intel_dp)
  1760. {
  1761. u8 buf[3];
  1762. if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  1763. return;
  1764. ironlake_edp_panel_vdd_on(intel_dp);
  1765. if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
  1766. DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  1767. buf[0], buf[1], buf[2]);
  1768. if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
  1769. DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  1770. buf[0], buf[1], buf[2]);
  1771. ironlake_edp_panel_vdd_off(intel_dp, false);
  1772. }
  1773. static bool
  1774. intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
  1775. {
  1776. int ret;
  1777. ret = intel_dp_aux_native_read_retry(intel_dp,
  1778. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1779. sink_irq_vector, 1);
  1780. if (!ret)
  1781. return false;
  1782. return true;
  1783. }
  1784. static void
  1785. intel_dp_handle_test_request(struct intel_dp *intel_dp)
  1786. {
  1787. /* NAK by default */
  1788. intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
  1789. }
  1790. /*
  1791. * According to DP spec
  1792. * 5.1.2:
  1793. * 1. Read DPCD
  1794. * 2. Configure link according to Receiver Capabilities
  1795. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  1796. * 4. Check link status on receipt of hot-plug interrupt
  1797. */
  1798. void
  1799. intel_dp_check_link_status(struct intel_dp *intel_dp)
  1800. {
  1801. struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
  1802. u8 sink_irq_vector;
  1803. u8 link_status[DP_LINK_STATUS_SIZE];
  1804. if (!intel_encoder->connectors_active)
  1805. return;
  1806. if (WARN_ON(!intel_encoder->base.crtc))
  1807. return;
  1808. /* Try to read receiver status if the link appears to be up */
  1809. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1810. intel_dp_link_down(intel_dp);
  1811. return;
  1812. }
  1813. /* Now read the DPCD to see if it's actually running */
  1814. if (!intel_dp_get_dpcd(intel_dp)) {
  1815. intel_dp_link_down(intel_dp);
  1816. return;
  1817. }
  1818. /* Try to read the source of the interrupt */
  1819. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  1820. intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
  1821. /* Clear interrupt source */
  1822. intel_dp_aux_native_write_1(intel_dp,
  1823. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1824. sink_irq_vector);
  1825. if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
  1826. intel_dp_handle_test_request(intel_dp);
  1827. if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
  1828. DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
  1829. }
  1830. if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  1831. DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
  1832. drm_get_encoder_name(&intel_encoder->base));
  1833. intel_dp_start_link_train(intel_dp);
  1834. intel_dp_complete_link_train(intel_dp);
  1835. }
  1836. }
  1837. /* XXX this is probably wrong for multiple downstream ports */
  1838. static enum drm_connector_status
  1839. intel_dp_detect_dpcd(struct intel_dp *intel_dp)
  1840. {
  1841. uint8_t *dpcd = intel_dp->dpcd;
  1842. bool hpd;
  1843. uint8_t type;
  1844. if (!intel_dp_get_dpcd(intel_dp))
  1845. return connector_status_disconnected;
  1846. /* if there's no downstream port, we're done */
  1847. if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
  1848. return connector_status_connected;
  1849. /* If we're HPD-aware, SINK_COUNT changes dynamically */
  1850. hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
  1851. if (hpd) {
  1852. uint8_t reg;
  1853. if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
  1854. &reg, 1))
  1855. return connector_status_unknown;
  1856. return DP_GET_SINK_COUNT(reg) ? connector_status_connected
  1857. : connector_status_disconnected;
  1858. }
  1859. /* If no HPD, poke DDC gently */
  1860. if (drm_probe_ddc(&intel_dp->adapter))
  1861. return connector_status_connected;
  1862. /* Well we tried, say unknown for unreliable port types */
  1863. type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
  1864. if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
  1865. return connector_status_unknown;
  1866. /* Anything else is out of spec, warn and ignore */
  1867. DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
  1868. return connector_status_disconnected;
  1869. }
  1870. static enum drm_connector_status
  1871. ironlake_dp_detect(struct intel_dp *intel_dp)
  1872. {
  1873. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1874. struct drm_i915_private *dev_priv = dev->dev_private;
  1875. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1876. enum drm_connector_status status;
  1877. /* Can't disconnect eDP, but you can close the lid... */
  1878. if (is_edp(intel_dp)) {
  1879. status = intel_panel_detect(dev);
  1880. if (status == connector_status_unknown)
  1881. status = connector_status_connected;
  1882. return status;
  1883. }
  1884. if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
  1885. return connector_status_disconnected;
  1886. return intel_dp_detect_dpcd(intel_dp);
  1887. }
  1888. static enum drm_connector_status
  1889. g4x_dp_detect(struct intel_dp *intel_dp)
  1890. {
  1891. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1892. struct drm_i915_private *dev_priv = dev->dev_private;
  1893. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1894. uint32_t bit;
  1895. /* Can't disconnect eDP, but you can close the lid... */
  1896. if (is_edp(intel_dp)) {
  1897. enum drm_connector_status status;
  1898. status = intel_panel_detect(dev);
  1899. if (status == connector_status_unknown)
  1900. status = connector_status_connected;
  1901. return status;
  1902. }
  1903. switch (intel_dig_port->port) {
  1904. case PORT_B:
  1905. bit = PORTB_HOTPLUG_LIVE_STATUS;
  1906. break;
  1907. case PORT_C:
  1908. bit = PORTC_HOTPLUG_LIVE_STATUS;
  1909. break;
  1910. case PORT_D:
  1911. bit = PORTD_HOTPLUG_LIVE_STATUS;
  1912. break;
  1913. default:
  1914. return connector_status_unknown;
  1915. }
  1916. if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
  1917. return connector_status_disconnected;
  1918. return intel_dp_detect_dpcd(intel_dp);
  1919. }
  1920. static struct edid *
  1921. intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
  1922. {
  1923. struct intel_connector *intel_connector = to_intel_connector(connector);
  1924. /* use cached edid if we have one */
  1925. if (intel_connector->edid) {
  1926. struct edid *edid;
  1927. int size;
  1928. /* invalid edid */
  1929. if (IS_ERR(intel_connector->edid))
  1930. return NULL;
  1931. size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
  1932. edid = kmalloc(size, GFP_KERNEL);
  1933. if (!edid)
  1934. return NULL;
  1935. memcpy(edid, intel_connector->edid, size);
  1936. return edid;
  1937. }
  1938. return drm_get_edid(connector, adapter);
  1939. }
  1940. static int
  1941. intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
  1942. {
  1943. struct intel_connector *intel_connector = to_intel_connector(connector);
  1944. /* use cached edid if we have one */
  1945. if (intel_connector->edid) {
  1946. /* invalid edid */
  1947. if (IS_ERR(intel_connector->edid))
  1948. return 0;
  1949. return intel_connector_update_modes(connector,
  1950. intel_connector->edid);
  1951. }
  1952. return intel_ddc_get_modes(connector, adapter);
  1953. }
  1954. static enum drm_connector_status
  1955. intel_dp_detect(struct drm_connector *connector, bool force)
  1956. {
  1957. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1958. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1959. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  1960. struct drm_device *dev = connector->dev;
  1961. enum drm_connector_status status;
  1962. struct edid *edid = NULL;
  1963. intel_dp->has_audio = false;
  1964. if (HAS_PCH_SPLIT(dev))
  1965. status = ironlake_dp_detect(intel_dp);
  1966. else
  1967. status = g4x_dp_detect(intel_dp);
  1968. if (status != connector_status_connected)
  1969. return status;
  1970. intel_dp_probe_oui(intel_dp);
  1971. if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
  1972. intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
  1973. } else {
  1974. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  1975. if (edid) {
  1976. intel_dp->has_audio = drm_detect_monitor_audio(edid);
  1977. kfree(edid);
  1978. }
  1979. }
  1980. if (intel_encoder->type != INTEL_OUTPUT_EDP)
  1981. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  1982. return connector_status_connected;
  1983. }
  1984. static int intel_dp_get_modes(struct drm_connector *connector)
  1985. {
  1986. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1987. struct intel_connector *intel_connector = to_intel_connector(connector);
  1988. struct drm_device *dev = connector->dev;
  1989. int ret;
  1990. /* We should parse the EDID data and find out if it has an audio sink
  1991. */
  1992. ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
  1993. if (ret)
  1994. return ret;
  1995. /* if eDP has no EDID, fall back to fixed mode */
  1996. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  1997. struct drm_display_mode *mode;
  1998. mode = drm_mode_duplicate(dev,
  1999. intel_connector->panel.fixed_mode);
  2000. if (mode) {
  2001. drm_mode_probed_add(connector, mode);
  2002. return 1;
  2003. }
  2004. }
  2005. return 0;
  2006. }
  2007. static bool
  2008. intel_dp_detect_audio(struct drm_connector *connector)
  2009. {
  2010. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2011. struct edid *edid;
  2012. bool has_audio = false;
  2013. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  2014. if (edid) {
  2015. has_audio = drm_detect_monitor_audio(edid);
  2016. kfree(edid);
  2017. }
  2018. return has_audio;
  2019. }
  2020. static int
  2021. intel_dp_set_property(struct drm_connector *connector,
  2022. struct drm_property *property,
  2023. uint64_t val)
  2024. {
  2025. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  2026. struct intel_connector *intel_connector = to_intel_connector(connector);
  2027. struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
  2028. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2029. int ret;
  2030. ret = drm_object_property_set_value(&connector->base, property, val);
  2031. if (ret)
  2032. return ret;
  2033. if (property == dev_priv->force_audio_property) {
  2034. int i = val;
  2035. bool has_audio;
  2036. if (i == intel_dp->force_audio)
  2037. return 0;
  2038. intel_dp->force_audio = i;
  2039. if (i == HDMI_AUDIO_AUTO)
  2040. has_audio = intel_dp_detect_audio(connector);
  2041. else
  2042. has_audio = (i == HDMI_AUDIO_ON);
  2043. if (has_audio == intel_dp->has_audio)
  2044. return 0;
  2045. intel_dp->has_audio = has_audio;
  2046. goto done;
  2047. }
  2048. if (property == dev_priv->broadcast_rgb_property) {
  2049. switch (val) {
  2050. case INTEL_BROADCAST_RGB_AUTO:
  2051. intel_dp->color_range_auto = true;
  2052. break;
  2053. case INTEL_BROADCAST_RGB_FULL:
  2054. intel_dp->color_range_auto = false;
  2055. intel_dp->color_range = 0;
  2056. break;
  2057. case INTEL_BROADCAST_RGB_LIMITED:
  2058. intel_dp->color_range_auto = false;
  2059. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  2060. break;
  2061. default:
  2062. return -EINVAL;
  2063. }
  2064. goto done;
  2065. }
  2066. if (is_edp(intel_dp) &&
  2067. property == connector->dev->mode_config.scaling_mode_property) {
  2068. if (val == DRM_MODE_SCALE_NONE) {
  2069. DRM_DEBUG_KMS("no scaling not supported\n");
  2070. return -EINVAL;
  2071. }
  2072. if (intel_connector->panel.fitting_mode == val) {
  2073. /* the eDP scaling property is not changed */
  2074. return 0;
  2075. }
  2076. intel_connector->panel.fitting_mode = val;
  2077. goto done;
  2078. }
  2079. return -EINVAL;
  2080. done:
  2081. if (intel_encoder->base.crtc)
  2082. intel_crtc_restore_mode(intel_encoder->base.crtc);
  2083. return 0;
  2084. }
  2085. static void
  2086. intel_dp_destroy(struct drm_connector *connector)
  2087. {
  2088. struct drm_device *dev = connector->dev;
  2089. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2090. struct intel_connector *intel_connector = to_intel_connector(connector);
  2091. if (!IS_ERR_OR_NULL(intel_connector->edid))
  2092. kfree(intel_connector->edid);
  2093. if (is_edp(intel_dp)) {
  2094. intel_panel_destroy_backlight(dev);
  2095. intel_panel_fini(&intel_connector->panel);
  2096. }
  2097. drm_sysfs_connector_remove(connector);
  2098. drm_connector_cleanup(connector);
  2099. kfree(connector);
  2100. }
  2101. void intel_dp_encoder_destroy(struct drm_encoder *encoder)
  2102. {
  2103. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  2104. struct intel_dp *intel_dp = &intel_dig_port->dp;
  2105. i2c_del_adapter(&intel_dp->adapter);
  2106. drm_encoder_cleanup(encoder);
  2107. if (is_edp(intel_dp)) {
  2108. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  2109. ironlake_panel_vdd_off_sync(intel_dp);
  2110. }
  2111. kfree(intel_dig_port);
  2112. }
  2113. static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
  2114. .mode_set = intel_dp_mode_set,
  2115. };
  2116. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  2117. .dpms = intel_connector_dpms,
  2118. .detect = intel_dp_detect,
  2119. .fill_modes = drm_helper_probe_single_connector_modes,
  2120. .set_property = intel_dp_set_property,
  2121. .destroy = intel_dp_destroy,
  2122. };
  2123. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  2124. .get_modes = intel_dp_get_modes,
  2125. .mode_valid = intel_dp_mode_valid,
  2126. .best_encoder = intel_best_encoder,
  2127. };
  2128. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  2129. .destroy = intel_dp_encoder_destroy,
  2130. };
  2131. static void
  2132. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  2133. {
  2134. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2135. intel_dp_check_link_status(intel_dp);
  2136. }
  2137. /* Return which DP Port should be selected for Transcoder DP control */
  2138. int
  2139. intel_trans_dp_port_sel(struct drm_crtc *crtc)
  2140. {
  2141. struct drm_device *dev = crtc->dev;
  2142. struct intel_encoder *intel_encoder;
  2143. struct intel_dp *intel_dp;
  2144. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  2145. intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2146. if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
  2147. intel_encoder->type == INTEL_OUTPUT_EDP)
  2148. return intel_dp->output_reg;
  2149. }
  2150. return -1;
  2151. }
  2152. /* check the VBT to see whether the eDP is on DP-D port */
  2153. bool intel_dpd_is_edp(struct drm_device *dev)
  2154. {
  2155. struct drm_i915_private *dev_priv = dev->dev_private;
  2156. struct child_device_config *p_child;
  2157. int i;
  2158. if (!dev_priv->child_dev_num)
  2159. return false;
  2160. for (i = 0; i < dev_priv->child_dev_num; i++) {
  2161. p_child = dev_priv->child_dev + i;
  2162. if (p_child->dvo_port == PORT_IDPD &&
  2163. p_child->device_type == DEVICE_TYPE_eDP)
  2164. return true;
  2165. }
  2166. return false;
  2167. }
  2168. static void
  2169. intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
  2170. {
  2171. struct intel_connector *intel_connector = to_intel_connector(connector);
  2172. intel_attach_force_audio_property(connector);
  2173. intel_attach_broadcast_rgb_property(connector);
  2174. intel_dp->color_range_auto = true;
  2175. if (is_edp(intel_dp)) {
  2176. drm_mode_create_scaling_mode_property(connector->dev);
  2177. drm_object_attach_property(
  2178. &connector->base,
  2179. connector->dev->mode_config.scaling_mode_property,
  2180. DRM_MODE_SCALE_ASPECT);
  2181. intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
  2182. }
  2183. }
  2184. static void
  2185. intel_dp_init_panel_power_sequencer(struct drm_device *dev,
  2186. struct intel_dp *intel_dp,
  2187. struct edp_power_seq *out)
  2188. {
  2189. struct drm_i915_private *dev_priv = dev->dev_private;
  2190. struct edp_power_seq cur, vbt, spec, final;
  2191. u32 pp_on, pp_off, pp_div, pp;
  2192. int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
  2193. if (HAS_PCH_SPLIT(dev)) {
  2194. pp_control_reg = PCH_PP_CONTROL;
  2195. pp_on_reg = PCH_PP_ON_DELAYS;
  2196. pp_off_reg = PCH_PP_OFF_DELAYS;
  2197. pp_div_reg = PCH_PP_DIVISOR;
  2198. } else {
  2199. pp_control_reg = PIPEA_PP_CONTROL;
  2200. pp_on_reg = PIPEA_PP_ON_DELAYS;
  2201. pp_off_reg = PIPEA_PP_OFF_DELAYS;
  2202. pp_div_reg = PIPEA_PP_DIVISOR;
  2203. }
  2204. /* Workaround: Need to write PP_CONTROL with the unlock key as
  2205. * the very first thing. */
  2206. pp = ironlake_get_pp_control(intel_dp);
  2207. I915_WRITE(pp_control_reg, pp);
  2208. pp_on = I915_READ(pp_on_reg);
  2209. pp_off = I915_READ(pp_off_reg);
  2210. pp_div = I915_READ(pp_div_reg);
  2211. /* Pull timing values out of registers */
  2212. cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
  2213. PANEL_POWER_UP_DELAY_SHIFT;
  2214. cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
  2215. PANEL_LIGHT_ON_DELAY_SHIFT;
  2216. cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
  2217. PANEL_LIGHT_OFF_DELAY_SHIFT;
  2218. cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
  2219. PANEL_POWER_DOWN_DELAY_SHIFT;
  2220. cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
  2221. PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
  2222. DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2223. cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
  2224. vbt = dev_priv->edp.pps;
  2225. /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
  2226. * our hw here, which are all in 100usec. */
  2227. spec.t1_t3 = 210 * 10;
  2228. spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
  2229. spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
  2230. spec.t10 = 500 * 10;
  2231. /* This one is special and actually in units of 100ms, but zero
  2232. * based in the hw (so we need to add 100 ms). But the sw vbt
  2233. * table multiplies it with 1000 to make it in units of 100usec,
  2234. * too. */
  2235. spec.t11_t12 = (510 + 100) * 10;
  2236. DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2237. vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
  2238. /* Use the max of the register settings and vbt. If both are
  2239. * unset, fall back to the spec limits. */
  2240. #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
  2241. spec.field : \
  2242. max(cur.field, vbt.field))
  2243. assign_final(t1_t3);
  2244. assign_final(t8);
  2245. assign_final(t9);
  2246. assign_final(t10);
  2247. assign_final(t11_t12);
  2248. #undef assign_final
  2249. #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
  2250. intel_dp->panel_power_up_delay = get_delay(t1_t3);
  2251. intel_dp->backlight_on_delay = get_delay(t8);
  2252. intel_dp->backlight_off_delay = get_delay(t9);
  2253. intel_dp->panel_power_down_delay = get_delay(t10);
  2254. intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
  2255. #undef get_delay
  2256. DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
  2257. intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
  2258. intel_dp->panel_power_cycle_delay);
  2259. DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
  2260. intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
  2261. if (out)
  2262. *out = final;
  2263. }
  2264. static void
  2265. intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
  2266. struct intel_dp *intel_dp,
  2267. struct edp_power_seq *seq)
  2268. {
  2269. struct drm_i915_private *dev_priv = dev->dev_private;
  2270. u32 pp_on, pp_off, pp_div, port_sel = 0;
  2271. int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
  2272. int pp_on_reg, pp_off_reg, pp_div_reg;
  2273. if (HAS_PCH_SPLIT(dev)) {
  2274. pp_on_reg = PCH_PP_ON_DELAYS;
  2275. pp_off_reg = PCH_PP_OFF_DELAYS;
  2276. pp_div_reg = PCH_PP_DIVISOR;
  2277. } else {
  2278. pp_on_reg = PIPEA_PP_ON_DELAYS;
  2279. pp_off_reg = PIPEA_PP_OFF_DELAYS;
  2280. pp_div_reg = PIPEA_PP_DIVISOR;
  2281. }
  2282. if (IS_VALLEYVIEW(dev))
  2283. port_sel = I915_READ(pp_on_reg) & 0xc0000000;
  2284. /* And finally store the new values in the power sequencer. */
  2285. pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
  2286. (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
  2287. pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
  2288. (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
  2289. /* Compute the divisor for the pp clock, simply match the Bspec
  2290. * formula. */
  2291. pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
  2292. pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
  2293. << PANEL_POWER_CYCLE_DELAY_SHIFT);
  2294. /* Haswell doesn't have any port selection bits for the panel
  2295. * power sequencer any more. */
  2296. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
  2297. if (is_cpu_edp(intel_dp))
  2298. port_sel = PANEL_POWER_PORT_DP_A;
  2299. else
  2300. port_sel = PANEL_POWER_PORT_DP_D;
  2301. }
  2302. pp_on |= port_sel;
  2303. I915_WRITE(pp_on_reg, pp_on);
  2304. I915_WRITE(pp_off_reg, pp_off);
  2305. I915_WRITE(pp_div_reg, pp_div);
  2306. DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
  2307. I915_READ(pp_on_reg),
  2308. I915_READ(pp_off_reg),
  2309. I915_READ(pp_div_reg));
  2310. }
  2311. void
  2312. intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  2313. struct intel_connector *intel_connector)
  2314. {
  2315. struct drm_connector *connector = &intel_connector->base;
  2316. struct intel_dp *intel_dp = &intel_dig_port->dp;
  2317. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2318. struct drm_device *dev = intel_encoder->base.dev;
  2319. struct drm_i915_private *dev_priv = dev->dev_private;
  2320. struct drm_display_mode *fixed_mode = NULL;
  2321. struct edp_power_seq power_seq = { 0 };
  2322. enum port port = intel_dig_port->port;
  2323. const char *name = NULL;
  2324. int type;
  2325. /* Preserve the current hw state. */
  2326. intel_dp->DP = I915_READ(intel_dp->output_reg);
  2327. intel_dp->attached_connector = intel_connector;
  2328. if (HAS_PCH_SPLIT(dev) && port == PORT_D)
  2329. if (intel_dpd_is_edp(dev))
  2330. intel_dp->is_pch_edp = true;
  2331. /*
  2332. * FIXME : We need to initialize built-in panels before external panels.
  2333. * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
  2334. */
  2335. if (IS_VALLEYVIEW(dev) && port == PORT_C) {
  2336. type = DRM_MODE_CONNECTOR_eDP;
  2337. intel_encoder->type = INTEL_OUTPUT_EDP;
  2338. } else if (port == PORT_A || is_pch_edp(intel_dp)) {
  2339. type = DRM_MODE_CONNECTOR_eDP;
  2340. intel_encoder->type = INTEL_OUTPUT_EDP;
  2341. } else {
  2342. /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
  2343. * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
  2344. * rewrite it.
  2345. */
  2346. type = DRM_MODE_CONNECTOR_DisplayPort;
  2347. }
  2348. drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
  2349. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  2350. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2351. connector->interlace_allowed = true;
  2352. connector->doublescan_allowed = 0;
  2353. INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
  2354. ironlake_panel_vdd_work);
  2355. intel_connector_attach_encoder(intel_connector, intel_encoder);
  2356. drm_sysfs_connector_add(connector);
  2357. if (HAS_DDI(dev))
  2358. intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  2359. else
  2360. intel_connector->get_hw_state = intel_connector_get_hw_state;
  2361. intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
  2362. if (HAS_DDI(dev)) {
  2363. switch (intel_dig_port->port) {
  2364. case PORT_A:
  2365. intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
  2366. break;
  2367. case PORT_B:
  2368. intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
  2369. break;
  2370. case PORT_C:
  2371. intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
  2372. break;
  2373. case PORT_D:
  2374. intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
  2375. break;
  2376. default:
  2377. BUG();
  2378. }
  2379. }
  2380. /* Set up the DDC bus. */
  2381. switch (port) {
  2382. case PORT_A:
  2383. intel_encoder->hpd_pin = HPD_PORT_A;
  2384. name = "DPDDC-A";
  2385. break;
  2386. case PORT_B:
  2387. intel_encoder->hpd_pin = HPD_PORT_B;
  2388. name = "DPDDC-B";
  2389. break;
  2390. case PORT_C:
  2391. intel_encoder->hpd_pin = HPD_PORT_C;
  2392. name = "DPDDC-C";
  2393. break;
  2394. case PORT_D:
  2395. intel_encoder->hpd_pin = HPD_PORT_D;
  2396. name = "DPDDC-D";
  2397. break;
  2398. default:
  2399. BUG();
  2400. }
  2401. if (is_edp(intel_dp))
  2402. intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
  2403. intel_dp_i2c_init(intel_dp, intel_connector, name);
  2404. /* Cache DPCD and EDID for edp. */
  2405. if (is_edp(intel_dp)) {
  2406. bool ret;
  2407. struct drm_display_mode *scan;
  2408. struct edid *edid;
  2409. ironlake_edp_panel_vdd_on(intel_dp);
  2410. ret = intel_dp_get_dpcd(intel_dp);
  2411. ironlake_edp_panel_vdd_off(intel_dp, false);
  2412. if (ret) {
  2413. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
  2414. dev_priv->no_aux_handshake =
  2415. intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
  2416. DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
  2417. } else {
  2418. /* if this fails, presume the device is a ghost */
  2419. DRM_INFO("failed to retrieve link info, disabling eDP\n");
  2420. intel_dp_encoder_destroy(&intel_encoder->base);
  2421. intel_dp_destroy(connector);
  2422. return;
  2423. }
  2424. /* We now know it's not a ghost, init power sequence regs. */
  2425. intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
  2426. &power_seq);
  2427. ironlake_edp_panel_vdd_on(intel_dp);
  2428. edid = drm_get_edid(connector, &intel_dp->adapter);
  2429. if (edid) {
  2430. if (drm_add_edid_modes(connector, edid)) {
  2431. drm_mode_connector_update_edid_property(connector, edid);
  2432. drm_edid_to_eld(connector, edid);
  2433. } else {
  2434. kfree(edid);
  2435. edid = ERR_PTR(-EINVAL);
  2436. }
  2437. } else {
  2438. edid = ERR_PTR(-ENOENT);
  2439. }
  2440. intel_connector->edid = edid;
  2441. /* prefer fixed mode from EDID if available */
  2442. list_for_each_entry(scan, &connector->probed_modes, head) {
  2443. if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
  2444. fixed_mode = drm_mode_duplicate(dev, scan);
  2445. break;
  2446. }
  2447. }
  2448. /* fallback to VBT if available for eDP */
  2449. if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
  2450. fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  2451. if (fixed_mode)
  2452. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  2453. }
  2454. ironlake_edp_panel_vdd_off(intel_dp, false);
  2455. }
  2456. if (is_edp(intel_dp)) {
  2457. intel_panel_init(&intel_connector->panel, fixed_mode);
  2458. intel_panel_setup_backlight(connector);
  2459. }
  2460. intel_dp_add_properties(intel_dp, connector);
  2461. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  2462. * 0xd. Failure to do so will result in spurious interrupts being
  2463. * generated on the port when a cable is not attached.
  2464. */
  2465. if (IS_G4X(dev) && !IS_GM45(dev)) {
  2466. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  2467. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  2468. }
  2469. }
  2470. void
  2471. intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
  2472. {
  2473. struct intel_digital_port *intel_dig_port;
  2474. struct intel_encoder *intel_encoder;
  2475. struct drm_encoder *encoder;
  2476. struct intel_connector *intel_connector;
  2477. intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
  2478. if (!intel_dig_port)
  2479. return;
  2480. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  2481. if (!intel_connector) {
  2482. kfree(intel_dig_port);
  2483. return;
  2484. }
  2485. intel_encoder = &intel_dig_port->base;
  2486. encoder = &intel_encoder->base;
  2487. drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
  2488. DRM_MODE_ENCODER_TMDS);
  2489. drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
  2490. intel_encoder->compute_config = intel_dp_compute_config;
  2491. intel_encoder->enable = intel_enable_dp;
  2492. intel_encoder->pre_enable = intel_pre_enable_dp;
  2493. intel_encoder->disable = intel_disable_dp;
  2494. intel_encoder->post_disable = intel_post_disable_dp;
  2495. intel_encoder->get_hw_state = intel_dp_get_hw_state;
  2496. intel_dig_port->port = port;
  2497. intel_dig_port->dp.output_reg = output_reg;
  2498. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  2499. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2500. intel_encoder->cloneable = false;
  2501. intel_encoder->hot_plug = intel_dp_hot_plug;
  2502. intel_dp_init_connector(intel_dig_port, intel_connector);
  2503. }