i915_irq.c 83 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/sysrq.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. static const u32 hpd_ibx[] = {
  37. [HPD_CRT] = SDE_CRT_HOTPLUG,
  38. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  39. [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  40. [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  41. [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  42. };
  43. static const u32 hpd_cpt[] = {
  44. [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  45. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  46. [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  47. [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  48. [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  49. };
  50. static const u32 hpd_mask_i915[] = {
  51. [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  52. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  53. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  54. [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  55. [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  56. [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  57. };
  58. static const u32 hpd_status_gen4[] = {
  59. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  60. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  61. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  62. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  63. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  64. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  65. };
  66. static const u32 hpd_status_i965[] = {
  67. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  68. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  69. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  70. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  71. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  72. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  73. };
  74. static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81. };
  82. /* For display hotplug interrupt */
  83. static void
  84. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  85. {
  86. if ((dev_priv->irq_mask & mask) != 0) {
  87. dev_priv->irq_mask &= ~mask;
  88. I915_WRITE(DEIMR, dev_priv->irq_mask);
  89. POSTING_READ(DEIMR);
  90. }
  91. }
  92. static void
  93. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  94. {
  95. if ((dev_priv->irq_mask & mask) != mask) {
  96. dev_priv->irq_mask |= mask;
  97. I915_WRITE(DEIMR, dev_priv->irq_mask);
  98. POSTING_READ(DEIMR);
  99. }
  100. }
  101. void
  102. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  103. {
  104. u32 reg = PIPESTAT(pipe);
  105. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  106. if ((pipestat & mask) == mask)
  107. return;
  108. /* Enable the interrupt, clear any pending status */
  109. pipestat |= mask | (mask >> 16);
  110. I915_WRITE(reg, pipestat);
  111. POSTING_READ(reg);
  112. }
  113. void
  114. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  115. {
  116. u32 reg = PIPESTAT(pipe);
  117. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  118. if ((pipestat & mask) == 0)
  119. return;
  120. pipestat &= ~mask;
  121. I915_WRITE(reg, pipestat);
  122. POSTING_READ(reg);
  123. }
  124. /**
  125. * intel_enable_asle - enable ASLE interrupt for OpRegion
  126. */
  127. void intel_enable_asle(struct drm_device *dev)
  128. {
  129. drm_i915_private_t *dev_priv = dev->dev_private;
  130. unsigned long irqflags;
  131. /* FIXME: opregion/asle for VLV */
  132. if (IS_VALLEYVIEW(dev))
  133. return;
  134. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  135. if (HAS_PCH_SPLIT(dev))
  136. ironlake_enable_display_irq(dev_priv, DE_GSE);
  137. else {
  138. i915_enable_pipestat(dev_priv, 1,
  139. PIPE_LEGACY_BLC_EVENT_ENABLE);
  140. if (INTEL_INFO(dev)->gen >= 4)
  141. i915_enable_pipestat(dev_priv, 0,
  142. PIPE_LEGACY_BLC_EVENT_ENABLE);
  143. }
  144. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  145. }
  146. /**
  147. * i915_pipe_enabled - check if a pipe is enabled
  148. * @dev: DRM device
  149. * @pipe: pipe to check
  150. *
  151. * Reading certain registers when the pipe is disabled can hang the chip.
  152. * Use this routine to make sure the PLL is running and the pipe is active
  153. * before reading such registers if unsure.
  154. */
  155. static int
  156. i915_pipe_enabled(struct drm_device *dev, int pipe)
  157. {
  158. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  159. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  160. pipe);
  161. return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
  162. }
  163. /* Called from drm generic code, passed a 'crtc', which
  164. * we use as a pipe index
  165. */
  166. static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  167. {
  168. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  169. unsigned long high_frame;
  170. unsigned long low_frame;
  171. u32 high1, high2, low;
  172. if (!i915_pipe_enabled(dev, pipe)) {
  173. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  174. "pipe %c\n", pipe_name(pipe));
  175. return 0;
  176. }
  177. high_frame = PIPEFRAME(pipe);
  178. low_frame = PIPEFRAMEPIXEL(pipe);
  179. /*
  180. * High & low register fields aren't synchronized, so make sure
  181. * we get a low value that's stable across two reads of the high
  182. * register.
  183. */
  184. do {
  185. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  186. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  187. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  188. } while (high1 != high2);
  189. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  190. low >>= PIPE_FRAME_LOW_SHIFT;
  191. return (high1 << 8) | low;
  192. }
  193. static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  194. {
  195. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  196. int reg = PIPE_FRMCOUNT_GM45(pipe);
  197. if (!i915_pipe_enabled(dev, pipe)) {
  198. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  199. "pipe %c\n", pipe_name(pipe));
  200. return 0;
  201. }
  202. return I915_READ(reg);
  203. }
  204. static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
  205. int *vpos, int *hpos)
  206. {
  207. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  208. u32 vbl = 0, position = 0;
  209. int vbl_start, vbl_end, htotal, vtotal;
  210. bool in_vbl = true;
  211. int ret = 0;
  212. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  213. pipe);
  214. if (!i915_pipe_enabled(dev, pipe)) {
  215. DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  216. "pipe %c\n", pipe_name(pipe));
  217. return 0;
  218. }
  219. /* Get vtotal. */
  220. vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  221. if (INTEL_INFO(dev)->gen >= 4) {
  222. /* No obvious pixelcount register. Only query vertical
  223. * scanout position from Display scan line register.
  224. */
  225. position = I915_READ(PIPEDSL(pipe));
  226. /* Decode into vertical scanout position. Don't have
  227. * horizontal scanout position.
  228. */
  229. *vpos = position & 0x1fff;
  230. *hpos = 0;
  231. } else {
  232. /* Have access to pixelcount since start of frame.
  233. * We can split this into vertical and horizontal
  234. * scanout position.
  235. */
  236. position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  237. htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  238. *vpos = position / htotal;
  239. *hpos = position - (*vpos * htotal);
  240. }
  241. /* Query vblank area. */
  242. vbl = I915_READ(VBLANK(cpu_transcoder));
  243. /* Test position against vblank region. */
  244. vbl_start = vbl & 0x1fff;
  245. vbl_end = (vbl >> 16) & 0x1fff;
  246. if ((*vpos < vbl_start) || (*vpos > vbl_end))
  247. in_vbl = false;
  248. /* Inside "upper part" of vblank area? Apply corrective offset: */
  249. if (in_vbl && (*vpos >= vbl_start))
  250. *vpos = *vpos - vtotal;
  251. /* Readouts valid? */
  252. if (vbl > 0)
  253. ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  254. /* In vblank? */
  255. if (in_vbl)
  256. ret |= DRM_SCANOUTPOS_INVBL;
  257. return ret;
  258. }
  259. static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
  260. int *max_error,
  261. struct timeval *vblank_time,
  262. unsigned flags)
  263. {
  264. struct drm_crtc *crtc;
  265. if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
  266. DRM_ERROR("Invalid crtc %d\n", pipe);
  267. return -EINVAL;
  268. }
  269. /* Get drm_crtc to timestamp: */
  270. crtc = intel_get_crtc_for_pipe(dev, pipe);
  271. if (crtc == NULL) {
  272. DRM_ERROR("Invalid crtc %d\n", pipe);
  273. return -EINVAL;
  274. }
  275. if (!crtc->enabled) {
  276. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  277. return -EBUSY;
  278. }
  279. /* Helper routine in DRM core does all the work: */
  280. return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  281. vblank_time, flags,
  282. crtc);
  283. }
  284. /*
  285. * Handle hotplug events outside the interrupt handler proper.
  286. */
  287. static void i915_hotplug_work_func(struct work_struct *work)
  288. {
  289. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  290. hotplug_work);
  291. struct drm_device *dev = dev_priv->dev;
  292. struct drm_mode_config *mode_config = &dev->mode_config;
  293. struct intel_encoder *encoder;
  294. /* HPD irq before everything is fully set up. */
  295. if (!dev_priv->enable_hotplug_processing)
  296. return;
  297. mutex_lock(&mode_config->mutex);
  298. DRM_DEBUG_KMS("running encoder hotplug functions\n");
  299. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  300. if (encoder->hot_plug)
  301. encoder->hot_plug(encoder);
  302. mutex_unlock(&mode_config->mutex);
  303. /* Just fire off a uevent and let userspace tell us what to do */
  304. drm_helper_hpd_irq_event(dev);
  305. }
  306. static void ironlake_handle_rps_change(struct drm_device *dev)
  307. {
  308. drm_i915_private_t *dev_priv = dev->dev_private;
  309. u32 busy_up, busy_down, max_avg, min_avg;
  310. u8 new_delay;
  311. unsigned long flags;
  312. spin_lock_irqsave(&mchdev_lock, flags);
  313. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  314. new_delay = dev_priv->ips.cur_delay;
  315. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  316. busy_up = I915_READ(RCPREVBSYTUPAVG);
  317. busy_down = I915_READ(RCPREVBSYTDNAVG);
  318. max_avg = I915_READ(RCBMAXAVG);
  319. min_avg = I915_READ(RCBMINAVG);
  320. /* Handle RCS change request from hw */
  321. if (busy_up > max_avg) {
  322. if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  323. new_delay = dev_priv->ips.cur_delay - 1;
  324. if (new_delay < dev_priv->ips.max_delay)
  325. new_delay = dev_priv->ips.max_delay;
  326. } else if (busy_down < min_avg) {
  327. if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  328. new_delay = dev_priv->ips.cur_delay + 1;
  329. if (new_delay > dev_priv->ips.min_delay)
  330. new_delay = dev_priv->ips.min_delay;
  331. }
  332. if (ironlake_set_drps(dev, new_delay))
  333. dev_priv->ips.cur_delay = new_delay;
  334. spin_unlock_irqrestore(&mchdev_lock, flags);
  335. return;
  336. }
  337. static void notify_ring(struct drm_device *dev,
  338. struct intel_ring_buffer *ring)
  339. {
  340. struct drm_i915_private *dev_priv = dev->dev_private;
  341. if (ring->obj == NULL)
  342. return;
  343. trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
  344. wake_up_all(&ring->irq_queue);
  345. if (i915_enable_hangcheck) {
  346. dev_priv->gpu_error.hangcheck_count = 0;
  347. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  348. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  349. }
  350. }
  351. static void gen6_pm_rps_work(struct work_struct *work)
  352. {
  353. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  354. rps.work);
  355. u32 pm_iir, pm_imr;
  356. u8 new_delay;
  357. spin_lock_irq(&dev_priv->rps.lock);
  358. pm_iir = dev_priv->rps.pm_iir;
  359. dev_priv->rps.pm_iir = 0;
  360. pm_imr = I915_READ(GEN6_PMIMR);
  361. I915_WRITE(GEN6_PMIMR, 0);
  362. spin_unlock_irq(&dev_priv->rps.lock);
  363. if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
  364. return;
  365. mutex_lock(&dev_priv->rps.hw_lock);
  366. if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
  367. new_delay = dev_priv->rps.cur_delay + 1;
  368. else
  369. new_delay = dev_priv->rps.cur_delay - 1;
  370. /* sysfs frequency interfaces may have snuck in while servicing the
  371. * interrupt
  372. */
  373. if (!(new_delay > dev_priv->rps.max_delay ||
  374. new_delay < dev_priv->rps.min_delay)) {
  375. gen6_set_rps(dev_priv->dev, new_delay);
  376. }
  377. mutex_unlock(&dev_priv->rps.hw_lock);
  378. }
  379. /**
  380. * ivybridge_parity_work - Workqueue called when a parity error interrupt
  381. * occurred.
  382. * @work: workqueue struct
  383. *
  384. * Doesn't actually do anything except notify userspace. As a consequence of
  385. * this event, userspace should try to remap the bad rows since statistically
  386. * it is likely the same row is more likely to go bad again.
  387. */
  388. static void ivybridge_parity_work(struct work_struct *work)
  389. {
  390. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  391. l3_parity.error_work);
  392. u32 error_status, row, bank, subbank;
  393. char *parity_event[5];
  394. uint32_t misccpctl;
  395. unsigned long flags;
  396. /* We must turn off DOP level clock gating to access the L3 registers.
  397. * In order to prevent a get/put style interface, acquire struct mutex
  398. * any time we access those registers.
  399. */
  400. mutex_lock(&dev_priv->dev->struct_mutex);
  401. misccpctl = I915_READ(GEN7_MISCCPCTL);
  402. I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  403. POSTING_READ(GEN7_MISCCPCTL);
  404. error_status = I915_READ(GEN7_L3CDERRST1);
  405. row = GEN7_PARITY_ERROR_ROW(error_status);
  406. bank = GEN7_PARITY_ERROR_BANK(error_status);
  407. subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  408. I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
  409. GEN7_L3CDERRST1_ENABLE);
  410. POSTING_READ(GEN7_L3CDERRST1);
  411. I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  412. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  413. dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  414. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  415. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  416. mutex_unlock(&dev_priv->dev->struct_mutex);
  417. parity_event[0] = "L3_PARITY_ERROR=1";
  418. parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
  419. parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
  420. parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
  421. parity_event[4] = NULL;
  422. kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
  423. KOBJ_CHANGE, parity_event);
  424. DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
  425. row, bank, subbank);
  426. kfree(parity_event[3]);
  427. kfree(parity_event[2]);
  428. kfree(parity_event[1]);
  429. }
  430. static void ivybridge_handle_parity_error(struct drm_device *dev)
  431. {
  432. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  433. unsigned long flags;
  434. if (!HAS_L3_GPU_CACHE(dev))
  435. return;
  436. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  437. dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  438. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  439. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  440. queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
  441. }
  442. static void snb_gt_irq_handler(struct drm_device *dev,
  443. struct drm_i915_private *dev_priv,
  444. u32 gt_iir)
  445. {
  446. if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
  447. GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
  448. notify_ring(dev, &dev_priv->ring[RCS]);
  449. if (gt_iir & GEN6_BSD_USER_INTERRUPT)
  450. notify_ring(dev, &dev_priv->ring[VCS]);
  451. if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
  452. notify_ring(dev, &dev_priv->ring[BCS]);
  453. if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
  454. GT_GEN6_BSD_CS_ERROR_INTERRUPT |
  455. GT_RENDER_CS_ERROR_INTERRUPT)) {
  456. DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
  457. i915_handle_error(dev, false);
  458. }
  459. if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
  460. ivybridge_handle_parity_error(dev);
  461. }
  462. static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
  463. u32 pm_iir)
  464. {
  465. unsigned long flags;
  466. /*
  467. * IIR bits should never already be set because IMR should
  468. * prevent an interrupt from being shown in IIR. The warning
  469. * displays a case where we've unsafely cleared
  470. * dev_priv->rps.pm_iir. Although missing an interrupt of the same
  471. * type is not a problem, it displays a problem in the logic.
  472. *
  473. * The mask bit in IMR is cleared by dev_priv->rps.work.
  474. */
  475. spin_lock_irqsave(&dev_priv->rps.lock, flags);
  476. dev_priv->rps.pm_iir |= pm_iir;
  477. I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
  478. POSTING_READ(GEN6_PMIMR);
  479. spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  480. queue_work(dev_priv->wq, &dev_priv->rps.work);
  481. }
  482. static void gmbus_irq_handler(struct drm_device *dev)
  483. {
  484. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  485. wake_up_all(&dev_priv->gmbus_wait_queue);
  486. }
  487. static void dp_aux_irq_handler(struct drm_device *dev)
  488. {
  489. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  490. wake_up_all(&dev_priv->gmbus_wait_queue);
  491. }
  492. static irqreturn_t valleyview_irq_handler(int irq, void *arg)
  493. {
  494. struct drm_device *dev = (struct drm_device *) arg;
  495. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  496. u32 iir, gt_iir, pm_iir;
  497. irqreturn_t ret = IRQ_NONE;
  498. unsigned long irqflags;
  499. int pipe;
  500. u32 pipe_stats[I915_MAX_PIPES];
  501. atomic_inc(&dev_priv->irq_received);
  502. while (true) {
  503. iir = I915_READ(VLV_IIR);
  504. gt_iir = I915_READ(GTIIR);
  505. pm_iir = I915_READ(GEN6_PMIIR);
  506. if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  507. goto out;
  508. ret = IRQ_HANDLED;
  509. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  510. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  511. for_each_pipe(pipe) {
  512. int reg = PIPESTAT(pipe);
  513. pipe_stats[pipe] = I915_READ(reg);
  514. /*
  515. * Clear the PIPE*STAT regs before the IIR
  516. */
  517. if (pipe_stats[pipe] & 0x8000ffff) {
  518. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  519. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  520. pipe_name(pipe));
  521. I915_WRITE(reg, pipe_stats[pipe]);
  522. }
  523. }
  524. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  525. for_each_pipe(pipe) {
  526. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
  527. drm_handle_vblank(dev, pipe);
  528. if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
  529. intel_prepare_page_flip(dev, pipe);
  530. intel_finish_page_flip(dev, pipe);
  531. }
  532. }
  533. /* Consume port. Then clear IIR or we'll miss events */
  534. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  535. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  536. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  537. hotplug_status);
  538. if (hotplug_status & HOTPLUG_INT_STATUS_I915)
  539. queue_work(dev_priv->wq,
  540. &dev_priv->hotplug_work);
  541. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  542. I915_READ(PORT_HOTPLUG_STAT);
  543. }
  544. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  545. gmbus_irq_handler(dev);
  546. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  547. gen6_queue_rps_work(dev_priv, pm_iir);
  548. I915_WRITE(GTIIR, gt_iir);
  549. I915_WRITE(GEN6_PMIIR, pm_iir);
  550. I915_WRITE(VLV_IIR, iir);
  551. }
  552. out:
  553. return ret;
  554. }
  555. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  556. {
  557. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  558. int pipe;
  559. if (pch_iir & SDE_HOTPLUG_MASK)
  560. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  561. if (pch_iir & SDE_AUDIO_POWER_MASK)
  562. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  563. (pch_iir & SDE_AUDIO_POWER_MASK) >>
  564. SDE_AUDIO_POWER_SHIFT);
  565. if (pch_iir & SDE_AUX_MASK)
  566. dp_aux_irq_handler(dev);
  567. if (pch_iir & SDE_GMBUS)
  568. gmbus_irq_handler(dev);
  569. if (pch_iir & SDE_AUDIO_HDCP_MASK)
  570. DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  571. if (pch_iir & SDE_AUDIO_TRANS_MASK)
  572. DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  573. if (pch_iir & SDE_POISON)
  574. DRM_ERROR("PCH poison interrupt\n");
  575. if (pch_iir & SDE_FDI_MASK)
  576. for_each_pipe(pipe)
  577. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  578. pipe_name(pipe),
  579. I915_READ(FDI_RX_IIR(pipe)));
  580. if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  581. DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  582. if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  583. DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  584. if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  585. DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
  586. if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  587. DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
  588. }
  589. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  590. {
  591. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  592. int pipe;
  593. if (pch_iir & SDE_HOTPLUG_MASK_CPT)
  594. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  595. if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
  596. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  597. (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  598. SDE_AUDIO_POWER_SHIFT_CPT);
  599. if (pch_iir & SDE_AUX_MASK_CPT)
  600. dp_aux_irq_handler(dev);
  601. if (pch_iir & SDE_GMBUS_CPT)
  602. gmbus_irq_handler(dev);
  603. if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  604. DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  605. if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  606. DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  607. if (pch_iir & SDE_FDI_MASK_CPT)
  608. for_each_pipe(pipe)
  609. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  610. pipe_name(pipe),
  611. I915_READ(FDI_RX_IIR(pipe)));
  612. }
  613. static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
  614. {
  615. struct drm_device *dev = (struct drm_device *) arg;
  616. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  617. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
  618. irqreturn_t ret = IRQ_NONE;
  619. int i;
  620. atomic_inc(&dev_priv->irq_received);
  621. /* disable master interrupt before clearing iir */
  622. de_ier = I915_READ(DEIER);
  623. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  624. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  625. * interrupts will will be stored on its back queue, and then we'll be
  626. * able to process them after we restore SDEIER (as soon as we restore
  627. * it, we'll get an interrupt if SDEIIR still has something to process
  628. * due to its back queue). */
  629. if (!HAS_PCH_NOP(dev)) {
  630. sde_ier = I915_READ(SDEIER);
  631. I915_WRITE(SDEIER, 0);
  632. POSTING_READ(SDEIER);
  633. }
  634. gt_iir = I915_READ(GTIIR);
  635. if (gt_iir) {
  636. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  637. I915_WRITE(GTIIR, gt_iir);
  638. ret = IRQ_HANDLED;
  639. }
  640. de_iir = I915_READ(DEIIR);
  641. if (de_iir) {
  642. if (de_iir & DE_AUX_CHANNEL_A_IVB)
  643. dp_aux_irq_handler(dev);
  644. if (de_iir & DE_GSE_IVB)
  645. intel_opregion_gse_intr(dev);
  646. for (i = 0; i < 3; i++) {
  647. if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
  648. drm_handle_vblank(dev, i);
  649. if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
  650. intel_prepare_page_flip(dev, i);
  651. intel_finish_page_flip_plane(dev, i);
  652. }
  653. }
  654. /* check event from PCH */
  655. if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
  656. u32 pch_iir = I915_READ(SDEIIR);
  657. cpt_irq_handler(dev, pch_iir);
  658. /* clear PCH hotplug event before clear CPU irq */
  659. I915_WRITE(SDEIIR, pch_iir);
  660. }
  661. I915_WRITE(DEIIR, de_iir);
  662. ret = IRQ_HANDLED;
  663. }
  664. pm_iir = I915_READ(GEN6_PMIIR);
  665. if (pm_iir) {
  666. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  667. gen6_queue_rps_work(dev_priv, pm_iir);
  668. I915_WRITE(GEN6_PMIIR, pm_iir);
  669. ret = IRQ_HANDLED;
  670. }
  671. I915_WRITE(DEIER, de_ier);
  672. POSTING_READ(DEIER);
  673. if (!HAS_PCH_NOP(dev)) {
  674. I915_WRITE(SDEIER, sde_ier);
  675. POSTING_READ(SDEIER);
  676. }
  677. return ret;
  678. }
  679. static void ilk_gt_irq_handler(struct drm_device *dev,
  680. struct drm_i915_private *dev_priv,
  681. u32 gt_iir)
  682. {
  683. if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
  684. notify_ring(dev, &dev_priv->ring[RCS]);
  685. if (gt_iir & GT_BSD_USER_INTERRUPT)
  686. notify_ring(dev, &dev_priv->ring[VCS]);
  687. }
  688. static irqreturn_t ironlake_irq_handler(int irq, void *arg)
  689. {
  690. struct drm_device *dev = (struct drm_device *) arg;
  691. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  692. int ret = IRQ_NONE;
  693. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
  694. atomic_inc(&dev_priv->irq_received);
  695. /* disable master interrupt before clearing iir */
  696. de_ier = I915_READ(DEIER);
  697. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  698. POSTING_READ(DEIER);
  699. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  700. * interrupts will will be stored on its back queue, and then we'll be
  701. * able to process them after we restore SDEIER (as soon as we restore
  702. * it, we'll get an interrupt if SDEIIR still has something to process
  703. * due to its back queue). */
  704. sde_ier = I915_READ(SDEIER);
  705. I915_WRITE(SDEIER, 0);
  706. POSTING_READ(SDEIER);
  707. de_iir = I915_READ(DEIIR);
  708. gt_iir = I915_READ(GTIIR);
  709. pm_iir = I915_READ(GEN6_PMIIR);
  710. if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
  711. goto done;
  712. ret = IRQ_HANDLED;
  713. if (IS_GEN5(dev))
  714. ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  715. else
  716. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  717. if (de_iir & DE_AUX_CHANNEL_A)
  718. dp_aux_irq_handler(dev);
  719. if (de_iir & DE_GSE)
  720. intel_opregion_gse_intr(dev);
  721. if (de_iir & DE_PIPEA_VBLANK)
  722. drm_handle_vblank(dev, 0);
  723. if (de_iir & DE_PIPEB_VBLANK)
  724. drm_handle_vblank(dev, 1);
  725. if (de_iir & DE_PLANEA_FLIP_DONE) {
  726. intel_prepare_page_flip(dev, 0);
  727. intel_finish_page_flip_plane(dev, 0);
  728. }
  729. if (de_iir & DE_PLANEB_FLIP_DONE) {
  730. intel_prepare_page_flip(dev, 1);
  731. intel_finish_page_flip_plane(dev, 1);
  732. }
  733. /* check event from PCH */
  734. if (de_iir & DE_PCH_EVENT) {
  735. u32 pch_iir = I915_READ(SDEIIR);
  736. if (HAS_PCH_CPT(dev))
  737. cpt_irq_handler(dev, pch_iir);
  738. else
  739. ibx_irq_handler(dev, pch_iir);
  740. /* should clear PCH hotplug event before clear CPU irq */
  741. I915_WRITE(SDEIIR, pch_iir);
  742. }
  743. if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  744. ironlake_handle_rps_change(dev);
  745. if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
  746. gen6_queue_rps_work(dev_priv, pm_iir);
  747. I915_WRITE(GTIIR, gt_iir);
  748. I915_WRITE(DEIIR, de_iir);
  749. I915_WRITE(GEN6_PMIIR, pm_iir);
  750. done:
  751. I915_WRITE(DEIER, de_ier);
  752. POSTING_READ(DEIER);
  753. I915_WRITE(SDEIER, sde_ier);
  754. POSTING_READ(SDEIER);
  755. return ret;
  756. }
  757. /**
  758. * i915_error_work_func - do process context error handling work
  759. * @work: work struct
  760. *
  761. * Fire an error uevent so userspace can see that a hang or error
  762. * was detected.
  763. */
  764. static void i915_error_work_func(struct work_struct *work)
  765. {
  766. struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
  767. work);
  768. drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
  769. gpu_error);
  770. struct drm_device *dev = dev_priv->dev;
  771. struct intel_ring_buffer *ring;
  772. char *error_event[] = { "ERROR=1", NULL };
  773. char *reset_event[] = { "RESET=1", NULL };
  774. char *reset_done_event[] = { "ERROR=0", NULL };
  775. int i, ret;
  776. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  777. /*
  778. * Note that there's only one work item which does gpu resets, so we
  779. * need not worry about concurrent gpu resets potentially incrementing
  780. * error->reset_counter twice. We only need to take care of another
  781. * racing irq/hangcheck declaring the gpu dead for a second time. A
  782. * quick check for that is good enough: schedule_work ensures the
  783. * correct ordering between hang detection and this work item, and since
  784. * the reset in-progress bit is only ever set by code outside of this
  785. * work we don't need to worry about any other races.
  786. */
  787. if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
  788. DRM_DEBUG_DRIVER("resetting chip\n");
  789. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
  790. reset_event);
  791. ret = i915_reset(dev);
  792. if (ret == 0) {
  793. /*
  794. * After all the gem state is reset, increment the reset
  795. * counter and wake up everyone waiting for the reset to
  796. * complete.
  797. *
  798. * Since unlock operations are a one-sided barrier only,
  799. * we need to insert a barrier here to order any seqno
  800. * updates before
  801. * the counter increment.
  802. */
  803. smp_mb__before_atomic_inc();
  804. atomic_inc(&dev_priv->gpu_error.reset_counter);
  805. kobject_uevent_env(&dev->primary->kdev.kobj,
  806. KOBJ_CHANGE, reset_done_event);
  807. } else {
  808. atomic_set(&error->reset_counter, I915_WEDGED);
  809. }
  810. for_each_ring(ring, dev_priv, i)
  811. wake_up_all(&ring->irq_queue);
  812. intel_display_handle_reset(dev);
  813. wake_up_all(&dev_priv->gpu_error.reset_queue);
  814. }
  815. }
  816. /* NB: please notice the memset */
  817. static void i915_get_extra_instdone(struct drm_device *dev,
  818. uint32_t *instdone)
  819. {
  820. struct drm_i915_private *dev_priv = dev->dev_private;
  821. memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
  822. switch(INTEL_INFO(dev)->gen) {
  823. case 2:
  824. case 3:
  825. instdone[0] = I915_READ(INSTDONE);
  826. break;
  827. case 4:
  828. case 5:
  829. case 6:
  830. instdone[0] = I915_READ(INSTDONE_I965);
  831. instdone[1] = I915_READ(INSTDONE1);
  832. break;
  833. default:
  834. WARN_ONCE(1, "Unsupported platform\n");
  835. case 7:
  836. instdone[0] = I915_READ(GEN7_INSTDONE_1);
  837. instdone[1] = I915_READ(GEN7_SC_INSTDONE);
  838. instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
  839. instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
  840. break;
  841. }
  842. }
  843. #ifdef CONFIG_DEBUG_FS
  844. static struct drm_i915_error_object *
  845. i915_error_object_create_sized(struct drm_i915_private *dev_priv,
  846. struct drm_i915_gem_object *src,
  847. const int num_pages)
  848. {
  849. struct drm_i915_error_object *dst;
  850. int i;
  851. u32 reloc_offset;
  852. if (src == NULL || src->pages == NULL)
  853. return NULL;
  854. dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
  855. if (dst == NULL)
  856. return NULL;
  857. reloc_offset = src->gtt_offset;
  858. for (i = 0; i < num_pages; i++) {
  859. unsigned long flags;
  860. void *d;
  861. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  862. if (d == NULL)
  863. goto unwind;
  864. local_irq_save(flags);
  865. if (reloc_offset < dev_priv->gtt.mappable_end &&
  866. src->has_global_gtt_mapping) {
  867. void __iomem *s;
  868. /* Simply ignore tiling or any overlapping fence.
  869. * It's part of the error state, and this hopefully
  870. * captures what the GPU read.
  871. */
  872. s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  873. reloc_offset);
  874. memcpy_fromio(d, s, PAGE_SIZE);
  875. io_mapping_unmap_atomic(s);
  876. } else if (src->stolen) {
  877. unsigned long offset;
  878. offset = dev_priv->mm.stolen_base;
  879. offset += src->stolen->start;
  880. offset += i << PAGE_SHIFT;
  881. memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
  882. } else {
  883. struct page *page;
  884. void *s;
  885. page = i915_gem_object_get_page(src, i);
  886. drm_clflush_pages(&page, 1);
  887. s = kmap_atomic(page);
  888. memcpy(d, s, PAGE_SIZE);
  889. kunmap_atomic(s);
  890. drm_clflush_pages(&page, 1);
  891. }
  892. local_irq_restore(flags);
  893. dst->pages[i] = d;
  894. reloc_offset += PAGE_SIZE;
  895. }
  896. dst->page_count = num_pages;
  897. dst->gtt_offset = src->gtt_offset;
  898. return dst;
  899. unwind:
  900. while (i--)
  901. kfree(dst->pages[i]);
  902. kfree(dst);
  903. return NULL;
  904. }
  905. #define i915_error_object_create(dev_priv, src) \
  906. i915_error_object_create_sized((dev_priv), (src), \
  907. (src)->base.size>>PAGE_SHIFT)
  908. static void
  909. i915_error_object_free(struct drm_i915_error_object *obj)
  910. {
  911. int page;
  912. if (obj == NULL)
  913. return;
  914. for (page = 0; page < obj->page_count; page++)
  915. kfree(obj->pages[page]);
  916. kfree(obj);
  917. }
  918. void
  919. i915_error_state_free(struct kref *error_ref)
  920. {
  921. struct drm_i915_error_state *error = container_of(error_ref,
  922. typeof(*error), ref);
  923. int i;
  924. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  925. i915_error_object_free(error->ring[i].batchbuffer);
  926. i915_error_object_free(error->ring[i].ringbuffer);
  927. kfree(error->ring[i].requests);
  928. }
  929. kfree(error->active_bo);
  930. kfree(error->overlay);
  931. kfree(error);
  932. }
  933. static void capture_bo(struct drm_i915_error_buffer *err,
  934. struct drm_i915_gem_object *obj)
  935. {
  936. err->size = obj->base.size;
  937. err->name = obj->base.name;
  938. err->rseqno = obj->last_read_seqno;
  939. err->wseqno = obj->last_write_seqno;
  940. err->gtt_offset = obj->gtt_offset;
  941. err->read_domains = obj->base.read_domains;
  942. err->write_domain = obj->base.write_domain;
  943. err->fence_reg = obj->fence_reg;
  944. err->pinned = 0;
  945. if (obj->pin_count > 0)
  946. err->pinned = 1;
  947. if (obj->user_pin_count > 0)
  948. err->pinned = -1;
  949. err->tiling = obj->tiling_mode;
  950. err->dirty = obj->dirty;
  951. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  952. err->ring = obj->ring ? obj->ring->id : -1;
  953. err->cache_level = obj->cache_level;
  954. }
  955. static u32 capture_active_bo(struct drm_i915_error_buffer *err,
  956. int count, struct list_head *head)
  957. {
  958. struct drm_i915_gem_object *obj;
  959. int i = 0;
  960. list_for_each_entry(obj, head, mm_list) {
  961. capture_bo(err++, obj);
  962. if (++i == count)
  963. break;
  964. }
  965. return i;
  966. }
  967. static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
  968. int count, struct list_head *head)
  969. {
  970. struct drm_i915_gem_object *obj;
  971. int i = 0;
  972. list_for_each_entry(obj, head, gtt_list) {
  973. if (obj->pin_count == 0)
  974. continue;
  975. capture_bo(err++, obj);
  976. if (++i == count)
  977. break;
  978. }
  979. return i;
  980. }
  981. static void i915_gem_record_fences(struct drm_device *dev,
  982. struct drm_i915_error_state *error)
  983. {
  984. struct drm_i915_private *dev_priv = dev->dev_private;
  985. int i;
  986. /* Fences */
  987. switch (INTEL_INFO(dev)->gen) {
  988. case 7:
  989. case 6:
  990. for (i = 0; i < 16; i++)
  991. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  992. break;
  993. case 5:
  994. case 4:
  995. for (i = 0; i < 16; i++)
  996. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  997. break;
  998. case 3:
  999. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  1000. for (i = 0; i < 8; i++)
  1001. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  1002. case 2:
  1003. for (i = 0; i < 8; i++)
  1004. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  1005. break;
  1006. default:
  1007. BUG();
  1008. }
  1009. }
  1010. static struct drm_i915_error_object *
  1011. i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
  1012. struct intel_ring_buffer *ring)
  1013. {
  1014. struct drm_i915_gem_object *obj;
  1015. u32 seqno;
  1016. if (!ring->get_seqno)
  1017. return NULL;
  1018. if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
  1019. u32 acthd = I915_READ(ACTHD);
  1020. if (WARN_ON(ring->id != RCS))
  1021. return NULL;
  1022. obj = ring->private;
  1023. if (acthd >= obj->gtt_offset &&
  1024. acthd < obj->gtt_offset + obj->base.size)
  1025. return i915_error_object_create(dev_priv, obj);
  1026. }
  1027. seqno = ring->get_seqno(ring, false);
  1028. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  1029. if (obj->ring != ring)
  1030. continue;
  1031. if (i915_seqno_passed(seqno, obj->last_read_seqno))
  1032. continue;
  1033. if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
  1034. continue;
  1035. /* We need to copy these to an anonymous buffer as the simplest
  1036. * method to avoid being overwritten by userspace.
  1037. */
  1038. return i915_error_object_create(dev_priv, obj);
  1039. }
  1040. return NULL;
  1041. }
  1042. static void i915_record_ring_state(struct drm_device *dev,
  1043. struct drm_i915_error_state *error,
  1044. struct intel_ring_buffer *ring)
  1045. {
  1046. struct drm_i915_private *dev_priv = dev->dev_private;
  1047. if (INTEL_INFO(dev)->gen >= 6) {
  1048. error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
  1049. error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
  1050. error->semaphore_mboxes[ring->id][0]
  1051. = I915_READ(RING_SYNC_0(ring->mmio_base));
  1052. error->semaphore_mboxes[ring->id][1]
  1053. = I915_READ(RING_SYNC_1(ring->mmio_base));
  1054. error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
  1055. error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
  1056. }
  1057. if (INTEL_INFO(dev)->gen >= 4) {
  1058. error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
  1059. error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
  1060. error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
  1061. error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
  1062. error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
  1063. if (ring->id == RCS)
  1064. error->bbaddr = I915_READ64(BB_ADDR);
  1065. } else {
  1066. error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
  1067. error->ipeir[ring->id] = I915_READ(IPEIR);
  1068. error->ipehr[ring->id] = I915_READ(IPEHR);
  1069. error->instdone[ring->id] = I915_READ(INSTDONE);
  1070. }
  1071. error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
  1072. error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
  1073. error->seqno[ring->id] = ring->get_seqno(ring, false);
  1074. error->acthd[ring->id] = intel_ring_get_active_head(ring);
  1075. error->head[ring->id] = I915_READ_HEAD(ring);
  1076. error->tail[ring->id] = I915_READ_TAIL(ring);
  1077. error->ctl[ring->id] = I915_READ_CTL(ring);
  1078. error->cpu_ring_head[ring->id] = ring->head;
  1079. error->cpu_ring_tail[ring->id] = ring->tail;
  1080. }
  1081. static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
  1082. struct drm_i915_error_state *error,
  1083. struct drm_i915_error_ring *ering)
  1084. {
  1085. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1086. struct drm_i915_gem_object *obj;
  1087. /* Currently render ring is the only HW context user */
  1088. if (ring->id != RCS || !error->ccid)
  1089. return;
  1090. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  1091. if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
  1092. ering->ctx = i915_error_object_create_sized(dev_priv,
  1093. obj, 1);
  1094. }
  1095. }
  1096. }
  1097. static void i915_gem_record_rings(struct drm_device *dev,
  1098. struct drm_i915_error_state *error)
  1099. {
  1100. struct drm_i915_private *dev_priv = dev->dev_private;
  1101. struct intel_ring_buffer *ring;
  1102. struct drm_i915_gem_request *request;
  1103. int i, count;
  1104. for_each_ring(ring, dev_priv, i) {
  1105. i915_record_ring_state(dev, error, ring);
  1106. error->ring[i].batchbuffer =
  1107. i915_error_first_batchbuffer(dev_priv, ring);
  1108. error->ring[i].ringbuffer =
  1109. i915_error_object_create(dev_priv, ring->obj);
  1110. i915_gem_record_active_context(ring, error, &error->ring[i]);
  1111. count = 0;
  1112. list_for_each_entry(request, &ring->request_list, list)
  1113. count++;
  1114. error->ring[i].num_requests = count;
  1115. error->ring[i].requests =
  1116. kmalloc(count*sizeof(struct drm_i915_error_request),
  1117. GFP_ATOMIC);
  1118. if (error->ring[i].requests == NULL) {
  1119. error->ring[i].num_requests = 0;
  1120. continue;
  1121. }
  1122. count = 0;
  1123. list_for_each_entry(request, &ring->request_list, list) {
  1124. struct drm_i915_error_request *erq;
  1125. erq = &error->ring[i].requests[count++];
  1126. erq->seqno = request->seqno;
  1127. erq->jiffies = request->emitted_jiffies;
  1128. erq->tail = request->tail;
  1129. }
  1130. }
  1131. }
  1132. /**
  1133. * i915_capture_error_state - capture an error record for later analysis
  1134. * @dev: drm device
  1135. *
  1136. * Should be called when an error is detected (either a hang or an error
  1137. * interrupt) to capture error state from the time of the error. Fills
  1138. * out a structure which becomes available in debugfs for user level tools
  1139. * to pick up.
  1140. */
  1141. static void i915_capture_error_state(struct drm_device *dev)
  1142. {
  1143. struct drm_i915_private *dev_priv = dev->dev_private;
  1144. struct drm_i915_gem_object *obj;
  1145. struct drm_i915_error_state *error;
  1146. unsigned long flags;
  1147. int i, pipe;
  1148. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1149. error = dev_priv->gpu_error.first_error;
  1150. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1151. if (error)
  1152. return;
  1153. /* Account for pipe specific data like PIPE*STAT */
  1154. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  1155. if (!error) {
  1156. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  1157. return;
  1158. }
  1159. DRM_INFO("capturing error event; look for more information in "
  1160. "/sys/kernel/debug/dri/%d/i915_error_state\n",
  1161. dev->primary->index);
  1162. kref_init(&error->ref);
  1163. error->eir = I915_READ(EIR);
  1164. error->pgtbl_er = I915_READ(PGTBL_ER);
  1165. if (HAS_HW_CONTEXTS(dev))
  1166. error->ccid = I915_READ(CCID);
  1167. if (HAS_PCH_SPLIT(dev))
  1168. error->ier = I915_READ(DEIER) | I915_READ(GTIER);
  1169. else if (IS_VALLEYVIEW(dev))
  1170. error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
  1171. else if (IS_GEN2(dev))
  1172. error->ier = I915_READ16(IER);
  1173. else
  1174. error->ier = I915_READ(IER);
  1175. if (INTEL_INFO(dev)->gen >= 6)
  1176. error->derrmr = I915_READ(DERRMR);
  1177. if (IS_VALLEYVIEW(dev))
  1178. error->forcewake = I915_READ(FORCEWAKE_VLV);
  1179. else if (INTEL_INFO(dev)->gen >= 7)
  1180. error->forcewake = I915_READ(FORCEWAKE_MT);
  1181. else if (INTEL_INFO(dev)->gen == 6)
  1182. error->forcewake = I915_READ(FORCEWAKE);
  1183. if (!HAS_PCH_SPLIT(dev))
  1184. for_each_pipe(pipe)
  1185. error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
  1186. if (INTEL_INFO(dev)->gen >= 6) {
  1187. error->error = I915_READ(ERROR_GEN6);
  1188. error->done_reg = I915_READ(DONE_REG);
  1189. }
  1190. if (INTEL_INFO(dev)->gen == 7)
  1191. error->err_int = I915_READ(GEN7_ERR_INT);
  1192. i915_get_extra_instdone(dev, error->extra_instdone);
  1193. i915_gem_record_fences(dev, error);
  1194. i915_gem_record_rings(dev, error);
  1195. /* Record buffers on the active and pinned lists. */
  1196. error->active_bo = NULL;
  1197. error->pinned_bo = NULL;
  1198. i = 0;
  1199. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
  1200. i++;
  1201. error->active_bo_count = i;
  1202. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
  1203. if (obj->pin_count)
  1204. i++;
  1205. error->pinned_bo_count = i - error->active_bo_count;
  1206. error->active_bo = NULL;
  1207. error->pinned_bo = NULL;
  1208. if (i) {
  1209. error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
  1210. GFP_ATOMIC);
  1211. if (error->active_bo)
  1212. error->pinned_bo =
  1213. error->active_bo + error->active_bo_count;
  1214. }
  1215. if (error->active_bo)
  1216. error->active_bo_count =
  1217. capture_active_bo(error->active_bo,
  1218. error->active_bo_count,
  1219. &dev_priv->mm.active_list);
  1220. if (error->pinned_bo)
  1221. error->pinned_bo_count =
  1222. capture_pinned_bo(error->pinned_bo,
  1223. error->pinned_bo_count,
  1224. &dev_priv->mm.bound_list);
  1225. do_gettimeofday(&error->time);
  1226. error->overlay = intel_overlay_capture_error_state(dev);
  1227. error->display = intel_display_capture_error_state(dev);
  1228. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1229. if (dev_priv->gpu_error.first_error == NULL) {
  1230. dev_priv->gpu_error.first_error = error;
  1231. error = NULL;
  1232. }
  1233. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1234. if (error)
  1235. i915_error_state_free(&error->ref);
  1236. }
  1237. void i915_destroy_error_state(struct drm_device *dev)
  1238. {
  1239. struct drm_i915_private *dev_priv = dev->dev_private;
  1240. struct drm_i915_error_state *error;
  1241. unsigned long flags;
  1242. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1243. error = dev_priv->gpu_error.first_error;
  1244. dev_priv->gpu_error.first_error = NULL;
  1245. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1246. if (error)
  1247. kref_put(&error->ref, i915_error_state_free);
  1248. }
  1249. #else
  1250. #define i915_capture_error_state(x)
  1251. #endif
  1252. static void i915_report_and_clear_eir(struct drm_device *dev)
  1253. {
  1254. struct drm_i915_private *dev_priv = dev->dev_private;
  1255. uint32_t instdone[I915_NUM_INSTDONE_REG];
  1256. u32 eir = I915_READ(EIR);
  1257. int pipe, i;
  1258. if (!eir)
  1259. return;
  1260. pr_err("render error detected, EIR: 0x%08x\n", eir);
  1261. i915_get_extra_instdone(dev, instdone);
  1262. if (IS_G4X(dev)) {
  1263. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  1264. u32 ipeir = I915_READ(IPEIR_I965);
  1265. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1266. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1267. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1268. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1269. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1270. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1271. I915_WRITE(IPEIR_I965, ipeir);
  1272. POSTING_READ(IPEIR_I965);
  1273. }
  1274. if (eir & GM45_ERROR_PAGE_TABLE) {
  1275. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1276. pr_err("page table error\n");
  1277. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1278. I915_WRITE(PGTBL_ER, pgtbl_err);
  1279. POSTING_READ(PGTBL_ER);
  1280. }
  1281. }
  1282. if (!IS_GEN2(dev)) {
  1283. if (eir & I915_ERROR_PAGE_TABLE) {
  1284. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1285. pr_err("page table error\n");
  1286. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1287. I915_WRITE(PGTBL_ER, pgtbl_err);
  1288. POSTING_READ(PGTBL_ER);
  1289. }
  1290. }
  1291. if (eir & I915_ERROR_MEMORY_REFRESH) {
  1292. pr_err("memory refresh error:\n");
  1293. for_each_pipe(pipe)
  1294. pr_err("pipe %c stat: 0x%08x\n",
  1295. pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  1296. /* pipestat has already been acked */
  1297. }
  1298. if (eir & I915_ERROR_INSTRUCTION) {
  1299. pr_err("instruction error\n");
  1300. pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
  1301. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1302. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1303. if (INTEL_INFO(dev)->gen < 4) {
  1304. u32 ipeir = I915_READ(IPEIR);
  1305. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
  1306. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
  1307. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
  1308. I915_WRITE(IPEIR, ipeir);
  1309. POSTING_READ(IPEIR);
  1310. } else {
  1311. u32 ipeir = I915_READ(IPEIR_I965);
  1312. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1313. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1314. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1315. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1316. I915_WRITE(IPEIR_I965, ipeir);
  1317. POSTING_READ(IPEIR_I965);
  1318. }
  1319. }
  1320. I915_WRITE(EIR, eir);
  1321. POSTING_READ(EIR);
  1322. eir = I915_READ(EIR);
  1323. if (eir) {
  1324. /*
  1325. * some errors might have become stuck,
  1326. * mask them.
  1327. */
  1328. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  1329. I915_WRITE(EMR, I915_READ(EMR) | eir);
  1330. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1331. }
  1332. }
  1333. /**
  1334. * i915_handle_error - handle an error interrupt
  1335. * @dev: drm device
  1336. *
  1337. * Do some basic checking of regsiter state at error interrupt time and
  1338. * dump it to the syslog. Also call i915_capture_error_state() to make
  1339. * sure we get a record and make it available in debugfs. Fire a uevent
  1340. * so userspace knows something bad happened (should trigger collection
  1341. * of a ring dump etc.).
  1342. */
  1343. void i915_handle_error(struct drm_device *dev, bool wedged)
  1344. {
  1345. struct drm_i915_private *dev_priv = dev->dev_private;
  1346. struct intel_ring_buffer *ring;
  1347. int i;
  1348. i915_capture_error_state(dev);
  1349. i915_report_and_clear_eir(dev);
  1350. if (wedged) {
  1351. atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
  1352. &dev_priv->gpu_error.reset_counter);
  1353. /*
  1354. * Wakeup waiting processes so that the reset work item
  1355. * doesn't deadlock trying to grab various locks.
  1356. */
  1357. for_each_ring(ring, dev_priv, i)
  1358. wake_up_all(&ring->irq_queue);
  1359. }
  1360. queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
  1361. }
  1362. static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  1363. {
  1364. drm_i915_private_t *dev_priv = dev->dev_private;
  1365. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1366. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1367. struct drm_i915_gem_object *obj;
  1368. struct intel_unpin_work *work;
  1369. unsigned long flags;
  1370. bool stall_detected;
  1371. /* Ignore early vblank irqs */
  1372. if (intel_crtc == NULL)
  1373. return;
  1374. spin_lock_irqsave(&dev->event_lock, flags);
  1375. work = intel_crtc->unpin_work;
  1376. if (work == NULL ||
  1377. atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
  1378. !work->enable_stall_check) {
  1379. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  1380. spin_unlock_irqrestore(&dev->event_lock, flags);
  1381. return;
  1382. }
  1383. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  1384. obj = work->pending_flip_obj;
  1385. if (INTEL_INFO(dev)->gen >= 4) {
  1386. int dspsurf = DSPSURF(intel_crtc->plane);
  1387. stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
  1388. obj->gtt_offset;
  1389. } else {
  1390. int dspaddr = DSPADDR(intel_crtc->plane);
  1391. stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
  1392. crtc->y * crtc->fb->pitches[0] +
  1393. crtc->x * crtc->fb->bits_per_pixel/8);
  1394. }
  1395. spin_unlock_irqrestore(&dev->event_lock, flags);
  1396. if (stall_detected) {
  1397. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  1398. intel_prepare_page_flip(dev, intel_crtc->plane);
  1399. }
  1400. }
  1401. /* Called from drm generic code, passed 'crtc' which
  1402. * we use as a pipe index
  1403. */
  1404. static int i915_enable_vblank(struct drm_device *dev, int pipe)
  1405. {
  1406. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1407. unsigned long irqflags;
  1408. if (!i915_pipe_enabled(dev, pipe))
  1409. return -EINVAL;
  1410. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1411. if (INTEL_INFO(dev)->gen >= 4)
  1412. i915_enable_pipestat(dev_priv, pipe,
  1413. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1414. else
  1415. i915_enable_pipestat(dev_priv, pipe,
  1416. PIPE_VBLANK_INTERRUPT_ENABLE);
  1417. /* maintain vblank delivery even in deep C-states */
  1418. if (dev_priv->info->gen == 3)
  1419. I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
  1420. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1421. return 0;
  1422. }
  1423. static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
  1424. {
  1425. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1426. unsigned long irqflags;
  1427. if (!i915_pipe_enabled(dev, pipe))
  1428. return -EINVAL;
  1429. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1430. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  1431. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1432. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1433. return 0;
  1434. }
  1435. static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
  1436. {
  1437. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1438. unsigned long irqflags;
  1439. if (!i915_pipe_enabled(dev, pipe))
  1440. return -EINVAL;
  1441. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1442. ironlake_enable_display_irq(dev_priv,
  1443. DE_PIPEA_VBLANK_IVB << (5 * pipe));
  1444. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1445. return 0;
  1446. }
  1447. static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
  1448. {
  1449. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1450. unsigned long irqflags;
  1451. u32 imr;
  1452. if (!i915_pipe_enabled(dev, pipe))
  1453. return -EINVAL;
  1454. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1455. imr = I915_READ(VLV_IMR);
  1456. if (pipe == 0)
  1457. imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1458. else
  1459. imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1460. I915_WRITE(VLV_IMR, imr);
  1461. i915_enable_pipestat(dev_priv, pipe,
  1462. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1463. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1464. return 0;
  1465. }
  1466. /* Called from drm generic code, passed 'crtc' which
  1467. * we use as a pipe index
  1468. */
  1469. static void i915_disable_vblank(struct drm_device *dev, int pipe)
  1470. {
  1471. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1472. unsigned long irqflags;
  1473. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1474. if (dev_priv->info->gen == 3)
  1475. I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
  1476. i915_disable_pipestat(dev_priv, pipe,
  1477. PIPE_VBLANK_INTERRUPT_ENABLE |
  1478. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1479. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1480. }
  1481. static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
  1482. {
  1483. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1484. unsigned long irqflags;
  1485. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1486. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  1487. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1488. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1489. }
  1490. static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
  1491. {
  1492. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1493. unsigned long irqflags;
  1494. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1495. ironlake_disable_display_irq(dev_priv,
  1496. DE_PIPEA_VBLANK_IVB << (pipe * 5));
  1497. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1498. }
  1499. static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
  1500. {
  1501. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1502. unsigned long irqflags;
  1503. u32 imr;
  1504. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1505. i915_disable_pipestat(dev_priv, pipe,
  1506. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1507. imr = I915_READ(VLV_IMR);
  1508. if (pipe == 0)
  1509. imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1510. else
  1511. imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1512. I915_WRITE(VLV_IMR, imr);
  1513. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1514. }
  1515. static u32
  1516. ring_last_seqno(struct intel_ring_buffer *ring)
  1517. {
  1518. return list_entry(ring->request_list.prev,
  1519. struct drm_i915_gem_request, list)->seqno;
  1520. }
  1521. static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
  1522. {
  1523. if (list_empty(&ring->request_list) ||
  1524. i915_seqno_passed(ring->get_seqno(ring, false),
  1525. ring_last_seqno(ring))) {
  1526. /* Issue a wake-up to catch stuck h/w. */
  1527. if (waitqueue_active(&ring->irq_queue)) {
  1528. DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  1529. ring->name);
  1530. wake_up_all(&ring->irq_queue);
  1531. *err = true;
  1532. }
  1533. return true;
  1534. }
  1535. return false;
  1536. }
  1537. static bool semaphore_passed(struct intel_ring_buffer *ring)
  1538. {
  1539. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1540. u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
  1541. struct intel_ring_buffer *signaller;
  1542. u32 cmd, ipehr, acthd_min;
  1543. ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
  1544. if ((ipehr & ~(0x3 << 16)) !=
  1545. (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
  1546. return false;
  1547. /* ACTHD is likely pointing to the dword after the actual command,
  1548. * so scan backwards until we find the MBOX.
  1549. */
  1550. acthd_min = max((int)acthd - 3 * 4, 0);
  1551. do {
  1552. cmd = ioread32(ring->virtual_start + acthd);
  1553. if (cmd == ipehr)
  1554. break;
  1555. acthd -= 4;
  1556. if (acthd < acthd_min)
  1557. return false;
  1558. } while (1);
  1559. signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
  1560. return i915_seqno_passed(signaller->get_seqno(signaller, false),
  1561. ioread32(ring->virtual_start+acthd+4)+1);
  1562. }
  1563. static bool kick_ring(struct intel_ring_buffer *ring)
  1564. {
  1565. struct drm_device *dev = ring->dev;
  1566. struct drm_i915_private *dev_priv = dev->dev_private;
  1567. u32 tmp = I915_READ_CTL(ring);
  1568. if (tmp & RING_WAIT) {
  1569. DRM_ERROR("Kicking stuck wait on %s\n",
  1570. ring->name);
  1571. I915_WRITE_CTL(ring, tmp);
  1572. return true;
  1573. }
  1574. if (INTEL_INFO(dev)->gen >= 6 &&
  1575. tmp & RING_WAIT_SEMAPHORE &&
  1576. semaphore_passed(ring)) {
  1577. DRM_ERROR("Kicking stuck semaphore on %s\n",
  1578. ring->name);
  1579. I915_WRITE_CTL(ring, tmp);
  1580. return true;
  1581. }
  1582. return false;
  1583. }
  1584. static bool i915_hangcheck_hung(struct drm_device *dev)
  1585. {
  1586. drm_i915_private_t *dev_priv = dev->dev_private;
  1587. if (dev_priv->gpu_error.hangcheck_count++ > 1) {
  1588. bool hung = true;
  1589. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  1590. i915_handle_error(dev, true);
  1591. if (!IS_GEN2(dev)) {
  1592. struct intel_ring_buffer *ring;
  1593. int i;
  1594. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1595. * If so we can simply poke the RB_WAIT bit
  1596. * and break the hang. This should work on
  1597. * all but the second generation chipsets.
  1598. */
  1599. for_each_ring(ring, dev_priv, i)
  1600. hung &= !kick_ring(ring);
  1601. }
  1602. return hung;
  1603. }
  1604. return false;
  1605. }
  1606. /**
  1607. * This is called when the chip hasn't reported back with completed
  1608. * batchbuffers in a long time. The first time this is called we simply record
  1609. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  1610. * again, we assume the chip is wedged and try to fix it.
  1611. */
  1612. void i915_hangcheck_elapsed(unsigned long data)
  1613. {
  1614. struct drm_device *dev = (struct drm_device *)data;
  1615. drm_i915_private_t *dev_priv = dev->dev_private;
  1616. uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
  1617. struct intel_ring_buffer *ring;
  1618. bool err = false, idle;
  1619. int i;
  1620. if (!i915_enable_hangcheck)
  1621. return;
  1622. memset(acthd, 0, sizeof(acthd));
  1623. idle = true;
  1624. for_each_ring(ring, dev_priv, i) {
  1625. idle &= i915_hangcheck_ring_idle(ring, &err);
  1626. acthd[i] = intel_ring_get_active_head(ring);
  1627. }
  1628. /* If all work is done then ACTHD clearly hasn't advanced. */
  1629. if (idle) {
  1630. if (err) {
  1631. if (i915_hangcheck_hung(dev))
  1632. return;
  1633. goto repeat;
  1634. }
  1635. dev_priv->gpu_error.hangcheck_count = 0;
  1636. return;
  1637. }
  1638. i915_get_extra_instdone(dev, instdone);
  1639. if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
  1640. sizeof(acthd)) == 0 &&
  1641. memcmp(dev_priv->gpu_error.prev_instdone, instdone,
  1642. sizeof(instdone)) == 0) {
  1643. if (i915_hangcheck_hung(dev))
  1644. return;
  1645. } else {
  1646. dev_priv->gpu_error.hangcheck_count = 0;
  1647. memcpy(dev_priv->gpu_error.last_acthd, acthd,
  1648. sizeof(acthd));
  1649. memcpy(dev_priv->gpu_error.prev_instdone, instdone,
  1650. sizeof(instdone));
  1651. }
  1652. repeat:
  1653. /* Reset timer case chip hangs without another request being added */
  1654. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  1655. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  1656. }
  1657. /* drm_dma.h hooks
  1658. */
  1659. static void ironlake_irq_preinstall(struct drm_device *dev)
  1660. {
  1661. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1662. atomic_set(&dev_priv->irq_received, 0);
  1663. I915_WRITE(HWSTAM, 0xeffe);
  1664. /* XXX hotplug from PCH */
  1665. I915_WRITE(DEIMR, 0xffffffff);
  1666. I915_WRITE(DEIER, 0x0);
  1667. POSTING_READ(DEIER);
  1668. /* and GT */
  1669. I915_WRITE(GTIMR, 0xffffffff);
  1670. I915_WRITE(GTIER, 0x0);
  1671. POSTING_READ(GTIER);
  1672. if (HAS_PCH_NOP(dev))
  1673. return;
  1674. /* south display irq */
  1675. I915_WRITE(SDEIMR, 0xffffffff);
  1676. /*
  1677. * SDEIER is also touched by the interrupt handler to work around missed
  1678. * PCH interrupts. Hence we can't update it after the interrupt handler
  1679. * is enabled - instead we unconditionally enable all PCH interrupt
  1680. * sources here, but then only unmask them as needed with SDEIMR.
  1681. */
  1682. I915_WRITE(SDEIER, 0xffffffff);
  1683. POSTING_READ(SDEIER);
  1684. }
  1685. static void valleyview_irq_preinstall(struct drm_device *dev)
  1686. {
  1687. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1688. int pipe;
  1689. atomic_set(&dev_priv->irq_received, 0);
  1690. /* VLV magic */
  1691. I915_WRITE(VLV_IMR, 0);
  1692. I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  1693. I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  1694. I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  1695. /* and GT */
  1696. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1697. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1698. I915_WRITE(GTIMR, 0xffffffff);
  1699. I915_WRITE(GTIER, 0x0);
  1700. POSTING_READ(GTIER);
  1701. I915_WRITE(DPINVGTT, 0xff);
  1702. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1703. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1704. for_each_pipe(pipe)
  1705. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1706. I915_WRITE(VLV_IIR, 0xffffffff);
  1707. I915_WRITE(VLV_IMR, 0xffffffff);
  1708. I915_WRITE(VLV_IER, 0x0);
  1709. POSTING_READ(VLV_IER);
  1710. }
  1711. static void ibx_hpd_irq_setup(struct drm_device *dev)
  1712. {
  1713. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1714. struct drm_mode_config *mode_config = &dev->mode_config;
  1715. struct intel_encoder *intel_encoder;
  1716. u32 mask = ~I915_READ(SDEIMR);
  1717. u32 hotplug;
  1718. if (HAS_PCH_IBX(dev)) {
  1719. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  1720. mask |= hpd_ibx[intel_encoder->hpd_pin];
  1721. } else {
  1722. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  1723. mask |= hpd_cpt[intel_encoder->hpd_pin];
  1724. }
  1725. I915_WRITE(SDEIMR, ~mask);
  1726. /*
  1727. * Enable digital hotplug on the PCH, and configure the DP short pulse
  1728. * duration to 2ms (which is the minimum in the Display Port spec)
  1729. *
  1730. * This register is the same on all known PCH chips.
  1731. */
  1732. hotplug = I915_READ(PCH_PORT_HOTPLUG);
  1733. hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
  1734. hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
  1735. hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
  1736. hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
  1737. I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  1738. }
  1739. static void ibx_irq_postinstall(struct drm_device *dev)
  1740. {
  1741. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1742. u32 mask;
  1743. if (HAS_PCH_IBX(dev))
  1744. mask = SDE_GMBUS | SDE_AUX_MASK;
  1745. else
  1746. mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
  1747. if (HAS_PCH_NOP(dev))
  1748. return;
  1749. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1750. I915_WRITE(SDEIMR, ~mask);
  1751. }
  1752. static int ironlake_irq_postinstall(struct drm_device *dev)
  1753. {
  1754. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1755. /* enable kind of interrupts always enabled */
  1756. u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  1757. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
  1758. DE_AUX_CHANNEL_A;
  1759. u32 render_irqs;
  1760. dev_priv->irq_mask = ~display_mask;
  1761. /* should always can generate irq */
  1762. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1763. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1764. I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
  1765. POSTING_READ(DEIER);
  1766. dev_priv->gt_irq_mask = ~0;
  1767. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1768. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1769. if (IS_GEN6(dev))
  1770. render_irqs =
  1771. GT_USER_INTERRUPT |
  1772. GEN6_BSD_USER_INTERRUPT |
  1773. GEN6_BLITTER_USER_INTERRUPT;
  1774. else
  1775. render_irqs =
  1776. GT_USER_INTERRUPT |
  1777. GT_PIPE_NOTIFY |
  1778. GT_BSD_USER_INTERRUPT;
  1779. I915_WRITE(GTIER, render_irqs);
  1780. POSTING_READ(GTIER);
  1781. ibx_irq_postinstall(dev);
  1782. if (IS_IRONLAKE_M(dev)) {
  1783. /* Clear & enable PCU event interrupts */
  1784. I915_WRITE(DEIIR, DE_PCU_EVENT);
  1785. I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
  1786. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  1787. }
  1788. return 0;
  1789. }
  1790. static int ivybridge_irq_postinstall(struct drm_device *dev)
  1791. {
  1792. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1793. /* enable kind of interrupts always enabled */
  1794. u32 display_mask =
  1795. DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
  1796. DE_PLANEC_FLIP_DONE_IVB |
  1797. DE_PLANEB_FLIP_DONE_IVB |
  1798. DE_PLANEA_FLIP_DONE_IVB |
  1799. DE_AUX_CHANNEL_A_IVB;
  1800. u32 render_irqs;
  1801. dev_priv->irq_mask = ~display_mask;
  1802. /* should always can generate irq */
  1803. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1804. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1805. I915_WRITE(DEIER,
  1806. display_mask |
  1807. DE_PIPEC_VBLANK_IVB |
  1808. DE_PIPEB_VBLANK_IVB |
  1809. DE_PIPEA_VBLANK_IVB);
  1810. POSTING_READ(DEIER);
  1811. dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  1812. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1813. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1814. render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
  1815. GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  1816. I915_WRITE(GTIER, render_irqs);
  1817. POSTING_READ(GTIER);
  1818. ibx_irq_postinstall(dev);
  1819. return 0;
  1820. }
  1821. static int valleyview_irq_postinstall(struct drm_device *dev)
  1822. {
  1823. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1824. u32 enable_mask;
  1825. u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
  1826. u32 render_irqs;
  1827. u16 msid;
  1828. enable_mask = I915_DISPLAY_PORT_INTERRUPT;
  1829. enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1830. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1831. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1832. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1833. /*
  1834. *Leave vblank interrupts masked initially. enable/disable will
  1835. * toggle them based on usage.
  1836. */
  1837. dev_priv->irq_mask = (~enable_mask) |
  1838. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1839. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1840. /* Hack for broken MSIs on VLV */
  1841. pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
  1842. pci_read_config_word(dev->pdev, 0x98, &msid);
  1843. msid &= 0xff; /* mask out delivery bits */
  1844. msid |= (1<<14);
  1845. pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
  1846. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1847. POSTING_READ(PORT_HOTPLUG_EN);
  1848. I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  1849. I915_WRITE(VLV_IER, enable_mask);
  1850. I915_WRITE(VLV_IIR, 0xffffffff);
  1851. I915_WRITE(PIPESTAT(0), 0xffff);
  1852. I915_WRITE(PIPESTAT(1), 0xffff);
  1853. POSTING_READ(VLV_IER);
  1854. i915_enable_pipestat(dev_priv, 0, pipestat_enable);
  1855. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  1856. i915_enable_pipestat(dev_priv, 1, pipestat_enable);
  1857. I915_WRITE(VLV_IIR, 0xffffffff);
  1858. I915_WRITE(VLV_IIR, 0xffffffff);
  1859. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1860. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1861. render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
  1862. GEN6_BLITTER_USER_INTERRUPT;
  1863. I915_WRITE(GTIER, render_irqs);
  1864. POSTING_READ(GTIER);
  1865. /* ack & enable invalid PTE error interrupts */
  1866. #if 0 /* FIXME: add support to irq handler for checking these bits */
  1867. I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  1868. I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
  1869. #endif
  1870. I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
  1871. return 0;
  1872. }
  1873. static void valleyview_irq_uninstall(struct drm_device *dev)
  1874. {
  1875. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1876. int pipe;
  1877. if (!dev_priv)
  1878. return;
  1879. for_each_pipe(pipe)
  1880. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1881. I915_WRITE(HWSTAM, 0xffffffff);
  1882. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1883. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1884. for_each_pipe(pipe)
  1885. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1886. I915_WRITE(VLV_IIR, 0xffffffff);
  1887. I915_WRITE(VLV_IMR, 0xffffffff);
  1888. I915_WRITE(VLV_IER, 0x0);
  1889. POSTING_READ(VLV_IER);
  1890. }
  1891. static void ironlake_irq_uninstall(struct drm_device *dev)
  1892. {
  1893. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1894. if (!dev_priv)
  1895. return;
  1896. I915_WRITE(HWSTAM, 0xffffffff);
  1897. I915_WRITE(DEIMR, 0xffffffff);
  1898. I915_WRITE(DEIER, 0x0);
  1899. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1900. I915_WRITE(GTIMR, 0xffffffff);
  1901. I915_WRITE(GTIER, 0x0);
  1902. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1903. if (HAS_PCH_NOP(dev))
  1904. return;
  1905. I915_WRITE(SDEIMR, 0xffffffff);
  1906. I915_WRITE(SDEIER, 0x0);
  1907. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1908. }
  1909. static void i8xx_irq_preinstall(struct drm_device * dev)
  1910. {
  1911. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1912. int pipe;
  1913. atomic_set(&dev_priv->irq_received, 0);
  1914. for_each_pipe(pipe)
  1915. I915_WRITE(PIPESTAT(pipe), 0);
  1916. I915_WRITE16(IMR, 0xffff);
  1917. I915_WRITE16(IER, 0x0);
  1918. POSTING_READ16(IER);
  1919. }
  1920. static int i8xx_irq_postinstall(struct drm_device *dev)
  1921. {
  1922. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1923. I915_WRITE16(EMR,
  1924. ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  1925. /* Unmask the interrupts that we always want on. */
  1926. dev_priv->irq_mask =
  1927. ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1928. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1929. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1930. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  1931. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1932. I915_WRITE16(IMR, dev_priv->irq_mask);
  1933. I915_WRITE16(IER,
  1934. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1935. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1936. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  1937. I915_USER_INTERRUPT);
  1938. POSTING_READ16(IER);
  1939. return 0;
  1940. }
  1941. /*
  1942. * Returns true when a page flip has completed.
  1943. */
  1944. static bool i8xx_handle_vblank(struct drm_device *dev,
  1945. int pipe, u16 iir)
  1946. {
  1947. drm_i915_private_t *dev_priv = dev->dev_private;
  1948. u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
  1949. if (!drm_handle_vblank(dev, pipe))
  1950. return false;
  1951. if ((iir & flip_pending) == 0)
  1952. return false;
  1953. intel_prepare_page_flip(dev, pipe);
  1954. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  1955. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  1956. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  1957. * the flip is completed (no longer pending). Since this doesn't raise
  1958. * an interrupt per se, we watch for the change at vblank.
  1959. */
  1960. if (I915_READ16(ISR) & flip_pending)
  1961. return false;
  1962. intel_finish_page_flip(dev, pipe);
  1963. return true;
  1964. }
  1965. static irqreturn_t i8xx_irq_handler(int irq, void *arg)
  1966. {
  1967. struct drm_device *dev = (struct drm_device *) arg;
  1968. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1969. u16 iir, new_iir;
  1970. u32 pipe_stats[2];
  1971. unsigned long irqflags;
  1972. int irq_received;
  1973. int pipe;
  1974. u16 flip_mask =
  1975. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1976. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  1977. atomic_inc(&dev_priv->irq_received);
  1978. iir = I915_READ16(IIR);
  1979. if (iir == 0)
  1980. return IRQ_NONE;
  1981. while (iir & ~flip_mask) {
  1982. /* Can't rely on pipestat interrupt bit in iir as it might
  1983. * have been cleared after the pipestat interrupt was received.
  1984. * It doesn't set the bit in iir again, but it still produces
  1985. * interrupts (for non-MSI).
  1986. */
  1987. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1988. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  1989. i915_handle_error(dev, false);
  1990. for_each_pipe(pipe) {
  1991. int reg = PIPESTAT(pipe);
  1992. pipe_stats[pipe] = I915_READ(reg);
  1993. /*
  1994. * Clear the PIPE*STAT regs before the IIR
  1995. */
  1996. if (pipe_stats[pipe] & 0x8000ffff) {
  1997. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  1998. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  1999. pipe_name(pipe));
  2000. I915_WRITE(reg, pipe_stats[pipe]);
  2001. irq_received = 1;
  2002. }
  2003. }
  2004. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2005. I915_WRITE16(IIR, iir & ~flip_mask);
  2006. new_iir = I915_READ16(IIR); /* Flush posted writes */
  2007. i915_update_dri1_breadcrumb(dev);
  2008. if (iir & I915_USER_INTERRUPT)
  2009. notify_ring(dev, &dev_priv->ring[RCS]);
  2010. if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2011. i8xx_handle_vblank(dev, 0, iir))
  2012. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
  2013. if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2014. i8xx_handle_vblank(dev, 1, iir))
  2015. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
  2016. iir = new_iir;
  2017. }
  2018. return IRQ_HANDLED;
  2019. }
  2020. static void i8xx_irq_uninstall(struct drm_device * dev)
  2021. {
  2022. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2023. int pipe;
  2024. for_each_pipe(pipe) {
  2025. /* Clear enable bits; then clear status bits */
  2026. I915_WRITE(PIPESTAT(pipe), 0);
  2027. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2028. }
  2029. I915_WRITE16(IMR, 0xffff);
  2030. I915_WRITE16(IER, 0x0);
  2031. I915_WRITE16(IIR, I915_READ16(IIR));
  2032. }
  2033. static void i915_irq_preinstall(struct drm_device * dev)
  2034. {
  2035. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2036. int pipe;
  2037. atomic_set(&dev_priv->irq_received, 0);
  2038. if (I915_HAS_HOTPLUG(dev)) {
  2039. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2040. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2041. }
  2042. I915_WRITE16(HWSTAM, 0xeffe);
  2043. for_each_pipe(pipe)
  2044. I915_WRITE(PIPESTAT(pipe), 0);
  2045. I915_WRITE(IMR, 0xffffffff);
  2046. I915_WRITE(IER, 0x0);
  2047. POSTING_READ(IER);
  2048. }
  2049. static int i915_irq_postinstall(struct drm_device *dev)
  2050. {
  2051. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2052. u32 enable_mask;
  2053. I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  2054. /* Unmask the interrupts that we always want on. */
  2055. dev_priv->irq_mask =
  2056. ~(I915_ASLE_INTERRUPT |
  2057. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2058. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2059. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2060. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2061. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2062. enable_mask =
  2063. I915_ASLE_INTERRUPT |
  2064. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2065. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2066. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  2067. I915_USER_INTERRUPT;
  2068. if (I915_HAS_HOTPLUG(dev)) {
  2069. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2070. POSTING_READ(PORT_HOTPLUG_EN);
  2071. /* Enable in IER... */
  2072. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  2073. /* and unmask in IMR */
  2074. dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  2075. }
  2076. I915_WRITE(IMR, dev_priv->irq_mask);
  2077. I915_WRITE(IER, enable_mask);
  2078. POSTING_READ(IER);
  2079. intel_opregion_enable_asle(dev);
  2080. return 0;
  2081. }
  2082. /*
  2083. * Returns true when a page flip has completed.
  2084. */
  2085. static bool i915_handle_vblank(struct drm_device *dev,
  2086. int plane, int pipe, u32 iir)
  2087. {
  2088. drm_i915_private_t *dev_priv = dev->dev_private;
  2089. u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
  2090. if (!drm_handle_vblank(dev, pipe))
  2091. return false;
  2092. if ((iir & flip_pending) == 0)
  2093. return false;
  2094. intel_prepare_page_flip(dev, plane);
  2095. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2096. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2097. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2098. * the flip is completed (no longer pending). Since this doesn't raise
  2099. * an interrupt per se, we watch for the change at vblank.
  2100. */
  2101. if (I915_READ(ISR) & flip_pending)
  2102. return false;
  2103. intel_finish_page_flip(dev, pipe);
  2104. return true;
  2105. }
  2106. static irqreturn_t i915_irq_handler(int irq, void *arg)
  2107. {
  2108. struct drm_device *dev = (struct drm_device *) arg;
  2109. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2110. u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
  2111. unsigned long irqflags;
  2112. u32 flip_mask =
  2113. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2114. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2115. int pipe, ret = IRQ_NONE;
  2116. atomic_inc(&dev_priv->irq_received);
  2117. iir = I915_READ(IIR);
  2118. do {
  2119. bool irq_received = (iir & ~flip_mask) != 0;
  2120. bool blc_event = false;
  2121. /* Can't rely on pipestat interrupt bit in iir as it might
  2122. * have been cleared after the pipestat interrupt was received.
  2123. * It doesn't set the bit in iir again, but it still produces
  2124. * interrupts (for non-MSI).
  2125. */
  2126. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2127. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2128. i915_handle_error(dev, false);
  2129. for_each_pipe(pipe) {
  2130. int reg = PIPESTAT(pipe);
  2131. pipe_stats[pipe] = I915_READ(reg);
  2132. /* Clear the PIPE*STAT regs before the IIR */
  2133. if (pipe_stats[pipe] & 0x8000ffff) {
  2134. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2135. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2136. pipe_name(pipe));
  2137. I915_WRITE(reg, pipe_stats[pipe]);
  2138. irq_received = true;
  2139. }
  2140. }
  2141. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2142. if (!irq_received)
  2143. break;
  2144. /* Consume port. Then clear IIR or we'll miss events */
  2145. if ((I915_HAS_HOTPLUG(dev)) &&
  2146. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  2147. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2148. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2149. hotplug_status);
  2150. if (hotplug_status & HOTPLUG_INT_STATUS_I915)
  2151. queue_work(dev_priv->wq,
  2152. &dev_priv->hotplug_work);
  2153. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2154. POSTING_READ(PORT_HOTPLUG_STAT);
  2155. }
  2156. I915_WRITE(IIR, iir & ~flip_mask);
  2157. new_iir = I915_READ(IIR); /* Flush posted writes */
  2158. if (iir & I915_USER_INTERRUPT)
  2159. notify_ring(dev, &dev_priv->ring[RCS]);
  2160. for_each_pipe(pipe) {
  2161. int plane = pipe;
  2162. if (IS_MOBILE(dev))
  2163. plane = !plane;
  2164. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2165. i915_handle_vblank(dev, plane, pipe, iir))
  2166. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
  2167. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2168. blc_event = true;
  2169. }
  2170. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2171. intel_opregion_asle_intr(dev);
  2172. /* With MSI, interrupts are only generated when iir
  2173. * transitions from zero to nonzero. If another bit got
  2174. * set while we were handling the existing iir bits, then
  2175. * we would never get another interrupt.
  2176. *
  2177. * This is fine on non-MSI as well, as if we hit this path
  2178. * we avoid exiting the interrupt handler only to generate
  2179. * another one.
  2180. *
  2181. * Note that for MSI this could cause a stray interrupt report
  2182. * if an interrupt landed in the time between writing IIR and
  2183. * the posting read. This should be rare enough to never
  2184. * trigger the 99% of 100,000 interrupts test for disabling
  2185. * stray interrupts.
  2186. */
  2187. ret = IRQ_HANDLED;
  2188. iir = new_iir;
  2189. } while (iir & ~flip_mask);
  2190. i915_update_dri1_breadcrumb(dev);
  2191. return ret;
  2192. }
  2193. static void i915_irq_uninstall(struct drm_device * dev)
  2194. {
  2195. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2196. int pipe;
  2197. if (I915_HAS_HOTPLUG(dev)) {
  2198. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2199. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2200. }
  2201. I915_WRITE16(HWSTAM, 0xffff);
  2202. for_each_pipe(pipe) {
  2203. /* Clear enable bits; then clear status bits */
  2204. I915_WRITE(PIPESTAT(pipe), 0);
  2205. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2206. }
  2207. I915_WRITE(IMR, 0xffffffff);
  2208. I915_WRITE(IER, 0x0);
  2209. I915_WRITE(IIR, I915_READ(IIR));
  2210. }
  2211. static void i965_irq_preinstall(struct drm_device * dev)
  2212. {
  2213. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2214. int pipe;
  2215. atomic_set(&dev_priv->irq_received, 0);
  2216. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2217. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2218. I915_WRITE(HWSTAM, 0xeffe);
  2219. for_each_pipe(pipe)
  2220. I915_WRITE(PIPESTAT(pipe), 0);
  2221. I915_WRITE(IMR, 0xffffffff);
  2222. I915_WRITE(IER, 0x0);
  2223. POSTING_READ(IER);
  2224. }
  2225. static int i965_irq_postinstall(struct drm_device *dev)
  2226. {
  2227. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2228. u32 enable_mask;
  2229. u32 error_mask;
  2230. /* Unmask the interrupts that we always want on. */
  2231. dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
  2232. I915_DISPLAY_PORT_INTERRUPT |
  2233. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2234. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2235. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2236. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2237. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2238. enable_mask = ~dev_priv->irq_mask;
  2239. enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2240. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  2241. enable_mask |= I915_USER_INTERRUPT;
  2242. if (IS_G4X(dev))
  2243. enable_mask |= I915_BSD_USER_INTERRUPT;
  2244. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  2245. /*
  2246. * Enable some error detection, note the instruction error mask
  2247. * bit is reserved, so we leave it masked.
  2248. */
  2249. if (IS_G4X(dev)) {
  2250. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  2251. GM45_ERROR_MEM_PRIV |
  2252. GM45_ERROR_CP_PRIV |
  2253. I915_ERROR_MEMORY_REFRESH);
  2254. } else {
  2255. error_mask = ~(I915_ERROR_PAGE_TABLE |
  2256. I915_ERROR_MEMORY_REFRESH);
  2257. }
  2258. I915_WRITE(EMR, error_mask);
  2259. I915_WRITE(IMR, dev_priv->irq_mask);
  2260. I915_WRITE(IER, enable_mask);
  2261. POSTING_READ(IER);
  2262. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2263. POSTING_READ(PORT_HOTPLUG_EN);
  2264. intel_opregion_enable_asle(dev);
  2265. return 0;
  2266. }
  2267. static void i915_hpd_irq_setup(struct drm_device *dev)
  2268. {
  2269. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2270. struct drm_mode_config *mode_config = &dev->mode_config;
  2271. struct intel_encoder *encoder;
  2272. u32 hotplug_en;
  2273. if (I915_HAS_HOTPLUG(dev)) {
  2274. hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  2275. hotplug_en &= ~HOTPLUG_INT_EN_MASK;
  2276. /* Note HDMI and DP share hotplug bits */
  2277. /* enable bits are the same for all generations */
  2278. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  2279. hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
  2280. /* Programming the CRT detection parameters tends
  2281. to generate a spurious hotplug event about three
  2282. seconds later. So just do it once.
  2283. */
  2284. if (IS_G4X(dev))
  2285. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  2286. hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
  2287. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  2288. /* Ignore TV since it's buggy */
  2289. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  2290. }
  2291. }
  2292. static irqreturn_t i965_irq_handler(int irq, void *arg)
  2293. {
  2294. struct drm_device *dev = (struct drm_device *) arg;
  2295. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2296. u32 iir, new_iir;
  2297. u32 pipe_stats[I915_MAX_PIPES];
  2298. unsigned long irqflags;
  2299. int irq_received;
  2300. int ret = IRQ_NONE, pipe;
  2301. u32 flip_mask =
  2302. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2303. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2304. atomic_inc(&dev_priv->irq_received);
  2305. iir = I915_READ(IIR);
  2306. for (;;) {
  2307. bool blc_event = false;
  2308. irq_received = (iir & ~flip_mask) != 0;
  2309. /* Can't rely on pipestat interrupt bit in iir as it might
  2310. * have been cleared after the pipestat interrupt was received.
  2311. * It doesn't set the bit in iir again, but it still produces
  2312. * interrupts (for non-MSI).
  2313. */
  2314. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2315. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2316. i915_handle_error(dev, false);
  2317. for_each_pipe(pipe) {
  2318. int reg = PIPESTAT(pipe);
  2319. pipe_stats[pipe] = I915_READ(reg);
  2320. /*
  2321. * Clear the PIPE*STAT regs before the IIR
  2322. */
  2323. if (pipe_stats[pipe] & 0x8000ffff) {
  2324. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2325. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2326. pipe_name(pipe));
  2327. I915_WRITE(reg, pipe_stats[pipe]);
  2328. irq_received = 1;
  2329. }
  2330. }
  2331. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2332. if (!irq_received)
  2333. break;
  2334. ret = IRQ_HANDLED;
  2335. /* Consume port. Then clear IIR or we'll miss events */
  2336. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  2337. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2338. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2339. hotplug_status);
  2340. if (hotplug_status & (IS_G4X(dev) ?
  2341. HOTPLUG_INT_STATUS_G4X :
  2342. HOTPLUG_INT_STATUS_I965))
  2343. queue_work(dev_priv->wq,
  2344. &dev_priv->hotplug_work);
  2345. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2346. I915_READ(PORT_HOTPLUG_STAT);
  2347. }
  2348. I915_WRITE(IIR, iir & ~flip_mask);
  2349. new_iir = I915_READ(IIR); /* Flush posted writes */
  2350. if (iir & I915_USER_INTERRUPT)
  2351. notify_ring(dev, &dev_priv->ring[RCS]);
  2352. if (iir & I915_BSD_USER_INTERRUPT)
  2353. notify_ring(dev, &dev_priv->ring[VCS]);
  2354. for_each_pipe(pipe) {
  2355. if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  2356. i915_handle_vblank(dev, pipe, pipe, iir))
  2357. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
  2358. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2359. blc_event = true;
  2360. }
  2361. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2362. intel_opregion_asle_intr(dev);
  2363. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  2364. gmbus_irq_handler(dev);
  2365. /* With MSI, interrupts are only generated when iir
  2366. * transitions from zero to nonzero. If another bit got
  2367. * set while we were handling the existing iir bits, then
  2368. * we would never get another interrupt.
  2369. *
  2370. * This is fine on non-MSI as well, as if we hit this path
  2371. * we avoid exiting the interrupt handler only to generate
  2372. * another one.
  2373. *
  2374. * Note that for MSI this could cause a stray interrupt report
  2375. * if an interrupt landed in the time between writing IIR and
  2376. * the posting read. This should be rare enough to never
  2377. * trigger the 99% of 100,000 interrupts test for disabling
  2378. * stray interrupts.
  2379. */
  2380. iir = new_iir;
  2381. }
  2382. i915_update_dri1_breadcrumb(dev);
  2383. return ret;
  2384. }
  2385. static void i965_irq_uninstall(struct drm_device * dev)
  2386. {
  2387. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2388. int pipe;
  2389. if (!dev_priv)
  2390. return;
  2391. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2392. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2393. I915_WRITE(HWSTAM, 0xffffffff);
  2394. for_each_pipe(pipe)
  2395. I915_WRITE(PIPESTAT(pipe), 0);
  2396. I915_WRITE(IMR, 0xffffffff);
  2397. I915_WRITE(IER, 0x0);
  2398. for_each_pipe(pipe)
  2399. I915_WRITE(PIPESTAT(pipe),
  2400. I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
  2401. I915_WRITE(IIR, I915_READ(IIR));
  2402. }
  2403. void intel_irq_init(struct drm_device *dev)
  2404. {
  2405. struct drm_i915_private *dev_priv = dev->dev_private;
  2406. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  2407. INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
  2408. INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
  2409. INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
  2410. setup_timer(&dev_priv->gpu_error.hangcheck_timer,
  2411. i915_hangcheck_elapsed,
  2412. (unsigned long) dev);
  2413. pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
  2414. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  2415. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  2416. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  2417. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  2418. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  2419. }
  2420. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2421. dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
  2422. else
  2423. dev->driver->get_vblank_timestamp = NULL;
  2424. dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
  2425. if (IS_VALLEYVIEW(dev)) {
  2426. dev->driver->irq_handler = valleyview_irq_handler;
  2427. dev->driver->irq_preinstall = valleyview_irq_preinstall;
  2428. dev->driver->irq_postinstall = valleyview_irq_postinstall;
  2429. dev->driver->irq_uninstall = valleyview_irq_uninstall;
  2430. dev->driver->enable_vblank = valleyview_enable_vblank;
  2431. dev->driver->disable_vblank = valleyview_disable_vblank;
  2432. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2433. } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  2434. /* Share pre & uninstall handlers with ILK/SNB */
  2435. dev->driver->irq_handler = ivybridge_irq_handler;
  2436. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2437. dev->driver->irq_postinstall = ivybridge_irq_postinstall;
  2438. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2439. dev->driver->enable_vblank = ivybridge_enable_vblank;
  2440. dev->driver->disable_vblank = ivybridge_disable_vblank;
  2441. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2442. } else if (HAS_PCH_SPLIT(dev)) {
  2443. dev->driver->irq_handler = ironlake_irq_handler;
  2444. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2445. dev->driver->irq_postinstall = ironlake_irq_postinstall;
  2446. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2447. dev->driver->enable_vblank = ironlake_enable_vblank;
  2448. dev->driver->disable_vblank = ironlake_disable_vblank;
  2449. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2450. } else {
  2451. if (INTEL_INFO(dev)->gen == 2) {
  2452. dev->driver->irq_preinstall = i8xx_irq_preinstall;
  2453. dev->driver->irq_postinstall = i8xx_irq_postinstall;
  2454. dev->driver->irq_handler = i8xx_irq_handler;
  2455. dev->driver->irq_uninstall = i8xx_irq_uninstall;
  2456. } else if (INTEL_INFO(dev)->gen == 3) {
  2457. dev->driver->irq_preinstall = i915_irq_preinstall;
  2458. dev->driver->irq_postinstall = i915_irq_postinstall;
  2459. dev->driver->irq_uninstall = i915_irq_uninstall;
  2460. dev->driver->irq_handler = i915_irq_handler;
  2461. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2462. } else {
  2463. dev->driver->irq_preinstall = i965_irq_preinstall;
  2464. dev->driver->irq_postinstall = i965_irq_postinstall;
  2465. dev->driver->irq_uninstall = i965_irq_uninstall;
  2466. dev->driver->irq_handler = i965_irq_handler;
  2467. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2468. }
  2469. dev->driver->enable_vblank = i915_enable_vblank;
  2470. dev->driver->disable_vblank = i915_disable_vblank;
  2471. }
  2472. }
  2473. void intel_hpd_init(struct drm_device *dev)
  2474. {
  2475. struct drm_i915_private *dev_priv = dev->dev_private;
  2476. if (dev_priv->display.hpd_irq_setup)
  2477. dev_priv->display.hpd_irq_setup(dev);
  2478. }