i915_debugfs.c 58 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include <generated/utsrelease.h>
  33. #include <drm/drmP.h>
  34. #include "intel_drv.h"
  35. #include "intel_ringbuffer.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #define DRM_I915_RING_DEBUG 1
  39. #if defined(CONFIG_DEBUG_FS)
  40. enum {
  41. ACTIVE_LIST,
  42. INACTIVE_LIST,
  43. PINNED_LIST,
  44. };
  45. static const char *yesno(int v)
  46. {
  47. return v ? "yes" : "no";
  48. }
  49. static int i915_capabilities(struct seq_file *m, void *data)
  50. {
  51. struct drm_info_node *node = (struct drm_info_node *) m->private;
  52. struct drm_device *dev = node->minor->dev;
  53. const struct intel_device_info *info = INTEL_INFO(dev);
  54. seq_printf(m, "gen: %d\n", info->gen);
  55. seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  56. #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  57. #define DEV_INFO_SEP ;
  58. DEV_INFO_FLAGS;
  59. #undef DEV_INFO_FLAG
  60. #undef DEV_INFO_SEP
  61. return 0;
  62. }
  63. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  64. {
  65. if (obj->user_pin_count > 0)
  66. return "P";
  67. else if (obj->pin_count > 0)
  68. return "p";
  69. else
  70. return " ";
  71. }
  72. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  73. {
  74. switch (obj->tiling_mode) {
  75. default:
  76. case I915_TILING_NONE: return " ";
  77. case I915_TILING_X: return "X";
  78. case I915_TILING_Y: return "Y";
  79. }
  80. }
  81. static const char *cache_level_str(int type)
  82. {
  83. switch (type) {
  84. case I915_CACHE_NONE: return " uncached";
  85. case I915_CACHE_LLC: return " snooped (LLC)";
  86. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  87. default: return "";
  88. }
  89. }
  90. static void
  91. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  92. {
  93. seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
  94. &obj->base,
  95. get_pin_flag(obj),
  96. get_tiling_flag(obj),
  97. obj->base.size / 1024,
  98. obj->base.read_domains,
  99. obj->base.write_domain,
  100. obj->last_read_seqno,
  101. obj->last_write_seqno,
  102. obj->last_fenced_seqno,
  103. cache_level_str(obj->cache_level),
  104. obj->dirty ? " dirty" : "",
  105. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  106. if (obj->base.name)
  107. seq_printf(m, " (name: %d)", obj->base.name);
  108. if (obj->pin_count)
  109. seq_printf(m, " (pinned x %d)", obj->pin_count);
  110. if (obj->fence_reg != I915_FENCE_REG_NONE)
  111. seq_printf(m, " (fence: %d)", obj->fence_reg);
  112. if (obj->gtt_space != NULL)
  113. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  114. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  115. if (obj->stolen)
  116. seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
  117. if (obj->pin_mappable || obj->fault_mappable) {
  118. char s[3], *t = s;
  119. if (obj->pin_mappable)
  120. *t++ = 'p';
  121. if (obj->fault_mappable)
  122. *t++ = 'f';
  123. *t = '\0';
  124. seq_printf(m, " (%s mappable)", s);
  125. }
  126. if (obj->ring != NULL)
  127. seq_printf(m, " (%s)", obj->ring->name);
  128. }
  129. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  130. {
  131. struct drm_info_node *node = (struct drm_info_node *) m->private;
  132. uintptr_t list = (uintptr_t) node->info_ent->data;
  133. struct list_head *head;
  134. struct drm_device *dev = node->minor->dev;
  135. drm_i915_private_t *dev_priv = dev->dev_private;
  136. struct drm_i915_gem_object *obj;
  137. size_t total_obj_size, total_gtt_size;
  138. int count, ret;
  139. ret = mutex_lock_interruptible(&dev->struct_mutex);
  140. if (ret)
  141. return ret;
  142. switch (list) {
  143. case ACTIVE_LIST:
  144. seq_printf(m, "Active:\n");
  145. head = &dev_priv->mm.active_list;
  146. break;
  147. case INACTIVE_LIST:
  148. seq_printf(m, "Inactive:\n");
  149. head = &dev_priv->mm.inactive_list;
  150. break;
  151. default:
  152. mutex_unlock(&dev->struct_mutex);
  153. return -EINVAL;
  154. }
  155. total_obj_size = total_gtt_size = count = 0;
  156. list_for_each_entry(obj, head, mm_list) {
  157. seq_printf(m, " ");
  158. describe_obj(m, obj);
  159. seq_printf(m, "\n");
  160. total_obj_size += obj->base.size;
  161. total_gtt_size += obj->gtt_space->size;
  162. count++;
  163. }
  164. mutex_unlock(&dev->struct_mutex);
  165. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  166. count, total_obj_size, total_gtt_size);
  167. return 0;
  168. }
  169. #define count_objects(list, member) do { \
  170. list_for_each_entry(obj, list, member) { \
  171. size += obj->gtt_space->size; \
  172. ++count; \
  173. if (obj->map_and_fenceable) { \
  174. mappable_size += obj->gtt_space->size; \
  175. ++mappable_count; \
  176. } \
  177. } \
  178. } while (0)
  179. static int i915_gem_object_info(struct seq_file *m, void* data)
  180. {
  181. struct drm_info_node *node = (struct drm_info_node *) m->private;
  182. struct drm_device *dev = node->minor->dev;
  183. struct drm_i915_private *dev_priv = dev->dev_private;
  184. u32 count, mappable_count, purgeable_count;
  185. size_t size, mappable_size, purgeable_size;
  186. struct drm_i915_gem_object *obj;
  187. int ret;
  188. ret = mutex_lock_interruptible(&dev->struct_mutex);
  189. if (ret)
  190. return ret;
  191. seq_printf(m, "%u objects, %zu bytes\n",
  192. dev_priv->mm.object_count,
  193. dev_priv->mm.object_memory);
  194. size = count = mappable_size = mappable_count = 0;
  195. count_objects(&dev_priv->mm.bound_list, gtt_list);
  196. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  197. count, mappable_count, size, mappable_size);
  198. size = count = mappable_size = mappable_count = 0;
  199. count_objects(&dev_priv->mm.active_list, mm_list);
  200. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  201. count, mappable_count, size, mappable_size);
  202. size = count = mappable_size = mappable_count = 0;
  203. count_objects(&dev_priv->mm.inactive_list, mm_list);
  204. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  205. count, mappable_count, size, mappable_size);
  206. size = count = purgeable_size = purgeable_count = 0;
  207. list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
  208. size += obj->base.size, ++count;
  209. if (obj->madv == I915_MADV_DONTNEED)
  210. purgeable_size += obj->base.size, ++purgeable_count;
  211. }
  212. seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
  213. size = count = mappable_size = mappable_count = 0;
  214. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  215. if (obj->fault_mappable) {
  216. size += obj->gtt_space->size;
  217. ++count;
  218. }
  219. if (obj->pin_mappable) {
  220. mappable_size += obj->gtt_space->size;
  221. ++mappable_count;
  222. }
  223. if (obj->madv == I915_MADV_DONTNEED) {
  224. purgeable_size += obj->base.size;
  225. ++purgeable_count;
  226. }
  227. }
  228. seq_printf(m, "%u purgeable objects, %zu bytes\n",
  229. purgeable_count, purgeable_size);
  230. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  231. mappable_count, mappable_size);
  232. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  233. count, size);
  234. seq_printf(m, "%zu [%lu] gtt total\n",
  235. dev_priv->gtt.total,
  236. dev_priv->gtt.mappable_end - dev_priv->gtt.start);
  237. mutex_unlock(&dev->struct_mutex);
  238. return 0;
  239. }
  240. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  241. {
  242. struct drm_info_node *node = (struct drm_info_node *) m->private;
  243. struct drm_device *dev = node->minor->dev;
  244. uintptr_t list = (uintptr_t) node->info_ent->data;
  245. struct drm_i915_private *dev_priv = dev->dev_private;
  246. struct drm_i915_gem_object *obj;
  247. size_t total_obj_size, total_gtt_size;
  248. int count, ret;
  249. ret = mutex_lock_interruptible(&dev->struct_mutex);
  250. if (ret)
  251. return ret;
  252. total_obj_size = total_gtt_size = count = 0;
  253. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  254. if (list == PINNED_LIST && obj->pin_count == 0)
  255. continue;
  256. seq_printf(m, " ");
  257. describe_obj(m, obj);
  258. seq_printf(m, "\n");
  259. total_obj_size += obj->base.size;
  260. total_gtt_size += obj->gtt_space->size;
  261. count++;
  262. }
  263. mutex_unlock(&dev->struct_mutex);
  264. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  265. count, total_obj_size, total_gtt_size);
  266. return 0;
  267. }
  268. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  269. {
  270. struct drm_info_node *node = (struct drm_info_node *) m->private;
  271. struct drm_device *dev = node->minor->dev;
  272. unsigned long flags;
  273. struct intel_crtc *crtc;
  274. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  275. const char pipe = pipe_name(crtc->pipe);
  276. const char plane = plane_name(crtc->plane);
  277. struct intel_unpin_work *work;
  278. spin_lock_irqsave(&dev->event_lock, flags);
  279. work = crtc->unpin_work;
  280. if (work == NULL) {
  281. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  282. pipe, plane);
  283. } else {
  284. if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  285. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  286. pipe, plane);
  287. } else {
  288. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  289. pipe, plane);
  290. }
  291. if (work->enable_stall_check)
  292. seq_printf(m, "Stall check enabled, ");
  293. else
  294. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  295. seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
  296. if (work->old_fb_obj) {
  297. struct drm_i915_gem_object *obj = work->old_fb_obj;
  298. if (obj)
  299. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  300. }
  301. if (work->pending_flip_obj) {
  302. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  303. if (obj)
  304. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  305. }
  306. }
  307. spin_unlock_irqrestore(&dev->event_lock, flags);
  308. }
  309. return 0;
  310. }
  311. static int i915_gem_request_info(struct seq_file *m, void *data)
  312. {
  313. struct drm_info_node *node = (struct drm_info_node *) m->private;
  314. struct drm_device *dev = node->minor->dev;
  315. drm_i915_private_t *dev_priv = dev->dev_private;
  316. struct intel_ring_buffer *ring;
  317. struct drm_i915_gem_request *gem_request;
  318. int ret, count, i;
  319. ret = mutex_lock_interruptible(&dev->struct_mutex);
  320. if (ret)
  321. return ret;
  322. count = 0;
  323. for_each_ring(ring, dev_priv, i) {
  324. if (list_empty(&ring->request_list))
  325. continue;
  326. seq_printf(m, "%s requests:\n", ring->name);
  327. list_for_each_entry(gem_request,
  328. &ring->request_list,
  329. list) {
  330. seq_printf(m, " %d @ %d\n",
  331. gem_request->seqno,
  332. (int) (jiffies - gem_request->emitted_jiffies));
  333. }
  334. count++;
  335. }
  336. mutex_unlock(&dev->struct_mutex);
  337. if (count == 0)
  338. seq_printf(m, "No requests\n");
  339. return 0;
  340. }
  341. static void i915_ring_seqno_info(struct seq_file *m,
  342. struct intel_ring_buffer *ring)
  343. {
  344. if (ring->get_seqno) {
  345. seq_printf(m, "Current sequence (%s): %u\n",
  346. ring->name, ring->get_seqno(ring, false));
  347. }
  348. }
  349. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  350. {
  351. struct drm_info_node *node = (struct drm_info_node *) m->private;
  352. struct drm_device *dev = node->minor->dev;
  353. drm_i915_private_t *dev_priv = dev->dev_private;
  354. struct intel_ring_buffer *ring;
  355. int ret, i;
  356. ret = mutex_lock_interruptible(&dev->struct_mutex);
  357. if (ret)
  358. return ret;
  359. for_each_ring(ring, dev_priv, i)
  360. i915_ring_seqno_info(m, ring);
  361. mutex_unlock(&dev->struct_mutex);
  362. return 0;
  363. }
  364. static int i915_interrupt_info(struct seq_file *m, void *data)
  365. {
  366. struct drm_info_node *node = (struct drm_info_node *) m->private;
  367. struct drm_device *dev = node->minor->dev;
  368. drm_i915_private_t *dev_priv = dev->dev_private;
  369. struct intel_ring_buffer *ring;
  370. int ret, i, pipe;
  371. ret = mutex_lock_interruptible(&dev->struct_mutex);
  372. if (ret)
  373. return ret;
  374. if (IS_VALLEYVIEW(dev)) {
  375. seq_printf(m, "Display IER:\t%08x\n",
  376. I915_READ(VLV_IER));
  377. seq_printf(m, "Display IIR:\t%08x\n",
  378. I915_READ(VLV_IIR));
  379. seq_printf(m, "Display IIR_RW:\t%08x\n",
  380. I915_READ(VLV_IIR_RW));
  381. seq_printf(m, "Display IMR:\t%08x\n",
  382. I915_READ(VLV_IMR));
  383. for_each_pipe(pipe)
  384. seq_printf(m, "Pipe %c stat:\t%08x\n",
  385. pipe_name(pipe),
  386. I915_READ(PIPESTAT(pipe)));
  387. seq_printf(m, "Master IER:\t%08x\n",
  388. I915_READ(VLV_MASTER_IER));
  389. seq_printf(m, "Render IER:\t%08x\n",
  390. I915_READ(GTIER));
  391. seq_printf(m, "Render IIR:\t%08x\n",
  392. I915_READ(GTIIR));
  393. seq_printf(m, "Render IMR:\t%08x\n",
  394. I915_READ(GTIMR));
  395. seq_printf(m, "PM IER:\t\t%08x\n",
  396. I915_READ(GEN6_PMIER));
  397. seq_printf(m, "PM IIR:\t\t%08x\n",
  398. I915_READ(GEN6_PMIIR));
  399. seq_printf(m, "PM IMR:\t\t%08x\n",
  400. I915_READ(GEN6_PMIMR));
  401. seq_printf(m, "Port hotplug:\t%08x\n",
  402. I915_READ(PORT_HOTPLUG_EN));
  403. seq_printf(m, "DPFLIPSTAT:\t%08x\n",
  404. I915_READ(VLV_DPFLIPSTAT));
  405. seq_printf(m, "DPINVGTT:\t%08x\n",
  406. I915_READ(DPINVGTT));
  407. } else if (!HAS_PCH_SPLIT(dev)) {
  408. seq_printf(m, "Interrupt enable: %08x\n",
  409. I915_READ(IER));
  410. seq_printf(m, "Interrupt identity: %08x\n",
  411. I915_READ(IIR));
  412. seq_printf(m, "Interrupt mask: %08x\n",
  413. I915_READ(IMR));
  414. for_each_pipe(pipe)
  415. seq_printf(m, "Pipe %c stat: %08x\n",
  416. pipe_name(pipe),
  417. I915_READ(PIPESTAT(pipe)));
  418. } else {
  419. seq_printf(m, "North Display Interrupt enable: %08x\n",
  420. I915_READ(DEIER));
  421. seq_printf(m, "North Display Interrupt identity: %08x\n",
  422. I915_READ(DEIIR));
  423. seq_printf(m, "North Display Interrupt mask: %08x\n",
  424. I915_READ(DEIMR));
  425. seq_printf(m, "South Display Interrupt enable: %08x\n",
  426. I915_READ(SDEIER));
  427. seq_printf(m, "South Display Interrupt identity: %08x\n",
  428. I915_READ(SDEIIR));
  429. seq_printf(m, "South Display Interrupt mask: %08x\n",
  430. I915_READ(SDEIMR));
  431. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  432. I915_READ(GTIER));
  433. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  434. I915_READ(GTIIR));
  435. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  436. I915_READ(GTIMR));
  437. }
  438. seq_printf(m, "Interrupts received: %d\n",
  439. atomic_read(&dev_priv->irq_received));
  440. for_each_ring(ring, dev_priv, i) {
  441. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  442. seq_printf(m,
  443. "Graphics Interrupt mask (%s): %08x\n",
  444. ring->name, I915_READ_IMR(ring));
  445. }
  446. i915_ring_seqno_info(m, ring);
  447. }
  448. mutex_unlock(&dev->struct_mutex);
  449. return 0;
  450. }
  451. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  452. {
  453. struct drm_info_node *node = (struct drm_info_node *) m->private;
  454. struct drm_device *dev = node->minor->dev;
  455. drm_i915_private_t *dev_priv = dev->dev_private;
  456. int i, ret;
  457. ret = mutex_lock_interruptible(&dev->struct_mutex);
  458. if (ret)
  459. return ret;
  460. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  461. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  462. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  463. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  464. seq_printf(m, "Fence %d, pin count = %d, object = ",
  465. i, dev_priv->fence_regs[i].pin_count);
  466. if (obj == NULL)
  467. seq_printf(m, "unused");
  468. else
  469. describe_obj(m, obj);
  470. seq_printf(m, "\n");
  471. }
  472. mutex_unlock(&dev->struct_mutex);
  473. return 0;
  474. }
  475. static int i915_hws_info(struct seq_file *m, void *data)
  476. {
  477. struct drm_info_node *node = (struct drm_info_node *) m->private;
  478. struct drm_device *dev = node->minor->dev;
  479. drm_i915_private_t *dev_priv = dev->dev_private;
  480. struct intel_ring_buffer *ring;
  481. const u32 *hws;
  482. int i;
  483. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  484. hws = ring->status_page.page_addr;
  485. if (hws == NULL)
  486. return 0;
  487. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  488. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  489. i * 4,
  490. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  491. }
  492. return 0;
  493. }
  494. static const char *ring_str(int ring)
  495. {
  496. switch (ring) {
  497. case RCS: return "render";
  498. case VCS: return "bsd";
  499. case BCS: return "blt";
  500. default: return "";
  501. }
  502. }
  503. static const char *pin_flag(int pinned)
  504. {
  505. if (pinned > 0)
  506. return " P";
  507. else if (pinned < 0)
  508. return " p";
  509. else
  510. return "";
  511. }
  512. static const char *tiling_flag(int tiling)
  513. {
  514. switch (tiling) {
  515. default:
  516. case I915_TILING_NONE: return "";
  517. case I915_TILING_X: return " X";
  518. case I915_TILING_Y: return " Y";
  519. }
  520. }
  521. static const char *dirty_flag(int dirty)
  522. {
  523. return dirty ? " dirty" : "";
  524. }
  525. static const char *purgeable_flag(int purgeable)
  526. {
  527. return purgeable ? " purgeable" : "";
  528. }
  529. static void print_error_buffers(struct seq_file *m,
  530. const char *name,
  531. struct drm_i915_error_buffer *err,
  532. int count)
  533. {
  534. seq_printf(m, "%s [%d]:\n", name, count);
  535. while (count--) {
  536. seq_printf(m, " %08x %8u %02x %02x %x %x%s%s%s%s%s%s%s",
  537. err->gtt_offset,
  538. err->size,
  539. err->read_domains,
  540. err->write_domain,
  541. err->rseqno, err->wseqno,
  542. pin_flag(err->pinned),
  543. tiling_flag(err->tiling),
  544. dirty_flag(err->dirty),
  545. purgeable_flag(err->purgeable),
  546. err->ring != -1 ? " " : "",
  547. ring_str(err->ring),
  548. cache_level_str(err->cache_level));
  549. if (err->name)
  550. seq_printf(m, " (name: %d)", err->name);
  551. if (err->fence_reg != I915_FENCE_REG_NONE)
  552. seq_printf(m, " (fence: %d)", err->fence_reg);
  553. seq_printf(m, "\n");
  554. err++;
  555. }
  556. }
  557. static void i915_ring_error_state(struct seq_file *m,
  558. struct drm_device *dev,
  559. struct drm_i915_error_state *error,
  560. unsigned ring)
  561. {
  562. BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
  563. seq_printf(m, "%s command stream:\n", ring_str(ring));
  564. seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
  565. seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
  566. seq_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
  567. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
  568. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
  569. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
  570. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
  571. if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
  572. seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
  573. if (INTEL_INFO(dev)->gen >= 4)
  574. seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
  575. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
  576. seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
  577. if (INTEL_INFO(dev)->gen >= 6) {
  578. seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
  579. seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
  580. seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
  581. error->semaphore_mboxes[ring][0],
  582. error->semaphore_seqno[ring][0]);
  583. seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
  584. error->semaphore_mboxes[ring][1],
  585. error->semaphore_seqno[ring][1]);
  586. }
  587. seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
  588. seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
  589. seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
  590. seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
  591. }
  592. struct i915_error_state_file_priv {
  593. struct drm_device *dev;
  594. struct drm_i915_error_state *error;
  595. };
  596. static int i915_error_state(struct seq_file *m, void *unused)
  597. {
  598. struct i915_error_state_file_priv *error_priv = m->private;
  599. struct drm_device *dev = error_priv->dev;
  600. drm_i915_private_t *dev_priv = dev->dev_private;
  601. struct drm_i915_error_state *error = error_priv->error;
  602. struct intel_ring_buffer *ring;
  603. int i, j, page, offset, elt;
  604. if (!error) {
  605. seq_printf(m, "no error state collected\n");
  606. return 0;
  607. }
  608. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  609. error->time.tv_usec);
  610. seq_printf(m, "Kernel: " UTS_RELEASE "\n");
  611. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  612. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  613. seq_printf(m, "IER: 0x%08x\n", error->ier);
  614. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  615. seq_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
  616. seq_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
  617. seq_printf(m, "CCID: 0x%08x\n", error->ccid);
  618. for (i = 0; i < dev_priv->num_fence_regs; i++)
  619. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  620. for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
  621. seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
  622. if (INTEL_INFO(dev)->gen >= 6) {
  623. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  624. seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  625. }
  626. if (INTEL_INFO(dev)->gen == 7)
  627. seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
  628. for_each_ring(ring, dev_priv, i)
  629. i915_ring_error_state(m, dev, error, i);
  630. if (error->active_bo)
  631. print_error_buffers(m, "Active",
  632. error->active_bo,
  633. error->active_bo_count);
  634. if (error->pinned_bo)
  635. print_error_buffers(m, "Pinned",
  636. error->pinned_bo,
  637. error->pinned_bo_count);
  638. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  639. struct drm_i915_error_object *obj;
  640. if ((obj = error->ring[i].batchbuffer)) {
  641. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  642. dev_priv->ring[i].name,
  643. obj->gtt_offset);
  644. offset = 0;
  645. for (page = 0; page < obj->page_count; page++) {
  646. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  647. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  648. offset += 4;
  649. }
  650. }
  651. }
  652. if (error->ring[i].num_requests) {
  653. seq_printf(m, "%s --- %d requests\n",
  654. dev_priv->ring[i].name,
  655. error->ring[i].num_requests);
  656. for (j = 0; j < error->ring[i].num_requests; j++) {
  657. seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
  658. error->ring[i].requests[j].seqno,
  659. error->ring[i].requests[j].jiffies,
  660. error->ring[i].requests[j].tail);
  661. }
  662. }
  663. if ((obj = error->ring[i].ringbuffer)) {
  664. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  665. dev_priv->ring[i].name,
  666. obj->gtt_offset);
  667. offset = 0;
  668. for (page = 0; page < obj->page_count; page++) {
  669. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  670. seq_printf(m, "%08x : %08x\n",
  671. offset,
  672. obj->pages[page][elt]);
  673. offset += 4;
  674. }
  675. }
  676. }
  677. obj = error->ring[i].ctx;
  678. if (obj) {
  679. seq_printf(m, "%s --- HW Context = 0x%08x\n",
  680. dev_priv->ring[i].name,
  681. obj->gtt_offset);
  682. offset = 0;
  683. for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
  684. seq_printf(m, "[%04x] %08x %08x %08x %08x\n",
  685. offset,
  686. obj->pages[0][elt],
  687. obj->pages[0][elt+1],
  688. obj->pages[0][elt+2],
  689. obj->pages[0][elt+3]);
  690. offset += 16;
  691. }
  692. }
  693. }
  694. if (error->overlay)
  695. intel_overlay_print_error_state(m, error->overlay);
  696. if (error->display)
  697. intel_display_print_error_state(m, dev, error->display);
  698. return 0;
  699. }
  700. static ssize_t
  701. i915_error_state_write(struct file *filp,
  702. const char __user *ubuf,
  703. size_t cnt,
  704. loff_t *ppos)
  705. {
  706. struct seq_file *m = filp->private_data;
  707. struct i915_error_state_file_priv *error_priv = m->private;
  708. struct drm_device *dev = error_priv->dev;
  709. int ret;
  710. DRM_DEBUG_DRIVER("Resetting error state\n");
  711. ret = mutex_lock_interruptible(&dev->struct_mutex);
  712. if (ret)
  713. return ret;
  714. i915_destroy_error_state(dev);
  715. mutex_unlock(&dev->struct_mutex);
  716. return cnt;
  717. }
  718. static int i915_error_state_open(struct inode *inode, struct file *file)
  719. {
  720. struct drm_device *dev = inode->i_private;
  721. drm_i915_private_t *dev_priv = dev->dev_private;
  722. struct i915_error_state_file_priv *error_priv;
  723. unsigned long flags;
  724. error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
  725. if (!error_priv)
  726. return -ENOMEM;
  727. error_priv->dev = dev;
  728. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  729. error_priv->error = dev_priv->gpu_error.first_error;
  730. if (error_priv->error)
  731. kref_get(&error_priv->error->ref);
  732. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  733. return single_open(file, i915_error_state, error_priv);
  734. }
  735. static int i915_error_state_release(struct inode *inode, struct file *file)
  736. {
  737. struct seq_file *m = file->private_data;
  738. struct i915_error_state_file_priv *error_priv = m->private;
  739. if (error_priv->error)
  740. kref_put(&error_priv->error->ref, i915_error_state_free);
  741. kfree(error_priv);
  742. return single_release(inode, file);
  743. }
  744. static const struct file_operations i915_error_state_fops = {
  745. .owner = THIS_MODULE,
  746. .open = i915_error_state_open,
  747. .read = seq_read,
  748. .write = i915_error_state_write,
  749. .llseek = default_llseek,
  750. .release = i915_error_state_release,
  751. };
  752. static int
  753. i915_next_seqno_get(void *data, u64 *val)
  754. {
  755. struct drm_device *dev = data;
  756. drm_i915_private_t *dev_priv = dev->dev_private;
  757. int ret;
  758. ret = mutex_lock_interruptible(&dev->struct_mutex);
  759. if (ret)
  760. return ret;
  761. *val = dev_priv->next_seqno;
  762. mutex_unlock(&dev->struct_mutex);
  763. return 0;
  764. }
  765. static int
  766. i915_next_seqno_set(void *data, u64 val)
  767. {
  768. struct drm_device *dev = data;
  769. int ret;
  770. ret = mutex_lock_interruptible(&dev->struct_mutex);
  771. if (ret)
  772. return ret;
  773. ret = i915_gem_set_seqno(dev, val);
  774. mutex_unlock(&dev->struct_mutex);
  775. return ret;
  776. }
  777. DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
  778. i915_next_seqno_get, i915_next_seqno_set,
  779. "next_seqno : 0x%llx\n");
  780. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  781. {
  782. struct drm_info_node *node = (struct drm_info_node *) m->private;
  783. struct drm_device *dev = node->minor->dev;
  784. drm_i915_private_t *dev_priv = dev->dev_private;
  785. u16 crstanddelay;
  786. int ret;
  787. ret = mutex_lock_interruptible(&dev->struct_mutex);
  788. if (ret)
  789. return ret;
  790. crstanddelay = I915_READ16(CRSTANDVID);
  791. mutex_unlock(&dev->struct_mutex);
  792. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  793. return 0;
  794. }
  795. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  796. {
  797. struct drm_info_node *node = (struct drm_info_node *) m->private;
  798. struct drm_device *dev = node->minor->dev;
  799. drm_i915_private_t *dev_priv = dev->dev_private;
  800. int ret;
  801. if (IS_GEN5(dev)) {
  802. u16 rgvswctl = I915_READ16(MEMSWCTL);
  803. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  804. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  805. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  806. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  807. MEMSTAT_VID_SHIFT);
  808. seq_printf(m, "Current P-state: %d\n",
  809. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  810. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  811. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  812. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  813. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  814. u32 rpstat, cagf;
  815. u32 rpupei, rpcurup, rpprevup;
  816. u32 rpdownei, rpcurdown, rpprevdown;
  817. int max_freq;
  818. /* RPSTAT1 is in the GT power well */
  819. ret = mutex_lock_interruptible(&dev->struct_mutex);
  820. if (ret)
  821. return ret;
  822. gen6_gt_force_wake_get(dev_priv);
  823. rpstat = I915_READ(GEN6_RPSTAT1);
  824. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  825. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  826. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  827. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  828. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  829. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  830. if (IS_HASWELL(dev))
  831. cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
  832. else
  833. cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
  834. cagf *= GT_FREQUENCY_MULTIPLIER;
  835. gen6_gt_force_wake_put(dev_priv);
  836. mutex_unlock(&dev->struct_mutex);
  837. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  838. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  839. seq_printf(m, "Render p-state ratio: %d\n",
  840. (gt_perf_status & 0xff00) >> 8);
  841. seq_printf(m, "Render p-state VID: %d\n",
  842. gt_perf_status & 0xff);
  843. seq_printf(m, "Render p-state limit: %d\n",
  844. rp_state_limits & 0xff);
  845. seq_printf(m, "CAGF: %dMHz\n", cagf);
  846. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  847. GEN6_CURICONT_MASK);
  848. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  849. GEN6_CURBSYTAVG_MASK);
  850. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  851. GEN6_CURBSYTAVG_MASK);
  852. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  853. GEN6_CURIAVG_MASK);
  854. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  855. GEN6_CURBSYTAVG_MASK);
  856. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  857. GEN6_CURBSYTAVG_MASK);
  858. max_freq = (rp_state_cap & 0xff0000) >> 16;
  859. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  860. max_freq * GT_FREQUENCY_MULTIPLIER);
  861. max_freq = (rp_state_cap & 0xff00) >> 8;
  862. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  863. max_freq * GT_FREQUENCY_MULTIPLIER);
  864. max_freq = rp_state_cap & 0xff;
  865. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  866. max_freq * GT_FREQUENCY_MULTIPLIER);
  867. } else {
  868. seq_printf(m, "no P-state info available\n");
  869. }
  870. return 0;
  871. }
  872. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  873. {
  874. struct drm_info_node *node = (struct drm_info_node *) m->private;
  875. struct drm_device *dev = node->minor->dev;
  876. drm_i915_private_t *dev_priv = dev->dev_private;
  877. u32 delayfreq;
  878. int ret, i;
  879. ret = mutex_lock_interruptible(&dev->struct_mutex);
  880. if (ret)
  881. return ret;
  882. for (i = 0; i < 16; i++) {
  883. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  884. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  885. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  886. }
  887. mutex_unlock(&dev->struct_mutex);
  888. return 0;
  889. }
  890. static inline int MAP_TO_MV(int map)
  891. {
  892. return 1250 - (map * 25);
  893. }
  894. static int i915_inttoext_table(struct seq_file *m, void *unused)
  895. {
  896. struct drm_info_node *node = (struct drm_info_node *) m->private;
  897. struct drm_device *dev = node->minor->dev;
  898. drm_i915_private_t *dev_priv = dev->dev_private;
  899. u32 inttoext;
  900. int ret, i;
  901. ret = mutex_lock_interruptible(&dev->struct_mutex);
  902. if (ret)
  903. return ret;
  904. for (i = 1; i <= 32; i++) {
  905. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  906. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  907. }
  908. mutex_unlock(&dev->struct_mutex);
  909. return 0;
  910. }
  911. static int ironlake_drpc_info(struct seq_file *m)
  912. {
  913. struct drm_info_node *node = (struct drm_info_node *) m->private;
  914. struct drm_device *dev = node->minor->dev;
  915. drm_i915_private_t *dev_priv = dev->dev_private;
  916. u32 rgvmodectl, rstdbyctl;
  917. u16 crstandvid;
  918. int ret;
  919. ret = mutex_lock_interruptible(&dev->struct_mutex);
  920. if (ret)
  921. return ret;
  922. rgvmodectl = I915_READ(MEMMODECTL);
  923. rstdbyctl = I915_READ(RSTDBYCTL);
  924. crstandvid = I915_READ16(CRSTANDVID);
  925. mutex_unlock(&dev->struct_mutex);
  926. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  927. "yes" : "no");
  928. seq_printf(m, "Boost freq: %d\n",
  929. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  930. MEMMODE_BOOST_FREQ_SHIFT);
  931. seq_printf(m, "HW control enabled: %s\n",
  932. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  933. seq_printf(m, "SW control enabled: %s\n",
  934. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  935. seq_printf(m, "Gated voltage change: %s\n",
  936. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  937. seq_printf(m, "Starting frequency: P%d\n",
  938. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  939. seq_printf(m, "Max P-state: P%d\n",
  940. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  941. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  942. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  943. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  944. seq_printf(m, "Render standby enabled: %s\n",
  945. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  946. seq_printf(m, "Current RS state: ");
  947. switch (rstdbyctl & RSX_STATUS_MASK) {
  948. case RSX_STATUS_ON:
  949. seq_printf(m, "on\n");
  950. break;
  951. case RSX_STATUS_RC1:
  952. seq_printf(m, "RC1\n");
  953. break;
  954. case RSX_STATUS_RC1E:
  955. seq_printf(m, "RC1E\n");
  956. break;
  957. case RSX_STATUS_RS1:
  958. seq_printf(m, "RS1\n");
  959. break;
  960. case RSX_STATUS_RS2:
  961. seq_printf(m, "RS2 (RC6)\n");
  962. break;
  963. case RSX_STATUS_RS3:
  964. seq_printf(m, "RC3 (RC6+)\n");
  965. break;
  966. default:
  967. seq_printf(m, "unknown\n");
  968. break;
  969. }
  970. return 0;
  971. }
  972. static int gen6_drpc_info(struct seq_file *m)
  973. {
  974. struct drm_info_node *node = (struct drm_info_node *) m->private;
  975. struct drm_device *dev = node->minor->dev;
  976. struct drm_i915_private *dev_priv = dev->dev_private;
  977. u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
  978. unsigned forcewake_count;
  979. int count=0, ret;
  980. ret = mutex_lock_interruptible(&dev->struct_mutex);
  981. if (ret)
  982. return ret;
  983. spin_lock_irq(&dev_priv->gt_lock);
  984. forcewake_count = dev_priv->forcewake_count;
  985. spin_unlock_irq(&dev_priv->gt_lock);
  986. if (forcewake_count) {
  987. seq_printf(m, "RC information inaccurate because somebody "
  988. "holds a forcewake reference \n");
  989. } else {
  990. /* NB: we cannot use forcewake, else we read the wrong values */
  991. while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  992. udelay(10);
  993. seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
  994. }
  995. gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
  996. trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
  997. rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
  998. rcctl1 = I915_READ(GEN6_RC_CONTROL);
  999. mutex_unlock(&dev->struct_mutex);
  1000. mutex_lock(&dev_priv->rps.hw_lock);
  1001. sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
  1002. mutex_unlock(&dev_priv->rps.hw_lock);
  1003. seq_printf(m, "Video Turbo Mode: %s\n",
  1004. yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
  1005. seq_printf(m, "HW control enabled: %s\n",
  1006. yesno(rpmodectl1 & GEN6_RP_ENABLE));
  1007. seq_printf(m, "SW control enabled: %s\n",
  1008. yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
  1009. GEN6_RP_MEDIA_SW_MODE));
  1010. seq_printf(m, "RC1e Enabled: %s\n",
  1011. yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
  1012. seq_printf(m, "RC6 Enabled: %s\n",
  1013. yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
  1014. seq_printf(m, "Deep RC6 Enabled: %s\n",
  1015. yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
  1016. seq_printf(m, "Deepest RC6 Enabled: %s\n",
  1017. yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
  1018. seq_printf(m, "Current RC state: ");
  1019. switch (gt_core_status & GEN6_RCn_MASK) {
  1020. case GEN6_RC0:
  1021. if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
  1022. seq_printf(m, "Core Power Down\n");
  1023. else
  1024. seq_printf(m, "on\n");
  1025. break;
  1026. case GEN6_RC3:
  1027. seq_printf(m, "RC3\n");
  1028. break;
  1029. case GEN6_RC6:
  1030. seq_printf(m, "RC6\n");
  1031. break;
  1032. case GEN6_RC7:
  1033. seq_printf(m, "RC7\n");
  1034. break;
  1035. default:
  1036. seq_printf(m, "Unknown\n");
  1037. break;
  1038. }
  1039. seq_printf(m, "Core Power Down: %s\n",
  1040. yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
  1041. /* Not exactly sure what this is */
  1042. seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
  1043. I915_READ(GEN6_GT_GFX_RC6_LOCKED));
  1044. seq_printf(m, "RC6 residency since boot: %u\n",
  1045. I915_READ(GEN6_GT_GFX_RC6));
  1046. seq_printf(m, "RC6+ residency since boot: %u\n",
  1047. I915_READ(GEN6_GT_GFX_RC6p));
  1048. seq_printf(m, "RC6++ residency since boot: %u\n",
  1049. I915_READ(GEN6_GT_GFX_RC6pp));
  1050. seq_printf(m, "RC6 voltage: %dmV\n",
  1051. GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
  1052. seq_printf(m, "RC6+ voltage: %dmV\n",
  1053. GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
  1054. seq_printf(m, "RC6++ voltage: %dmV\n",
  1055. GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
  1056. return 0;
  1057. }
  1058. static int i915_drpc_info(struct seq_file *m, void *unused)
  1059. {
  1060. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1061. struct drm_device *dev = node->minor->dev;
  1062. if (IS_GEN6(dev) || IS_GEN7(dev))
  1063. return gen6_drpc_info(m);
  1064. else
  1065. return ironlake_drpc_info(m);
  1066. }
  1067. static int i915_fbc_status(struct seq_file *m, void *unused)
  1068. {
  1069. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1070. struct drm_device *dev = node->minor->dev;
  1071. drm_i915_private_t *dev_priv = dev->dev_private;
  1072. if (!I915_HAS_FBC(dev)) {
  1073. seq_printf(m, "FBC unsupported on this chipset\n");
  1074. return 0;
  1075. }
  1076. if (intel_fbc_enabled(dev)) {
  1077. seq_printf(m, "FBC enabled\n");
  1078. } else {
  1079. seq_printf(m, "FBC disabled: ");
  1080. switch (dev_priv->no_fbc_reason) {
  1081. case FBC_NO_OUTPUT:
  1082. seq_printf(m, "no outputs");
  1083. break;
  1084. case FBC_STOLEN_TOO_SMALL:
  1085. seq_printf(m, "not enough stolen memory");
  1086. break;
  1087. case FBC_UNSUPPORTED_MODE:
  1088. seq_printf(m, "mode not supported");
  1089. break;
  1090. case FBC_MODE_TOO_LARGE:
  1091. seq_printf(m, "mode too large");
  1092. break;
  1093. case FBC_BAD_PLANE:
  1094. seq_printf(m, "FBC unsupported on plane");
  1095. break;
  1096. case FBC_NOT_TILED:
  1097. seq_printf(m, "scanout buffer not tiled");
  1098. break;
  1099. case FBC_MULTIPLE_PIPES:
  1100. seq_printf(m, "multiple pipes are enabled");
  1101. break;
  1102. case FBC_MODULE_PARAM:
  1103. seq_printf(m, "disabled per module param (default off)");
  1104. break;
  1105. default:
  1106. seq_printf(m, "unknown reason");
  1107. }
  1108. seq_printf(m, "\n");
  1109. }
  1110. return 0;
  1111. }
  1112. static int i915_sr_status(struct seq_file *m, void *unused)
  1113. {
  1114. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1115. struct drm_device *dev = node->minor->dev;
  1116. drm_i915_private_t *dev_priv = dev->dev_private;
  1117. bool sr_enabled = false;
  1118. if (HAS_PCH_SPLIT(dev))
  1119. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  1120. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  1121. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  1122. else if (IS_I915GM(dev))
  1123. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  1124. else if (IS_PINEVIEW(dev))
  1125. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  1126. seq_printf(m, "self-refresh: %s\n",
  1127. sr_enabled ? "enabled" : "disabled");
  1128. return 0;
  1129. }
  1130. static int i915_emon_status(struct seq_file *m, void *unused)
  1131. {
  1132. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1133. struct drm_device *dev = node->minor->dev;
  1134. drm_i915_private_t *dev_priv = dev->dev_private;
  1135. unsigned long temp, chipset, gfx;
  1136. int ret;
  1137. if (!IS_GEN5(dev))
  1138. return -ENODEV;
  1139. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1140. if (ret)
  1141. return ret;
  1142. temp = i915_mch_val(dev_priv);
  1143. chipset = i915_chipset_val(dev_priv);
  1144. gfx = i915_gfx_val(dev_priv);
  1145. mutex_unlock(&dev->struct_mutex);
  1146. seq_printf(m, "GMCH temp: %ld\n", temp);
  1147. seq_printf(m, "Chipset power: %ld\n", chipset);
  1148. seq_printf(m, "GFX power: %ld\n", gfx);
  1149. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1150. return 0;
  1151. }
  1152. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1153. {
  1154. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1155. struct drm_device *dev = node->minor->dev;
  1156. drm_i915_private_t *dev_priv = dev->dev_private;
  1157. int ret;
  1158. int gpu_freq, ia_freq;
  1159. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1160. seq_printf(m, "unsupported on this chipset\n");
  1161. return 0;
  1162. }
  1163. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1164. if (ret)
  1165. return ret;
  1166. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1167. for (gpu_freq = dev_priv->rps.min_delay;
  1168. gpu_freq <= dev_priv->rps.max_delay;
  1169. gpu_freq++) {
  1170. ia_freq = gpu_freq;
  1171. sandybridge_pcode_read(dev_priv,
  1172. GEN6_PCODE_READ_MIN_FREQ_TABLE,
  1173. &ia_freq);
  1174. seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
  1175. }
  1176. mutex_unlock(&dev_priv->rps.hw_lock);
  1177. return 0;
  1178. }
  1179. static int i915_gfxec(struct seq_file *m, void *unused)
  1180. {
  1181. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1182. struct drm_device *dev = node->minor->dev;
  1183. drm_i915_private_t *dev_priv = dev->dev_private;
  1184. int ret;
  1185. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1186. if (ret)
  1187. return ret;
  1188. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1189. mutex_unlock(&dev->struct_mutex);
  1190. return 0;
  1191. }
  1192. static int i915_opregion(struct seq_file *m, void *unused)
  1193. {
  1194. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1195. struct drm_device *dev = node->minor->dev;
  1196. drm_i915_private_t *dev_priv = dev->dev_private;
  1197. struct intel_opregion *opregion = &dev_priv->opregion;
  1198. void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
  1199. int ret;
  1200. if (data == NULL)
  1201. return -ENOMEM;
  1202. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1203. if (ret)
  1204. goto out;
  1205. if (opregion->header) {
  1206. memcpy_fromio(data, opregion->header, OPREGION_SIZE);
  1207. seq_write(m, data, OPREGION_SIZE);
  1208. }
  1209. mutex_unlock(&dev->struct_mutex);
  1210. out:
  1211. kfree(data);
  1212. return 0;
  1213. }
  1214. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1215. {
  1216. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1217. struct drm_device *dev = node->minor->dev;
  1218. drm_i915_private_t *dev_priv = dev->dev_private;
  1219. struct intel_fbdev *ifbdev;
  1220. struct intel_framebuffer *fb;
  1221. int ret;
  1222. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1223. if (ret)
  1224. return ret;
  1225. ifbdev = dev_priv->fbdev;
  1226. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1227. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
  1228. fb->base.width,
  1229. fb->base.height,
  1230. fb->base.depth,
  1231. fb->base.bits_per_pixel,
  1232. atomic_read(&fb->base.refcount.refcount));
  1233. describe_obj(m, fb->obj);
  1234. seq_printf(m, "\n");
  1235. mutex_unlock(&dev->mode_config.mutex);
  1236. mutex_lock(&dev->mode_config.fb_lock);
  1237. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1238. if (&fb->base == ifbdev->helper.fb)
  1239. continue;
  1240. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
  1241. fb->base.width,
  1242. fb->base.height,
  1243. fb->base.depth,
  1244. fb->base.bits_per_pixel,
  1245. atomic_read(&fb->base.refcount.refcount));
  1246. describe_obj(m, fb->obj);
  1247. seq_printf(m, "\n");
  1248. }
  1249. mutex_unlock(&dev->mode_config.fb_lock);
  1250. return 0;
  1251. }
  1252. static int i915_context_status(struct seq_file *m, void *unused)
  1253. {
  1254. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1255. struct drm_device *dev = node->minor->dev;
  1256. drm_i915_private_t *dev_priv = dev->dev_private;
  1257. struct intel_ring_buffer *ring;
  1258. int ret, i;
  1259. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1260. if (ret)
  1261. return ret;
  1262. if (dev_priv->ips.pwrctx) {
  1263. seq_printf(m, "power context ");
  1264. describe_obj(m, dev_priv->ips.pwrctx);
  1265. seq_printf(m, "\n");
  1266. }
  1267. if (dev_priv->ips.renderctx) {
  1268. seq_printf(m, "render context ");
  1269. describe_obj(m, dev_priv->ips.renderctx);
  1270. seq_printf(m, "\n");
  1271. }
  1272. for_each_ring(ring, dev_priv, i) {
  1273. if (ring->default_context) {
  1274. seq_printf(m, "HW default context %s ring ", ring->name);
  1275. describe_obj(m, ring->default_context->obj);
  1276. seq_printf(m, "\n");
  1277. }
  1278. }
  1279. mutex_unlock(&dev->mode_config.mutex);
  1280. return 0;
  1281. }
  1282. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1283. {
  1284. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1285. struct drm_device *dev = node->minor->dev;
  1286. struct drm_i915_private *dev_priv = dev->dev_private;
  1287. unsigned forcewake_count;
  1288. spin_lock_irq(&dev_priv->gt_lock);
  1289. forcewake_count = dev_priv->forcewake_count;
  1290. spin_unlock_irq(&dev_priv->gt_lock);
  1291. seq_printf(m, "forcewake count = %u\n", forcewake_count);
  1292. return 0;
  1293. }
  1294. static const char *swizzle_string(unsigned swizzle)
  1295. {
  1296. switch(swizzle) {
  1297. case I915_BIT_6_SWIZZLE_NONE:
  1298. return "none";
  1299. case I915_BIT_6_SWIZZLE_9:
  1300. return "bit9";
  1301. case I915_BIT_6_SWIZZLE_9_10:
  1302. return "bit9/bit10";
  1303. case I915_BIT_6_SWIZZLE_9_11:
  1304. return "bit9/bit11";
  1305. case I915_BIT_6_SWIZZLE_9_10_11:
  1306. return "bit9/bit10/bit11";
  1307. case I915_BIT_6_SWIZZLE_9_17:
  1308. return "bit9/bit17";
  1309. case I915_BIT_6_SWIZZLE_9_10_17:
  1310. return "bit9/bit10/bit17";
  1311. case I915_BIT_6_SWIZZLE_UNKNOWN:
  1312. return "unknown";
  1313. }
  1314. return "bug";
  1315. }
  1316. static int i915_swizzle_info(struct seq_file *m, void *data)
  1317. {
  1318. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1319. struct drm_device *dev = node->minor->dev;
  1320. struct drm_i915_private *dev_priv = dev->dev_private;
  1321. int ret;
  1322. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1323. if (ret)
  1324. return ret;
  1325. seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
  1326. swizzle_string(dev_priv->mm.bit_6_swizzle_x));
  1327. seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
  1328. swizzle_string(dev_priv->mm.bit_6_swizzle_y));
  1329. if (IS_GEN3(dev) || IS_GEN4(dev)) {
  1330. seq_printf(m, "DDC = 0x%08x\n",
  1331. I915_READ(DCC));
  1332. seq_printf(m, "C0DRB3 = 0x%04x\n",
  1333. I915_READ16(C0DRB3));
  1334. seq_printf(m, "C1DRB3 = 0x%04x\n",
  1335. I915_READ16(C1DRB3));
  1336. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  1337. seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
  1338. I915_READ(MAD_DIMM_C0));
  1339. seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
  1340. I915_READ(MAD_DIMM_C1));
  1341. seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
  1342. I915_READ(MAD_DIMM_C2));
  1343. seq_printf(m, "TILECTL = 0x%08x\n",
  1344. I915_READ(TILECTL));
  1345. seq_printf(m, "ARB_MODE = 0x%08x\n",
  1346. I915_READ(ARB_MODE));
  1347. seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
  1348. I915_READ(DISP_ARB_CTL));
  1349. }
  1350. mutex_unlock(&dev->struct_mutex);
  1351. return 0;
  1352. }
  1353. static int i915_ppgtt_info(struct seq_file *m, void *data)
  1354. {
  1355. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1356. struct drm_device *dev = node->minor->dev;
  1357. struct drm_i915_private *dev_priv = dev->dev_private;
  1358. struct intel_ring_buffer *ring;
  1359. int i, ret;
  1360. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1361. if (ret)
  1362. return ret;
  1363. if (INTEL_INFO(dev)->gen == 6)
  1364. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
  1365. for_each_ring(ring, dev_priv, i) {
  1366. seq_printf(m, "%s\n", ring->name);
  1367. if (INTEL_INFO(dev)->gen == 7)
  1368. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
  1369. seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
  1370. seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
  1371. seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
  1372. }
  1373. if (dev_priv->mm.aliasing_ppgtt) {
  1374. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  1375. seq_printf(m, "aliasing PPGTT:\n");
  1376. seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
  1377. }
  1378. seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
  1379. mutex_unlock(&dev->struct_mutex);
  1380. return 0;
  1381. }
  1382. static int i915_dpio_info(struct seq_file *m, void *data)
  1383. {
  1384. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1385. struct drm_device *dev = node->minor->dev;
  1386. struct drm_i915_private *dev_priv = dev->dev_private;
  1387. int ret;
  1388. if (!IS_VALLEYVIEW(dev)) {
  1389. seq_printf(m, "unsupported\n");
  1390. return 0;
  1391. }
  1392. ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
  1393. if (ret)
  1394. return ret;
  1395. seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
  1396. seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
  1397. intel_dpio_read(dev_priv, _DPIO_DIV_A));
  1398. seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
  1399. intel_dpio_read(dev_priv, _DPIO_DIV_B));
  1400. seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
  1401. intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
  1402. seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
  1403. intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
  1404. seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
  1405. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
  1406. seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
  1407. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
  1408. seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
  1409. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
  1410. seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
  1411. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
  1412. seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
  1413. intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
  1414. mutex_unlock(&dev_priv->dpio_lock);
  1415. return 0;
  1416. }
  1417. static int
  1418. i915_wedged_get(void *data, u64 *val)
  1419. {
  1420. struct drm_device *dev = data;
  1421. drm_i915_private_t *dev_priv = dev->dev_private;
  1422. *val = atomic_read(&dev_priv->gpu_error.reset_counter);
  1423. return 0;
  1424. }
  1425. static int
  1426. i915_wedged_set(void *data, u64 val)
  1427. {
  1428. struct drm_device *dev = data;
  1429. DRM_INFO("Manually setting wedged to %llu\n", val);
  1430. i915_handle_error(dev, val);
  1431. return 0;
  1432. }
  1433. DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
  1434. i915_wedged_get, i915_wedged_set,
  1435. "wedged : %llu\n");
  1436. static int
  1437. i915_ring_stop_get(void *data, u64 *val)
  1438. {
  1439. struct drm_device *dev = data;
  1440. drm_i915_private_t *dev_priv = dev->dev_private;
  1441. *val = dev_priv->gpu_error.stop_rings;
  1442. return 0;
  1443. }
  1444. static int
  1445. i915_ring_stop_set(void *data, u64 val)
  1446. {
  1447. struct drm_device *dev = data;
  1448. struct drm_i915_private *dev_priv = dev->dev_private;
  1449. int ret;
  1450. DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
  1451. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1452. if (ret)
  1453. return ret;
  1454. dev_priv->gpu_error.stop_rings = val;
  1455. mutex_unlock(&dev->struct_mutex);
  1456. return 0;
  1457. }
  1458. DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
  1459. i915_ring_stop_get, i915_ring_stop_set,
  1460. "0x%08llx\n");
  1461. #define DROP_UNBOUND 0x1
  1462. #define DROP_BOUND 0x2
  1463. #define DROP_RETIRE 0x4
  1464. #define DROP_ACTIVE 0x8
  1465. #define DROP_ALL (DROP_UNBOUND | \
  1466. DROP_BOUND | \
  1467. DROP_RETIRE | \
  1468. DROP_ACTIVE)
  1469. static int
  1470. i915_drop_caches_get(void *data, u64 *val)
  1471. {
  1472. *val = DROP_ALL;
  1473. return 0;
  1474. }
  1475. static int
  1476. i915_drop_caches_set(void *data, u64 val)
  1477. {
  1478. struct drm_device *dev = data;
  1479. struct drm_i915_private *dev_priv = dev->dev_private;
  1480. struct drm_i915_gem_object *obj, *next;
  1481. int ret;
  1482. DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
  1483. /* No need to check and wait for gpu resets, only libdrm auto-restarts
  1484. * on ioctls on -EAGAIN. */
  1485. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1486. if (ret)
  1487. return ret;
  1488. if (val & DROP_ACTIVE) {
  1489. ret = i915_gpu_idle(dev);
  1490. if (ret)
  1491. goto unlock;
  1492. }
  1493. if (val & (DROP_RETIRE | DROP_ACTIVE))
  1494. i915_gem_retire_requests(dev);
  1495. if (val & DROP_BOUND) {
  1496. list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list)
  1497. if (obj->pin_count == 0) {
  1498. ret = i915_gem_object_unbind(obj);
  1499. if (ret)
  1500. goto unlock;
  1501. }
  1502. }
  1503. if (val & DROP_UNBOUND) {
  1504. list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
  1505. if (obj->pages_pin_count == 0) {
  1506. ret = i915_gem_object_put_pages(obj);
  1507. if (ret)
  1508. goto unlock;
  1509. }
  1510. }
  1511. unlock:
  1512. mutex_unlock(&dev->struct_mutex);
  1513. return ret;
  1514. }
  1515. DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
  1516. i915_drop_caches_get, i915_drop_caches_set,
  1517. "0x%08llx\n");
  1518. static int
  1519. i915_max_freq_get(void *data, u64 *val)
  1520. {
  1521. struct drm_device *dev = data;
  1522. drm_i915_private_t *dev_priv = dev->dev_private;
  1523. int ret;
  1524. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1525. return -ENODEV;
  1526. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1527. if (ret)
  1528. return ret;
  1529. *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
  1530. mutex_unlock(&dev_priv->rps.hw_lock);
  1531. return 0;
  1532. }
  1533. static int
  1534. i915_max_freq_set(void *data, u64 val)
  1535. {
  1536. struct drm_device *dev = data;
  1537. struct drm_i915_private *dev_priv = dev->dev_private;
  1538. int ret;
  1539. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1540. return -ENODEV;
  1541. DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
  1542. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1543. if (ret)
  1544. return ret;
  1545. /*
  1546. * Turbo will still be enabled, but won't go above the set value.
  1547. */
  1548. do_div(val, GT_FREQUENCY_MULTIPLIER);
  1549. dev_priv->rps.max_delay = val;
  1550. gen6_set_rps(dev, val);
  1551. mutex_unlock(&dev_priv->rps.hw_lock);
  1552. return 0;
  1553. }
  1554. DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
  1555. i915_max_freq_get, i915_max_freq_set,
  1556. "max freq: %llu\n");
  1557. static int
  1558. i915_min_freq_get(void *data, u64 *val)
  1559. {
  1560. struct drm_device *dev = data;
  1561. drm_i915_private_t *dev_priv = dev->dev_private;
  1562. int ret;
  1563. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1564. return -ENODEV;
  1565. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1566. if (ret)
  1567. return ret;
  1568. *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
  1569. mutex_unlock(&dev_priv->rps.hw_lock);
  1570. return 0;
  1571. }
  1572. static int
  1573. i915_min_freq_set(void *data, u64 val)
  1574. {
  1575. struct drm_device *dev = data;
  1576. struct drm_i915_private *dev_priv = dev->dev_private;
  1577. int ret;
  1578. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1579. return -ENODEV;
  1580. DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
  1581. ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
  1582. if (ret)
  1583. return ret;
  1584. /*
  1585. * Turbo will still be enabled, but won't go below the set value.
  1586. */
  1587. do_div(val, GT_FREQUENCY_MULTIPLIER);
  1588. dev_priv->rps.min_delay = val;
  1589. gen6_set_rps(dev, val);
  1590. mutex_unlock(&dev_priv->rps.hw_lock);
  1591. return 0;
  1592. }
  1593. DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
  1594. i915_min_freq_get, i915_min_freq_set,
  1595. "min freq: %llu\n");
  1596. static int
  1597. i915_cache_sharing_get(void *data, u64 *val)
  1598. {
  1599. struct drm_device *dev = data;
  1600. drm_i915_private_t *dev_priv = dev->dev_private;
  1601. u32 snpcr;
  1602. int ret;
  1603. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1604. return -ENODEV;
  1605. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1606. if (ret)
  1607. return ret;
  1608. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1609. mutex_unlock(&dev_priv->dev->struct_mutex);
  1610. *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
  1611. return 0;
  1612. }
  1613. static int
  1614. i915_cache_sharing_set(void *data, u64 val)
  1615. {
  1616. struct drm_device *dev = data;
  1617. struct drm_i915_private *dev_priv = dev->dev_private;
  1618. u32 snpcr;
  1619. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1620. return -ENODEV;
  1621. if (val > 3)
  1622. return -EINVAL;
  1623. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
  1624. /* Update the cache sharing policy here as well */
  1625. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1626. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1627. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1628. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1629. return 0;
  1630. }
  1631. DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
  1632. i915_cache_sharing_get, i915_cache_sharing_set,
  1633. "%llu\n");
  1634. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1635. * allocated we need to hook into the minor for release. */
  1636. static int
  1637. drm_add_fake_info_node(struct drm_minor *minor,
  1638. struct dentry *ent,
  1639. const void *key)
  1640. {
  1641. struct drm_info_node *node;
  1642. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1643. if (node == NULL) {
  1644. debugfs_remove(ent);
  1645. return -ENOMEM;
  1646. }
  1647. node->minor = minor;
  1648. node->dent = ent;
  1649. node->info_ent = (void *) key;
  1650. mutex_lock(&minor->debugfs_lock);
  1651. list_add(&node->list, &minor->debugfs_list);
  1652. mutex_unlock(&minor->debugfs_lock);
  1653. return 0;
  1654. }
  1655. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1656. {
  1657. struct drm_device *dev = inode->i_private;
  1658. struct drm_i915_private *dev_priv = dev->dev_private;
  1659. if (INTEL_INFO(dev)->gen < 6)
  1660. return 0;
  1661. gen6_gt_force_wake_get(dev_priv);
  1662. return 0;
  1663. }
  1664. static int i915_forcewake_release(struct inode *inode, struct file *file)
  1665. {
  1666. struct drm_device *dev = inode->i_private;
  1667. struct drm_i915_private *dev_priv = dev->dev_private;
  1668. if (INTEL_INFO(dev)->gen < 6)
  1669. return 0;
  1670. gen6_gt_force_wake_put(dev_priv);
  1671. return 0;
  1672. }
  1673. static const struct file_operations i915_forcewake_fops = {
  1674. .owner = THIS_MODULE,
  1675. .open = i915_forcewake_open,
  1676. .release = i915_forcewake_release,
  1677. };
  1678. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1679. {
  1680. struct drm_device *dev = minor->dev;
  1681. struct dentry *ent;
  1682. ent = debugfs_create_file("i915_forcewake_user",
  1683. S_IRUSR,
  1684. root, dev,
  1685. &i915_forcewake_fops);
  1686. if (IS_ERR(ent))
  1687. return PTR_ERR(ent);
  1688. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1689. }
  1690. static int i915_debugfs_create(struct dentry *root,
  1691. struct drm_minor *minor,
  1692. const char *name,
  1693. const struct file_operations *fops)
  1694. {
  1695. struct drm_device *dev = minor->dev;
  1696. struct dentry *ent;
  1697. ent = debugfs_create_file(name,
  1698. S_IRUGO | S_IWUSR,
  1699. root, dev,
  1700. fops);
  1701. if (IS_ERR(ent))
  1702. return PTR_ERR(ent);
  1703. return drm_add_fake_info_node(minor, ent, fops);
  1704. }
  1705. static struct drm_info_list i915_debugfs_list[] = {
  1706. {"i915_capabilities", i915_capabilities, 0},
  1707. {"i915_gem_objects", i915_gem_object_info, 0},
  1708. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1709. {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
  1710. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1711. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1712. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1713. {"i915_gem_request", i915_gem_request_info, 0},
  1714. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1715. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1716. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1717. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1718. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1719. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1720. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1721. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1722. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1723. {"i915_inttoext_table", i915_inttoext_table, 0},
  1724. {"i915_drpc_info", i915_drpc_info, 0},
  1725. {"i915_emon_status", i915_emon_status, 0},
  1726. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1727. {"i915_gfxec", i915_gfxec, 0},
  1728. {"i915_fbc_status", i915_fbc_status, 0},
  1729. {"i915_sr_status", i915_sr_status, 0},
  1730. {"i915_opregion", i915_opregion, 0},
  1731. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1732. {"i915_context_status", i915_context_status, 0},
  1733. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1734. {"i915_swizzle_info", i915_swizzle_info, 0},
  1735. {"i915_ppgtt_info", i915_ppgtt_info, 0},
  1736. {"i915_dpio", i915_dpio_info, 0},
  1737. };
  1738. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1739. int i915_debugfs_init(struct drm_minor *minor)
  1740. {
  1741. int ret;
  1742. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1743. "i915_wedged",
  1744. &i915_wedged_fops);
  1745. if (ret)
  1746. return ret;
  1747. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1748. if (ret)
  1749. return ret;
  1750. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1751. "i915_max_freq",
  1752. &i915_max_freq_fops);
  1753. if (ret)
  1754. return ret;
  1755. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1756. "i915_min_freq",
  1757. &i915_min_freq_fops);
  1758. if (ret)
  1759. return ret;
  1760. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1761. "i915_cache_sharing",
  1762. &i915_cache_sharing_fops);
  1763. if (ret)
  1764. return ret;
  1765. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1766. "i915_ring_stop",
  1767. &i915_ring_stop_fops);
  1768. if (ret)
  1769. return ret;
  1770. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1771. "i915_gem_drop_caches",
  1772. &i915_drop_caches_fops);
  1773. if (ret)
  1774. return ret;
  1775. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1776. "i915_error_state",
  1777. &i915_error_state_fops);
  1778. if (ret)
  1779. return ret;
  1780. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1781. "i915_next_seqno",
  1782. &i915_next_seqno_fops);
  1783. if (ret)
  1784. return ret;
  1785. return drm_debugfs_create_files(i915_debugfs_list,
  1786. I915_DEBUGFS_ENTRIES,
  1787. minor->debugfs_root, minor);
  1788. }
  1789. void i915_debugfs_cleanup(struct drm_minor *minor)
  1790. {
  1791. drm_debugfs_remove_files(i915_debugfs_list,
  1792. I915_DEBUGFS_ENTRIES, minor);
  1793. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1794. 1, minor);
  1795. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1796. 1, minor);
  1797. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1798. 1, minor);
  1799. drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
  1800. 1, minor);
  1801. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1802. 1, minor);
  1803. drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops,
  1804. 1, minor);
  1805. drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
  1806. 1, minor);
  1807. drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
  1808. 1, minor);
  1809. drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
  1810. 1, minor);
  1811. }
  1812. #endif /* CONFIG_DEBUG_FS */