main.c 72 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. static char *dev_info = "ath9k";
  19. MODULE_AUTHOR("Atheros Communications");
  20. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  21. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  22. MODULE_LICENSE("Dual BSD/GPL");
  23. static int modparam_nohwcrypt;
  24. module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  25. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  26. /* We use the hw_value as an index into our private channel structure */
  27. #define CHAN2G(_freq, _idx) { \
  28. .center_freq = (_freq), \
  29. .hw_value = (_idx), \
  30. .max_power = 20, \
  31. }
  32. #define CHAN5G(_freq, _idx) { \
  33. .band = IEEE80211_BAND_5GHZ, \
  34. .center_freq = (_freq), \
  35. .hw_value = (_idx), \
  36. .max_power = 20, \
  37. }
  38. /* Some 2 GHz radios are actually tunable on 2312-2732
  39. * on 5 MHz steps, we support the channels which we know
  40. * we have calibration data for all cards though to make
  41. * this static */
  42. static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  43. CHAN2G(2412, 0), /* Channel 1 */
  44. CHAN2G(2417, 1), /* Channel 2 */
  45. CHAN2G(2422, 2), /* Channel 3 */
  46. CHAN2G(2427, 3), /* Channel 4 */
  47. CHAN2G(2432, 4), /* Channel 5 */
  48. CHAN2G(2437, 5), /* Channel 6 */
  49. CHAN2G(2442, 6), /* Channel 7 */
  50. CHAN2G(2447, 7), /* Channel 8 */
  51. CHAN2G(2452, 8), /* Channel 9 */
  52. CHAN2G(2457, 9), /* Channel 10 */
  53. CHAN2G(2462, 10), /* Channel 11 */
  54. CHAN2G(2467, 11), /* Channel 12 */
  55. CHAN2G(2472, 12), /* Channel 13 */
  56. CHAN2G(2484, 13), /* Channel 14 */
  57. };
  58. /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  59. * on 5 MHz steps, we support the channels which we know
  60. * we have calibration data for all cards though to make
  61. * this static */
  62. static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  63. /* _We_ call this UNII 1 */
  64. CHAN5G(5180, 14), /* Channel 36 */
  65. CHAN5G(5200, 15), /* Channel 40 */
  66. CHAN5G(5220, 16), /* Channel 44 */
  67. CHAN5G(5240, 17), /* Channel 48 */
  68. /* _We_ call this UNII 2 */
  69. CHAN5G(5260, 18), /* Channel 52 */
  70. CHAN5G(5280, 19), /* Channel 56 */
  71. CHAN5G(5300, 20), /* Channel 60 */
  72. CHAN5G(5320, 21), /* Channel 64 */
  73. /* _We_ call this "Middle band" */
  74. CHAN5G(5500, 22), /* Channel 100 */
  75. CHAN5G(5520, 23), /* Channel 104 */
  76. CHAN5G(5540, 24), /* Channel 108 */
  77. CHAN5G(5560, 25), /* Channel 112 */
  78. CHAN5G(5580, 26), /* Channel 116 */
  79. CHAN5G(5600, 27), /* Channel 120 */
  80. CHAN5G(5620, 28), /* Channel 124 */
  81. CHAN5G(5640, 29), /* Channel 128 */
  82. CHAN5G(5660, 30), /* Channel 132 */
  83. CHAN5G(5680, 31), /* Channel 136 */
  84. CHAN5G(5700, 32), /* Channel 140 */
  85. /* _We_ call this UNII 3 */
  86. CHAN5G(5745, 33), /* Channel 149 */
  87. CHAN5G(5765, 34), /* Channel 153 */
  88. CHAN5G(5785, 35), /* Channel 157 */
  89. CHAN5G(5805, 36), /* Channel 161 */
  90. CHAN5G(5825, 37), /* Channel 165 */
  91. };
  92. static void ath_cache_conf_rate(struct ath_softc *sc,
  93. struct ieee80211_conf *conf)
  94. {
  95. switch (conf->channel->band) {
  96. case IEEE80211_BAND_2GHZ:
  97. if (conf_is_ht20(conf))
  98. sc->cur_rate_table =
  99. sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  100. else if (conf_is_ht40_minus(conf))
  101. sc->cur_rate_table =
  102. sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  103. else if (conf_is_ht40_plus(conf))
  104. sc->cur_rate_table =
  105. sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  106. else
  107. sc->cur_rate_table =
  108. sc->hw_rate_table[ATH9K_MODE_11G];
  109. break;
  110. case IEEE80211_BAND_5GHZ:
  111. if (conf_is_ht20(conf))
  112. sc->cur_rate_table =
  113. sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  114. else if (conf_is_ht40_minus(conf))
  115. sc->cur_rate_table =
  116. sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  117. else if (conf_is_ht40_plus(conf))
  118. sc->cur_rate_table =
  119. sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  120. else
  121. sc->cur_rate_table =
  122. sc->hw_rate_table[ATH9K_MODE_11A];
  123. break;
  124. default:
  125. BUG_ON(1);
  126. break;
  127. }
  128. }
  129. static void ath_update_txpow(struct ath_softc *sc)
  130. {
  131. struct ath_hw *ah = sc->sc_ah;
  132. u32 txpow;
  133. if (sc->curtxpow != sc->config.txpowlimit) {
  134. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  135. /* read back in case value is clamped */
  136. ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  137. sc->curtxpow = txpow;
  138. }
  139. }
  140. static u8 parse_mpdudensity(u8 mpdudensity)
  141. {
  142. /*
  143. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  144. * 0 for no restriction
  145. * 1 for 1/4 us
  146. * 2 for 1/2 us
  147. * 3 for 1 us
  148. * 4 for 2 us
  149. * 5 for 4 us
  150. * 6 for 8 us
  151. * 7 for 16 us
  152. */
  153. switch (mpdudensity) {
  154. case 0:
  155. return 0;
  156. case 1:
  157. case 2:
  158. case 3:
  159. /* Our lower layer calculations limit our precision to
  160. 1 microsecond */
  161. return 1;
  162. case 4:
  163. return 2;
  164. case 5:
  165. return 4;
  166. case 6:
  167. return 8;
  168. case 7:
  169. return 16;
  170. default:
  171. return 0;
  172. }
  173. }
  174. static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
  175. {
  176. const struct ath_rate_table *rate_table = NULL;
  177. struct ieee80211_supported_band *sband;
  178. struct ieee80211_rate *rate;
  179. int i, maxrates;
  180. switch (band) {
  181. case IEEE80211_BAND_2GHZ:
  182. rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
  183. break;
  184. case IEEE80211_BAND_5GHZ:
  185. rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
  186. break;
  187. default:
  188. break;
  189. }
  190. if (rate_table == NULL)
  191. return;
  192. sband = &sc->sbands[band];
  193. rate = sc->rates[band];
  194. if (rate_table->rate_cnt > ATH_RATE_MAX)
  195. maxrates = ATH_RATE_MAX;
  196. else
  197. maxrates = rate_table->rate_cnt;
  198. for (i = 0; i < maxrates; i++) {
  199. rate[i].bitrate = rate_table->info[i].ratekbps / 100;
  200. rate[i].hw_value = rate_table->info[i].ratecode;
  201. if (rate_table->info[i].short_preamble) {
  202. rate[i].hw_value_short = rate_table->info[i].ratecode |
  203. rate_table->info[i].short_preamble;
  204. rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
  205. }
  206. sband->n_bitrates++;
  207. DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
  208. rate[i].bitrate / 10, rate[i].hw_value);
  209. }
  210. }
  211. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  212. struct ieee80211_hw *hw)
  213. {
  214. struct ieee80211_channel *curchan = hw->conf.channel;
  215. struct ath9k_channel *channel;
  216. u8 chan_idx;
  217. chan_idx = curchan->hw_value;
  218. channel = &sc->sc_ah->channels[chan_idx];
  219. ath9k_update_ichannel(sc, hw, channel);
  220. return channel;
  221. }
  222. /*
  223. * Set/change channels. If the channel is really being changed, it's done
  224. * by reseting the chip. To accomplish this we must first cleanup any pending
  225. * DMA, then restart stuff.
  226. */
  227. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  228. struct ath9k_channel *hchan)
  229. {
  230. struct ath_hw *ah = sc->sc_ah;
  231. bool fastcc = true, stopped;
  232. struct ieee80211_channel *channel = hw->conf.channel;
  233. int r;
  234. if (sc->sc_flags & SC_OP_INVALID)
  235. return -EIO;
  236. ath9k_ps_wakeup(sc);
  237. /*
  238. * This is only performed if the channel settings have
  239. * actually changed.
  240. *
  241. * To switch channels clear any pending DMA operations;
  242. * wait long enough for the RX fifo to drain, reset the
  243. * hardware at the new frequency, and then re-enable
  244. * the relevant bits of the h/w.
  245. */
  246. ath9k_hw_set_interrupts(ah, 0);
  247. ath_drain_all_txq(sc, false);
  248. stopped = ath_stoprecv(sc);
  249. /* XXX: do not flush receive queue here. We don't want
  250. * to flush data frames already in queue because of
  251. * changing channel. */
  252. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  253. fastcc = false;
  254. DPRINTF(sc, ATH_DBG_CONFIG,
  255. "(%u MHz) -> (%u MHz), chanwidth: %d\n",
  256. sc->sc_ah->curchan->channel,
  257. channel->center_freq, sc->tx_chan_width);
  258. spin_lock_bh(&sc->sc_resetlock);
  259. r = ath9k_hw_reset(ah, hchan, fastcc);
  260. if (r) {
  261. DPRINTF(sc, ATH_DBG_FATAL,
  262. "Unable to reset channel (%u Mhz) "
  263. "reset status %d\n",
  264. channel->center_freq, r);
  265. spin_unlock_bh(&sc->sc_resetlock);
  266. goto ps_restore;
  267. }
  268. spin_unlock_bh(&sc->sc_resetlock);
  269. sc->sc_flags &= ~SC_OP_FULL_RESET;
  270. if (ath_startrecv(sc) != 0) {
  271. DPRINTF(sc, ATH_DBG_FATAL,
  272. "Unable to restart recv logic\n");
  273. r = -EIO;
  274. goto ps_restore;
  275. }
  276. ath_cache_conf_rate(sc, &hw->conf);
  277. ath_update_txpow(sc);
  278. ath9k_hw_set_interrupts(ah, sc->imask);
  279. ps_restore:
  280. ath9k_ps_restore(sc);
  281. return r;
  282. }
  283. /*
  284. * This routine performs the periodic noise floor calibration function
  285. * that is used to adjust and optimize the chip performance. This
  286. * takes environmental changes (location, temperature) into account.
  287. * When the task is complete, it reschedules itself depending on the
  288. * appropriate interval that was calculated.
  289. */
  290. static void ath_ani_calibrate(unsigned long data)
  291. {
  292. struct ath_softc *sc = (struct ath_softc *)data;
  293. struct ath_hw *ah = sc->sc_ah;
  294. bool longcal = false;
  295. bool shortcal = false;
  296. bool aniflag = false;
  297. unsigned int timestamp = jiffies_to_msecs(jiffies);
  298. u32 cal_interval, short_cal_interval;
  299. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  300. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  301. /*
  302. * don't calibrate when we're scanning.
  303. * we are most likely not on our home channel.
  304. */
  305. spin_lock(&sc->ani_lock);
  306. if (sc->sc_flags & SC_OP_SCANNING)
  307. goto set_timer;
  308. /* Only calibrate if awake */
  309. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  310. goto set_timer;
  311. ath9k_ps_wakeup(sc);
  312. /* Long calibration runs independently of short calibration. */
  313. if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  314. longcal = true;
  315. DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  316. sc->ani.longcal_timer = timestamp;
  317. }
  318. /* Short calibration applies only while caldone is false */
  319. if (!sc->ani.caldone) {
  320. if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
  321. shortcal = true;
  322. DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
  323. sc->ani.shortcal_timer = timestamp;
  324. sc->ani.resetcal_timer = timestamp;
  325. }
  326. } else {
  327. if ((timestamp - sc->ani.resetcal_timer) >=
  328. ATH_RESTART_CALINTERVAL) {
  329. sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
  330. if (sc->ani.caldone)
  331. sc->ani.resetcal_timer = timestamp;
  332. }
  333. }
  334. /* Verify whether we must check ANI */
  335. if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
  336. aniflag = true;
  337. sc->ani.checkani_timer = timestamp;
  338. }
  339. /* Skip all processing if there's nothing to do. */
  340. if (longcal || shortcal || aniflag) {
  341. /* Call ANI routine if necessary */
  342. if (aniflag)
  343. ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
  344. /* Perform calibration if necessary */
  345. if (longcal || shortcal) {
  346. sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
  347. sc->rx_chainmask, longcal);
  348. if (longcal)
  349. sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  350. ah->curchan);
  351. DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
  352. ah->curchan->channel, ah->curchan->channelFlags,
  353. sc->ani.noise_floor);
  354. }
  355. }
  356. ath9k_ps_restore(sc);
  357. set_timer:
  358. spin_unlock(&sc->ani_lock);
  359. /*
  360. * Set timer interval based on previous results.
  361. * The interval must be the shortest necessary to satisfy ANI,
  362. * short calibration and long calibration.
  363. */
  364. cal_interval = ATH_LONG_CALINTERVAL;
  365. if (sc->sc_ah->config.enable_ani)
  366. cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
  367. if (!sc->ani.caldone)
  368. cal_interval = min(cal_interval, (u32)short_cal_interval);
  369. mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  370. }
  371. static void ath_start_ani(struct ath_softc *sc)
  372. {
  373. unsigned long timestamp = jiffies_to_msecs(jiffies);
  374. sc->ani.longcal_timer = timestamp;
  375. sc->ani.shortcal_timer = timestamp;
  376. sc->ani.checkani_timer = timestamp;
  377. mod_timer(&sc->ani.timer,
  378. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  379. }
  380. /*
  381. * Update tx/rx chainmask. For legacy association,
  382. * hard code chainmask to 1x1, for 11n association, use
  383. * the chainmask configuration, for bt coexistence, use
  384. * the chainmask configuration even in legacy mode.
  385. */
  386. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  387. {
  388. if (is_ht ||
  389. (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
  390. sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
  391. sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
  392. } else {
  393. sc->tx_chainmask = 1;
  394. sc->rx_chainmask = 1;
  395. }
  396. DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
  397. sc->tx_chainmask, sc->rx_chainmask);
  398. }
  399. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  400. {
  401. struct ath_node *an;
  402. an = (struct ath_node *)sta->drv_priv;
  403. if (sc->sc_flags & SC_OP_TXAGGR) {
  404. ath_tx_node_init(sc, an);
  405. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  406. sta->ht_cap.ampdu_factor);
  407. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  408. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  409. }
  410. }
  411. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  412. {
  413. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  414. if (sc->sc_flags & SC_OP_TXAGGR)
  415. ath_tx_node_cleanup(sc, an);
  416. }
  417. static void ath9k_tasklet(unsigned long data)
  418. {
  419. struct ath_softc *sc = (struct ath_softc *)data;
  420. u32 status = sc->intrstatus;
  421. ath9k_ps_wakeup(sc);
  422. if (status & ATH9K_INT_FATAL) {
  423. ath_reset(sc, false);
  424. ath9k_ps_restore(sc);
  425. return;
  426. }
  427. if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
  428. spin_lock_bh(&sc->rx.rxflushlock);
  429. ath_rx_tasklet(sc, 0);
  430. spin_unlock_bh(&sc->rx.rxflushlock);
  431. }
  432. if (status & ATH9K_INT_TX)
  433. ath_tx_tasklet(sc);
  434. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  435. /*
  436. * TSF sync does not look correct; remain awake to sync with
  437. * the next Beacon.
  438. */
  439. DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
  440. sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
  441. }
  442. /* re-enable hardware interrupt */
  443. ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
  444. ath9k_ps_restore(sc);
  445. }
  446. irqreturn_t ath_isr(int irq, void *dev)
  447. {
  448. #define SCHED_INTR ( \
  449. ATH9K_INT_FATAL | \
  450. ATH9K_INT_RXORN | \
  451. ATH9K_INT_RXEOL | \
  452. ATH9K_INT_RX | \
  453. ATH9K_INT_TX | \
  454. ATH9K_INT_BMISS | \
  455. ATH9K_INT_CST | \
  456. ATH9K_INT_TSFOOR)
  457. struct ath_softc *sc = dev;
  458. struct ath_hw *ah = sc->sc_ah;
  459. enum ath9k_int status;
  460. bool sched = false;
  461. /*
  462. * The hardware is not ready/present, don't
  463. * touch anything. Note this can happen early
  464. * on if the IRQ is shared.
  465. */
  466. if (sc->sc_flags & SC_OP_INVALID)
  467. return IRQ_NONE;
  468. /* shared irq, not for us */
  469. if (!ath9k_hw_intrpend(ah))
  470. return IRQ_NONE;
  471. /*
  472. * Figure out the reason(s) for the interrupt. Note
  473. * that the hal returns a pseudo-ISR that may include
  474. * bits we haven't explicitly enabled so we mask the
  475. * value to insure we only process bits we requested.
  476. */
  477. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  478. status &= sc->imask; /* discard unasked-for bits */
  479. /*
  480. * If there are no status bits set, then this interrupt was not
  481. * for me (should have been caught above).
  482. */
  483. if (!status)
  484. return IRQ_NONE;
  485. /* Cache the status */
  486. sc->intrstatus = status;
  487. if (status & SCHED_INTR)
  488. sched = true;
  489. /*
  490. * If a FATAL or RXORN interrupt is received, we have to reset the
  491. * chip immediately.
  492. */
  493. if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
  494. goto chip_reset;
  495. if (status & ATH9K_INT_SWBA)
  496. tasklet_schedule(&sc->bcon_tasklet);
  497. if (status & ATH9K_INT_TXURN)
  498. ath9k_hw_updatetxtriglevel(ah, true);
  499. if (status & ATH9K_INT_MIB) {
  500. /*
  501. * Disable interrupts until we service the MIB
  502. * interrupt; otherwise it will continue to
  503. * fire.
  504. */
  505. ath9k_hw_set_interrupts(ah, 0);
  506. /*
  507. * Let the hal handle the event. We assume
  508. * it will clear whatever condition caused
  509. * the interrupt.
  510. */
  511. ath9k_hw_procmibevent(ah, &sc->nodestats);
  512. ath9k_hw_set_interrupts(ah, sc->imask);
  513. }
  514. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  515. if (status & ATH9K_INT_TIM_TIMER) {
  516. /* Clear RxAbort bit so that we can
  517. * receive frames */
  518. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  519. ath9k_hw_setrxabort(sc->sc_ah, 0);
  520. sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
  521. }
  522. chip_reset:
  523. ath_debug_stat_interrupt(sc, status);
  524. if (sched) {
  525. /* turn off every interrupt except SWBA */
  526. ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
  527. tasklet_schedule(&sc->intr_tq);
  528. }
  529. return IRQ_HANDLED;
  530. #undef SCHED_INTR
  531. }
  532. static u32 ath_get_extchanmode(struct ath_softc *sc,
  533. struct ieee80211_channel *chan,
  534. enum nl80211_channel_type channel_type)
  535. {
  536. u32 chanmode = 0;
  537. switch (chan->band) {
  538. case IEEE80211_BAND_2GHZ:
  539. switch(channel_type) {
  540. case NL80211_CHAN_NO_HT:
  541. case NL80211_CHAN_HT20:
  542. chanmode = CHANNEL_G_HT20;
  543. break;
  544. case NL80211_CHAN_HT40PLUS:
  545. chanmode = CHANNEL_G_HT40PLUS;
  546. break;
  547. case NL80211_CHAN_HT40MINUS:
  548. chanmode = CHANNEL_G_HT40MINUS;
  549. break;
  550. }
  551. break;
  552. case IEEE80211_BAND_5GHZ:
  553. switch(channel_type) {
  554. case NL80211_CHAN_NO_HT:
  555. case NL80211_CHAN_HT20:
  556. chanmode = CHANNEL_A_HT20;
  557. break;
  558. case NL80211_CHAN_HT40PLUS:
  559. chanmode = CHANNEL_A_HT40PLUS;
  560. break;
  561. case NL80211_CHAN_HT40MINUS:
  562. chanmode = CHANNEL_A_HT40MINUS;
  563. break;
  564. }
  565. break;
  566. default:
  567. break;
  568. }
  569. return chanmode;
  570. }
  571. static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
  572. struct ath9k_keyval *hk, const u8 *addr,
  573. bool authenticator)
  574. {
  575. const u8 *key_rxmic;
  576. const u8 *key_txmic;
  577. key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  578. key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  579. if (addr == NULL) {
  580. /*
  581. * Group key installation - only two key cache entries are used
  582. * regardless of splitmic capability since group key is only
  583. * used either for TX or RX.
  584. */
  585. if (authenticator) {
  586. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  587. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
  588. } else {
  589. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  590. memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
  591. }
  592. return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
  593. }
  594. if (!sc->splitmic) {
  595. /* TX and RX keys share the same key cache entry. */
  596. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  597. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  598. return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
  599. }
  600. /* Separate key cache entries for TX and RX */
  601. /* TX key goes at first index, RX key at +32. */
  602. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  603. if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
  604. /* TX MIC entry failed. No need to proceed further */
  605. DPRINTF(sc, ATH_DBG_FATAL,
  606. "Setting TX MIC Key Failed\n");
  607. return 0;
  608. }
  609. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  610. /* XXX delete tx key on failure? */
  611. return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
  612. }
  613. static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
  614. {
  615. int i;
  616. for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
  617. if (test_bit(i, sc->keymap) ||
  618. test_bit(i + 64, sc->keymap))
  619. continue; /* At least one part of TKIP key allocated */
  620. if (sc->splitmic &&
  621. (test_bit(i + 32, sc->keymap) ||
  622. test_bit(i + 64 + 32, sc->keymap)))
  623. continue; /* At least one part of TKIP key allocated */
  624. /* Found a free slot for a TKIP key */
  625. return i;
  626. }
  627. return -1;
  628. }
  629. static int ath_reserve_key_cache_slot(struct ath_softc *sc)
  630. {
  631. int i;
  632. /* First, try to find slots that would not be available for TKIP. */
  633. if (sc->splitmic) {
  634. for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
  635. if (!test_bit(i, sc->keymap) &&
  636. (test_bit(i + 32, sc->keymap) ||
  637. test_bit(i + 64, sc->keymap) ||
  638. test_bit(i + 64 + 32, sc->keymap)))
  639. return i;
  640. if (!test_bit(i + 32, sc->keymap) &&
  641. (test_bit(i, sc->keymap) ||
  642. test_bit(i + 64, sc->keymap) ||
  643. test_bit(i + 64 + 32, sc->keymap)))
  644. return i + 32;
  645. if (!test_bit(i + 64, sc->keymap) &&
  646. (test_bit(i , sc->keymap) ||
  647. test_bit(i + 32, sc->keymap) ||
  648. test_bit(i + 64 + 32, sc->keymap)))
  649. return i + 64;
  650. if (!test_bit(i + 64 + 32, sc->keymap) &&
  651. (test_bit(i, sc->keymap) ||
  652. test_bit(i + 32, sc->keymap) ||
  653. test_bit(i + 64, sc->keymap)))
  654. return i + 64 + 32;
  655. }
  656. } else {
  657. for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
  658. if (!test_bit(i, sc->keymap) &&
  659. test_bit(i + 64, sc->keymap))
  660. return i;
  661. if (test_bit(i, sc->keymap) &&
  662. !test_bit(i + 64, sc->keymap))
  663. return i + 64;
  664. }
  665. }
  666. /* No partially used TKIP slots, pick any available slot */
  667. for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
  668. /* Do not allow slots that could be needed for TKIP group keys
  669. * to be used. This limitation could be removed if we know that
  670. * TKIP will not be used. */
  671. if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
  672. continue;
  673. if (sc->splitmic) {
  674. if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
  675. continue;
  676. if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
  677. continue;
  678. }
  679. if (!test_bit(i, sc->keymap))
  680. return i; /* Found a free slot for a key */
  681. }
  682. /* No free slot found */
  683. return -1;
  684. }
  685. static int ath_key_config(struct ath_softc *sc,
  686. struct ieee80211_vif *vif,
  687. struct ieee80211_sta *sta,
  688. struct ieee80211_key_conf *key)
  689. {
  690. struct ath9k_keyval hk;
  691. const u8 *mac = NULL;
  692. int ret = 0;
  693. int idx;
  694. memset(&hk, 0, sizeof(hk));
  695. switch (key->alg) {
  696. case ALG_WEP:
  697. hk.kv_type = ATH9K_CIPHER_WEP;
  698. break;
  699. case ALG_TKIP:
  700. hk.kv_type = ATH9K_CIPHER_TKIP;
  701. break;
  702. case ALG_CCMP:
  703. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  704. break;
  705. default:
  706. return -EOPNOTSUPP;
  707. }
  708. hk.kv_len = key->keylen;
  709. memcpy(hk.kv_val, key->key, key->keylen);
  710. if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  711. /* For now, use the default keys for broadcast keys. This may
  712. * need to change with virtual interfaces. */
  713. idx = key->keyidx;
  714. } else if (key->keyidx) {
  715. if (WARN_ON(!sta))
  716. return -EOPNOTSUPP;
  717. mac = sta->addr;
  718. if (vif->type != NL80211_IFTYPE_AP) {
  719. /* Only keyidx 0 should be used with unicast key, but
  720. * allow this for client mode for now. */
  721. idx = key->keyidx;
  722. } else
  723. return -EIO;
  724. } else {
  725. if (WARN_ON(!sta))
  726. return -EOPNOTSUPP;
  727. mac = sta->addr;
  728. if (key->alg == ALG_TKIP)
  729. idx = ath_reserve_key_cache_slot_tkip(sc);
  730. else
  731. idx = ath_reserve_key_cache_slot(sc);
  732. if (idx < 0)
  733. return -ENOSPC; /* no free key cache entries */
  734. }
  735. if (key->alg == ALG_TKIP)
  736. ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
  737. vif->type == NL80211_IFTYPE_AP);
  738. else
  739. ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
  740. if (!ret)
  741. return -EIO;
  742. set_bit(idx, sc->keymap);
  743. if (key->alg == ALG_TKIP) {
  744. set_bit(idx + 64, sc->keymap);
  745. if (sc->splitmic) {
  746. set_bit(idx + 32, sc->keymap);
  747. set_bit(idx + 64 + 32, sc->keymap);
  748. }
  749. }
  750. return idx;
  751. }
  752. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  753. {
  754. ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
  755. if (key->hw_key_idx < IEEE80211_WEP_NKID)
  756. return;
  757. clear_bit(key->hw_key_idx, sc->keymap);
  758. if (key->alg != ALG_TKIP)
  759. return;
  760. clear_bit(key->hw_key_idx + 64, sc->keymap);
  761. if (sc->splitmic) {
  762. clear_bit(key->hw_key_idx + 32, sc->keymap);
  763. clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
  764. }
  765. }
  766. static void setup_ht_cap(struct ath_softc *sc,
  767. struct ieee80211_sta_ht_cap *ht_info)
  768. {
  769. u8 tx_streams, rx_streams;
  770. ht_info->ht_supported = true;
  771. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  772. IEEE80211_HT_CAP_SM_PS |
  773. IEEE80211_HT_CAP_SGI_40 |
  774. IEEE80211_HT_CAP_DSSSCCK40;
  775. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  776. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
  777. /* set up supported mcs set */
  778. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  779. tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
  780. rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
  781. if (tx_streams != rx_streams) {
  782. DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
  783. tx_streams, rx_streams);
  784. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  785. ht_info->mcs.tx_params |= ((tx_streams - 1) <<
  786. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  787. }
  788. ht_info->mcs.rx_mask[0] = 0xff;
  789. if (rx_streams >= 2)
  790. ht_info->mcs.rx_mask[1] = 0xff;
  791. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
  792. }
  793. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  794. struct ieee80211_vif *vif,
  795. struct ieee80211_bss_conf *bss_conf)
  796. {
  797. if (bss_conf->assoc) {
  798. DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  799. bss_conf->aid, sc->curbssid);
  800. /* New association, store aid */
  801. sc->curaid = bss_conf->aid;
  802. ath9k_hw_write_associd(sc);
  803. /*
  804. * Request a re-configuration of Beacon related timers
  805. * on the receipt of the first Beacon frame (i.e.,
  806. * after time sync with the AP).
  807. */
  808. sc->sc_flags |= SC_OP_BEACON_SYNC;
  809. /* Configure the beacon */
  810. ath_beacon_config(sc, vif);
  811. /* Reset rssi stats */
  812. sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  813. sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  814. sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  815. sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  816. ath_start_ani(sc);
  817. } else {
  818. DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  819. sc->curaid = 0;
  820. /* Stop ANI */
  821. del_timer_sync(&sc->ani.timer);
  822. }
  823. }
  824. /********************************/
  825. /* LED functions */
  826. /********************************/
  827. static void ath_led_blink_work(struct work_struct *work)
  828. {
  829. struct ath_softc *sc = container_of(work, struct ath_softc,
  830. ath_led_blink_work.work);
  831. if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
  832. return;
  833. if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
  834. (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
  835. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  836. else
  837. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  838. (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
  839. ieee80211_queue_delayed_work(sc->hw,
  840. &sc->ath_led_blink_work,
  841. (sc->sc_flags & SC_OP_LED_ON) ?
  842. msecs_to_jiffies(sc->led_off_duration) :
  843. msecs_to_jiffies(sc->led_on_duration));
  844. sc->led_on_duration = sc->led_on_cnt ?
  845. max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
  846. ATH_LED_ON_DURATION_IDLE;
  847. sc->led_off_duration = sc->led_off_cnt ?
  848. max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
  849. ATH_LED_OFF_DURATION_IDLE;
  850. sc->led_on_cnt = sc->led_off_cnt = 0;
  851. if (sc->sc_flags & SC_OP_LED_ON)
  852. sc->sc_flags &= ~SC_OP_LED_ON;
  853. else
  854. sc->sc_flags |= SC_OP_LED_ON;
  855. }
  856. static void ath_led_brightness(struct led_classdev *led_cdev,
  857. enum led_brightness brightness)
  858. {
  859. struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
  860. struct ath_softc *sc = led->sc;
  861. switch (brightness) {
  862. case LED_OFF:
  863. if (led->led_type == ATH_LED_ASSOC ||
  864. led->led_type == ATH_LED_RADIO) {
  865. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  866. (led->led_type == ATH_LED_RADIO));
  867. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  868. if (led->led_type == ATH_LED_RADIO)
  869. sc->sc_flags &= ~SC_OP_LED_ON;
  870. } else {
  871. sc->led_off_cnt++;
  872. }
  873. break;
  874. case LED_FULL:
  875. if (led->led_type == ATH_LED_ASSOC) {
  876. sc->sc_flags |= SC_OP_LED_ASSOCIATED;
  877. ieee80211_queue_delayed_work(sc->hw,
  878. &sc->ath_led_blink_work, 0);
  879. } else if (led->led_type == ATH_LED_RADIO) {
  880. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  881. sc->sc_flags |= SC_OP_LED_ON;
  882. } else {
  883. sc->led_on_cnt++;
  884. }
  885. break;
  886. default:
  887. break;
  888. }
  889. }
  890. static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
  891. char *trigger)
  892. {
  893. int ret;
  894. led->sc = sc;
  895. led->led_cdev.name = led->name;
  896. led->led_cdev.default_trigger = trigger;
  897. led->led_cdev.brightness_set = ath_led_brightness;
  898. ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
  899. if (ret)
  900. DPRINTF(sc, ATH_DBG_FATAL,
  901. "Failed to register led:%s", led->name);
  902. else
  903. led->registered = 1;
  904. return ret;
  905. }
  906. static void ath_unregister_led(struct ath_led *led)
  907. {
  908. if (led->registered) {
  909. led_classdev_unregister(&led->led_cdev);
  910. led->registered = 0;
  911. }
  912. }
  913. static void ath_deinit_leds(struct ath_softc *sc)
  914. {
  915. ath_unregister_led(&sc->assoc_led);
  916. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  917. ath_unregister_led(&sc->tx_led);
  918. ath_unregister_led(&sc->rx_led);
  919. ath_unregister_led(&sc->radio_led);
  920. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  921. }
  922. static void ath_init_leds(struct ath_softc *sc)
  923. {
  924. char *trigger;
  925. int ret;
  926. /* Configure gpio 1 for output */
  927. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  928. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  929. /* LED off, active low */
  930. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  931. INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
  932. trigger = ieee80211_get_radio_led_name(sc->hw);
  933. snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
  934. "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
  935. ret = ath_register_led(sc, &sc->radio_led, trigger);
  936. sc->radio_led.led_type = ATH_LED_RADIO;
  937. if (ret)
  938. goto fail;
  939. trigger = ieee80211_get_assoc_led_name(sc->hw);
  940. snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
  941. "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
  942. ret = ath_register_led(sc, &sc->assoc_led, trigger);
  943. sc->assoc_led.led_type = ATH_LED_ASSOC;
  944. if (ret)
  945. goto fail;
  946. trigger = ieee80211_get_tx_led_name(sc->hw);
  947. snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
  948. "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
  949. ret = ath_register_led(sc, &sc->tx_led, trigger);
  950. sc->tx_led.led_type = ATH_LED_TX;
  951. if (ret)
  952. goto fail;
  953. trigger = ieee80211_get_rx_led_name(sc->hw);
  954. snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
  955. "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
  956. ret = ath_register_led(sc, &sc->rx_led, trigger);
  957. sc->rx_led.led_type = ATH_LED_RX;
  958. if (ret)
  959. goto fail;
  960. return;
  961. fail:
  962. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  963. ath_deinit_leds(sc);
  964. }
  965. void ath_radio_enable(struct ath_softc *sc)
  966. {
  967. struct ath_hw *ah = sc->sc_ah;
  968. struct ieee80211_channel *channel = sc->hw->conf.channel;
  969. int r;
  970. ath9k_ps_wakeup(sc);
  971. ath9k_hw_configpcipowersave(ah, 0);
  972. if (!ah->curchan)
  973. ah->curchan = ath_get_curchannel(sc, sc->hw);
  974. spin_lock_bh(&sc->sc_resetlock);
  975. r = ath9k_hw_reset(ah, ah->curchan, false);
  976. if (r) {
  977. DPRINTF(sc, ATH_DBG_FATAL,
  978. "Unable to reset channel %u (%uMhz) ",
  979. "reset status %d\n",
  980. channel->center_freq, r);
  981. }
  982. spin_unlock_bh(&sc->sc_resetlock);
  983. ath_update_txpow(sc);
  984. if (ath_startrecv(sc) != 0) {
  985. DPRINTF(sc, ATH_DBG_FATAL,
  986. "Unable to restart recv logic\n");
  987. return;
  988. }
  989. if (sc->sc_flags & SC_OP_BEACONS)
  990. ath_beacon_config(sc, NULL); /* restart beacons */
  991. /* Re-Enable interrupts */
  992. ath9k_hw_set_interrupts(ah, sc->imask);
  993. /* Enable LED */
  994. ath9k_hw_cfg_output(ah, ATH_LED_PIN,
  995. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  996. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
  997. ieee80211_wake_queues(sc->hw);
  998. ath9k_ps_restore(sc);
  999. }
  1000. void ath_radio_disable(struct ath_softc *sc)
  1001. {
  1002. struct ath_hw *ah = sc->sc_ah;
  1003. struct ieee80211_channel *channel = sc->hw->conf.channel;
  1004. int r;
  1005. ath9k_ps_wakeup(sc);
  1006. ieee80211_stop_queues(sc->hw);
  1007. /* Disable LED */
  1008. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
  1009. ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
  1010. /* Disable interrupts */
  1011. ath9k_hw_set_interrupts(ah, 0);
  1012. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  1013. ath_stoprecv(sc); /* turn off frame recv */
  1014. ath_flushrecv(sc); /* flush recv queue */
  1015. if (!ah->curchan)
  1016. ah->curchan = ath_get_curchannel(sc, sc->hw);
  1017. spin_lock_bh(&sc->sc_resetlock);
  1018. r = ath9k_hw_reset(ah, ah->curchan, false);
  1019. if (r) {
  1020. DPRINTF(sc, ATH_DBG_FATAL,
  1021. "Unable to reset channel %u (%uMhz) "
  1022. "reset status %d\n",
  1023. channel->center_freq, r);
  1024. }
  1025. spin_unlock_bh(&sc->sc_resetlock);
  1026. ath9k_hw_phy_disable(ah);
  1027. ath9k_hw_configpcipowersave(ah, 1);
  1028. ath9k_ps_restore(sc);
  1029. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  1030. }
  1031. /*******************/
  1032. /* Rfkill */
  1033. /*******************/
  1034. static bool ath_is_rfkill_set(struct ath_softc *sc)
  1035. {
  1036. struct ath_hw *ah = sc->sc_ah;
  1037. return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
  1038. ah->rfkill_polarity;
  1039. }
  1040. static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
  1041. {
  1042. struct ath_wiphy *aphy = hw->priv;
  1043. struct ath_softc *sc = aphy->sc;
  1044. bool blocked = !!ath_is_rfkill_set(sc);
  1045. wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
  1046. if (blocked)
  1047. ath_radio_disable(sc);
  1048. else
  1049. ath_radio_enable(sc);
  1050. }
  1051. static void ath_start_rfkill_poll(struct ath_softc *sc)
  1052. {
  1053. struct ath_hw *ah = sc->sc_ah;
  1054. if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1055. wiphy_rfkill_start_polling(sc->hw->wiphy);
  1056. }
  1057. void ath_cleanup(struct ath_softc *sc)
  1058. {
  1059. ath_detach(sc);
  1060. free_irq(sc->irq, sc);
  1061. ath_bus_cleanup(sc);
  1062. kfree(sc->sec_wiphy);
  1063. ieee80211_free_hw(sc->hw);
  1064. }
  1065. void ath_detach(struct ath_softc *sc)
  1066. {
  1067. struct ieee80211_hw *hw = sc->hw;
  1068. int i = 0;
  1069. ath9k_ps_wakeup(sc);
  1070. DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
  1071. ath_deinit_leds(sc);
  1072. for (i = 0; i < sc->num_sec_wiphy; i++) {
  1073. struct ath_wiphy *aphy = sc->sec_wiphy[i];
  1074. if (aphy == NULL)
  1075. continue;
  1076. sc->sec_wiphy[i] = NULL;
  1077. ieee80211_unregister_hw(aphy->hw);
  1078. ieee80211_free_hw(aphy->hw);
  1079. }
  1080. ieee80211_unregister_hw(hw);
  1081. ath_rx_cleanup(sc);
  1082. ath_tx_cleanup(sc);
  1083. tasklet_kill(&sc->intr_tq);
  1084. tasklet_kill(&sc->bcon_tasklet);
  1085. if (!(sc->sc_flags & SC_OP_INVALID))
  1086. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  1087. /* cleanup tx queues */
  1088. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  1089. if (ATH_TXQ_SETUP(sc, i))
  1090. ath_tx_cleanupq(sc, &sc->tx.txq[i]);
  1091. ath9k_hw_detach(sc->sc_ah);
  1092. ath9k_exit_debug(sc);
  1093. }
  1094. static int ath9k_reg_notifier(struct wiphy *wiphy,
  1095. struct regulatory_request *request)
  1096. {
  1097. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  1098. struct ath_wiphy *aphy = hw->priv;
  1099. struct ath_softc *sc = aphy->sc;
  1100. struct ath_regulatory *reg = &sc->sc_ah->regulatory;
  1101. return ath_reg_notifier_apply(wiphy, request, reg);
  1102. }
  1103. /*
  1104. * Initialize and fill ath_softc, ath_sofct is the
  1105. * "Software Carrier" struct. Historically it has existed
  1106. * to allow the separation between hardware specific
  1107. * variables (now in ath_hw) and driver specific variables.
  1108. */
  1109. static int ath_init_softc(u16 devid, struct ath_softc *sc)
  1110. {
  1111. struct ath_hw *ah = NULL;
  1112. int r = 0, i;
  1113. int csz = 0;
  1114. /* XXX: hardware will not be ready until ath_open() being called */
  1115. sc->sc_flags |= SC_OP_INVALID;
  1116. if (ath9k_init_debug(sc) < 0)
  1117. printk(KERN_ERR "Unable to create debugfs files\n");
  1118. spin_lock_init(&sc->wiphy_lock);
  1119. spin_lock_init(&sc->sc_resetlock);
  1120. spin_lock_init(&sc->sc_serial_rw);
  1121. spin_lock_init(&sc->ani_lock);
  1122. spin_lock_init(&sc->sc_pm_lock);
  1123. mutex_init(&sc->mutex);
  1124. tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
  1125. tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
  1126. (unsigned long)sc);
  1127. /*
  1128. * Cache line size is used to size and align various
  1129. * structures used to communicate with the hardware.
  1130. */
  1131. ath_read_cachesize(sc, &csz);
  1132. /* XXX assert csz is non-zero */
  1133. sc->cachelsz = csz << 2; /* convert to bytes */
  1134. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  1135. if (!ah) {
  1136. r = -ENOMEM;
  1137. goto bad_no_ah;
  1138. }
  1139. ah->ah_sc = sc;
  1140. ah->hw_version.devid = devid;
  1141. sc->sc_ah = ah;
  1142. r = ath9k_hw_init(ah);
  1143. if (r) {
  1144. DPRINTF(sc, ATH_DBG_FATAL,
  1145. "Unable to initialize hardware; "
  1146. "initialization status: %d\n", r);
  1147. goto bad;
  1148. }
  1149. /* Get the hardware key cache size. */
  1150. sc->keymax = ah->caps.keycache_size;
  1151. if (sc->keymax > ATH_KEYMAX) {
  1152. DPRINTF(sc, ATH_DBG_ANY,
  1153. "Warning, using only %u entries in %u key cache\n",
  1154. ATH_KEYMAX, sc->keymax);
  1155. sc->keymax = ATH_KEYMAX;
  1156. }
  1157. /*
  1158. * Reset the key cache since some parts do not
  1159. * reset the contents on initial power up.
  1160. */
  1161. for (i = 0; i < sc->keymax; i++)
  1162. ath9k_hw_keyreset(ah, (u16) i);
  1163. if (r)
  1164. goto bad;
  1165. /* default to MONITOR mode */
  1166. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1167. /* Setup rate tables */
  1168. ath_rate_attach(sc);
  1169. ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
  1170. ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
  1171. /*
  1172. * Allocate hardware transmit queues: one queue for
  1173. * beacon frames and one data queue for each QoS
  1174. * priority. Note that the hal handles reseting
  1175. * these queues at the needed time.
  1176. */
  1177. sc->beacon.beaconq = ath_beaconq_setup(ah);
  1178. if (sc->beacon.beaconq == -1) {
  1179. DPRINTF(sc, ATH_DBG_FATAL,
  1180. "Unable to setup a beacon xmit queue\n");
  1181. r = -EIO;
  1182. goto bad2;
  1183. }
  1184. sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
  1185. if (sc->beacon.cabq == NULL) {
  1186. DPRINTF(sc, ATH_DBG_FATAL,
  1187. "Unable to setup CAB xmit queue\n");
  1188. r = -EIO;
  1189. goto bad2;
  1190. }
  1191. sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
  1192. ath_cabq_update(sc);
  1193. for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
  1194. sc->tx.hwq_map[i] = -1;
  1195. /* Setup data queues */
  1196. /* NB: ensure BK queue is the lowest priority h/w queue */
  1197. if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
  1198. DPRINTF(sc, ATH_DBG_FATAL,
  1199. "Unable to setup xmit queue for BK traffic\n");
  1200. r = -EIO;
  1201. goto bad2;
  1202. }
  1203. if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
  1204. DPRINTF(sc, ATH_DBG_FATAL,
  1205. "Unable to setup xmit queue for BE traffic\n");
  1206. r = -EIO;
  1207. goto bad2;
  1208. }
  1209. if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
  1210. DPRINTF(sc, ATH_DBG_FATAL,
  1211. "Unable to setup xmit queue for VI traffic\n");
  1212. r = -EIO;
  1213. goto bad2;
  1214. }
  1215. if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
  1216. DPRINTF(sc, ATH_DBG_FATAL,
  1217. "Unable to setup xmit queue for VO traffic\n");
  1218. r = -EIO;
  1219. goto bad2;
  1220. }
  1221. /* Initializes the noise floor to a reasonable default value.
  1222. * Later on this will be updated during ANI processing. */
  1223. sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
  1224. setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
  1225. if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
  1226. ATH9K_CIPHER_TKIP, NULL)) {
  1227. /*
  1228. * Whether we should enable h/w TKIP MIC.
  1229. * XXX: if we don't support WME TKIP MIC, then we wouldn't
  1230. * report WMM capable, so it's always safe to turn on
  1231. * TKIP MIC in this case.
  1232. */
  1233. ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
  1234. 0, 1, NULL);
  1235. }
  1236. /*
  1237. * Check whether the separate key cache entries
  1238. * are required to handle both tx+rx MIC keys.
  1239. * With split mic keys the number of stations is limited
  1240. * to 27 otherwise 59.
  1241. */
  1242. if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
  1243. ATH9K_CIPHER_TKIP, NULL)
  1244. && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
  1245. ATH9K_CIPHER_MIC, NULL)
  1246. && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
  1247. 0, NULL))
  1248. sc->splitmic = 1;
  1249. /* turn on mcast key search if possible */
  1250. if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
  1251. (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
  1252. 1, NULL);
  1253. sc->config.txpowlimit = ATH_TXPOWER_MAX;
  1254. /* 11n Capabilities */
  1255. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  1256. sc->sc_flags |= SC_OP_TXAGGR;
  1257. sc->sc_flags |= SC_OP_RXAGGR;
  1258. }
  1259. sc->tx_chainmask = ah->caps.tx_chainmask;
  1260. sc->rx_chainmask = ah->caps.rx_chainmask;
  1261. ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
  1262. sc->rx.defant = ath9k_hw_getdefantenna(ah);
  1263. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1264. memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
  1265. sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
  1266. /* initialize beacon slots */
  1267. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1268. sc->beacon.bslot[i] = NULL;
  1269. sc->beacon.bslot_aphy[i] = NULL;
  1270. }
  1271. /* setup channels and rates */
  1272. sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
  1273. sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
  1274. sc->rates[IEEE80211_BAND_2GHZ];
  1275. sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  1276. sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
  1277. ARRAY_SIZE(ath9k_2ghz_chantable);
  1278. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
  1279. sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
  1280. sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
  1281. sc->rates[IEEE80211_BAND_5GHZ];
  1282. sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
  1283. sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
  1284. ARRAY_SIZE(ath9k_5ghz_chantable);
  1285. }
  1286. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
  1287. ath9k_hw_btcoex_enable(sc->sc_ah);
  1288. return 0;
  1289. bad2:
  1290. /* cleanup tx queues */
  1291. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  1292. if (ATH_TXQ_SETUP(sc, i))
  1293. ath_tx_cleanupq(sc, &sc->tx.txq[i]);
  1294. bad:
  1295. if (ah)
  1296. ath9k_hw_detach(ah);
  1297. bad_no_ah:
  1298. ath9k_exit_debug(sc);
  1299. return r;
  1300. }
  1301. void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
  1302. {
  1303. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  1304. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1305. IEEE80211_HW_SIGNAL_DBM |
  1306. IEEE80211_HW_AMPDU_AGGREGATION |
  1307. IEEE80211_HW_SUPPORTS_PS |
  1308. IEEE80211_HW_PS_NULLFUNC_STACK |
  1309. IEEE80211_HW_SPECTRUM_MGMT;
  1310. if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
  1311. hw->flags |= IEEE80211_HW_MFP_CAPABLE;
  1312. hw->wiphy->interface_modes =
  1313. BIT(NL80211_IFTYPE_AP) |
  1314. BIT(NL80211_IFTYPE_STATION) |
  1315. BIT(NL80211_IFTYPE_ADHOC) |
  1316. BIT(NL80211_IFTYPE_MESH_POINT);
  1317. hw->queues = 4;
  1318. hw->max_rates = 4;
  1319. hw->channel_change_time = 5000;
  1320. hw->max_listen_interval = 10;
  1321. /* Hardware supports 10 but we use 4 */
  1322. hw->max_rate_tries = 4;
  1323. hw->sta_data_size = sizeof(struct ath_node);
  1324. hw->vif_data_size = sizeof(struct ath_vif);
  1325. hw->rate_control_algorithm = "ath9k_rate_control";
  1326. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1327. &sc->sbands[IEEE80211_BAND_2GHZ];
  1328. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
  1329. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1330. &sc->sbands[IEEE80211_BAND_5GHZ];
  1331. }
  1332. /* Device driver core initialization */
  1333. int ath_init_device(u16 devid, struct ath_softc *sc)
  1334. {
  1335. struct ieee80211_hw *hw = sc->hw;
  1336. int error = 0, i;
  1337. struct ath_regulatory *reg;
  1338. DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
  1339. error = ath_init_softc(devid, sc);
  1340. if (error != 0)
  1341. return error;
  1342. /* get mac address from hardware and set in mac80211 */
  1343. SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
  1344. ath_set_hw_capab(sc, hw);
  1345. error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
  1346. ath9k_reg_notifier);
  1347. if (error)
  1348. return error;
  1349. reg = &sc->sc_ah->regulatory;
  1350. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  1351. setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  1352. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
  1353. setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  1354. }
  1355. /* initialize tx/rx engine */
  1356. error = ath_tx_init(sc, ATH_TXBUF);
  1357. if (error != 0)
  1358. goto error_attach;
  1359. error = ath_rx_init(sc, ATH_RXBUF);
  1360. if (error != 0)
  1361. goto error_attach;
  1362. INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
  1363. INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
  1364. sc->wiphy_scheduler_int = msecs_to_jiffies(500);
  1365. error = ieee80211_register_hw(hw);
  1366. if (!ath_is_world_regd(reg)) {
  1367. error = regulatory_hint(hw->wiphy, reg->alpha2);
  1368. if (error)
  1369. goto error_attach;
  1370. }
  1371. /* Initialize LED control */
  1372. ath_init_leds(sc);
  1373. ath_start_rfkill_poll(sc);
  1374. return 0;
  1375. error_attach:
  1376. /* cleanup tx queues */
  1377. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
  1378. if (ATH_TXQ_SETUP(sc, i))
  1379. ath_tx_cleanupq(sc, &sc->tx.txq[i]);
  1380. ath9k_hw_detach(sc->sc_ah);
  1381. ath9k_exit_debug(sc);
  1382. return error;
  1383. }
  1384. int ath_reset(struct ath_softc *sc, bool retry_tx)
  1385. {
  1386. struct ath_hw *ah = sc->sc_ah;
  1387. struct ieee80211_hw *hw = sc->hw;
  1388. int r;
  1389. ath9k_hw_set_interrupts(ah, 0);
  1390. ath_drain_all_txq(sc, retry_tx);
  1391. ath_stoprecv(sc);
  1392. ath_flushrecv(sc);
  1393. spin_lock_bh(&sc->sc_resetlock);
  1394. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  1395. if (r)
  1396. DPRINTF(sc, ATH_DBG_FATAL,
  1397. "Unable to reset hardware; reset status %d\n", r);
  1398. spin_unlock_bh(&sc->sc_resetlock);
  1399. if (ath_startrecv(sc) != 0)
  1400. DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
  1401. /*
  1402. * We may be doing a reset in response to a request
  1403. * that changes the channel so update any state that
  1404. * might change as a result.
  1405. */
  1406. ath_cache_conf_rate(sc, &hw->conf);
  1407. ath_update_txpow(sc);
  1408. if (sc->sc_flags & SC_OP_BEACONS)
  1409. ath_beacon_config(sc, NULL); /* restart beacons */
  1410. ath9k_hw_set_interrupts(ah, sc->imask);
  1411. if (retry_tx) {
  1412. int i;
  1413. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1414. if (ATH_TXQ_SETUP(sc, i)) {
  1415. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  1416. ath_txq_schedule(sc, &sc->tx.txq[i]);
  1417. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  1418. }
  1419. }
  1420. }
  1421. return r;
  1422. }
  1423. /*
  1424. * This function will allocate both the DMA descriptor structure, and the
  1425. * buffers it contains. These are used to contain the descriptors used
  1426. * by the system.
  1427. */
  1428. int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
  1429. struct list_head *head, const char *name,
  1430. int nbuf, int ndesc)
  1431. {
  1432. #define DS2PHYS(_dd, _ds) \
  1433. ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
  1434. #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
  1435. #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
  1436. struct ath_desc *ds;
  1437. struct ath_buf *bf;
  1438. int i, bsize, error;
  1439. DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
  1440. name, nbuf, ndesc);
  1441. INIT_LIST_HEAD(head);
  1442. /* ath_desc must be a multiple of DWORDs */
  1443. if ((sizeof(struct ath_desc) % 4) != 0) {
  1444. DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
  1445. ASSERT((sizeof(struct ath_desc) % 4) == 0);
  1446. error = -ENOMEM;
  1447. goto fail;
  1448. }
  1449. dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
  1450. /*
  1451. * Need additional DMA memory because we can't use
  1452. * descriptors that cross the 4K page boundary. Assume
  1453. * one skipped descriptor per 4K page.
  1454. */
  1455. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
  1456. u32 ndesc_skipped =
  1457. ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
  1458. u32 dma_len;
  1459. while (ndesc_skipped) {
  1460. dma_len = ndesc_skipped * sizeof(struct ath_desc);
  1461. dd->dd_desc_len += dma_len;
  1462. ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
  1463. };
  1464. }
  1465. /* allocate descriptors */
  1466. dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
  1467. &dd->dd_desc_paddr, GFP_KERNEL);
  1468. if (dd->dd_desc == NULL) {
  1469. error = -ENOMEM;
  1470. goto fail;
  1471. }
  1472. ds = dd->dd_desc;
  1473. DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
  1474. name, ds, (u32) dd->dd_desc_len,
  1475. ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
  1476. /* allocate buffers */
  1477. bsize = sizeof(struct ath_buf) * nbuf;
  1478. bf = kzalloc(bsize, GFP_KERNEL);
  1479. if (bf == NULL) {
  1480. error = -ENOMEM;
  1481. goto fail2;
  1482. }
  1483. dd->dd_bufptr = bf;
  1484. for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
  1485. bf->bf_desc = ds;
  1486. bf->bf_daddr = DS2PHYS(dd, ds);
  1487. if (!(sc->sc_ah->caps.hw_caps &
  1488. ATH9K_HW_CAP_4KB_SPLITTRANS)) {
  1489. /*
  1490. * Skip descriptor addresses which can cause 4KB
  1491. * boundary crossing (addr + length) with a 32 dword
  1492. * descriptor fetch.
  1493. */
  1494. while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
  1495. ASSERT((caddr_t) bf->bf_desc <
  1496. ((caddr_t) dd->dd_desc +
  1497. dd->dd_desc_len));
  1498. ds += ndesc;
  1499. bf->bf_desc = ds;
  1500. bf->bf_daddr = DS2PHYS(dd, ds);
  1501. }
  1502. }
  1503. list_add_tail(&bf->list, head);
  1504. }
  1505. return 0;
  1506. fail2:
  1507. dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
  1508. dd->dd_desc_paddr);
  1509. fail:
  1510. memset(dd, 0, sizeof(*dd));
  1511. return error;
  1512. #undef ATH_DESC_4KB_BOUND_CHECK
  1513. #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
  1514. #undef DS2PHYS
  1515. }
  1516. void ath_descdma_cleanup(struct ath_softc *sc,
  1517. struct ath_descdma *dd,
  1518. struct list_head *head)
  1519. {
  1520. dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
  1521. dd->dd_desc_paddr);
  1522. INIT_LIST_HEAD(head);
  1523. kfree(dd->dd_bufptr);
  1524. memset(dd, 0, sizeof(*dd));
  1525. }
  1526. int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  1527. {
  1528. int qnum;
  1529. switch (queue) {
  1530. case 0:
  1531. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
  1532. break;
  1533. case 1:
  1534. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
  1535. break;
  1536. case 2:
  1537. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  1538. break;
  1539. case 3:
  1540. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
  1541. break;
  1542. default:
  1543. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  1544. break;
  1545. }
  1546. return qnum;
  1547. }
  1548. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  1549. {
  1550. int qnum;
  1551. switch (queue) {
  1552. case ATH9K_WME_AC_VO:
  1553. qnum = 0;
  1554. break;
  1555. case ATH9K_WME_AC_VI:
  1556. qnum = 1;
  1557. break;
  1558. case ATH9K_WME_AC_BE:
  1559. qnum = 2;
  1560. break;
  1561. case ATH9K_WME_AC_BK:
  1562. qnum = 3;
  1563. break;
  1564. default:
  1565. qnum = -1;
  1566. break;
  1567. }
  1568. return qnum;
  1569. }
  1570. /* XXX: Remove me once we don't depend on ath9k_channel for all
  1571. * this redundant data */
  1572. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  1573. struct ath9k_channel *ichan)
  1574. {
  1575. struct ieee80211_channel *chan = hw->conf.channel;
  1576. struct ieee80211_conf *conf = &hw->conf;
  1577. ichan->channel = chan->center_freq;
  1578. ichan->chan = chan;
  1579. if (chan->band == IEEE80211_BAND_2GHZ) {
  1580. ichan->chanmode = CHANNEL_G;
  1581. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
  1582. } else {
  1583. ichan->chanmode = CHANNEL_A;
  1584. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  1585. }
  1586. sc->tx_chan_width = ATH9K_HT_MACMODE_20;
  1587. if (conf_is_ht(conf)) {
  1588. if (conf_is_ht40(conf))
  1589. sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
  1590. ichan->chanmode = ath_get_extchanmode(sc, chan,
  1591. conf->channel_type);
  1592. }
  1593. }
  1594. /**********************/
  1595. /* mac80211 callbacks */
  1596. /**********************/
  1597. static int ath9k_start(struct ieee80211_hw *hw)
  1598. {
  1599. struct ath_wiphy *aphy = hw->priv;
  1600. struct ath_softc *sc = aphy->sc;
  1601. struct ieee80211_channel *curchan = hw->conf.channel;
  1602. struct ath9k_channel *init_channel;
  1603. int r;
  1604. DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
  1605. "initial channel: %d MHz\n", curchan->center_freq);
  1606. mutex_lock(&sc->mutex);
  1607. if (ath9k_wiphy_started(sc)) {
  1608. if (sc->chan_idx == curchan->hw_value) {
  1609. /*
  1610. * Already on the operational channel, the new wiphy
  1611. * can be marked active.
  1612. */
  1613. aphy->state = ATH_WIPHY_ACTIVE;
  1614. ieee80211_wake_queues(hw);
  1615. } else {
  1616. /*
  1617. * Another wiphy is on another channel, start the new
  1618. * wiphy in paused state.
  1619. */
  1620. aphy->state = ATH_WIPHY_PAUSED;
  1621. ieee80211_stop_queues(hw);
  1622. }
  1623. mutex_unlock(&sc->mutex);
  1624. return 0;
  1625. }
  1626. aphy->state = ATH_WIPHY_ACTIVE;
  1627. /* setup initial channel */
  1628. sc->chan_idx = curchan->hw_value;
  1629. init_channel = ath_get_curchannel(sc, hw);
  1630. /* Reset SERDES registers */
  1631. ath9k_hw_configpcipowersave(sc->sc_ah, 0);
  1632. /*
  1633. * The basic interface to setting the hardware in a good
  1634. * state is ``reset''. On return the hardware is known to
  1635. * be powered up and with interrupts disabled. This must
  1636. * be followed by initialization of the appropriate bits
  1637. * and then setup of the interrupt mask.
  1638. */
  1639. spin_lock_bh(&sc->sc_resetlock);
  1640. r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
  1641. if (r) {
  1642. DPRINTF(sc, ATH_DBG_FATAL,
  1643. "Unable to reset hardware; reset status %d "
  1644. "(freq %u MHz)\n", r,
  1645. curchan->center_freq);
  1646. spin_unlock_bh(&sc->sc_resetlock);
  1647. goto mutex_unlock;
  1648. }
  1649. spin_unlock_bh(&sc->sc_resetlock);
  1650. /*
  1651. * This is needed only to setup initial state
  1652. * but it's best done after a reset.
  1653. */
  1654. ath_update_txpow(sc);
  1655. /*
  1656. * Setup the hardware after reset:
  1657. * The receive engine is set going.
  1658. * Frame transmit is handled entirely
  1659. * in the frame output path; there's nothing to do
  1660. * here except setup the interrupt mask.
  1661. */
  1662. if (ath_startrecv(sc) != 0) {
  1663. DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
  1664. r = -EIO;
  1665. goto mutex_unlock;
  1666. }
  1667. /* Setup our intr mask. */
  1668. sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
  1669. | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
  1670. | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
  1671. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  1672. sc->imask |= ATH9K_INT_GTT;
  1673. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  1674. sc->imask |= ATH9K_INT_CST;
  1675. ath_cache_conf_rate(sc, &hw->conf);
  1676. sc->sc_flags &= ~SC_OP_INVALID;
  1677. /* Disable BMISS interrupt when we're not associated */
  1678. sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1679. ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
  1680. ieee80211_wake_queues(hw);
  1681. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1682. mutex_unlock:
  1683. mutex_unlock(&sc->mutex);
  1684. return r;
  1685. }
  1686. static int ath9k_tx(struct ieee80211_hw *hw,
  1687. struct sk_buff *skb)
  1688. {
  1689. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1690. struct ath_wiphy *aphy = hw->priv;
  1691. struct ath_softc *sc = aphy->sc;
  1692. struct ath_tx_control txctl;
  1693. int hdrlen, padsize;
  1694. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  1695. printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
  1696. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  1697. goto exit;
  1698. }
  1699. if (sc->ps_enabled) {
  1700. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1701. /*
  1702. * mac80211 does not set PM field for normal data frames, so we
  1703. * need to update that based on the current PS mode.
  1704. */
  1705. if (ieee80211_is_data(hdr->frame_control) &&
  1706. !ieee80211_is_nullfunc(hdr->frame_control) &&
  1707. !ieee80211_has_pm(hdr->frame_control)) {
  1708. DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
  1709. "while in PS mode\n");
  1710. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  1711. }
  1712. }
  1713. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  1714. /*
  1715. * We are using PS-Poll and mac80211 can request TX while in
  1716. * power save mode. Need to wake up hardware for the TX to be
  1717. * completed and if needed, also for RX of buffered frames.
  1718. */
  1719. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1720. ath9k_ps_wakeup(sc);
  1721. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1722. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1723. DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
  1724. "buffered frame\n");
  1725. sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
  1726. } else {
  1727. DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
  1728. sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
  1729. }
  1730. /*
  1731. * The actual restore operation will happen only after
  1732. * the sc_flags bit is cleared. We are just dropping
  1733. * the ps_usecount here.
  1734. */
  1735. ath9k_ps_restore(sc);
  1736. }
  1737. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1738. /*
  1739. * As a temporary workaround, assign seq# here; this will likely need
  1740. * to be cleaned up to work better with Beacon transmission and virtual
  1741. * BSSes.
  1742. */
  1743. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1744. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1745. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1746. sc->tx.seq_no += 0x10;
  1747. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1748. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1749. }
  1750. /* Add the padding after the header if this is not already done */
  1751. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  1752. if (hdrlen & 3) {
  1753. padsize = hdrlen % 4;
  1754. if (skb_headroom(skb) < padsize)
  1755. return -1;
  1756. skb_push(skb, padsize);
  1757. memmove(skb->data, skb->data + padsize, hdrlen);
  1758. }
  1759. /* Check if a tx queue is available */
  1760. txctl.txq = ath_test_get_txq(sc, skb);
  1761. if (!txctl.txq)
  1762. goto exit;
  1763. DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1764. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1765. DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
  1766. goto exit;
  1767. }
  1768. return 0;
  1769. exit:
  1770. dev_kfree_skb_any(skb);
  1771. return 0;
  1772. }
  1773. static void ath9k_stop(struct ieee80211_hw *hw)
  1774. {
  1775. struct ath_wiphy *aphy = hw->priv;
  1776. struct ath_softc *sc = aphy->sc;
  1777. aphy->state = ATH_WIPHY_INACTIVE;
  1778. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1779. cancel_delayed_work_sync(&sc->tx_complete_work);
  1780. if (!sc->num_sec_wiphy) {
  1781. cancel_delayed_work_sync(&sc->wiphy_work);
  1782. cancel_work_sync(&sc->chan_work);
  1783. }
  1784. if (sc->sc_flags & SC_OP_INVALID) {
  1785. DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
  1786. return;
  1787. }
  1788. mutex_lock(&sc->mutex);
  1789. if (ath9k_wiphy_started(sc)) {
  1790. mutex_unlock(&sc->mutex);
  1791. return; /* another wiphy still in use */
  1792. }
  1793. /* make sure h/w will not generate any interrupt
  1794. * before setting the invalid flag. */
  1795. ath9k_hw_set_interrupts(sc->sc_ah, 0);
  1796. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1797. ath_drain_all_txq(sc, false);
  1798. ath_stoprecv(sc);
  1799. ath9k_hw_phy_disable(sc->sc_ah);
  1800. } else
  1801. sc->rx.rxlink = NULL;
  1802. wiphy_rfkill_stop_polling(sc->hw->wiphy);
  1803. /* disable HAL and put h/w to sleep */
  1804. ath9k_hw_disable(sc->sc_ah);
  1805. ath9k_hw_configpcipowersave(sc->sc_ah, 1);
  1806. sc->sc_flags |= SC_OP_INVALID;
  1807. mutex_unlock(&sc->mutex);
  1808. DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
  1809. }
  1810. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1811. struct ieee80211_if_init_conf *conf)
  1812. {
  1813. struct ath_wiphy *aphy = hw->priv;
  1814. struct ath_softc *sc = aphy->sc;
  1815. struct ath_vif *avp = (void *)conf->vif->drv_priv;
  1816. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1817. int ret = 0;
  1818. mutex_lock(&sc->mutex);
  1819. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1820. sc->nvifs > 0) {
  1821. ret = -ENOBUFS;
  1822. goto out;
  1823. }
  1824. switch (conf->type) {
  1825. case NL80211_IFTYPE_STATION:
  1826. ic_opmode = NL80211_IFTYPE_STATION;
  1827. break;
  1828. case NL80211_IFTYPE_ADHOC:
  1829. case NL80211_IFTYPE_AP:
  1830. case NL80211_IFTYPE_MESH_POINT:
  1831. if (sc->nbcnvifs >= ATH_BCBUF) {
  1832. ret = -ENOBUFS;
  1833. goto out;
  1834. }
  1835. ic_opmode = conf->type;
  1836. break;
  1837. default:
  1838. DPRINTF(sc, ATH_DBG_FATAL,
  1839. "Interface type %d not yet supported\n", conf->type);
  1840. ret = -EOPNOTSUPP;
  1841. goto out;
  1842. }
  1843. DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
  1844. /* Set the VIF opmode */
  1845. avp->av_opmode = ic_opmode;
  1846. avp->av_bslot = -1;
  1847. sc->nvifs++;
  1848. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1849. ath9k_set_bssid_mask(hw);
  1850. if (sc->nvifs > 1)
  1851. goto out; /* skip global settings for secondary vif */
  1852. if (ic_opmode == NL80211_IFTYPE_AP) {
  1853. ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
  1854. sc->sc_flags |= SC_OP_TSF_RESET;
  1855. }
  1856. /* Set the device opmode */
  1857. sc->sc_ah->opmode = ic_opmode;
  1858. /*
  1859. * Enable MIB interrupts when there are hardware phy counters.
  1860. * Note we only do this (at the moment) for station mode.
  1861. */
  1862. if ((conf->type == NL80211_IFTYPE_STATION) ||
  1863. (conf->type == NL80211_IFTYPE_ADHOC) ||
  1864. (conf->type == NL80211_IFTYPE_MESH_POINT)) {
  1865. if (ath9k_hw_phycounters(sc->sc_ah))
  1866. sc->imask |= ATH9K_INT_MIB;
  1867. sc->imask |= ATH9K_INT_TSFOOR;
  1868. }
  1869. ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
  1870. if (conf->type == NL80211_IFTYPE_AP ||
  1871. conf->type == NL80211_IFTYPE_ADHOC ||
  1872. conf->type == NL80211_IFTYPE_MONITOR)
  1873. ath_start_ani(sc);
  1874. out:
  1875. mutex_unlock(&sc->mutex);
  1876. return ret;
  1877. }
  1878. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1879. struct ieee80211_if_init_conf *conf)
  1880. {
  1881. struct ath_wiphy *aphy = hw->priv;
  1882. struct ath_softc *sc = aphy->sc;
  1883. struct ath_vif *avp = (void *)conf->vif->drv_priv;
  1884. int i;
  1885. DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
  1886. mutex_lock(&sc->mutex);
  1887. /* Stop ANI */
  1888. del_timer_sync(&sc->ani.timer);
  1889. /* Reclaim beacon resources */
  1890. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1891. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1892. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1893. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1894. ath_beacon_return(sc, avp);
  1895. }
  1896. sc->sc_flags &= ~SC_OP_BEACONS;
  1897. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1898. if (sc->beacon.bslot[i] == conf->vif) {
  1899. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1900. "slot\n", __func__);
  1901. sc->beacon.bslot[i] = NULL;
  1902. sc->beacon.bslot_aphy[i] = NULL;
  1903. }
  1904. }
  1905. sc->nvifs--;
  1906. mutex_unlock(&sc->mutex);
  1907. }
  1908. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1909. {
  1910. struct ath_wiphy *aphy = hw->priv;
  1911. struct ath_softc *sc = aphy->sc;
  1912. struct ieee80211_conf *conf = &hw->conf;
  1913. struct ath_hw *ah = sc->sc_ah;
  1914. bool all_wiphys_idle = false, disable_radio = false;
  1915. mutex_lock(&sc->mutex);
  1916. /* Leave this as the first check */
  1917. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1918. spin_lock_bh(&sc->wiphy_lock);
  1919. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1920. spin_unlock_bh(&sc->wiphy_lock);
  1921. if (conf->flags & IEEE80211_CONF_IDLE){
  1922. if (all_wiphys_idle)
  1923. disable_radio = true;
  1924. }
  1925. else if (all_wiphys_idle) {
  1926. ath_radio_enable(sc);
  1927. DPRINTF(sc, ATH_DBG_CONFIG,
  1928. "not-idle: enabling radio\n");
  1929. }
  1930. }
  1931. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1932. if (conf->flags & IEEE80211_CONF_PS) {
  1933. if (!(ah->caps.hw_caps &
  1934. ATH9K_HW_CAP_AUTOSLEEP)) {
  1935. if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1936. sc->imask |= ATH9K_INT_TIM_TIMER;
  1937. ath9k_hw_set_interrupts(sc->sc_ah,
  1938. sc->imask);
  1939. }
  1940. ath9k_hw_setrxabort(sc->sc_ah, 1);
  1941. }
  1942. sc->ps_enabled = true;
  1943. } else {
  1944. sc->ps_enabled = false;
  1945. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  1946. if (!(ah->caps.hw_caps &
  1947. ATH9K_HW_CAP_AUTOSLEEP)) {
  1948. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1949. sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
  1950. SC_OP_WAIT_FOR_CAB |
  1951. SC_OP_WAIT_FOR_PSPOLL_DATA |
  1952. SC_OP_WAIT_FOR_TX_ACK);
  1953. if (sc->imask & ATH9K_INT_TIM_TIMER) {
  1954. sc->imask &= ~ATH9K_INT_TIM_TIMER;
  1955. ath9k_hw_set_interrupts(sc->sc_ah,
  1956. sc->imask);
  1957. }
  1958. }
  1959. }
  1960. }
  1961. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1962. struct ieee80211_channel *curchan = hw->conf.channel;
  1963. int pos = curchan->hw_value;
  1964. aphy->chan_idx = pos;
  1965. aphy->chan_is_ht = conf_is_ht(conf);
  1966. if (aphy->state == ATH_WIPHY_SCAN ||
  1967. aphy->state == ATH_WIPHY_ACTIVE)
  1968. ath9k_wiphy_pause_all_forced(sc, aphy);
  1969. else {
  1970. /*
  1971. * Do not change operational channel based on a paused
  1972. * wiphy changes.
  1973. */
  1974. goto skip_chan_change;
  1975. }
  1976. DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1977. curchan->center_freq);
  1978. /* XXX: remove me eventualy */
  1979. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1980. ath_update_chainmask(sc, conf_is_ht(conf));
  1981. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1982. DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
  1983. mutex_unlock(&sc->mutex);
  1984. return -EINVAL;
  1985. }
  1986. }
  1987. skip_chan_change:
  1988. if (changed & IEEE80211_CONF_CHANGE_POWER)
  1989. sc->config.txpowlimit = 2 * conf->power_level;
  1990. if (disable_radio) {
  1991. DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1992. ath_radio_disable(sc);
  1993. }
  1994. mutex_unlock(&sc->mutex);
  1995. return 0;
  1996. }
  1997. #define SUPPORTED_FILTERS \
  1998. (FIF_PROMISC_IN_BSS | \
  1999. FIF_ALLMULTI | \
  2000. FIF_CONTROL | \
  2001. FIF_OTHER_BSS | \
  2002. FIF_BCN_PRBRESP_PROMISC | \
  2003. FIF_FCSFAIL)
  2004. /* FIXME: sc->sc_full_reset ? */
  2005. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  2006. unsigned int changed_flags,
  2007. unsigned int *total_flags,
  2008. int mc_count,
  2009. struct dev_mc_list *mclist)
  2010. {
  2011. struct ath_wiphy *aphy = hw->priv;
  2012. struct ath_softc *sc = aphy->sc;
  2013. u32 rfilt;
  2014. changed_flags &= SUPPORTED_FILTERS;
  2015. *total_flags &= SUPPORTED_FILTERS;
  2016. sc->rx.rxfilter = *total_flags;
  2017. ath9k_ps_wakeup(sc);
  2018. rfilt = ath_calcrxfilter(sc);
  2019. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  2020. ath9k_ps_restore(sc);
  2021. DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
  2022. }
  2023. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  2024. struct ieee80211_vif *vif,
  2025. enum sta_notify_cmd cmd,
  2026. struct ieee80211_sta *sta)
  2027. {
  2028. struct ath_wiphy *aphy = hw->priv;
  2029. struct ath_softc *sc = aphy->sc;
  2030. switch (cmd) {
  2031. case STA_NOTIFY_ADD:
  2032. ath_node_attach(sc, sta);
  2033. break;
  2034. case STA_NOTIFY_REMOVE:
  2035. ath_node_detach(sc, sta);
  2036. break;
  2037. default:
  2038. break;
  2039. }
  2040. }
  2041. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  2042. const struct ieee80211_tx_queue_params *params)
  2043. {
  2044. struct ath_wiphy *aphy = hw->priv;
  2045. struct ath_softc *sc = aphy->sc;
  2046. struct ath9k_tx_queue_info qi;
  2047. int ret = 0, qnum;
  2048. if (queue >= WME_NUM_AC)
  2049. return 0;
  2050. mutex_lock(&sc->mutex);
  2051. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  2052. qi.tqi_aifs = params->aifs;
  2053. qi.tqi_cwmin = params->cw_min;
  2054. qi.tqi_cwmax = params->cw_max;
  2055. qi.tqi_burstTime = params->txop;
  2056. qnum = ath_get_hal_qnum(queue, sc);
  2057. DPRINTF(sc, ATH_DBG_CONFIG,
  2058. "Configure tx [queue/halq] [%d/%d], "
  2059. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  2060. queue, qnum, params->aifs, params->cw_min,
  2061. params->cw_max, params->txop);
  2062. ret = ath_txq_update(sc, qnum, &qi);
  2063. if (ret)
  2064. DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
  2065. mutex_unlock(&sc->mutex);
  2066. return ret;
  2067. }
  2068. static int ath9k_set_key(struct ieee80211_hw *hw,
  2069. enum set_key_cmd cmd,
  2070. struct ieee80211_vif *vif,
  2071. struct ieee80211_sta *sta,
  2072. struct ieee80211_key_conf *key)
  2073. {
  2074. struct ath_wiphy *aphy = hw->priv;
  2075. struct ath_softc *sc = aphy->sc;
  2076. int ret = 0;
  2077. if (modparam_nohwcrypt)
  2078. return -ENOSPC;
  2079. mutex_lock(&sc->mutex);
  2080. ath9k_ps_wakeup(sc);
  2081. DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
  2082. switch (cmd) {
  2083. case SET_KEY:
  2084. ret = ath_key_config(sc, vif, sta, key);
  2085. if (ret >= 0) {
  2086. key->hw_key_idx = ret;
  2087. /* push IV and Michael MIC generation to stack */
  2088. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  2089. if (key->alg == ALG_TKIP)
  2090. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  2091. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  2092. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  2093. ret = 0;
  2094. }
  2095. break;
  2096. case DISABLE_KEY:
  2097. ath_key_delete(sc, key);
  2098. break;
  2099. default:
  2100. ret = -EINVAL;
  2101. }
  2102. ath9k_ps_restore(sc);
  2103. mutex_unlock(&sc->mutex);
  2104. return ret;
  2105. }
  2106. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  2107. struct ieee80211_vif *vif,
  2108. struct ieee80211_bss_conf *bss_conf,
  2109. u32 changed)
  2110. {
  2111. struct ath_wiphy *aphy = hw->priv;
  2112. struct ath_softc *sc = aphy->sc;
  2113. struct ath_hw *ah = sc->sc_ah;
  2114. struct ath_vif *avp = (void *)vif->drv_priv;
  2115. u32 rfilt = 0;
  2116. int error, i;
  2117. mutex_lock(&sc->mutex);
  2118. /*
  2119. * TODO: Need to decide which hw opmode to use for
  2120. * multi-interface cases
  2121. * XXX: This belongs into add_interface!
  2122. */
  2123. if (vif->type == NL80211_IFTYPE_AP &&
  2124. ah->opmode != NL80211_IFTYPE_AP) {
  2125. ah->opmode = NL80211_IFTYPE_STATION;
  2126. ath9k_hw_setopmode(ah);
  2127. memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
  2128. sc->curaid = 0;
  2129. ath9k_hw_write_associd(sc);
  2130. /* Request full reset to get hw opmode changed properly */
  2131. sc->sc_flags |= SC_OP_FULL_RESET;
  2132. }
  2133. if ((changed & BSS_CHANGED_BSSID) &&
  2134. !is_zero_ether_addr(bss_conf->bssid)) {
  2135. switch (vif->type) {
  2136. case NL80211_IFTYPE_STATION:
  2137. case NL80211_IFTYPE_ADHOC:
  2138. case NL80211_IFTYPE_MESH_POINT:
  2139. /* Set BSSID */
  2140. memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
  2141. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  2142. sc->curaid = 0;
  2143. ath9k_hw_write_associd(sc);
  2144. /* Set aggregation protection mode parameters */
  2145. sc->config.ath_aggr_prot = 0;
  2146. DPRINTF(sc, ATH_DBG_CONFIG,
  2147. "RX filter 0x%x bssid %pM aid 0x%x\n",
  2148. rfilt, sc->curbssid, sc->curaid);
  2149. /* need to reconfigure the beacon */
  2150. sc->sc_flags &= ~SC_OP_BEACONS ;
  2151. break;
  2152. default:
  2153. break;
  2154. }
  2155. }
  2156. if ((vif->type == NL80211_IFTYPE_ADHOC) ||
  2157. (vif->type == NL80211_IFTYPE_AP) ||
  2158. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  2159. if ((changed & BSS_CHANGED_BEACON) ||
  2160. (changed & BSS_CHANGED_BEACON_ENABLED &&
  2161. bss_conf->enable_beacon)) {
  2162. /*
  2163. * Allocate and setup the beacon frame.
  2164. *
  2165. * Stop any previous beacon DMA. This may be
  2166. * necessary, for example, when an ibss merge
  2167. * causes reconfiguration; we may be called
  2168. * with beacon transmission active.
  2169. */
  2170. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  2171. error = ath_beacon_alloc(aphy, vif);
  2172. if (!error)
  2173. ath_beacon_config(sc, vif);
  2174. }
  2175. }
  2176. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  2177. if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
  2178. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  2179. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  2180. ath9k_hw_keysetmac(sc->sc_ah,
  2181. (u16)i,
  2182. sc->curbssid);
  2183. }
  2184. /* Only legacy IBSS for now */
  2185. if (vif->type == NL80211_IFTYPE_ADHOC)
  2186. ath_update_chainmask(sc, 0);
  2187. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2188. DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  2189. bss_conf->use_short_preamble);
  2190. if (bss_conf->use_short_preamble)
  2191. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  2192. else
  2193. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  2194. }
  2195. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  2196. DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  2197. bss_conf->use_cts_prot);
  2198. if (bss_conf->use_cts_prot &&
  2199. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  2200. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  2201. else
  2202. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  2203. }
  2204. if (changed & BSS_CHANGED_ASSOC) {
  2205. DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  2206. bss_conf->assoc);
  2207. ath9k_bss_assoc_info(sc, vif, bss_conf);
  2208. }
  2209. /*
  2210. * The HW TSF has to be reset when the beacon interval changes.
  2211. * We set the flag here, and ath_beacon_config_ap() would take this
  2212. * into account when it gets called through the subsequent
  2213. * config_interface() call - with IFCC_BEACON in the changed field.
  2214. */
  2215. if (changed & BSS_CHANGED_BEACON_INT) {
  2216. sc->sc_flags |= SC_OP_TSF_RESET;
  2217. sc->beacon_interval = bss_conf->beacon_int;
  2218. }
  2219. mutex_unlock(&sc->mutex);
  2220. }
  2221. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  2222. {
  2223. u64 tsf;
  2224. struct ath_wiphy *aphy = hw->priv;
  2225. struct ath_softc *sc = aphy->sc;
  2226. mutex_lock(&sc->mutex);
  2227. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  2228. mutex_unlock(&sc->mutex);
  2229. return tsf;
  2230. }
  2231. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  2232. {
  2233. struct ath_wiphy *aphy = hw->priv;
  2234. struct ath_softc *sc = aphy->sc;
  2235. mutex_lock(&sc->mutex);
  2236. ath9k_hw_settsf64(sc->sc_ah, tsf);
  2237. mutex_unlock(&sc->mutex);
  2238. }
  2239. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  2240. {
  2241. struct ath_wiphy *aphy = hw->priv;
  2242. struct ath_softc *sc = aphy->sc;
  2243. mutex_lock(&sc->mutex);
  2244. ath9k_hw_reset_tsf(sc->sc_ah);
  2245. mutex_unlock(&sc->mutex);
  2246. }
  2247. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  2248. enum ieee80211_ampdu_mlme_action action,
  2249. struct ieee80211_sta *sta,
  2250. u16 tid, u16 *ssn)
  2251. {
  2252. struct ath_wiphy *aphy = hw->priv;
  2253. struct ath_softc *sc = aphy->sc;
  2254. int ret = 0;
  2255. switch (action) {
  2256. case IEEE80211_AMPDU_RX_START:
  2257. if (!(sc->sc_flags & SC_OP_RXAGGR))
  2258. ret = -ENOTSUPP;
  2259. break;
  2260. case IEEE80211_AMPDU_RX_STOP:
  2261. break;
  2262. case IEEE80211_AMPDU_TX_START:
  2263. ath_tx_aggr_start(sc, sta, tid, ssn);
  2264. ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  2265. break;
  2266. case IEEE80211_AMPDU_TX_STOP:
  2267. ath_tx_aggr_stop(sc, sta, tid);
  2268. ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  2269. break;
  2270. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2271. ath_tx_aggr_resume(sc, sta, tid);
  2272. break;
  2273. default:
  2274. DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
  2275. }
  2276. return ret;
  2277. }
  2278. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  2279. {
  2280. struct ath_wiphy *aphy = hw->priv;
  2281. struct ath_softc *sc = aphy->sc;
  2282. if (ath9k_wiphy_scanning(sc)) {
  2283. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  2284. "same time\n");
  2285. /*
  2286. * Do not allow the concurrent scanning state for now. This
  2287. * could be improved with scanning control moved into ath9k.
  2288. */
  2289. return;
  2290. }
  2291. aphy->state = ATH_WIPHY_SCAN;
  2292. ath9k_wiphy_pause_all_forced(sc, aphy);
  2293. spin_lock_bh(&sc->ani_lock);
  2294. sc->sc_flags |= SC_OP_SCANNING;
  2295. spin_unlock_bh(&sc->ani_lock);
  2296. }
  2297. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  2298. {
  2299. struct ath_wiphy *aphy = hw->priv;
  2300. struct ath_softc *sc = aphy->sc;
  2301. spin_lock_bh(&sc->ani_lock);
  2302. aphy->state = ATH_WIPHY_ACTIVE;
  2303. sc->sc_flags &= ~SC_OP_SCANNING;
  2304. sc->sc_flags |= SC_OP_FULL_RESET;
  2305. spin_unlock_bh(&sc->ani_lock);
  2306. }
  2307. struct ieee80211_ops ath9k_ops = {
  2308. .tx = ath9k_tx,
  2309. .start = ath9k_start,
  2310. .stop = ath9k_stop,
  2311. .add_interface = ath9k_add_interface,
  2312. .remove_interface = ath9k_remove_interface,
  2313. .config = ath9k_config,
  2314. .configure_filter = ath9k_configure_filter,
  2315. .sta_notify = ath9k_sta_notify,
  2316. .conf_tx = ath9k_conf_tx,
  2317. .bss_info_changed = ath9k_bss_info_changed,
  2318. .set_key = ath9k_set_key,
  2319. .get_tsf = ath9k_get_tsf,
  2320. .set_tsf = ath9k_set_tsf,
  2321. .reset_tsf = ath9k_reset_tsf,
  2322. .ampdu_action = ath9k_ampdu_action,
  2323. .sw_scan_start = ath9k_sw_scan_start,
  2324. .sw_scan_complete = ath9k_sw_scan_complete,
  2325. .rfkill_poll = ath9k_rfkill_poll_state,
  2326. };
  2327. static struct {
  2328. u32 version;
  2329. const char * name;
  2330. } ath_mac_bb_names[] = {
  2331. { AR_SREV_VERSION_5416_PCI, "5416" },
  2332. { AR_SREV_VERSION_5416_PCIE, "5418" },
  2333. { AR_SREV_VERSION_9100, "9100" },
  2334. { AR_SREV_VERSION_9160, "9160" },
  2335. { AR_SREV_VERSION_9280, "9280" },
  2336. { AR_SREV_VERSION_9285, "9285" },
  2337. { AR_SREV_VERSION_9287, "9287" }
  2338. };
  2339. static struct {
  2340. u16 version;
  2341. const char * name;
  2342. } ath_rf_names[] = {
  2343. { 0, "5133" },
  2344. { AR_RAD5133_SREV_MAJOR, "5133" },
  2345. { AR_RAD5122_SREV_MAJOR, "5122" },
  2346. { AR_RAD2133_SREV_MAJOR, "2133" },
  2347. { AR_RAD2122_SREV_MAJOR, "2122" }
  2348. };
  2349. /*
  2350. * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
  2351. */
  2352. const char *
  2353. ath_mac_bb_name(u32 mac_bb_version)
  2354. {
  2355. int i;
  2356. for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
  2357. if (ath_mac_bb_names[i].version == mac_bb_version) {
  2358. return ath_mac_bb_names[i].name;
  2359. }
  2360. }
  2361. return "????";
  2362. }
  2363. /*
  2364. * Return the RF name. "????" is returned if the RF is unknown.
  2365. */
  2366. const char *
  2367. ath_rf_name(u16 rf_version)
  2368. {
  2369. int i;
  2370. for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
  2371. if (ath_rf_names[i].version == rf_version) {
  2372. return ath_rf_names[i].name;
  2373. }
  2374. }
  2375. return "????";
  2376. }
  2377. static int __init ath9k_init(void)
  2378. {
  2379. int error;
  2380. /* Register rate control algorithm */
  2381. error = ath_rate_control_register();
  2382. if (error != 0) {
  2383. printk(KERN_ERR
  2384. "ath9k: Unable to register rate control "
  2385. "algorithm: %d\n",
  2386. error);
  2387. goto err_out;
  2388. }
  2389. error = ath9k_debug_create_root();
  2390. if (error) {
  2391. printk(KERN_ERR
  2392. "ath9k: Unable to create debugfs root: %d\n",
  2393. error);
  2394. goto err_rate_unregister;
  2395. }
  2396. error = ath_pci_init();
  2397. if (error < 0) {
  2398. printk(KERN_ERR
  2399. "ath9k: No PCI devices found, driver not installed.\n");
  2400. error = -ENODEV;
  2401. goto err_remove_root;
  2402. }
  2403. error = ath_ahb_init();
  2404. if (error < 0) {
  2405. error = -ENODEV;
  2406. goto err_pci_exit;
  2407. }
  2408. return 0;
  2409. err_pci_exit:
  2410. ath_pci_exit();
  2411. err_remove_root:
  2412. ath9k_debug_remove_root();
  2413. err_rate_unregister:
  2414. ath_rate_control_unregister();
  2415. err_out:
  2416. return error;
  2417. }
  2418. module_init(ath9k_init);
  2419. static void __exit ath9k_exit(void)
  2420. {
  2421. ath_ahb_exit();
  2422. ath_pci_exit();
  2423. ath9k_debug_remove_root();
  2424. ath_rate_control_unregister();
  2425. printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
  2426. }
  2427. module_exit(ath9k_exit);