iwl3945-base.c 216 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-fh.h"
  47. #include "iwl-3945-fh.h"
  48. #include "iwl-commands.h"
  49. #include "iwl-3945.h"
  50. #include "iwl-helpers.h"
  51. #include "iwl-core.h"
  52. #include "iwl-dev.h"
  53. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  54. struct iwl_tx_queue *txq);
  55. /*
  56. * module name, copyright, version, etc.
  57. */
  58. #define DRV_DESCRIPTION \
  59. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  60. #ifdef CONFIG_IWL3945_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define IWL39_VERSION "1.2.26k" VD VS
  71. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  72. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  73. #define DRV_VERSION IWL39_VERSION
  74. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  75. MODULE_VERSION(DRV_VERSION);
  76. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  77. MODULE_LICENSE("GPL");
  78. /* module parameters */
  79. struct iwl_mod_params iwl3945_mod_params = {
  80. .num_of_queues = IWL39_MAX_NUM_QUEUES,
  81. /* the rest are 0 by default */
  82. };
  83. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  84. * DMA services
  85. *
  86. * Theory of operation
  87. *
  88. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  89. * of buffer descriptors, each of which points to one or more data buffers for
  90. * the device to read from or fill. Driver and device exchange status of each
  91. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  92. * entries in each circular buffer, to protect against confusing empty and full
  93. * queue states.
  94. *
  95. * The device reads or writes the data in the queues via the device's several
  96. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  97. *
  98. * For Tx queue, there are low mark and high mark limits. If, after queuing
  99. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  100. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  101. * Tx queue resumed.
  102. *
  103. * The 3945 operates with six queues: One receive queue, one transmit queue
  104. * (#4) for sending commands to the device firmware, and four transmit queues
  105. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  106. ***************************************************/
  107. /**
  108. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  109. */
  110. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  111. int count, int slots_num, u32 id)
  112. {
  113. q->n_bd = count;
  114. q->n_window = slots_num;
  115. q->id = id;
  116. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  117. * and iwl_queue_dec_wrap are broken. */
  118. BUG_ON(!is_power_of_2(count));
  119. /* slots_num must be power-of-two size, otherwise
  120. * get_cmd_index is broken. */
  121. BUG_ON(!is_power_of_2(slots_num));
  122. q->low_mark = q->n_window / 4;
  123. if (q->low_mark < 4)
  124. q->low_mark = 4;
  125. q->high_mark = q->n_window / 8;
  126. if (q->high_mark < 2)
  127. q->high_mark = 2;
  128. q->write_ptr = q->read_ptr = 0;
  129. return 0;
  130. }
  131. /**
  132. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  133. */
  134. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  135. struct iwl_tx_queue *txq, u32 id)
  136. {
  137. struct pci_dev *dev = priv->pci_dev;
  138. /* Driver private data, only for Tx (not command) queues,
  139. * not shared with device. */
  140. if (id != IWL_CMD_QUEUE_NUM) {
  141. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  142. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  143. if (!txq->txb) {
  144. IWL_ERR(priv, "kmalloc for auxiliary BD "
  145. "structures failed\n");
  146. goto error;
  147. }
  148. } else
  149. txq->txb = NULL;
  150. /* Circular buffer of transmit frame descriptors (TFDs),
  151. * shared with device */
  152. txq->tfds39 = pci_alloc_consistent(dev,
  153. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
  154. &txq->q.dma_addr);
  155. if (!txq->tfds39) {
  156. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
  157. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
  158. goto error;
  159. }
  160. txq->q.id = id;
  161. return 0;
  162. error:
  163. kfree(txq->txb);
  164. txq->txb = NULL;
  165. return -ENOMEM;
  166. }
  167. /**
  168. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  169. */
  170. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  171. struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
  172. {
  173. int len, i;
  174. int rc = 0;
  175. /*
  176. * Alloc buffer array for commands (Tx or other types of commands).
  177. * For the command queue (#4), allocate command space + one big
  178. * command for scan, since scan command is very huge; the system will
  179. * not have two scans at the same time, so only one is needed.
  180. * For data Tx queues (all other queues), no super-size command
  181. * space is needed.
  182. */
  183. len = sizeof(struct iwl_cmd);
  184. for (i = 0; i <= slots_num; i++) {
  185. if (i == slots_num) {
  186. if (txq_id == IWL_CMD_QUEUE_NUM)
  187. len += IWL_MAX_SCAN_SIZE;
  188. else
  189. continue;
  190. }
  191. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  192. if (!txq->cmd[i])
  193. goto err;
  194. }
  195. /* Alloc driver data array and TFD circular buffer */
  196. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  197. if (rc)
  198. goto err;
  199. txq->need_update = 0;
  200. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  201. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  202. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  203. /* Initialize queue high/low-water, head/tail indexes */
  204. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  205. /* Tell device where to find queue, enable DMA channel. */
  206. iwl3945_hw_tx_queue_init(priv, txq);
  207. return 0;
  208. err:
  209. for (i = 0; i < slots_num; i++) {
  210. kfree(txq->cmd[i]);
  211. txq->cmd[i] = NULL;
  212. }
  213. if (txq_id == IWL_CMD_QUEUE_NUM) {
  214. kfree(txq->cmd[slots_num]);
  215. txq->cmd[slots_num] = NULL;
  216. }
  217. return -ENOMEM;
  218. }
  219. /**
  220. * iwl3945_tx_queue_free - Deallocate DMA queue.
  221. * @txq: Transmit queue to deallocate.
  222. *
  223. * Empty queue by removing and destroying all BD's.
  224. * Free all buffers.
  225. * 0-fill, but do not free "txq" descriptor structure.
  226. */
  227. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  228. {
  229. struct iwl_queue *q = &txq->q;
  230. struct pci_dev *dev = priv->pci_dev;
  231. int len, i;
  232. if (q->n_bd == 0)
  233. return;
  234. /* first, empty all BD's */
  235. for (; q->write_ptr != q->read_ptr;
  236. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  237. iwl3945_hw_txq_free_tfd(priv, txq);
  238. len = sizeof(struct iwl_cmd) * q->n_window;
  239. if (q->id == IWL_CMD_QUEUE_NUM)
  240. len += IWL_MAX_SCAN_SIZE;
  241. /* De-alloc array of command/tx buffers */
  242. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  243. kfree(txq->cmd[i]);
  244. /* De-alloc circular buffer of TFDs */
  245. if (txq->q.n_bd)
  246. pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
  247. txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
  248. /* De-alloc array of per-TFD driver data */
  249. kfree(txq->txb);
  250. txq->txb = NULL;
  251. /* 0-fill queue descriptor structure */
  252. memset(txq, 0, sizeof(*txq));
  253. }
  254. /*************** STATION TABLE MANAGEMENT ****
  255. * mac80211 should be examined to determine if sta_info is duplicating
  256. * the functionality provided here
  257. */
  258. /**************************************************************/
  259. #if 0 /* temporary disable till we add real remove station */
  260. /**
  261. * iwl3945_remove_station - Remove driver's knowledge of station.
  262. *
  263. * NOTE: This does not remove station from device's station table.
  264. */
  265. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  266. {
  267. int index = IWL_INVALID_STATION;
  268. int i;
  269. unsigned long flags;
  270. spin_lock_irqsave(&priv->sta_lock, flags);
  271. if (is_ap)
  272. index = IWL_AP_ID;
  273. else if (is_broadcast_ether_addr(addr))
  274. index = priv->hw_params.bcast_sta_id;
  275. else
  276. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  277. if (priv->stations_39[i].used &&
  278. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  279. addr)) {
  280. index = i;
  281. break;
  282. }
  283. if (unlikely(index == IWL_INVALID_STATION))
  284. goto out;
  285. if (priv->stations_39[index].used) {
  286. priv->stations_39[index].used = 0;
  287. priv->num_stations--;
  288. }
  289. BUG_ON(priv->num_stations < 0);
  290. out:
  291. spin_unlock_irqrestore(&priv->sta_lock, flags);
  292. return 0;
  293. }
  294. #endif
  295. /**
  296. * iwl3945_clear_stations_table - Clear the driver's station table
  297. *
  298. * NOTE: This does not clear or otherwise alter the device's station table.
  299. */
  300. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  301. {
  302. unsigned long flags;
  303. spin_lock_irqsave(&priv->sta_lock, flags);
  304. priv->num_stations = 0;
  305. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  306. spin_unlock_irqrestore(&priv->sta_lock, flags);
  307. }
  308. /**
  309. * iwl3945_add_station - Add station to station tables in driver and device
  310. */
  311. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  312. {
  313. int i;
  314. int index = IWL_INVALID_STATION;
  315. struct iwl3945_station_entry *station;
  316. unsigned long flags_spin;
  317. u8 rate;
  318. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  319. if (is_ap)
  320. index = IWL_AP_ID;
  321. else if (is_broadcast_ether_addr(addr))
  322. index = priv->hw_params.bcast_sta_id;
  323. else
  324. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  325. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  326. addr)) {
  327. index = i;
  328. break;
  329. }
  330. if (!priv->stations_39[i].used &&
  331. index == IWL_INVALID_STATION)
  332. index = i;
  333. }
  334. /* These two conditions has the same outcome but keep them separate
  335. since they have different meaning */
  336. if (unlikely(index == IWL_INVALID_STATION)) {
  337. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  338. return index;
  339. }
  340. if (priv->stations_39[index].used &&
  341. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  342. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  343. return index;
  344. }
  345. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  346. station = &priv->stations_39[index];
  347. station->used = 1;
  348. priv->num_stations++;
  349. /* Set up the REPLY_ADD_STA command to send to device */
  350. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  351. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  352. station->sta.mode = 0;
  353. station->sta.sta.sta_id = index;
  354. station->sta.station_flags = 0;
  355. if (priv->band == IEEE80211_BAND_5GHZ)
  356. rate = IWL_RATE_6M_PLCP;
  357. else
  358. rate = IWL_RATE_1M_PLCP;
  359. /* Turn on both antennas for the station... */
  360. station->sta.rate_n_flags =
  361. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  362. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  363. /* Add station to device's station table */
  364. iwl3945_send_add_station(priv, &station->sta, flags);
  365. return index;
  366. }
  367. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  368. #define IWL_CMD(x) case x: return #x
  369. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  370. /**
  371. * iwl3945_enqueue_hcmd - enqueue a uCode command
  372. * @priv: device private data point
  373. * @cmd: a point to the ucode command structure
  374. *
  375. * The function returns < 0 values to indicate the operation is
  376. * failed. On success, it turns the index (> 0) of command in the
  377. * command queue.
  378. */
  379. static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  380. {
  381. struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  382. struct iwl_queue *q = &txq->q;
  383. struct iwl3945_tfd *tfd;
  384. struct iwl_cmd *out_cmd;
  385. u32 idx;
  386. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  387. dma_addr_t phys_addr;
  388. int pad;
  389. int ret, len;
  390. unsigned long flags;
  391. /* If any of the command structures end up being larger than
  392. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  393. * we will need to increase the size of the TFD entries */
  394. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  395. !(cmd->meta.flags & CMD_SIZE_HUGE));
  396. if (iwl_is_rfkill(priv)) {
  397. IWL_DEBUG_INFO("Not sending command - RF KILL");
  398. return -EIO;
  399. }
  400. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  401. IWL_ERR(priv, "No space for Tx\n");
  402. return -ENOSPC;
  403. }
  404. spin_lock_irqsave(&priv->hcmd_lock, flags);
  405. tfd = &txq->tfds39[q->write_ptr];
  406. memset(tfd, 0, sizeof(*tfd));
  407. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  408. out_cmd = txq->cmd[idx];
  409. out_cmd->hdr.cmd = cmd->id;
  410. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  411. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  412. /* At this point, the out_cmd now has all of the incoming cmd
  413. * information */
  414. out_cmd->hdr.flags = 0;
  415. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  416. INDEX_TO_SEQ(q->write_ptr));
  417. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  418. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  419. len = (idx == TFD_CMD_SLOTS) ?
  420. IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
  421. phys_addr = pci_map_single(priv->pci_dev, out_cmd,
  422. len, PCI_DMA_TODEVICE);
  423. pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
  424. pci_unmap_len_set(&out_cmd->meta, len, len);
  425. phys_addr += offsetof(struct iwl_cmd, hdr);
  426. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  427. pad = U32_PAD(cmd->len);
  428. tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad));
  429. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  430. "%d bytes at %d[%d]:%d\n",
  431. get_cmd_string(out_cmd->hdr.cmd),
  432. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  433. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  434. txq->need_update = 1;
  435. /* Increment and update queue's write index */
  436. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  437. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  438. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  439. return ret ? ret : idx;
  440. }
  441. static int iwl3945_send_cmd_async(struct iwl_priv *priv,
  442. struct iwl_host_cmd *cmd)
  443. {
  444. int ret;
  445. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  446. /* An asynchronous command can not expect an SKB to be set. */
  447. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  448. /* An asynchronous command MUST have a callback. */
  449. BUG_ON(!cmd->meta.u.callback);
  450. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  451. return -EBUSY;
  452. ret = iwl3945_enqueue_hcmd(priv, cmd);
  453. if (ret < 0) {
  454. IWL_ERR(priv,
  455. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  456. get_cmd_string(cmd->id), ret);
  457. return ret;
  458. }
  459. return 0;
  460. }
  461. static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
  462. struct iwl_host_cmd *cmd)
  463. {
  464. int cmd_idx;
  465. int ret;
  466. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  467. /* A synchronous command can not have a callback set. */
  468. BUG_ON(cmd->meta.u.callback != NULL);
  469. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  470. IWL_ERR(priv,
  471. "Error sending %s: Already sending a host command\n",
  472. get_cmd_string(cmd->id));
  473. ret = -EBUSY;
  474. goto out;
  475. }
  476. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  477. if (cmd->meta.flags & CMD_WANT_SKB)
  478. cmd->meta.source = &cmd->meta;
  479. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  480. if (cmd_idx < 0) {
  481. ret = cmd_idx;
  482. IWL_ERR(priv,
  483. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  484. get_cmd_string(cmd->id), ret);
  485. goto out;
  486. }
  487. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  488. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  489. HOST_COMPLETE_TIMEOUT);
  490. if (!ret) {
  491. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  492. IWL_ERR(priv, "Error sending %s: time out after %dms\n",
  493. get_cmd_string(cmd->id),
  494. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  495. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  496. ret = -ETIMEDOUT;
  497. goto cancel;
  498. }
  499. }
  500. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  501. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  502. get_cmd_string(cmd->id));
  503. ret = -ECANCELED;
  504. goto fail;
  505. }
  506. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  507. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  508. get_cmd_string(cmd->id));
  509. ret = -EIO;
  510. goto fail;
  511. }
  512. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  513. IWL_ERR(priv, "Error: Response NULL in '%s'\n",
  514. get_cmd_string(cmd->id));
  515. ret = -EIO;
  516. goto cancel;
  517. }
  518. ret = 0;
  519. goto out;
  520. cancel:
  521. if (cmd->meta.flags & CMD_WANT_SKB) {
  522. struct iwl_cmd *qcmd;
  523. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  524. * TX cmd queue. Otherwise in case the cmd comes
  525. * in later, it will possibly set an invalid
  526. * address (cmd->meta.source). */
  527. qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  528. qcmd->meta.flags &= ~CMD_WANT_SKB;
  529. }
  530. fail:
  531. if (cmd->meta.u.skb) {
  532. dev_kfree_skb_any(cmd->meta.u.skb);
  533. cmd->meta.u.skb = NULL;
  534. }
  535. out:
  536. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  537. return ret;
  538. }
  539. int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  540. {
  541. if (cmd->meta.flags & CMD_ASYNC)
  542. return iwl3945_send_cmd_async(priv, cmd);
  543. return iwl3945_send_cmd_sync(priv, cmd);
  544. }
  545. int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
  546. {
  547. struct iwl_host_cmd cmd = {
  548. .id = id,
  549. .len = len,
  550. .data = data,
  551. };
  552. return iwl3945_send_cmd_sync(priv, &cmd);
  553. }
  554. static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
  555. {
  556. struct iwl_host_cmd cmd = {
  557. .id = id,
  558. .len = sizeof(val),
  559. .data = &val,
  560. };
  561. return iwl3945_send_cmd_sync(priv, &cmd);
  562. }
  563. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  564. {
  565. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  566. }
  567. /**
  568. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  569. * @band: 2.4 or 5 GHz band
  570. * @channel: Any channel valid for the requested band
  571. * In addition to setting the staging RXON, priv->band is also set.
  572. *
  573. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  574. * in the staging RXON flag structure based on the band
  575. */
  576. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  577. enum ieee80211_band band,
  578. u16 channel)
  579. {
  580. if (!iwl3945_get_channel_info(priv, band, channel)) {
  581. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  582. channel, band);
  583. return -EINVAL;
  584. }
  585. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  586. (priv->band == band))
  587. return 0;
  588. priv->staging39_rxon.channel = cpu_to_le16(channel);
  589. if (band == IEEE80211_BAND_5GHZ)
  590. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  591. else
  592. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  593. priv->band = band;
  594. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  595. return 0;
  596. }
  597. /**
  598. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  599. *
  600. * NOTE: This is really only useful during development and can eventually
  601. * be #ifdef'd out once the driver is stable and folks aren't actively
  602. * making changes
  603. */
  604. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  605. {
  606. int error = 0;
  607. int counter = 1;
  608. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  609. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  610. error |= le32_to_cpu(rxon->flags &
  611. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  612. RXON_FLG_RADAR_DETECT_MSK));
  613. if (error)
  614. IWL_WARN(priv, "check 24G fields %d | %d\n",
  615. counter++, error);
  616. } else {
  617. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  618. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  619. if (error)
  620. IWL_WARN(priv, "check 52 fields %d | %d\n",
  621. counter++, error);
  622. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  623. if (error)
  624. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  625. counter++, error);
  626. }
  627. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  628. if (error)
  629. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  630. /* make sure basic rates 6Mbps and 1Mbps are supported */
  631. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  632. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  633. if (error)
  634. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  635. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  636. if (error)
  637. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  638. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  639. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  640. if (error)
  641. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  642. counter++, error);
  643. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  644. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  645. if (error)
  646. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  647. counter++, error);
  648. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  649. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  650. if (error)
  651. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  652. counter++, error);
  653. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  654. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  655. RXON_FLG_ANT_A_MSK)) == 0);
  656. if (error)
  657. IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
  658. if (error)
  659. IWL_WARN(priv, "Tuning to channel %d\n",
  660. le16_to_cpu(rxon->channel));
  661. if (error) {
  662. IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
  663. return -1;
  664. }
  665. return 0;
  666. }
  667. /**
  668. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  669. * @priv: staging_rxon is compared to active_rxon
  670. *
  671. * If the RXON structure is changing enough to require a new tune,
  672. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  673. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  674. */
  675. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  676. {
  677. /* These items are only settable from the full RXON command */
  678. if (!(iwl3945_is_associated(priv)) ||
  679. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  680. priv->active39_rxon.bssid_addr) ||
  681. compare_ether_addr(priv->staging39_rxon.node_addr,
  682. priv->active39_rxon.node_addr) ||
  683. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  684. priv->active39_rxon.wlap_bssid_addr) ||
  685. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  686. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  687. (priv->staging39_rxon.air_propagation !=
  688. priv->active39_rxon.air_propagation) ||
  689. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  690. return 1;
  691. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  692. * be updated with the RXON_ASSOC command -- however only some
  693. * flag transitions are allowed using RXON_ASSOC */
  694. /* Check if we are not switching bands */
  695. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  696. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  697. return 1;
  698. /* Check if we are switching association toggle */
  699. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  700. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  701. return 1;
  702. return 0;
  703. }
  704. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  705. {
  706. int rc = 0;
  707. struct iwl_rx_packet *res = NULL;
  708. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  709. struct iwl_host_cmd cmd = {
  710. .id = REPLY_RXON_ASSOC,
  711. .len = sizeof(rxon_assoc),
  712. .meta.flags = CMD_WANT_SKB,
  713. .data = &rxon_assoc,
  714. };
  715. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  716. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  717. if ((rxon1->flags == rxon2->flags) &&
  718. (rxon1->filter_flags == rxon2->filter_flags) &&
  719. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  720. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  721. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  722. return 0;
  723. }
  724. rxon_assoc.flags = priv->staging39_rxon.flags;
  725. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  726. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  727. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  728. rxon_assoc.reserved = 0;
  729. rc = iwl3945_send_cmd_sync(priv, &cmd);
  730. if (rc)
  731. return rc;
  732. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  733. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  734. IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
  735. rc = -EIO;
  736. }
  737. priv->alloc_rxb_skb--;
  738. dev_kfree_skb_any(cmd.meta.u.skb);
  739. return rc;
  740. }
  741. /**
  742. * iwl3945_commit_rxon - commit staging_rxon to hardware
  743. *
  744. * The RXON command in staging_rxon is committed to the hardware and
  745. * the active_rxon structure is updated with the new data. This
  746. * function correctly transitions out of the RXON_ASSOC_MSK state if
  747. * a HW tune is required based on the RXON structure changes.
  748. */
  749. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  750. {
  751. /* cast away the const for active_rxon in this function */
  752. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  753. int rc = 0;
  754. if (!iwl_is_alive(priv))
  755. return -1;
  756. /* always get timestamp with Rx frame */
  757. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  758. /* select antenna */
  759. priv->staging39_rxon.flags &=
  760. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  761. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  762. rc = iwl3945_check_rxon_cmd(priv);
  763. if (rc) {
  764. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  765. return -EINVAL;
  766. }
  767. /* If we don't need to send a full RXON, we can use
  768. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  769. * and other flags for the current radio configuration. */
  770. if (!iwl3945_full_rxon_required(priv)) {
  771. rc = iwl3945_send_rxon_assoc(priv);
  772. if (rc) {
  773. IWL_ERR(priv, "Error setting RXON_ASSOC "
  774. "configuration (%d).\n", rc);
  775. return rc;
  776. }
  777. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  778. return 0;
  779. }
  780. /* If we are currently associated and the new config requires
  781. * an RXON_ASSOC and the new config wants the associated mask enabled,
  782. * we must clear the associated from the active configuration
  783. * before we apply the new config */
  784. if (iwl3945_is_associated(priv) &&
  785. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  786. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  787. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  788. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  789. sizeof(struct iwl3945_rxon_cmd),
  790. &priv->active39_rxon);
  791. /* If the mask clearing failed then we set
  792. * active_rxon back to what it was previously */
  793. if (rc) {
  794. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  795. IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
  796. "configuration (%d).\n", rc);
  797. return rc;
  798. }
  799. }
  800. IWL_DEBUG_INFO("Sending RXON\n"
  801. "* with%s RXON_FILTER_ASSOC_MSK\n"
  802. "* channel = %d\n"
  803. "* bssid = %pM\n",
  804. ((priv->staging39_rxon.filter_flags &
  805. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  806. le16_to_cpu(priv->staging39_rxon.channel),
  807. priv->staging_rxon.bssid_addr);
  808. /* Apply the new configuration */
  809. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  810. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  811. if (rc) {
  812. IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
  813. return rc;
  814. }
  815. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  816. iwl3945_clear_stations_table(priv);
  817. /* If we issue a new RXON command which required a tune then we must
  818. * send a new TXPOWER command or we won't be able to Tx any frames */
  819. rc = iwl3945_hw_reg_send_txpower(priv);
  820. if (rc) {
  821. IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
  822. return rc;
  823. }
  824. /* Add the broadcast address so we can send broadcast frames */
  825. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  826. IWL_INVALID_STATION) {
  827. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  828. return -EIO;
  829. }
  830. /* If we have set the ASSOC_MSK and we are in BSS mode then
  831. * add the IWL_AP_ID to the station rate table */
  832. if (iwl3945_is_associated(priv) &&
  833. (priv->iw_mode == NL80211_IFTYPE_STATION))
  834. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  835. == IWL_INVALID_STATION) {
  836. IWL_ERR(priv, "Error adding AP address for transmit\n");
  837. return -EIO;
  838. }
  839. /* Init the hardware's rate fallback order based on the band */
  840. rc = iwl3945_init_hw_rate_table(priv);
  841. if (rc) {
  842. IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
  843. return -EIO;
  844. }
  845. return 0;
  846. }
  847. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  848. {
  849. struct iwl_bt_cmd bt_cmd = {
  850. .flags = 3,
  851. .lead_time = 0xAA,
  852. .max_kill = 1,
  853. .kill_ack_mask = 0,
  854. .kill_cts_mask = 0,
  855. };
  856. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  857. sizeof(bt_cmd), &bt_cmd);
  858. }
  859. static int iwl3945_send_scan_abort(struct iwl_priv *priv)
  860. {
  861. int rc = 0;
  862. struct iwl_rx_packet *res;
  863. struct iwl_host_cmd cmd = {
  864. .id = REPLY_SCAN_ABORT_CMD,
  865. .meta.flags = CMD_WANT_SKB,
  866. };
  867. /* If there isn't a scan actively going on in the hardware
  868. * then we are in between scan bands and not actually
  869. * actively scanning, so don't send the abort command */
  870. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  871. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  872. return 0;
  873. }
  874. rc = iwl3945_send_cmd_sync(priv, &cmd);
  875. if (rc) {
  876. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  877. return rc;
  878. }
  879. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  880. if (res->u.status != CAN_ABORT_STATUS) {
  881. /* The scan abort will return 1 for success or
  882. * 2 for "failure". A failure condition can be
  883. * due to simply not being in an active scan which
  884. * can occur if we send the scan abort before we
  885. * the microcode has notified us that a scan is
  886. * completed. */
  887. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  888. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  889. clear_bit(STATUS_SCAN_HW, &priv->status);
  890. }
  891. dev_kfree_skb_any(cmd.meta.u.skb);
  892. return rc;
  893. }
  894. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  895. struct iwl_cmd *cmd, struct sk_buff *skb)
  896. {
  897. struct iwl_rx_packet *res = NULL;
  898. if (!skb) {
  899. IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
  900. return 1;
  901. }
  902. res = (struct iwl_rx_packet *)skb->data;
  903. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  904. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  905. res->hdr.flags);
  906. return 1;
  907. }
  908. switch (res->u.add_sta.status) {
  909. case ADD_STA_SUCCESS_MSK:
  910. break;
  911. default:
  912. break;
  913. }
  914. /* We didn't cache the SKB; let the caller free it */
  915. return 1;
  916. }
  917. int iwl3945_send_add_station(struct iwl_priv *priv,
  918. struct iwl3945_addsta_cmd *sta, u8 flags)
  919. {
  920. struct iwl_rx_packet *res = NULL;
  921. int rc = 0;
  922. struct iwl_host_cmd cmd = {
  923. .id = REPLY_ADD_STA,
  924. .len = sizeof(struct iwl3945_addsta_cmd),
  925. .meta.flags = flags,
  926. .data = sta,
  927. };
  928. if (flags & CMD_ASYNC)
  929. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  930. else
  931. cmd.meta.flags |= CMD_WANT_SKB;
  932. rc = iwl3945_send_cmd(priv, &cmd);
  933. if (rc || (flags & CMD_ASYNC))
  934. return rc;
  935. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  936. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  937. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  938. res->hdr.flags);
  939. rc = -EIO;
  940. }
  941. if (rc == 0) {
  942. switch (res->u.add_sta.status) {
  943. case ADD_STA_SUCCESS_MSK:
  944. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  945. break;
  946. default:
  947. rc = -EIO;
  948. IWL_WARN(priv, "REPLY_ADD_STA failed\n");
  949. break;
  950. }
  951. }
  952. priv->alloc_rxb_skb--;
  953. dev_kfree_skb_any(cmd.meta.u.skb);
  954. return rc;
  955. }
  956. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  957. struct ieee80211_key_conf *keyconf,
  958. u8 sta_id)
  959. {
  960. unsigned long flags;
  961. __le16 key_flags = 0;
  962. switch (keyconf->alg) {
  963. case ALG_CCMP:
  964. key_flags |= STA_KEY_FLG_CCMP;
  965. key_flags |= cpu_to_le16(
  966. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  967. key_flags &= ~STA_KEY_FLG_INVALID;
  968. break;
  969. case ALG_TKIP:
  970. case ALG_WEP:
  971. default:
  972. return -EINVAL;
  973. }
  974. spin_lock_irqsave(&priv->sta_lock, flags);
  975. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  976. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  977. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  978. keyconf->keylen);
  979. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  980. keyconf->keylen);
  981. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  982. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  983. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  984. spin_unlock_irqrestore(&priv->sta_lock, flags);
  985. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  986. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  987. return 0;
  988. }
  989. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  990. {
  991. unsigned long flags;
  992. spin_lock_irqsave(&priv->sta_lock, flags);
  993. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  994. memset(&priv->stations_39[sta_id].sta.key, 0,
  995. sizeof(struct iwl4965_keyinfo));
  996. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  997. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  998. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  999. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1000. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1001. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1002. return 0;
  1003. }
  1004. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  1005. {
  1006. struct list_head *element;
  1007. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1008. priv->frames_count);
  1009. while (!list_empty(&priv->free_frames)) {
  1010. element = priv->free_frames.next;
  1011. list_del(element);
  1012. kfree(list_entry(element, struct iwl3945_frame, list));
  1013. priv->frames_count--;
  1014. }
  1015. if (priv->frames_count) {
  1016. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  1017. priv->frames_count);
  1018. priv->frames_count = 0;
  1019. }
  1020. }
  1021. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  1022. {
  1023. struct iwl3945_frame *frame;
  1024. struct list_head *element;
  1025. if (list_empty(&priv->free_frames)) {
  1026. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1027. if (!frame) {
  1028. IWL_ERR(priv, "Could not allocate frame!\n");
  1029. return NULL;
  1030. }
  1031. priv->frames_count++;
  1032. return frame;
  1033. }
  1034. element = priv->free_frames.next;
  1035. list_del(element);
  1036. return list_entry(element, struct iwl3945_frame, list);
  1037. }
  1038. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  1039. {
  1040. memset(frame, 0, sizeof(*frame));
  1041. list_add(&frame->list, &priv->free_frames);
  1042. }
  1043. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  1044. struct ieee80211_hdr *hdr,
  1045. int left)
  1046. {
  1047. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1048. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1049. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1050. return 0;
  1051. if (priv->ibss_beacon->len > left)
  1052. return 0;
  1053. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1054. return priv->ibss_beacon->len;
  1055. }
  1056. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  1057. {
  1058. u8 i;
  1059. int rate_mask;
  1060. /* Set rate mask*/
  1061. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1062. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1063. else
  1064. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1065. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1066. i = iwl3945_rates[i].next_ieee) {
  1067. if (rate_mask & (1 << i))
  1068. return iwl3945_rates[i].plcp;
  1069. }
  1070. /* No valid rate was found. Assign the lowest one */
  1071. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1072. return IWL_RATE_1M_PLCP;
  1073. else
  1074. return IWL_RATE_6M_PLCP;
  1075. }
  1076. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  1077. {
  1078. struct iwl3945_frame *frame;
  1079. unsigned int frame_size;
  1080. int rc;
  1081. u8 rate;
  1082. frame = iwl3945_get_free_frame(priv);
  1083. if (!frame) {
  1084. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  1085. "command.\n");
  1086. return -ENOMEM;
  1087. }
  1088. rate = iwl3945_rate_get_lowest_plcp(priv);
  1089. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1090. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1091. &frame->u.cmd[0]);
  1092. iwl3945_free_frame(priv, frame);
  1093. return rc;
  1094. }
  1095. /******************************************************************************
  1096. *
  1097. * EEPROM related functions
  1098. *
  1099. ******************************************************************************/
  1100. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  1101. {
  1102. memcpy(mac, priv->eeprom39.mac_address, 6);
  1103. }
  1104. /*
  1105. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1106. * embedded controller) as EEPROM reader; each read is a series of pulses
  1107. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1108. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1109. * simply claims ownership, which should be safe when this function is called
  1110. * (i.e. before loading uCode!).
  1111. */
  1112. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  1113. {
  1114. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1115. return 0;
  1116. }
  1117. /**
  1118. * iwl3945_eeprom_init - read EEPROM contents
  1119. *
  1120. * Load the EEPROM contents from adapter into priv->eeprom39
  1121. *
  1122. * NOTE: This routine uses the non-debug IO access functions.
  1123. */
  1124. int iwl3945_eeprom_init(struct iwl_priv *priv)
  1125. {
  1126. u16 *e = (u16 *)&priv->eeprom39;
  1127. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  1128. int sz = sizeof(priv->eeprom39);
  1129. int ret;
  1130. u16 addr;
  1131. /* The EEPROM structure has several padding buffers within it
  1132. * and when adding new EEPROM maps is subject to programmer errors
  1133. * which may be very difficult to identify without explicitly
  1134. * checking the resulting size of the eeprom map. */
  1135. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  1136. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1137. IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1138. return -ENOENT;
  1139. }
  1140. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1141. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1142. if (ret < 0) {
  1143. IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
  1144. return -ENOENT;
  1145. }
  1146. /* eeprom is an array of 16bit values */
  1147. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1148. u32 r;
  1149. _iwl_write32(priv, CSR_EEPROM_REG,
  1150. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1151. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1152. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  1153. CSR_EEPROM_REG_READ_VALID_MSK,
  1154. IWL_EEPROM_ACCESS_TIMEOUT);
  1155. if (ret < 0) {
  1156. IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
  1157. return ret;
  1158. }
  1159. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  1160. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1161. }
  1162. return 0;
  1163. }
  1164. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  1165. {
  1166. if (priv->shared_virt)
  1167. pci_free_consistent(priv->pci_dev,
  1168. sizeof(struct iwl3945_shared),
  1169. priv->shared_virt,
  1170. priv->shared_phys);
  1171. }
  1172. /**
  1173. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1174. *
  1175. * return : set the bit for each supported rate insert in ie
  1176. */
  1177. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1178. u16 basic_rate, int *left)
  1179. {
  1180. u16 ret_rates = 0, bit;
  1181. int i;
  1182. u8 *cnt = ie;
  1183. u8 *rates = ie + 1;
  1184. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1185. if (bit & supported_rate) {
  1186. ret_rates |= bit;
  1187. rates[*cnt] = iwl3945_rates[i].ieee |
  1188. ((bit & basic_rate) ? 0x80 : 0x00);
  1189. (*cnt)++;
  1190. (*left)--;
  1191. if ((*left <= 0) ||
  1192. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1193. break;
  1194. }
  1195. }
  1196. return ret_rates;
  1197. }
  1198. /**
  1199. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1200. */
  1201. static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
  1202. struct ieee80211_mgmt *frame,
  1203. int left)
  1204. {
  1205. int len = 0;
  1206. u8 *pos = NULL;
  1207. u16 active_rates, ret_rates, cck_rates;
  1208. /* Make sure there is enough space for the probe request,
  1209. * two mandatory IEs and the data */
  1210. left -= 24;
  1211. if (left < 0)
  1212. return 0;
  1213. len += 24;
  1214. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1215. memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
  1216. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1217. memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
  1218. frame->seq_ctrl = 0;
  1219. /* fill in our indirect SSID IE */
  1220. /* ...next IE... */
  1221. left -= 2;
  1222. if (left < 0)
  1223. return 0;
  1224. len += 2;
  1225. pos = &(frame->u.probe_req.variable[0]);
  1226. *pos++ = WLAN_EID_SSID;
  1227. *pos++ = 0;
  1228. /* fill in supported rate */
  1229. /* ...next IE... */
  1230. left -= 2;
  1231. if (left < 0)
  1232. return 0;
  1233. /* ... fill it in... */
  1234. *pos++ = WLAN_EID_SUPP_RATES;
  1235. *pos = 0;
  1236. priv->active_rate = priv->rates_mask;
  1237. active_rates = priv->active_rate;
  1238. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1239. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1240. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1241. priv->active_rate_basic, &left);
  1242. active_rates &= ~ret_rates;
  1243. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1244. priv->active_rate_basic, &left);
  1245. active_rates &= ~ret_rates;
  1246. len += 2 + *pos;
  1247. pos += (*pos) + 1;
  1248. if (active_rates == 0)
  1249. goto fill_end;
  1250. /* fill in supported extended rate */
  1251. /* ...next IE... */
  1252. left -= 2;
  1253. if (left < 0)
  1254. return 0;
  1255. /* ... fill it in... */
  1256. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1257. *pos = 0;
  1258. iwl3945_supported_rate_to_ie(pos, active_rates,
  1259. priv->active_rate_basic, &left);
  1260. if (*pos > 0)
  1261. len += 2 + *pos;
  1262. fill_end:
  1263. return (u16)len;
  1264. }
  1265. /*
  1266. * QoS support
  1267. */
  1268. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  1269. struct iwl_qosparam_cmd *qos)
  1270. {
  1271. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1272. sizeof(struct iwl_qosparam_cmd), qos);
  1273. }
  1274. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  1275. {
  1276. unsigned long flags;
  1277. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1278. return;
  1279. spin_lock_irqsave(&priv->lock, flags);
  1280. priv->qos_data.def_qos_parm.qos_flags = 0;
  1281. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1282. !priv->qos_data.qos_cap.q_AP.txop_request)
  1283. priv->qos_data.def_qos_parm.qos_flags |=
  1284. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1285. if (priv->qos_data.qos_active)
  1286. priv->qos_data.def_qos_parm.qos_flags |=
  1287. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1288. spin_unlock_irqrestore(&priv->lock, flags);
  1289. if (force || iwl3945_is_associated(priv)) {
  1290. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1291. priv->qos_data.qos_active);
  1292. iwl3945_send_qos_params_command(priv,
  1293. &(priv->qos_data.def_qos_parm));
  1294. }
  1295. }
  1296. /*
  1297. * Power management (not Tx power!) functions
  1298. */
  1299. #define MSEC_TO_USEC 1024
  1300. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1301. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1302. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1303. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1304. __constant_cpu_to_le32(X1), \
  1305. __constant_cpu_to_le32(X2), \
  1306. __constant_cpu_to_le32(X3), \
  1307. __constant_cpu_to_le32(X4)}
  1308. /* default power management (not Tx power) table values */
  1309. /* for TIM 0-10 */
  1310. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1311. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1312. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1313. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1314. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1315. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1316. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1317. };
  1318. /* for TIM > 10 */
  1319. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1320. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1321. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1322. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1323. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1324. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1325. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1326. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1327. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1328. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1329. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1330. };
  1331. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1332. {
  1333. int rc = 0, i;
  1334. struct iwl3945_power_mgr *pow_data;
  1335. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1336. u16 pci_pm;
  1337. IWL_DEBUG_POWER("Initialize power \n");
  1338. pow_data = &(priv->power_data_39);
  1339. memset(pow_data, 0, sizeof(*pow_data));
  1340. pow_data->active_index = IWL_POWER_RANGE_0;
  1341. pow_data->dtim_val = 0xffff;
  1342. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1343. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1344. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1345. if (rc != 0)
  1346. return 0;
  1347. else {
  1348. struct iwl_powertable_cmd *cmd;
  1349. IWL_DEBUG_POWER("adjust power command flags\n");
  1350. for (i = 0; i < IWL39_POWER_AC; i++) {
  1351. cmd = &pow_data->pwr_range_0[i].cmd;
  1352. if (pci_pm & 0x1)
  1353. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1354. else
  1355. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1356. }
  1357. }
  1358. return rc;
  1359. }
  1360. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1361. struct iwl_powertable_cmd *cmd, u32 mode)
  1362. {
  1363. int rc = 0, i;
  1364. u8 skip;
  1365. u32 max_sleep = 0;
  1366. struct iwl_power_vec_entry *range;
  1367. u8 period = 0;
  1368. struct iwl3945_power_mgr *pow_data;
  1369. if (mode > IWL_POWER_INDEX_5) {
  1370. IWL_DEBUG_POWER("Error invalid power mode \n");
  1371. return -1;
  1372. }
  1373. pow_data = &(priv->power_data_39);
  1374. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1375. range = &pow_data->pwr_range_0[0];
  1376. else
  1377. range = &pow_data->pwr_range_1[1];
  1378. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1379. #ifdef IWL_MAC80211_DISABLE
  1380. if (priv->assoc_network != NULL) {
  1381. unsigned long flags;
  1382. period = priv->assoc_network->tim.tim_period;
  1383. }
  1384. #endif /*IWL_MAC80211_DISABLE */
  1385. skip = range[mode].no_dtim;
  1386. if (period == 0) {
  1387. period = 1;
  1388. skip = 0;
  1389. }
  1390. if (skip == 0) {
  1391. max_sleep = period;
  1392. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1393. } else {
  1394. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1395. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1396. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1397. }
  1398. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1399. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1400. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1401. }
  1402. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1403. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1404. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1405. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1406. le32_to_cpu(cmd->sleep_interval[0]),
  1407. le32_to_cpu(cmd->sleep_interval[1]),
  1408. le32_to_cpu(cmd->sleep_interval[2]),
  1409. le32_to_cpu(cmd->sleep_interval[3]),
  1410. le32_to_cpu(cmd->sleep_interval[4]));
  1411. return rc;
  1412. }
  1413. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1414. {
  1415. u32 uninitialized_var(final_mode);
  1416. int rc;
  1417. struct iwl_powertable_cmd cmd;
  1418. /* If on battery, set to 3,
  1419. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1420. * else user level */
  1421. switch (mode) {
  1422. case IWL39_POWER_BATTERY:
  1423. final_mode = IWL_POWER_INDEX_3;
  1424. break;
  1425. case IWL39_POWER_AC:
  1426. final_mode = IWL_POWER_MODE_CAM;
  1427. break;
  1428. default:
  1429. final_mode = mode;
  1430. break;
  1431. }
  1432. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1433. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1434. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1435. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1436. if (final_mode == IWL_POWER_MODE_CAM)
  1437. clear_bit(STATUS_POWER_PMI, &priv->status);
  1438. else
  1439. set_bit(STATUS_POWER_PMI, &priv->status);
  1440. return rc;
  1441. }
  1442. /**
  1443. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1444. *
  1445. * NOTE: priv->mutex is not required before calling this function
  1446. */
  1447. static int iwl3945_scan_cancel(struct iwl_priv *priv)
  1448. {
  1449. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1450. clear_bit(STATUS_SCANNING, &priv->status);
  1451. return 0;
  1452. }
  1453. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1454. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1455. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1456. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1457. queue_work(priv->workqueue, &priv->abort_scan);
  1458. } else
  1459. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1460. return test_bit(STATUS_SCANNING, &priv->status);
  1461. }
  1462. return 0;
  1463. }
  1464. /**
  1465. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1466. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1467. *
  1468. * NOTE: priv->mutex must be held before calling this function
  1469. */
  1470. static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
  1471. {
  1472. unsigned long now = jiffies;
  1473. int ret;
  1474. ret = iwl3945_scan_cancel(priv);
  1475. if (ret && ms) {
  1476. mutex_unlock(&priv->mutex);
  1477. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1478. test_bit(STATUS_SCANNING, &priv->status))
  1479. msleep(1);
  1480. mutex_lock(&priv->mutex);
  1481. return test_bit(STATUS_SCANNING, &priv->status);
  1482. }
  1483. return ret;
  1484. }
  1485. #define MAX_UCODE_BEACON_INTERVAL 1024
  1486. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1487. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1488. {
  1489. u16 new_val = 0;
  1490. u16 beacon_factor = 0;
  1491. beacon_factor =
  1492. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1493. / MAX_UCODE_BEACON_INTERVAL;
  1494. new_val = beacon_val / beacon_factor;
  1495. return cpu_to_le16(new_val);
  1496. }
  1497. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1498. {
  1499. u64 interval_tm_unit;
  1500. u64 tsf, result;
  1501. unsigned long flags;
  1502. struct ieee80211_conf *conf = NULL;
  1503. u16 beacon_int = 0;
  1504. conf = ieee80211_get_hw_conf(priv->hw);
  1505. spin_lock_irqsave(&priv->lock, flags);
  1506. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1507. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1508. tsf = priv->timestamp;
  1509. beacon_int = priv->beacon_int;
  1510. spin_unlock_irqrestore(&priv->lock, flags);
  1511. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1512. if (beacon_int == 0) {
  1513. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1514. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1515. } else {
  1516. priv->rxon_timing.beacon_interval =
  1517. cpu_to_le16(beacon_int);
  1518. priv->rxon_timing.beacon_interval =
  1519. iwl3945_adjust_beacon_interval(
  1520. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1521. }
  1522. priv->rxon_timing.atim_window = 0;
  1523. } else {
  1524. priv->rxon_timing.beacon_interval =
  1525. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1526. /* TODO: we need to get atim_window from upper stack
  1527. * for now we set to 0 */
  1528. priv->rxon_timing.atim_window = 0;
  1529. }
  1530. interval_tm_unit =
  1531. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1532. result = do_div(tsf, interval_tm_unit);
  1533. priv->rxon_timing.beacon_init_val =
  1534. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1535. IWL_DEBUG_ASSOC
  1536. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1537. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1538. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1539. le16_to_cpu(priv->rxon_timing.atim_window));
  1540. }
  1541. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1542. {
  1543. if (!iwl_is_ready_rf(priv)) {
  1544. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1545. return -EIO;
  1546. }
  1547. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1548. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1549. return -EAGAIN;
  1550. }
  1551. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1552. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1553. "Queuing.\n");
  1554. return -EAGAIN;
  1555. }
  1556. IWL_DEBUG_INFO("Starting scan...\n");
  1557. if (priv->cfg->sku & IWL_SKU_G)
  1558. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1559. if (priv->cfg->sku & IWL_SKU_A)
  1560. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1561. set_bit(STATUS_SCANNING, &priv->status);
  1562. priv->scan_start = jiffies;
  1563. priv->scan_pass_start = priv->scan_start;
  1564. queue_work(priv->workqueue, &priv->request_scan);
  1565. return 0;
  1566. }
  1567. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1568. {
  1569. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1570. if (hw_decrypt)
  1571. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1572. else
  1573. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1574. return 0;
  1575. }
  1576. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1577. enum ieee80211_band band)
  1578. {
  1579. if (band == IEEE80211_BAND_5GHZ) {
  1580. priv->staging39_rxon.flags &=
  1581. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1582. | RXON_FLG_CCK_MSK);
  1583. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1584. } else {
  1585. /* Copied from iwl3945_bg_post_associate() */
  1586. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1587. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1588. else
  1589. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1590. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1591. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1592. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1593. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1594. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1595. }
  1596. }
  1597. /*
  1598. * initialize rxon structure with default values from eeprom
  1599. */
  1600. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1601. int mode)
  1602. {
  1603. const struct iwl_channel_info *ch_info;
  1604. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1605. switch (mode) {
  1606. case NL80211_IFTYPE_AP:
  1607. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1608. break;
  1609. case NL80211_IFTYPE_STATION:
  1610. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1611. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1612. break;
  1613. case NL80211_IFTYPE_ADHOC:
  1614. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1615. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1616. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1617. RXON_FILTER_ACCEPT_GRP_MSK;
  1618. break;
  1619. case NL80211_IFTYPE_MONITOR:
  1620. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1621. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1622. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1623. break;
  1624. default:
  1625. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1626. break;
  1627. }
  1628. #if 0
  1629. /* TODO: Figure out when short_preamble would be set and cache from
  1630. * that */
  1631. if (!hw_to_local(priv->hw)->short_preamble)
  1632. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1633. else
  1634. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1635. #endif
  1636. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1637. le16_to_cpu(priv->active39_rxon.channel));
  1638. if (!ch_info)
  1639. ch_info = &priv->channel_info[0];
  1640. /*
  1641. * in some case A channels are all non IBSS
  1642. * in this case force B/G channel
  1643. */
  1644. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1645. ch_info = &priv->channel_info[0];
  1646. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1647. if (is_channel_a_band(ch_info))
  1648. priv->band = IEEE80211_BAND_5GHZ;
  1649. else
  1650. priv->band = IEEE80211_BAND_2GHZ;
  1651. iwl3945_set_flags_for_phymode(priv, priv->band);
  1652. priv->staging39_rxon.ofdm_basic_rates =
  1653. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1654. priv->staging39_rxon.cck_basic_rates =
  1655. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1656. }
  1657. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1658. {
  1659. if (mode == NL80211_IFTYPE_ADHOC) {
  1660. const struct iwl_channel_info *ch_info;
  1661. ch_info = iwl3945_get_channel_info(priv,
  1662. priv->band,
  1663. le16_to_cpu(priv->staging39_rxon.channel));
  1664. if (!ch_info || !is_channel_ibss(ch_info)) {
  1665. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1666. le16_to_cpu(priv->staging39_rxon.channel));
  1667. return -EINVAL;
  1668. }
  1669. }
  1670. iwl3945_connection_init_rx_config(priv, mode);
  1671. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1672. iwl3945_clear_stations_table(priv);
  1673. /* don't commit rxon if rf-kill is on*/
  1674. if (!iwl_is_ready_rf(priv))
  1675. return -EAGAIN;
  1676. cancel_delayed_work(&priv->scan_check);
  1677. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1678. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1679. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1680. return -EAGAIN;
  1681. }
  1682. iwl3945_commit_rxon(priv);
  1683. return 0;
  1684. }
  1685. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1686. struct ieee80211_tx_info *info,
  1687. struct iwl_cmd *cmd,
  1688. struct sk_buff *skb_frag,
  1689. int last_frag)
  1690. {
  1691. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1692. struct iwl3945_hw_key *keyinfo =
  1693. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1694. switch (keyinfo->alg) {
  1695. case ALG_CCMP:
  1696. tx->sec_ctl = TX_CMD_SEC_CCM;
  1697. memcpy(tx->key, keyinfo->key, keyinfo->keylen);
  1698. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1699. break;
  1700. case ALG_TKIP:
  1701. #if 0
  1702. tx->sec_ctl = TX_CMD_SEC_TKIP;
  1703. if (last_frag)
  1704. memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
  1705. 8);
  1706. else
  1707. memset(tx->tkip_mic.byte, 0, 8);
  1708. #endif
  1709. break;
  1710. case ALG_WEP:
  1711. tx->sec_ctl = TX_CMD_SEC_WEP |
  1712. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1713. if (keyinfo->keylen == 13)
  1714. tx->sec_ctl |= TX_CMD_SEC_KEY128;
  1715. memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
  1716. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1717. "with key %d\n", info->control.hw_key->hw_key_idx);
  1718. break;
  1719. default:
  1720. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1721. break;
  1722. }
  1723. }
  1724. /*
  1725. * handle build REPLY_TX command notification.
  1726. */
  1727. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1728. struct iwl_cmd *cmd,
  1729. struct ieee80211_tx_info *info,
  1730. struct ieee80211_hdr *hdr, u8 std_id)
  1731. {
  1732. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1733. __le32 tx_flags = tx->tx_flags;
  1734. __le16 fc = hdr->frame_control;
  1735. u8 rc_flags = info->control.rates[0].flags;
  1736. tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1737. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1738. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1739. if (ieee80211_is_mgmt(fc))
  1740. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1741. if (ieee80211_is_probe_resp(fc) &&
  1742. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1743. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1744. } else {
  1745. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1746. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1747. }
  1748. tx->sta_id = std_id;
  1749. if (ieee80211_has_morefrags(fc))
  1750. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1751. if (ieee80211_is_data_qos(fc)) {
  1752. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1753. tx->tid_tspec = qc[0] & 0xf;
  1754. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1755. } else {
  1756. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1757. }
  1758. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1759. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1760. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1761. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1762. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1763. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1764. }
  1765. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1766. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1767. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1768. if (ieee80211_is_mgmt(fc)) {
  1769. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1770. tx->timeout.pm_frame_timeout = cpu_to_le16(3);
  1771. else
  1772. tx->timeout.pm_frame_timeout = cpu_to_le16(2);
  1773. } else {
  1774. tx->timeout.pm_frame_timeout = 0;
  1775. #ifdef CONFIG_IWL3945_LEDS
  1776. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1777. #endif
  1778. }
  1779. tx->driver_txop = 0;
  1780. tx->tx_flags = tx_flags;
  1781. tx->next_frame_len = 0;
  1782. }
  1783. /**
  1784. * iwl3945_get_sta_id - Find station's index within station table
  1785. */
  1786. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1787. {
  1788. int sta_id;
  1789. u16 fc = le16_to_cpu(hdr->frame_control);
  1790. /* If this frame is broadcast or management, use broadcast station id */
  1791. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1792. is_multicast_ether_addr(hdr->addr1))
  1793. return priv->hw_params.bcast_sta_id;
  1794. switch (priv->iw_mode) {
  1795. /* If we are a client station in a BSS network, use the special
  1796. * AP station entry (that's the only station we communicate with) */
  1797. case NL80211_IFTYPE_STATION:
  1798. return IWL_AP_ID;
  1799. /* If we are an AP, then find the station, or use BCAST */
  1800. case NL80211_IFTYPE_AP:
  1801. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1802. if (sta_id != IWL_INVALID_STATION)
  1803. return sta_id;
  1804. return priv->hw_params.bcast_sta_id;
  1805. /* If this frame is going out to an IBSS network, find the station,
  1806. * or create a new station table entry */
  1807. case NL80211_IFTYPE_ADHOC: {
  1808. /* Create new station table entry */
  1809. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1810. if (sta_id != IWL_INVALID_STATION)
  1811. return sta_id;
  1812. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1813. if (sta_id != IWL_INVALID_STATION)
  1814. return sta_id;
  1815. IWL_DEBUG_DROP("Station %pM not in station map. "
  1816. "Defaulting to broadcast...\n",
  1817. hdr->addr1);
  1818. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1819. return priv->hw_params.bcast_sta_id;
  1820. }
  1821. /* If we are in monitor mode, use BCAST. This is required for
  1822. * packet injection. */
  1823. case NL80211_IFTYPE_MONITOR:
  1824. return priv->hw_params.bcast_sta_id;
  1825. default:
  1826. IWL_WARN(priv, "Unknown mode of operation: %d\n",
  1827. priv->iw_mode);
  1828. return priv->hw_params.bcast_sta_id;
  1829. }
  1830. }
  1831. /*
  1832. * start REPLY_TX command process
  1833. */
  1834. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1835. {
  1836. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1837. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1838. struct iwl3945_tfd *tfd;
  1839. struct iwl3945_tx_cmd *tx;
  1840. struct iwl_tx_queue *txq = NULL;
  1841. struct iwl_queue *q = NULL;
  1842. struct iwl_cmd *out_cmd = NULL;
  1843. dma_addr_t phys_addr;
  1844. dma_addr_t txcmd_phys;
  1845. int txq_id = skb_get_queue_mapping(skb);
  1846. u16 len, idx, len_org, hdr_len;
  1847. u8 id;
  1848. u8 unicast;
  1849. u8 sta_id;
  1850. u8 tid = 0;
  1851. u16 seq_number = 0;
  1852. __le16 fc;
  1853. u8 wait_write_ptr = 0;
  1854. u8 *qc = NULL;
  1855. unsigned long flags;
  1856. int rc;
  1857. spin_lock_irqsave(&priv->lock, flags);
  1858. if (iwl_is_rfkill(priv)) {
  1859. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1860. goto drop_unlock;
  1861. }
  1862. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  1863. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  1864. goto drop_unlock;
  1865. }
  1866. unicast = !is_multicast_ether_addr(hdr->addr1);
  1867. id = 0;
  1868. fc = hdr->frame_control;
  1869. #ifdef CONFIG_IWL3945_DEBUG
  1870. if (ieee80211_is_auth(fc))
  1871. IWL_DEBUG_TX("Sending AUTH frame\n");
  1872. else if (ieee80211_is_assoc_req(fc))
  1873. IWL_DEBUG_TX("Sending ASSOC frame\n");
  1874. else if (ieee80211_is_reassoc_req(fc))
  1875. IWL_DEBUG_TX("Sending REASSOC frame\n");
  1876. #endif
  1877. /* drop all data frame if we are not associated */
  1878. if (ieee80211_is_data(fc) &&
  1879. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  1880. (!iwl3945_is_associated(priv) ||
  1881. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  1882. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  1883. goto drop_unlock;
  1884. }
  1885. spin_unlock_irqrestore(&priv->lock, flags);
  1886. hdr_len = ieee80211_hdrlen(fc);
  1887. /* Find (or create) index into station table for destination station */
  1888. sta_id = iwl3945_get_sta_id(priv, hdr);
  1889. if (sta_id == IWL_INVALID_STATION) {
  1890. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  1891. hdr->addr1);
  1892. goto drop;
  1893. }
  1894. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  1895. if (ieee80211_is_data_qos(fc)) {
  1896. qc = ieee80211_get_qos_ctl(hdr);
  1897. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1898. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  1899. IEEE80211_SCTL_SEQ;
  1900. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  1901. (hdr->seq_ctrl &
  1902. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  1903. seq_number += 0x10;
  1904. }
  1905. /* Descriptor for chosen Tx queue */
  1906. txq = &priv->txq[txq_id];
  1907. q = &txq->q;
  1908. spin_lock_irqsave(&priv->lock, flags);
  1909. /* Set up first empty TFD within this queue's circular TFD buffer */
  1910. tfd = &txq->tfds39[q->write_ptr];
  1911. memset(tfd, 0, sizeof(*tfd));
  1912. idx = get_cmd_index(q, q->write_ptr, 0);
  1913. /* Set up driver data for this TFD */
  1914. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  1915. txq->txb[q->write_ptr].skb[0] = skb;
  1916. /* Init first empty entry in queue's array of Tx/cmd buffers */
  1917. out_cmd = txq->cmd[idx];
  1918. tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  1919. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  1920. memset(tx, 0, sizeof(*tx));
  1921. /*
  1922. * Set up the Tx-command (not MAC!) header.
  1923. * Store the chosen Tx queue and TFD index within the sequence field;
  1924. * after Tx, uCode's Tx response will return this value so driver can
  1925. * locate the frame within the tx queue and do post-tx processing.
  1926. */
  1927. out_cmd->hdr.cmd = REPLY_TX;
  1928. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  1929. INDEX_TO_SEQ(q->write_ptr)));
  1930. /* Copy MAC header from skb into command buffer */
  1931. memcpy(tx->hdr, hdr, hdr_len);
  1932. /*
  1933. * Use the first empty entry in this queue's command buffer array
  1934. * to contain the Tx command and MAC header concatenated together
  1935. * (payload data will be in another buffer).
  1936. * Size of this varies, due to varying MAC header length.
  1937. * If end is not dword aligned, we'll have 2 extra bytes at the end
  1938. * of the MAC header (device reads on dword boundaries).
  1939. * We'll tell device about this padding later.
  1940. */
  1941. len = sizeof(struct iwl3945_tx_cmd) +
  1942. sizeof(struct iwl_cmd_header) + hdr_len;
  1943. len_org = len;
  1944. len = (len + 3) & ~3;
  1945. if (len_org != len)
  1946. len_org = 1;
  1947. else
  1948. len_org = 0;
  1949. /* Physical address of this Tx command's header (not MAC header!),
  1950. * within command buffer array. */
  1951. txcmd_phys = pci_map_single(priv->pci_dev,
  1952. out_cmd, sizeof(struct iwl_cmd),
  1953. PCI_DMA_TODEVICE);
  1954. pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
  1955. pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
  1956. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1957. * first entry */
  1958. txcmd_phys += offsetof(struct iwl_cmd, hdr);
  1959. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1960. * first entry */
  1961. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  1962. if (info->control.hw_key)
  1963. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  1964. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  1965. * if any (802.11 null frames have no payload). */
  1966. len = skb->len - hdr_len;
  1967. if (len) {
  1968. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  1969. len, PCI_DMA_TODEVICE);
  1970. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  1971. }
  1972. if (!len)
  1973. /* If there is no payload, then we use only one Tx buffer */
  1974. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1));
  1975. else
  1976. /* Else use 2 buffers.
  1977. * Tell 3945 about any padding after MAC header */
  1978. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) |
  1979. TFD_CTL_PAD_SET(U32_PAD(len)));
  1980. /* Total # bytes to be transmitted */
  1981. len = (u16)skb->len;
  1982. tx->len = cpu_to_le16(len);
  1983. /* TODO need this for burst mode later on */
  1984. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  1985. /* set is_hcca to 0; it probably will never be implemented */
  1986. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  1987. tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  1988. tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  1989. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  1990. txq->need_update = 1;
  1991. if (qc)
  1992. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  1993. } else {
  1994. wait_write_ptr = 1;
  1995. txq->need_update = 0;
  1996. }
  1997. iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
  1998. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
  1999. ieee80211_hdrlen(fc));
  2000. /* Tell device the write index *just past* this latest filled TFD */
  2001. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2002. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2003. spin_unlock_irqrestore(&priv->lock, flags);
  2004. if (rc)
  2005. return rc;
  2006. if ((iwl_queue_space(q) < q->high_mark)
  2007. && priv->mac80211_registered) {
  2008. if (wait_write_ptr) {
  2009. spin_lock_irqsave(&priv->lock, flags);
  2010. txq->need_update = 1;
  2011. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2012. spin_unlock_irqrestore(&priv->lock, flags);
  2013. }
  2014. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2015. }
  2016. return 0;
  2017. drop_unlock:
  2018. spin_unlock_irqrestore(&priv->lock, flags);
  2019. drop:
  2020. return -1;
  2021. }
  2022. static void iwl3945_set_rate(struct iwl_priv *priv)
  2023. {
  2024. const struct ieee80211_supported_band *sband = NULL;
  2025. struct ieee80211_rate *rate;
  2026. int i;
  2027. sband = iwl_get_hw_mode(priv, priv->band);
  2028. if (!sband) {
  2029. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  2030. return;
  2031. }
  2032. priv->active_rate = 0;
  2033. priv->active_rate_basic = 0;
  2034. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2035. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2036. for (i = 0; i < sband->n_bitrates; i++) {
  2037. rate = &sband->bitrates[i];
  2038. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2039. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2040. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2041. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2042. priv->active_rate |= (1 << rate->hw_value);
  2043. }
  2044. }
  2045. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2046. priv->active_rate, priv->active_rate_basic);
  2047. /*
  2048. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2049. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2050. * OFDM
  2051. */
  2052. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2053. priv->staging39_rxon.cck_basic_rates =
  2054. ((priv->active_rate_basic &
  2055. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2056. else
  2057. priv->staging39_rxon.cck_basic_rates =
  2058. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2059. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2060. priv->staging39_rxon.ofdm_basic_rates =
  2061. ((priv->active_rate_basic &
  2062. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2063. IWL_FIRST_OFDM_RATE) & 0xFF;
  2064. else
  2065. priv->staging39_rxon.ofdm_basic_rates =
  2066. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2067. }
  2068. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  2069. {
  2070. unsigned long flags;
  2071. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2072. return;
  2073. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2074. disable_radio ? "OFF" : "ON");
  2075. if (disable_radio) {
  2076. iwl3945_scan_cancel(priv);
  2077. /* FIXME: This is a workaround for AP */
  2078. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2079. spin_lock_irqsave(&priv->lock, flags);
  2080. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2081. CSR_UCODE_SW_BIT_RFKILL);
  2082. spin_unlock_irqrestore(&priv->lock, flags);
  2083. iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2084. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2085. }
  2086. return;
  2087. }
  2088. spin_lock_irqsave(&priv->lock, flags);
  2089. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2090. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2091. spin_unlock_irqrestore(&priv->lock, flags);
  2092. /* wake up ucode */
  2093. msleep(10);
  2094. spin_lock_irqsave(&priv->lock, flags);
  2095. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2096. if (!iwl_grab_nic_access(priv))
  2097. iwl_release_nic_access(priv);
  2098. spin_unlock_irqrestore(&priv->lock, flags);
  2099. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2100. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2101. "disabled by HW switch\n");
  2102. return;
  2103. }
  2104. if (priv->is_open)
  2105. queue_work(priv->workqueue, &priv->restart);
  2106. return;
  2107. }
  2108. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  2109. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2110. {
  2111. u16 fc =
  2112. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2113. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2114. return;
  2115. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2116. return;
  2117. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2118. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2119. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2120. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2121. RX_RES_STATUS_BAD_ICV_MIC)
  2122. stats->flag |= RX_FLAG_MMIC_ERROR;
  2123. case RX_RES_STATUS_SEC_TYPE_WEP:
  2124. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2125. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2126. RX_RES_STATUS_DECRYPT_OK) {
  2127. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2128. stats->flag |= RX_FLAG_DECRYPTED;
  2129. }
  2130. break;
  2131. default:
  2132. break;
  2133. }
  2134. }
  2135. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2136. #include "iwl-spectrum.h"
  2137. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2138. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2139. #define TIME_UNIT 1024
  2140. /*
  2141. * extended beacon time format
  2142. * time in usec will be changed into a 32-bit value in 8:24 format
  2143. * the high 1 byte is the beacon counts
  2144. * the lower 3 bytes is the time in usec within one beacon interval
  2145. */
  2146. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2147. {
  2148. u32 quot;
  2149. u32 rem;
  2150. u32 interval = beacon_interval * 1024;
  2151. if (!interval || !usec)
  2152. return 0;
  2153. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2154. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2155. return (quot << 24) + rem;
  2156. }
  2157. /* base is usually what we get from ucode with each received frame,
  2158. * the same as HW timer counter counting down
  2159. */
  2160. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2161. {
  2162. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2163. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2164. u32 interval = beacon_interval * TIME_UNIT;
  2165. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2166. (addon & BEACON_TIME_MASK_HIGH);
  2167. if (base_low > addon_low)
  2168. res += base_low - addon_low;
  2169. else if (base_low < addon_low) {
  2170. res += interval + base_low - addon_low;
  2171. res += (1 << 24);
  2172. } else
  2173. res += (1 << 24);
  2174. return cpu_to_le32(res);
  2175. }
  2176. static int iwl3945_get_measurement(struct iwl_priv *priv,
  2177. struct ieee80211_measurement_params *params,
  2178. u8 type)
  2179. {
  2180. struct iwl_spectrum_cmd spectrum;
  2181. struct iwl_rx_packet *res;
  2182. struct iwl_host_cmd cmd = {
  2183. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2184. .data = (void *)&spectrum,
  2185. .meta.flags = CMD_WANT_SKB,
  2186. };
  2187. u32 add_time = le64_to_cpu(params->start_time);
  2188. int rc;
  2189. int spectrum_resp_status;
  2190. int duration = le16_to_cpu(params->duration);
  2191. if (iwl3945_is_associated(priv))
  2192. add_time =
  2193. iwl3945_usecs_to_beacons(
  2194. le64_to_cpu(params->start_time) - priv->last_tsf,
  2195. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2196. memset(&spectrum, 0, sizeof(spectrum));
  2197. spectrum.channel_count = cpu_to_le16(1);
  2198. spectrum.flags =
  2199. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2200. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2201. cmd.len = sizeof(spectrum);
  2202. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2203. if (iwl3945_is_associated(priv))
  2204. spectrum.start_time =
  2205. iwl3945_add_beacon_time(priv->last_beacon_time,
  2206. add_time,
  2207. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2208. else
  2209. spectrum.start_time = 0;
  2210. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2211. spectrum.channels[0].channel = params->channel;
  2212. spectrum.channels[0].type = type;
  2213. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2214. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2215. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2216. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2217. if (rc)
  2218. return rc;
  2219. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2220. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2221. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  2222. rc = -EIO;
  2223. }
  2224. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2225. switch (spectrum_resp_status) {
  2226. case 0: /* Command will be handled */
  2227. if (res->u.spectrum.id != 0xff) {
  2228. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2229. res->u.spectrum.id);
  2230. priv->measurement_status &= ~MEASUREMENT_READY;
  2231. }
  2232. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2233. rc = 0;
  2234. break;
  2235. case 1: /* Command will not be handled */
  2236. rc = -EAGAIN;
  2237. break;
  2238. }
  2239. dev_kfree_skb_any(cmd.meta.u.skb);
  2240. return rc;
  2241. }
  2242. #endif
  2243. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  2244. struct iwl_rx_mem_buffer *rxb)
  2245. {
  2246. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2247. struct iwl_alive_resp *palive;
  2248. struct delayed_work *pwork;
  2249. palive = &pkt->u.alive_frame;
  2250. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2251. "0x%01X 0x%01X\n",
  2252. palive->is_valid, palive->ver_type,
  2253. palive->ver_subtype);
  2254. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2255. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2256. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2257. sizeof(struct iwl_alive_resp));
  2258. pwork = &priv->init_alive_start;
  2259. } else {
  2260. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2261. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2262. sizeof(struct iwl_alive_resp));
  2263. pwork = &priv->alive_start;
  2264. iwl3945_disable_events(priv);
  2265. }
  2266. /* We delay the ALIVE response by 5ms to
  2267. * give the HW RF Kill time to activate... */
  2268. if (palive->is_valid == UCODE_VALID_OK)
  2269. queue_delayed_work(priv->workqueue, pwork,
  2270. msecs_to_jiffies(5));
  2271. else
  2272. IWL_WARN(priv, "uCode did not respond OK.\n");
  2273. }
  2274. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  2275. struct iwl_rx_mem_buffer *rxb)
  2276. {
  2277. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2278. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2279. return;
  2280. }
  2281. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  2282. struct iwl_rx_mem_buffer *rxb)
  2283. {
  2284. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2285. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  2286. "seq 0x%04X ser 0x%08X\n",
  2287. le32_to_cpu(pkt->u.err_resp.error_type),
  2288. get_cmd_string(pkt->u.err_resp.cmd_id),
  2289. pkt->u.err_resp.cmd_id,
  2290. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2291. le32_to_cpu(pkt->u.err_resp.error_info));
  2292. }
  2293. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2294. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2295. {
  2296. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2297. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  2298. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2299. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2300. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2301. rxon->channel = csa->channel;
  2302. priv->staging39_rxon.channel = csa->channel;
  2303. }
  2304. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  2305. struct iwl_rx_mem_buffer *rxb)
  2306. {
  2307. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2308. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2309. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2310. if (!report->state) {
  2311. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2312. "Spectrum Measure Notification: Start\n");
  2313. return;
  2314. }
  2315. memcpy(&priv->measure_report, report, sizeof(*report));
  2316. priv->measurement_status |= MEASUREMENT_READY;
  2317. #endif
  2318. }
  2319. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  2320. struct iwl_rx_mem_buffer *rxb)
  2321. {
  2322. #ifdef CONFIG_IWL3945_DEBUG
  2323. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2324. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2325. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2326. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2327. #endif
  2328. }
  2329. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  2330. struct iwl_rx_mem_buffer *rxb)
  2331. {
  2332. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2333. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2334. "notification for %s:\n",
  2335. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2336. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2337. le32_to_cpu(pkt->len));
  2338. }
  2339. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2340. {
  2341. struct iwl_priv *priv =
  2342. container_of(work, struct iwl_priv, beacon_update);
  2343. struct sk_buff *beacon;
  2344. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2345. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2346. if (!beacon) {
  2347. IWL_ERR(priv, "update beacon failed\n");
  2348. return;
  2349. }
  2350. mutex_lock(&priv->mutex);
  2351. /* new beacon skb is allocated every time; dispose previous.*/
  2352. if (priv->ibss_beacon)
  2353. dev_kfree_skb(priv->ibss_beacon);
  2354. priv->ibss_beacon = beacon;
  2355. mutex_unlock(&priv->mutex);
  2356. iwl3945_send_beacon_cmd(priv);
  2357. }
  2358. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  2359. struct iwl_rx_mem_buffer *rxb)
  2360. {
  2361. #ifdef CONFIG_IWL3945_DEBUG
  2362. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2363. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2364. u8 rate = beacon->beacon_notify_hdr.rate;
  2365. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2366. "tsf %d %d rate %d\n",
  2367. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2368. beacon->beacon_notify_hdr.failure_frame,
  2369. le32_to_cpu(beacon->ibss_mgr_status),
  2370. le32_to_cpu(beacon->high_tsf),
  2371. le32_to_cpu(beacon->low_tsf), rate);
  2372. #endif
  2373. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2374. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2375. queue_work(priv->workqueue, &priv->beacon_update);
  2376. }
  2377. /* Service response to REPLY_SCAN_CMD (0x80) */
  2378. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  2379. struct iwl_rx_mem_buffer *rxb)
  2380. {
  2381. #ifdef CONFIG_IWL3945_DEBUG
  2382. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2383. struct iwl_scanreq_notification *notif =
  2384. (struct iwl_scanreq_notification *)pkt->u.raw;
  2385. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2386. #endif
  2387. }
  2388. /* Service SCAN_START_NOTIFICATION (0x82) */
  2389. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2390. struct iwl_rx_mem_buffer *rxb)
  2391. {
  2392. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2393. struct iwl_scanstart_notification *notif =
  2394. (struct iwl_scanstart_notification *)pkt->u.raw;
  2395. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2396. IWL_DEBUG_SCAN("Scan start: "
  2397. "%d [802.11%s] "
  2398. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2399. notif->channel,
  2400. notif->band ? "bg" : "a",
  2401. notif->tsf_high,
  2402. notif->tsf_low, notif->status, notif->beacon_timer);
  2403. }
  2404. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2405. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2406. struct iwl_rx_mem_buffer *rxb)
  2407. {
  2408. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2409. struct iwl_scanresults_notification *notif =
  2410. (struct iwl_scanresults_notification *)pkt->u.raw;
  2411. IWL_DEBUG_SCAN("Scan ch.res: "
  2412. "%d [802.11%s] "
  2413. "(TSF: 0x%08X:%08X) - %d "
  2414. "elapsed=%lu usec (%dms since last)\n",
  2415. notif->channel,
  2416. notif->band ? "bg" : "a",
  2417. le32_to_cpu(notif->tsf_high),
  2418. le32_to_cpu(notif->tsf_low),
  2419. le32_to_cpu(notif->statistics[0]),
  2420. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2421. jiffies_to_msecs(elapsed_jiffies
  2422. (priv->last_scan_jiffies, jiffies)));
  2423. priv->last_scan_jiffies = jiffies;
  2424. priv->next_scan_jiffies = 0;
  2425. }
  2426. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2427. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2428. struct iwl_rx_mem_buffer *rxb)
  2429. {
  2430. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2431. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2432. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2433. scan_notif->scanned_channels,
  2434. scan_notif->tsf_low,
  2435. scan_notif->tsf_high, scan_notif->status);
  2436. /* The HW is no longer scanning */
  2437. clear_bit(STATUS_SCAN_HW, &priv->status);
  2438. /* The scan completion notification came in, so kill that timer... */
  2439. cancel_delayed_work(&priv->scan_check);
  2440. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2441. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2442. "2.4" : "5.2",
  2443. jiffies_to_msecs(elapsed_jiffies
  2444. (priv->scan_pass_start, jiffies)));
  2445. /* Remove this scanned band from the list of pending
  2446. * bands to scan, band G precedes A in order of scanning
  2447. * as seen in iwl3945_bg_request_scan */
  2448. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2449. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2450. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2451. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2452. /* If a request to abort was given, or the scan did not succeed
  2453. * then we reset the scan state machine and terminate,
  2454. * re-queuing another scan if one has been requested */
  2455. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2456. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2457. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2458. } else {
  2459. /* If there are more bands on this scan pass reschedule */
  2460. if (priv->scan_bands > 0)
  2461. goto reschedule;
  2462. }
  2463. priv->last_scan_jiffies = jiffies;
  2464. priv->next_scan_jiffies = 0;
  2465. IWL_DEBUG_INFO("Setting scan to off\n");
  2466. clear_bit(STATUS_SCANNING, &priv->status);
  2467. IWL_DEBUG_INFO("Scan took %dms\n",
  2468. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2469. queue_work(priv->workqueue, &priv->scan_completed);
  2470. return;
  2471. reschedule:
  2472. priv->scan_pass_start = jiffies;
  2473. queue_work(priv->workqueue, &priv->request_scan);
  2474. }
  2475. /* Handle notification from uCode that card's power state is changing
  2476. * due to software, hardware, or critical temperature RFKILL */
  2477. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2478. struct iwl_rx_mem_buffer *rxb)
  2479. {
  2480. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2481. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2482. unsigned long status = priv->status;
  2483. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2484. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2485. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2486. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2487. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2488. if (flags & HW_CARD_DISABLED)
  2489. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2490. else
  2491. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2492. if (flags & SW_CARD_DISABLED)
  2493. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2494. else
  2495. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2496. iwl3945_scan_cancel(priv);
  2497. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2498. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2499. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2500. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2501. queue_work(priv->workqueue, &priv->rf_kill);
  2502. else
  2503. wake_up_interruptible(&priv->wait_command_queue);
  2504. }
  2505. /**
  2506. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2507. *
  2508. * Setup the RX handlers for each of the reply types sent from the uCode
  2509. * to the host.
  2510. *
  2511. * This function chains into the hardware specific files for them to setup
  2512. * any hardware specific handlers as well.
  2513. */
  2514. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2515. {
  2516. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2517. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2518. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2519. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2520. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2521. iwl3945_rx_spectrum_measure_notif;
  2522. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2523. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2524. iwl3945_rx_pm_debug_statistics_notif;
  2525. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2526. /*
  2527. * The same handler is used for both the REPLY to a discrete
  2528. * statistics request from the host as well as for the periodic
  2529. * statistics notifications (after received beacons) from the uCode.
  2530. */
  2531. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2532. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2533. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2534. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2535. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2536. iwl3945_rx_scan_results_notif;
  2537. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2538. iwl3945_rx_scan_complete_notif;
  2539. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2540. /* Set up hardware specific Rx handlers */
  2541. iwl3945_hw_rx_handler_setup(priv);
  2542. }
  2543. /**
  2544. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2545. * When FW advances 'R' index, all entries between old and new 'R' index
  2546. * need to be reclaimed.
  2547. */
  2548. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2549. int txq_id, int index)
  2550. {
  2551. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2552. struct iwl_queue *q = &txq->q;
  2553. int nfreed = 0;
  2554. if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
  2555. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  2556. "is out of range [0-%d] %d %d.\n", txq_id,
  2557. index, q->n_bd, q->write_ptr, q->read_ptr);
  2558. return;
  2559. }
  2560. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2561. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2562. if (nfreed > 1) {
  2563. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
  2564. q->write_ptr, q->read_ptr);
  2565. queue_work(priv->workqueue, &priv->restart);
  2566. break;
  2567. }
  2568. nfreed++;
  2569. }
  2570. }
  2571. /**
  2572. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2573. * @rxb: Rx buffer to reclaim
  2574. *
  2575. * If an Rx buffer has an async callback associated with it the callback
  2576. * will be executed. The attached skb (if present) will only be freed
  2577. * if the callback returns 1
  2578. */
  2579. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2580. struct iwl_rx_mem_buffer *rxb)
  2581. {
  2582. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2583. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2584. int txq_id = SEQ_TO_QUEUE(sequence);
  2585. int index = SEQ_TO_INDEX(sequence);
  2586. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2587. int cmd_index;
  2588. struct iwl_cmd *cmd;
  2589. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2590. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2591. cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2592. /* Input error checking is done when commands are added to queue. */
  2593. if (cmd->meta.flags & CMD_WANT_SKB) {
  2594. cmd->meta.source->u.skb = rxb->skb;
  2595. rxb->skb = NULL;
  2596. } else if (cmd->meta.u.callback &&
  2597. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2598. rxb->skb = NULL;
  2599. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2600. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2601. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2602. wake_up_interruptible(&priv->wait_command_queue);
  2603. }
  2604. }
  2605. /************************** RX-FUNCTIONS ****************************/
  2606. /*
  2607. * Rx theory of operation
  2608. *
  2609. * The host allocates 32 DMA target addresses and passes the host address
  2610. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2611. * 0 to 31
  2612. *
  2613. * Rx Queue Indexes
  2614. * The host/firmware share two index registers for managing the Rx buffers.
  2615. *
  2616. * The READ index maps to the first position that the firmware may be writing
  2617. * to -- the driver can read up to (but not including) this position and get
  2618. * good data.
  2619. * The READ index is managed by the firmware once the card is enabled.
  2620. *
  2621. * The WRITE index maps to the last position the driver has read from -- the
  2622. * position preceding WRITE is the last slot the firmware can place a packet.
  2623. *
  2624. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2625. * WRITE = READ.
  2626. *
  2627. * During initialization, the host sets up the READ queue position to the first
  2628. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2629. *
  2630. * When the firmware places a packet in a buffer, it will advance the READ index
  2631. * and fire the RX interrupt. The driver can then query the READ index and
  2632. * process as many packets as possible, moving the WRITE index forward as it
  2633. * resets the Rx queue buffers with new memory.
  2634. *
  2635. * The management in the driver is as follows:
  2636. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2637. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2638. * to replenish the iwl->rxq->rx_free.
  2639. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2640. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2641. * 'processed' and 'read' driver indexes as well)
  2642. * + A received packet is processed and handed to the kernel network stack,
  2643. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2644. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2645. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2646. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2647. * were enough free buffers and RX_STALLED is set it is cleared.
  2648. *
  2649. *
  2650. * Driver sequence:
  2651. *
  2652. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2653. * iwl3945_rx_queue_restock
  2654. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2655. * queue, updates firmware pointers, and updates
  2656. * the WRITE index. If insufficient rx_free buffers
  2657. * are available, schedules iwl3945_rx_replenish
  2658. *
  2659. * -- enable interrupts --
  2660. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2661. * READ INDEX, detaching the SKB from the pool.
  2662. * Moves the packet buffer from queue to rx_used.
  2663. * Calls iwl3945_rx_queue_restock to refill any empty
  2664. * slots.
  2665. * ...
  2666. *
  2667. */
  2668. /**
  2669. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2670. */
  2671. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2672. dma_addr_t dma_addr)
  2673. {
  2674. return cpu_to_le32((u32)dma_addr);
  2675. }
  2676. /**
  2677. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2678. *
  2679. * If there are slots in the RX queue that need to be restocked,
  2680. * and we have free pre-allocated buffers, fill the ranks as much
  2681. * as we can, pulling from rx_free.
  2682. *
  2683. * This moves the 'write' index forward to catch up with 'processed', and
  2684. * also updates the memory address in the firmware to reference the new
  2685. * target buffer.
  2686. */
  2687. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2688. {
  2689. struct iwl_rx_queue *rxq = &priv->rxq;
  2690. struct list_head *element;
  2691. struct iwl_rx_mem_buffer *rxb;
  2692. unsigned long flags;
  2693. int write, rc;
  2694. spin_lock_irqsave(&rxq->lock, flags);
  2695. write = rxq->write & ~0x7;
  2696. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2697. /* Get next free Rx buffer, remove from free list */
  2698. element = rxq->rx_free.next;
  2699. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2700. list_del(element);
  2701. /* Point to Rx buffer via next RBD in circular buffer */
  2702. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2703. rxq->queue[rxq->write] = rxb;
  2704. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2705. rxq->free_count--;
  2706. }
  2707. spin_unlock_irqrestore(&rxq->lock, flags);
  2708. /* If the pre-allocated buffer pool is dropping low, schedule to
  2709. * refill it */
  2710. if (rxq->free_count <= RX_LOW_WATERMARK)
  2711. queue_work(priv->workqueue, &priv->rx_replenish);
  2712. /* If we've added more space for the firmware to place data, tell it.
  2713. * Increment device's write pointer in multiples of 8. */
  2714. if ((write != (rxq->write & ~0x7))
  2715. || (abs(rxq->write - rxq->read) > 7)) {
  2716. spin_lock_irqsave(&rxq->lock, flags);
  2717. rxq->need_update = 1;
  2718. spin_unlock_irqrestore(&rxq->lock, flags);
  2719. rc = iwl_rx_queue_update_write_ptr(priv, rxq);
  2720. if (rc)
  2721. return rc;
  2722. }
  2723. return 0;
  2724. }
  2725. /**
  2726. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2727. *
  2728. * When moving to rx_free an SKB is allocated for the slot.
  2729. *
  2730. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2731. * This is called as a scheduled work item (except for during initialization)
  2732. */
  2733. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2734. {
  2735. struct iwl_rx_queue *rxq = &priv->rxq;
  2736. struct list_head *element;
  2737. struct iwl_rx_mem_buffer *rxb;
  2738. unsigned long flags;
  2739. spin_lock_irqsave(&rxq->lock, flags);
  2740. while (!list_empty(&rxq->rx_used)) {
  2741. element = rxq->rx_used.next;
  2742. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2743. /* Alloc a new receive buffer */
  2744. rxb->skb =
  2745. alloc_skb(priv->hw_params.rx_buf_size,
  2746. __GFP_NOWARN | GFP_ATOMIC);
  2747. if (!rxb->skb) {
  2748. if (net_ratelimit())
  2749. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2750. /* We don't reschedule replenish work here -- we will
  2751. * call the restock method and if it still needs
  2752. * more buffers it will schedule replenish */
  2753. break;
  2754. }
  2755. /* If radiotap head is required, reserve some headroom here.
  2756. * The physical head count is a variable rx_stats->phy_count.
  2757. * We reserve 4 bytes here. Plus these extra bytes, the
  2758. * headroom of the physical head should be enough for the
  2759. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2760. */
  2761. skb_reserve(rxb->skb, 4);
  2762. priv->alloc_rxb_skb++;
  2763. list_del(element);
  2764. /* Get physical address of RB/SKB */
  2765. rxb->real_dma_addr = pci_map_single(priv->pci_dev,
  2766. rxb->skb->data,
  2767. priv->hw_params.rx_buf_size,
  2768. PCI_DMA_FROMDEVICE);
  2769. list_add_tail(&rxb->list, &rxq->rx_free);
  2770. rxq->free_count++;
  2771. }
  2772. spin_unlock_irqrestore(&rxq->lock, flags);
  2773. }
  2774. /*
  2775. * this should be called while priv->lock is locked
  2776. */
  2777. static void __iwl3945_rx_replenish(void *data)
  2778. {
  2779. struct iwl_priv *priv = data;
  2780. iwl3945_rx_allocate(priv);
  2781. iwl3945_rx_queue_restock(priv);
  2782. }
  2783. void iwl3945_rx_replenish(void *data)
  2784. {
  2785. struct iwl_priv *priv = data;
  2786. unsigned long flags;
  2787. iwl3945_rx_allocate(priv);
  2788. spin_lock_irqsave(&priv->lock, flags);
  2789. iwl3945_rx_queue_restock(priv);
  2790. spin_unlock_irqrestore(&priv->lock, flags);
  2791. }
  2792. /* Convert linear signal-to-noise ratio into dB */
  2793. static u8 ratio2dB[100] = {
  2794. /* 0 1 2 3 4 5 6 7 8 9 */
  2795. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  2796. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  2797. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  2798. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  2799. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  2800. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  2801. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  2802. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  2803. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  2804. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  2805. };
  2806. /* Calculates a relative dB value from a ratio of linear
  2807. * (i.e. not dB) signal levels.
  2808. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  2809. int iwl3945_calc_db_from_ratio(int sig_ratio)
  2810. {
  2811. /* 1000:1 or higher just report as 60 dB */
  2812. if (sig_ratio >= 1000)
  2813. return 60;
  2814. /* 100:1 or higher, divide by 10 and use table,
  2815. * add 20 dB to make up for divide by 10 */
  2816. if (sig_ratio >= 100)
  2817. return 20 + (int)ratio2dB[sig_ratio/10];
  2818. /* We shouldn't see this */
  2819. if (sig_ratio < 1)
  2820. return 0;
  2821. /* Use table for ratios 1:1 - 99:1 */
  2822. return (int)ratio2dB[sig_ratio];
  2823. }
  2824. #define PERFECT_RSSI (-20) /* dBm */
  2825. #define WORST_RSSI (-95) /* dBm */
  2826. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  2827. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  2828. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  2829. * about formulas used below. */
  2830. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  2831. {
  2832. int sig_qual;
  2833. int degradation = PERFECT_RSSI - rssi_dbm;
  2834. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  2835. * as indicator; formula is (signal dbm - noise dbm).
  2836. * SNR at or above 40 is a great signal (100%).
  2837. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  2838. * Weakest usable signal is usually 10 - 15 dB SNR. */
  2839. if (noise_dbm) {
  2840. if (rssi_dbm - noise_dbm >= 40)
  2841. return 100;
  2842. else if (rssi_dbm < noise_dbm)
  2843. return 0;
  2844. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  2845. /* Else use just the signal level.
  2846. * This formula is a least squares fit of data points collected and
  2847. * compared with a reference system that had a percentage (%) display
  2848. * for signal quality. */
  2849. } else
  2850. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  2851. (15 * RSSI_RANGE + 62 * degradation)) /
  2852. (RSSI_RANGE * RSSI_RANGE);
  2853. if (sig_qual > 100)
  2854. sig_qual = 100;
  2855. else if (sig_qual < 1)
  2856. sig_qual = 0;
  2857. return sig_qual;
  2858. }
  2859. /**
  2860. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  2861. *
  2862. * Uses the priv->rx_handlers callback function array to invoke
  2863. * the appropriate handlers, including command responses,
  2864. * frame-received notifications, and other notifications.
  2865. */
  2866. static void iwl3945_rx_handle(struct iwl_priv *priv)
  2867. {
  2868. struct iwl_rx_mem_buffer *rxb;
  2869. struct iwl_rx_packet *pkt;
  2870. struct iwl_rx_queue *rxq = &priv->rxq;
  2871. u32 r, i;
  2872. int reclaim;
  2873. unsigned long flags;
  2874. u8 fill_rx = 0;
  2875. u32 count = 8;
  2876. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  2877. * buffer that the driver may process (last buffer filled by ucode). */
  2878. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  2879. i = rxq->read;
  2880. if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  2881. fill_rx = 1;
  2882. /* Rx interrupt, but nothing sent from uCode */
  2883. if (i == r)
  2884. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  2885. while (i != r) {
  2886. rxb = rxq->queue[i];
  2887. /* If an RXB doesn't have a Rx queue slot associated with it,
  2888. * then a bug has been introduced in the queue refilling
  2889. * routines -- catch it here */
  2890. BUG_ON(rxb == NULL);
  2891. rxq->queue[i] = NULL;
  2892. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  2893. priv->hw_params.rx_buf_size,
  2894. PCI_DMA_FROMDEVICE);
  2895. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2896. /* Reclaim a command buffer only if this packet is a response
  2897. * to a (driver-originated) command.
  2898. * If the packet (e.g. Rx frame) originated from uCode,
  2899. * there is no command buffer to reclaim.
  2900. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  2901. * but apparently a few don't get set; catch them here. */
  2902. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  2903. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  2904. (pkt->hdr.cmd != REPLY_TX);
  2905. /* Based on type of command response or notification,
  2906. * handle those that need handling via function in
  2907. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  2908. if (priv->rx_handlers[pkt->hdr.cmd]) {
  2909. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2910. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  2911. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  2912. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  2913. } else {
  2914. /* No handling needed */
  2915. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2916. "r %d i %d No handler needed for %s, 0x%02x\n",
  2917. r, i, get_cmd_string(pkt->hdr.cmd),
  2918. pkt->hdr.cmd);
  2919. }
  2920. if (reclaim) {
  2921. /* Invoke any callbacks, transfer the skb to caller, and
  2922. * fire off the (possibly) blocking iwl3945_send_cmd()
  2923. * as we reclaim the driver command queue */
  2924. if (rxb && rxb->skb)
  2925. iwl3945_tx_cmd_complete(priv, rxb);
  2926. else
  2927. IWL_WARN(priv, "Claim null rxb?\n");
  2928. }
  2929. /* For now we just don't re-use anything. We can tweak this
  2930. * later to try and re-use notification packets and SKBs that
  2931. * fail to Rx correctly */
  2932. if (rxb->skb != NULL) {
  2933. priv->alloc_rxb_skb--;
  2934. dev_kfree_skb_any(rxb->skb);
  2935. rxb->skb = NULL;
  2936. }
  2937. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  2938. priv->hw_params.rx_buf_size,
  2939. PCI_DMA_FROMDEVICE);
  2940. spin_lock_irqsave(&rxq->lock, flags);
  2941. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  2942. spin_unlock_irqrestore(&rxq->lock, flags);
  2943. i = (i + 1) & RX_QUEUE_MASK;
  2944. /* If there are a lot of unused frames,
  2945. * restock the Rx queue so ucode won't assert. */
  2946. if (fill_rx) {
  2947. count++;
  2948. if (count >= 8) {
  2949. priv->rxq.read = i;
  2950. __iwl3945_rx_replenish(priv);
  2951. count = 0;
  2952. }
  2953. }
  2954. }
  2955. /* Backtrack one entry */
  2956. priv->rxq.read = i;
  2957. iwl3945_rx_queue_restock(priv);
  2958. }
  2959. /**
  2960. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  2961. */
  2962. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  2963. struct iwl_tx_queue *txq)
  2964. {
  2965. u32 reg = 0;
  2966. int rc = 0;
  2967. int txq_id = txq->q.id;
  2968. if (txq->need_update == 0)
  2969. return rc;
  2970. /* if we're trying to save power */
  2971. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2972. /* wake up nic if it's powered down ...
  2973. * uCode will wake up, and interrupt us again, so next
  2974. * time we'll skip this part. */
  2975. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2976. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2977. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  2978. iwl_set_bit(priv, CSR_GP_CNTRL,
  2979. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2980. return rc;
  2981. }
  2982. /* restore this queue's parameters in nic hardware. */
  2983. rc = iwl_grab_nic_access(priv);
  2984. if (rc)
  2985. return rc;
  2986. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  2987. txq->q.write_ptr | (txq_id << 8));
  2988. iwl_release_nic_access(priv);
  2989. /* else not in power-save mode, uCode will never sleep when we're
  2990. * trying to tx (during RFKILL, we're not trying to tx). */
  2991. } else
  2992. iwl_write32(priv, HBUS_TARG_WRPTR,
  2993. txq->q.write_ptr | (txq_id << 8));
  2994. txq->need_update = 0;
  2995. return rc;
  2996. }
  2997. #ifdef CONFIG_IWL3945_DEBUG
  2998. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  2999. struct iwl3945_rxon_cmd *rxon)
  3000. {
  3001. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3002. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3003. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3004. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3005. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3006. le32_to_cpu(rxon->filter_flags));
  3007. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3008. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3009. rxon->ofdm_basic_rates);
  3010. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3011. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3012. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3013. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3014. }
  3015. #endif
  3016. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  3017. {
  3018. IWL_DEBUG_ISR("Enabling interrupts\n");
  3019. set_bit(STATUS_INT_ENABLED, &priv->status);
  3020. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3021. }
  3022. /* call this function to flush any scheduled tasklet */
  3023. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  3024. {
  3025. /* wait to make sure we flush pending tasklet*/
  3026. synchronize_irq(priv->pci_dev->irq);
  3027. tasklet_kill(&priv->irq_tasklet);
  3028. }
  3029. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  3030. {
  3031. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3032. /* disable interrupts from uCode/NIC to host */
  3033. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3034. /* acknowledge/clear/reset any interrupts still pending
  3035. * from uCode or flow handler (Rx/Tx DMA) */
  3036. iwl_write32(priv, CSR_INT, 0xffffffff);
  3037. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3038. IWL_DEBUG_ISR("Disabled interrupts\n");
  3039. }
  3040. static const char *desc_lookup(int i)
  3041. {
  3042. switch (i) {
  3043. case 1:
  3044. return "FAIL";
  3045. case 2:
  3046. return "BAD_PARAM";
  3047. case 3:
  3048. return "BAD_CHECKSUM";
  3049. case 4:
  3050. return "NMI_INTERRUPT";
  3051. case 5:
  3052. return "SYSASSERT";
  3053. case 6:
  3054. return "FATAL_ERROR";
  3055. }
  3056. return "UNKNOWN";
  3057. }
  3058. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3059. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3060. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  3061. {
  3062. u32 i;
  3063. u32 desc, time, count, base, data1;
  3064. u32 blink1, blink2, ilink1, ilink2;
  3065. int rc;
  3066. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3067. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3068. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  3069. return;
  3070. }
  3071. rc = iwl_grab_nic_access(priv);
  3072. if (rc) {
  3073. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3074. return;
  3075. }
  3076. count = iwl_read_targ_mem(priv, base);
  3077. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3078. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  3079. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  3080. priv->status, count);
  3081. }
  3082. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  3083. "ilink1 nmiPC Line\n");
  3084. for (i = ERROR_START_OFFSET;
  3085. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3086. i += ERROR_ELEM_SIZE) {
  3087. desc = iwl_read_targ_mem(priv, base + i);
  3088. time =
  3089. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3090. blink1 =
  3091. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3092. blink2 =
  3093. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3094. ilink1 =
  3095. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3096. ilink2 =
  3097. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3098. data1 =
  3099. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3100. IWL_ERR(priv,
  3101. "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3102. desc_lookup(desc), desc, time, blink1, blink2,
  3103. ilink1, ilink2, data1);
  3104. }
  3105. iwl_release_nic_access(priv);
  3106. }
  3107. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3108. /**
  3109. * iwl3945_print_event_log - Dump error event log to syslog
  3110. *
  3111. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  3112. */
  3113. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  3114. u32 num_events, u32 mode)
  3115. {
  3116. u32 i;
  3117. u32 base; /* SRAM byte address of event log header */
  3118. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3119. u32 ptr; /* SRAM byte address of log data */
  3120. u32 ev, time, data; /* event log data */
  3121. if (num_events == 0)
  3122. return;
  3123. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3124. if (mode == 0)
  3125. event_size = 2 * sizeof(u32);
  3126. else
  3127. event_size = 3 * sizeof(u32);
  3128. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3129. /* "time" is actually "data" for mode 0 (no timestamp).
  3130. * place event id # at far right for easier visual parsing. */
  3131. for (i = 0; i < num_events; i++) {
  3132. ev = iwl_read_targ_mem(priv, ptr);
  3133. ptr += sizeof(u32);
  3134. time = iwl_read_targ_mem(priv, ptr);
  3135. ptr += sizeof(u32);
  3136. if (mode == 0) {
  3137. /* data, ev */
  3138. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  3139. } else {
  3140. data = iwl_read_targ_mem(priv, ptr);
  3141. ptr += sizeof(u32);
  3142. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
  3143. }
  3144. }
  3145. }
  3146. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  3147. {
  3148. int rc;
  3149. u32 base; /* SRAM byte address of event log header */
  3150. u32 capacity; /* event log capacity in # entries */
  3151. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3152. u32 num_wraps; /* # times uCode wrapped to top of log */
  3153. u32 next_entry; /* index of next entry to be written by uCode */
  3154. u32 size; /* # entries that we'll print */
  3155. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3156. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3157. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  3158. return;
  3159. }
  3160. rc = iwl_grab_nic_access(priv);
  3161. if (rc) {
  3162. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3163. return;
  3164. }
  3165. /* event log header */
  3166. capacity = iwl_read_targ_mem(priv, base);
  3167. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3168. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3169. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3170. size = num_wraps ? capacity : next_entry;
  3171. /* bail out if nothing in log */
  3172. if (size == 0) {
  3173. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  3174. iwl_release_nic_access(priv);
  3175. return;
  3176. }
  3177. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  3178. size, num_wraps);
  3179. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3180. * i.e the next one that uCode would fill. */
  3181. if (num_wraps)
  3182. iwl3945_print_event_log(priv, next_entry,
  3183. capacity - next_entry, mode);
  3184. /* (then/else) start at top of log */
  3185. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3186. iwl_release_nic_access(priv);
  3187. }
  3188. /**
  3189. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3190. */
  3191. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  3192. {
  3193. /* Set the FW error flag -- cleared on iwl3945_down */
  3194. set_bit(STATUS_FW_ERROR, &priv->status);
  3195. /* Cancel currently queued command. */
  3196. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3197. #ifdef CONFIG_IWL3945_DEBUG
  3198. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3199. iwl3945_dump_nic_error_log(priv);
  3200. iwl3945_dump_nic_event_log(priv);
  3201. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  3202. }
  3203. #endif
  3204. wake_up_interruptible(&priv->wait_command_queue);
  3205. /* Keep the restart process from trying to send host
  3206. * commands by clearing the INIT status bit */
  3207. clear_bit(STATUS_READY, &priv->status);
  3208. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3209. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3210. "Restarting adapter due to uCode error.\n");
  3211. if (iwl3945_is_associated(priv)) {
  3212. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  3213. sizeof(priv->recovery39_rxon));
  3214. priv->error_recovering = 1;
  3215. }
  3216. queue_work(priv->workqueue, &priv->restart);
  3217. }
  3218. }
  3219. static void iwl3945_error_recovery(struct iwl_priv *priv)
  3220. {
  3221. unsigned long flags;
  3222. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  3223. sizeof(priv->staging39_rxon));
  3224. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3225. iwl3945_commit_rxon(priv);
  3226. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3227. spin_lock_irqsave(&priv->lock, flags);
  3228. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  3229. priv->error_recovering = 0;
  3230. spin_unlock_irqrestore(&priv->lock, flags);
  3231. }
  3232. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  3233. {
  3234. u32 inta, handled = 0;
  3235. u32 inta_fh;
  3236. unsigned long flags;
  3237. #ifdef CONFIG_IWL3945_DEBUG
  3238. u32 inta_mask;
  3239. #endif
  3240. spin_lock_irqsave(&priv->lock, flags);
  3241. /* Ack/clear/reset pending uCode interrupts.
  3242. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3243. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3244. inta = iwl_read32(priv, CSR_INT);
  3245. iwl_write32(priv, CSR_INT, inta);
  3246. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3247. * Any new interrupts that happen after this, either while we're
  3248. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3249. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3250. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3251. #ifdef CONFIG_IWL3945_DEBUG
  3252. if (priv->debug_level & IWL_DL_ISR) {
  3253. /* just for debug */
  3254. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3255. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3256. inta, inta_mask, inta_fh);
  3257. }
  3258. #endif
  3259. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3260. * atomic, make sure that inta covers all the interrupts that
  3261. * we've discovered, even if FH interrupt came in just after
  3262. * reading CSR_INT. */
  3263. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3264. inta |= CSR_INT_BIT_FH_RX;
  3265. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3266. inta |= CSR_INT_BIT_FH_TX;
  3267. /* Now service all interrupt bits discovered above. */
  3268. if (inta & CSR_INT_BIT_HW_ERR) {
  3269. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  3270. /* Tell the device to stop sending interrupts */
  3271. iwl3945_disable_interrupts(priv);
  3272. iwl3945_irq_handle_error(priv);
  3273. handled |= CSR_INT_BIT_HW_ERR;
  3274. spin_unlock_irqrestore(&priv->lock, flags);
  3275. return;
  3276. }
  3277. #ifdef CONFIG_IWL3945_DEBUG
  3278. if (priv->debug_level & (IWL_DL_ISR)) {
  3279. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3280. if (inta & CSR_INT_BIT_SCD)
  3281. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3282. "the frame/frames.\n");
  3283. /* Alive notification via Rx interrupt will do the real work */
  3284. if (inta & CSR_INT_BIT_ALIVE)
  3285. IWL_DEBUG_ISR("Alive interrupt\n");
  3286. }
  3287. #endif
  3288. /* Safely ignore these bits for debug checks below */
  3289. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3290. /* Error detected by uCode */
  3291. if (inta & CSR_INT_BIT_SW_ERR) {
  3292. IWL_ERR(priv, "Microcode SW error detected. "
  3293. "Restarting 0x%X.\n", inta);
  3294. iwl3945_irq_handle_error(priv);
  3295. handled |= CSR_INT_BIT_SW_ERR;
  3296. }
  3297. /* uCode wakes up after power-down sleep */
  3298. if (inta & CSR_INT_BIT_WAKEUP) {
  3299. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3300. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  3301. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3302. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3303. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3304. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3305. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3306. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3307. handled |= CSR_INT_BIT_WAKEUP;
  3308. }
  3309. /* All uCode command responses, including Tx command responses,
  3310. * Rx "responses" (frame-received notification), and other
  3311. * notifications from uCode come through here*/
  3312. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3313. iwl3945_rx_handle(priv);
  3314. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3315. }
  3316. if (inta & CSR_INT_BIT_FH_TX) {
  3317. IWL_DEBUG_ISR("Tx interrupt\n");
  3318. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3319. if (!iwl_grab_nic_access(priv)) {
  3320. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  3321. (FH39_SRVC_CHNL), 0x0);
  3322. iwl_release_nic_access(priv);
  3323. }
  3324. handled |= CSR_INT_BIT_FH_TX;
  3325. }
  3326. if (inta & ~handled)
  3327. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3328. if (inta & ~CSR_INI_SET_MASK) {
  3329. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  3330. inta & ~CSR_INI_SET_MASK);
  3331. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  3332. }
  3333. /* Re-enable all interrupts */
  3334. /* only Re-enable if disabled by irq */
  3335. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3336. iwl3945_enable_interrupts(priv);
  3337. #ifdef CONFIG_IWL3945_DEBUG
  3338. if (priv->debug_level & (IWL_DL_ISR)) {
  3339. inta = iwl_read32(priv, CSR_INT);
  3340. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3341. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3342. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3343. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3344. }
  3345. #endif
  3346. spin_unlock_irqrestore(&priv->lock, flags);
  3347. }
  3348. static irqreturn_t iwl3945_isr(int irq, void *data)
  3349. {
  3350. struct iwl_priv *priv = data;
  3351. u32 inta, inta_mask;
  3352. u32 inta_fh;
  3353. if (!priv)
  3354. return IRQ_NONE;
  3355. spin_lock(&priv->lock);
  3356. /* Disable (but don't clear!) interrupts here to avoid
  3357. * back-to-back ISRs and sporadic interrupts from our NIC.
  3358. * If we have something to service, the tasklet will re-enable ints.
  3359. * If we *don't* have something, we'll re-enable before leaving here. */
  3360. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  3361. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3362. /* Discover which interrupts are active/pending */
  3363. inta = iwl_read32(priv, CSR_INT);
  3364. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3365. /* Ignore interrupt if there's nothing in NIC to service.
  3366. * This may be due to IRQ shared with another device,
  3367. * or due to sporadic interrupts thrown from our NIC. */
  3368. if (!inta && !inta_fh) {
  3369. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3370. goto none;
  3371. }
  3372. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3373. /* Hardware disappeared */
  3374. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3375. goto unplugged;
  3376. }
  3377. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3378. inta, inta_mask, inta_fh);
  3379. inta &= ~CSR_INT_BIT_SCD;
  3380. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3381. if (likely(inta || inta_fh))
  3382. tasklet_schedule(&priv->irq_tasklet);
  3383. unplugged:
  3384. spin_unlock(&priv->lock);
  3385. return IRQ_HANDLED;
  3386. none:
  3387. /* re-enable interrupts here since we don't have anything to service. */
  3388. /* only Re-enable if disabled by irq */
  3389. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3390. iwl3945_enable_interrupts(priv);
  3391. spin_unlock(&priv->lock);
  3392. return IRQ_NONE;
  3393. }
  3394. /************************** EEPROM BANDS ****************************
  3395. *
  3396. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3397. * EEPROM contents to the specific channel number supported for each
  3398. * band.
  3399. *
  3400. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  3401. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3402. * The specific geography and calibration information for that channel
  3403. * is contained in the eeprom map itself.
  3404. *
  3405. * During init, we copy the eeprom information and channel map
  3406. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3407. *
  3408. * channel_map_24/52 provides the index in the channel_info array for a
  3409. * given channel. We have to have two separate maps as there is channel
  3410. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3411. * band_2
  3412. *
  3413. * A value of 0xff stored in the channel_map indicates that the channel
  3414. * is not supported by the hardware at all.
  3415. *
  3416. * A value of 0xfe in the channel_map indicates that the channel is not
  3417. * valid for Tx with the current hardware. This means that
  3418. * while the system can tune and receive on a given channel, it may not
  3419. * be able to associate or transmit any frames on that
  3420. * channel. There is no corresponding channel information for that
  3421. * entry.
  3422. *
  3423. *********************************************************************/
  3424. /* 2.4 GHz */
  3425. static const u8 iwl3945_eeprom_band_1[14] = {
  3426. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3427. };
  3428. /* 5.2 GHz bands */
  3429. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3430. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3431. };
  3432. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3433. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3434. };
  3435. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3436. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3437. };
  3438. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3439. 145, 149, 153, 157, 161, 165
  3440. };
  3441. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3442. int *eeprom_ch_count,
  3443. const struct iwl_eeprom_channel
  3444. **eeprom_ch_info,
  3445. const u8 **eeprom_ch_index)
  3446. {
  3447. switch (band) {
  3448. case 1: /* 2.4GHz band */
  3449. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3450. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3451. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3452. break;
  3453. case 2: /* 4.9GHz band */
  3454. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3455. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3456. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3457. break;
  3458. case 3: /* 5.2GHz band */
  3459. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3460. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3461. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3462. break;
  3463. case 4: /* 5.5GHz band */
  3464. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3465. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3466. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3467. break;
  3468. case 5: /* 5.7GHz band */
  3469. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3470. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3471. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3472. break;
  3473. default:
  3474. BUG();
  3475. return;
  3476. }
  3477. }
  3478. /**
  3479. * iwl3945_get_channel_info - Find driver's private channel info
  3480. *
  3481. * Based on band and channel number.
  3482. */
  3483. const struct iwl_channel_info *
  3484. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3485. enum ieee80211_band band, u16 channel)
  3486. {
  3487. int i;
  3488. switch (band) {
  3489. case IEEE80211_BAND_5GHZ:
  3490. for (i = 14; i < priv->channel_count; i++) {
  3491. if (priv->channel_info[i].channel == channel)
  3492. return &priv->channel_info[i];
  3493. }
  3494. break;
  3495. case IEEE80211_BAND_2GHZ:
  3496. if (channel >= 1 && channel <= 14)
  3497. return &priv->channel_info[channel - 1];
  3498. break;
  3499. case IEEE80211_NUM_BANDS:
  3500. WARN_ON(1);
  3501. }
  3502. return NULL;
  3503. }
  3504. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3505. ? # x " " : "")
  3506. /**
  3507. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3508. */
  3509. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3510. {
  3511. int eeprom_ch_count = 0;
  3512. const u8 *eeprom_ch_index = NULL;
  3513. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3514. int band, ch;
  3515. struct iwl_channel_info *ch_info;
  3516. if (priv->channel_count) {
  3517. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3518. return 0;
  3519. }
  3520. if (priv->eeprom39.version < 0x2f) {
  3521. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3522. priv->eeprom39.version);
  3523. return -EINVAL;
  3524. }
  3525. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3526. priv->channel_count =
  3527. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3528. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3529. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3530. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3531. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3532. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3533. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3534. priv->channel_count, GFP_KERNEL);
  3535. if (!priv->channel_info) {
  3536. IWL_ERR(priv, "Could not allocate channel_info\n");
  3537. priv->channel_count = 0;
  3538. return -ENOMEM;
  3539. }
  3540. ch_info = priv->channel_info;
  3541. /* Loop through the 5 EEPROM bands adding them in order to the
  3542. * channel map we maintain (that contains additional information than
  3543. * what just in the EEPROM) */
  3544. for (band = 1; band <= 5; band++) {
  3545. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3546. &eeprom_ch_info, &eeprom_ch_index);
  3547. /* Loop through each band adding each of the channels */
  3548. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3549. ch_info->channel = eeprom_ch_index[ch];
  3550. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3551. IEEE80211_BAND_5GHZ;
  3552. /* permanently store EEPROM's channel regulatory flags
  3553. * and max power in channel info database. */
  3554. ch_info->eeprom = eeprom_ch_info[ch];
  3555. /* Copy the run-time flags so they are there even on
  3556. * invalid channels */
  3557. ch_info->flags = eeprom_ch_info[ch].flags;
  3558. if (!(is_channel_valid(ch_info))) {
  3559. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3560. "No traffic\n",
  3561. ch_info->channel,
  3562. ch_info->flags,
  3563. is_channel_a_band(ch_info) ?
  3564. "5.2" : "2.4");
  3565. ch_info++;
  3566. continue;
  3567. }
  3568. /* Initialize regulatory-based run-time data */
  3569. ch_info->max_power_avg = ch_info->curr_txpow =
  3570. eeprom_ch_info[ch].max_power_avg;
  3571. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3572. ch_info->min_power = 0;
  3573. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3574. " %ddBm): Ad-Hoc %ssupported\n",
  3575. ch_info->channel,
  3576. is_channel_a_band(ch_info) ?
  3577. "5.2" : "2.4",
  3578. CHECK_AND_PRINT(VALID),
  3579. CHECK_AND_PRINT(IBSS),
  3580. CHECK_AND_PRINT(ACTIVE),
  3581. CHECK_AND_PRINT(RADAR),
  3582. CHECK_AND_PRINT(WIDE),
  3583. CHECK_AND_PRINT(DFS),
  3584. eeprom_ch_info[ch].flags,
  3585. eeprom_ch_info[ch].max_power_avg,
  3586. ((eeprom_ch_info[ch].
  3587. flags & EEPROM_CHANNEL_IBSS)
  3588. && !(eeprom_ch_info[ch].
  3589. flags & EEPROM_CHANNEL_RADAR))
  3590. ? "" : "not ");
  3591. /* Set the user_txpower_limit to the highest power
  3592. * supported by any channel */
  3593. if (eeprom_ch_info[ch].max_power_avg >
  3594. priv->user_txpower_limit)
  3595. priv->user_txpower_limit =
  3596. eeprom_ch_info[ch].max_power_avg;
  3597. ch_info++;
  3598. }
  3599. }
  3600. /* Set up txpower settings in driver for all channels */
  3601. if (iwl3945_txpower_set_from_eeprom(priv))
  3602. return -EIO;
  3603. return 0;
  3604. }
  3605. /*
  3606. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3607. */
  3608. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3609. {
  3610. kfree(priv->channel_info);
  3611. priv->channel_count = 0;
  3612. }
  3613. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3614. * sending probe req. This should be set long enough to hear probe responses
  3615. * from more than one AP. */
  3616. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3617. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3618. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3619. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3620. /* For faster active scanning, scan will move to the next channel if fewer than
  3621. * PLCP_QUIET_THRESH packets are heard on this channel within
  3622. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3623. * time if it's a quiet channel (nothing responded to our probe, and there's
  3624. * no other traffic).
  3625. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3626. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3627. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3628. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3629. * Must be set longer than active dwell time.
  3630. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3631. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3632. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3633. #define IWL_PASSIVE_DWELL_BASE (100)
  3634. #define IWL_CHANNEL_TUNE_TIME 5
  3635. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3636. static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
  3637. enum ieee80211_band band,
  3638. u8 n_probes)
  3639. {
  3640. if (band == IEEE80211_BAND_5GHZ)
  3641. return IWL_ACTIVE_DWELL_TIME_52 +
  3642. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3643. else
  3644. return IWL_ACTIVE_DWELL_TIME_24 +
  3645. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3646. }
  3647. static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
  3648. enum ieee80211_band band)
  3649. {
  3650. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3651. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3652. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3653. if (iwl3945_is_associated(priv)) {
  3654. /* If we're associated, we clamp the maximum passive
  3655. * dwell time to be 98% of the beacon interval (minus
  3656. * 2 * channel tune time) */
  3657. passive = priv->beacon_int;
  3658. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3659. passive = IWL_PASSIVE_DWELL_BASE;
  3660. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3661. }
  3662. return passive;
  3663. }
  3664. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3665. enum ieee80211_band band,
  3666. u8 is_active, u8 n_probes,
  3667. struct iwl3945_scan_channel *scan_ch)
  3668. {
  3669. const struct ieee80211_channel *channels = NULL;
  3670. const struct ieee80211_supported_band *sband;
  3671. const struct iwl_channel_info *ch_info;
  3672. u16 passive_dwell = 0;
  3673. u16 active_dwell = 0;
  3674. int added, i;
  3675. sband = iwl_get_hw_mode(priv, band);
  3676. if (!sband)
  3677. return 0;
  3678. channels = sband->channels;
  3679. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3680. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3681. if (passive_dwell <= active_dwell)
  3682. passive_dwell = active_dwell + 1;
  3683. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3684. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3685. continue;
  3686. scan_ch->channel = channels[i].hw_value;
  3687. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3688. if (!is_channel_valid(ch_info)) {
  3689. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3690. scan_ch->channel);
  3691. continue;
  3692. }
  3693. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3694. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3695. /* If passive , set up for auto-switch
  3696. * and use long active_dwell time.
  3697. */
  3698. if (!is_active || is_channel_passive(ch_info) ||
  3699. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3700. scan_ch->type = 0; /* passive */
  3701. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3702. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3703. } else {
  3704. scan_ch->type = 1; /* active */
  3705. }
  3706. /* Set direct probe bits. These may be used both for active
  3707. * scan channels (probes gets sent right away),
  3708. * or for passive channels (probes get se sent only after
  3709. * hearing clear Rx packet).*/
  3710. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3711. if (n_probes)
  3712. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3713. } else {
  3714. /* uCode v1 does not allow setting direct probe bits on
  3715. * passive channel. */
  3716. if ((scan_ch->type & 1) && n_probes)
  3717. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3718. }
  3719. /* Set txpower levels to defaults */
  3720. scan_ch->tpc.dsp_atten = 110;
  3721. /* scan_pwr_info->tpc.dsp_atten; */
  3722. /*scan_pwr_info->tpc.tx_gain; */
  3723. if (band == IEEE80211_BAND_5GHZ)
  3724. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3725. else {
  3726. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3727. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3728. * power level:
  3729. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3730. */
  3731. }
  3732. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3733. scan_ch->channel,
  3734. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3735. (scan_ch->type & 1) ?
  3736. active_dwell : passive_dwell);
  3737. scan_ch++;
  3738. added++;
  3739. }
  3740. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3741. return added;
  3742. }
  3743. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3744. struct ieee80211_rate *rates)
  3745. {
  3746. int i;
  3747. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3748. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3749. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3750. rates[i].hw_value_short = i;
  3751. rates[i].flags = 0;
  3752. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  3753. /*
  3754. * If CCK != 1M then set short preamble rate flag.
  3755. */
  3756. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  3757. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3758. }
  3759. }
  3760. }
  3761. /**
  3762. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  3763. */
  3764. static int iwl3945_init_geos(struct iwl_priv *priv)
  3765. {
  3766. struct iwl_channel_info *ch;
  3767. struct ieee80211_supported_band *sband;
  3768. struct ieee80211_channel *channels;
  3769. struct ieee80211_channel *geo_ch;
  3770. struct ieee80211_rate *rates;
  3771. int i = 0;
  3772. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  3773. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  3774. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  3775. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3776. return 0;
  3777. }
  3778. channels = kzalloc(sizeof(struct ieee80211_channel) *
  3779. priv->channel_count, GFP_KERNEL);
  3780. if (!channels)
  3781. return -ENOMEM;
  3782. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  3783. GFP_KERNEL);
  3784. if (!rates) {
  3785. kfree(channels);
  3786. return -ENOMEM;
  3787. }
  3788. /* 5.2GHz channels start after the 2.4GHz channels */
  3789. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3790. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  3791. /* just OFDM */
  3792. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  3793. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  3794. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3795. sband->channels = channels;
  3796. /* OFDM & CCK */
  3797. sband->bitrates = rates;
  3798. sband->n_bitrates = IWL_RATE_COUNT;
  3799. priv->ieee_channels = channels;
  3800. priv->ieee_rates = rates;
  3801. iwl3945_init_hw_rates(priv, rates);
  3802. for (i = 0; i < priv->channel_count; i++) {
  3803. ch = &priv->channel_info[i];
  3804. /* FIXME: might be removed if scan is OK*/
  3805. if (!is_channel_valid(ch))
  3806. continue;
  3807. if (is_channel_a_band(ch))
  3808. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3809. else
  3810. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3811. geo_ch = &sband->channels[sband->n_channels++];
  3812. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  3813. geo_ch->max_power = ch->max_power_avg;
  3814. geo_ch->max_antenna_gain = 0xff;
  3815. geo_ch->hw_value = ch->channel;
  3816. if (is_channel_valid(ch)) {
  3817. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  3818. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  3819. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  3820. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  3821. if (ch->flags & EEPROM_CHANNEL_RADAR)
  3822. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  3823. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  3824. priv->max_channel_txpower_limit =
  3825. ch->max_power_avg;
  3826. } else {
  3827. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  3828. }
  3829. /* Save flags for reg domain usage */
  3830. geo_ch->orig_flags = geo_ch->flags;
  3831. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  3832. ch->channel, geo_ch->center_freq,
  3833. is_channel_a_band(ch) ? "5.2" : "2.4",
  3834. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  3835. "restricted" : "valid",
  3836. geo_ch->flags);
  3837. }
  3838. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  3839. priv->cfg->sku & IWL_SKU_A) {
  3840. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  3841. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  3842. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  3843. priv->cfg->sku &= ~IWL_SKU_A;
  3844. }
  3845. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  3846. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  3847. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  3848. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3849. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3850. &priv->bands[IEEE80211_BAND_2GHZ];
  3851. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3852. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3853. &priv->bands[IEEE80211_BAND_5GHZ];
  3854. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3855. return 0;
  3856. }
  3857. /*
  3858. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  3859. */
  3860. static void iwl3945_free_geos(struct iwl_priv *priv)
  3861. {
  3862. kfree(priv->ieee_channels);
  3863. kfree(priv->ieee_rates);
  3864. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3865. }
  3866. /******************************************************************************
  3867. *
  3868. * uCode download functions
  3869. *
  3870. ******************************************************************************/
  3871. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  3872. {
  3873. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  3874. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  3875. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  3876. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  3877. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  3878. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  3879. }
  3880. /**
  3881. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  3882. * looking at all data.
  3883. */
  3884. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  3885. {
  3886. u32 val;
  3887. u32 save_len = len;
  3888. int rc = 0;
  3889. u32 errcnt;
  3890. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3891. rc = iwl_grab_nic_access(priv);
  3892. if (rc)
  3893. return rc;
  3894. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3895. IWL39_RTC_INST_LOWER_BOUND);
  3896. errcnt = 0;
  3897. for (; len > 0; len -= sizeof(u32), image++) {
  3898. /* read data comes through single port, auto-incr addr */
  3899. /* NOTE: Use the debugless read so we don't flood kernel log
  3900. * if IWL_DL_IO is set */
  3901. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3902. if (val != le32_to_cpu(*image)) {
  3903. IWL_ERR(priv, "uCode INST section is invalid at "
  3904. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3905. save_len - len, val, le32_to_cpu(*image));
  3906. rc = -EIO;
  3907. errcnt++;
  3908. if (errcnt >= 20)
  3909. break;
  3910. }
  3911. }
  3912. iwl_release_nic_access(priv);
  3913. if (!errcnt)
  3914. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  3915. return rc;
  3916. }
  3917. /**
  3918. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  3919. * using sample data 100 bytes apart. If these sample points are good,
  3920. * it's a pretty good bet that everything between them is good, too.
  3921. */
  3922. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  3923. {
  3924. u32 val;
  3925. int rc = 0;
  3926. u32 errcnt = 0;
  3927. u32 i;
  3928. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3929. rc = iwl_grab_nic_access(priv);
  3930. if (rc)
  3931. return rc;
  3932. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  3933. /* read data comes through single port, auto-incr addr */
  3934. /* NOTE: Use the debugless read so we don't flood kernel log
  3935. * if IWL_DL_IO is set */
  3936. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3937. i + IWL39_RTC_INST_LOWER_BOUND);
  3938. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3939. if (val != le32_to_cpu(*image)) {
  3940. #if 0 /* Enable this if you want to see details */
  3941. IWL_ERR(priv, "uCode INST section is invalid at "
  3942. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3943. i, val, *image);
  3944. #endif
  3945. rc = -EIO;
  3946. errcnt++;
  3947. if (errcnt >= 3)
  3948. break;
  3949. }
  3950. }
  3951. iwl_release_nic_access(priv);
  3952. return rc;
  3953. }
  3954. /**
  3955. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  3956. * and verify its contents
  3957. */
  3958. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  3959. {
  3960. __le32 *image;
  3961. u32 len;
  3962. int rc = 0;
  3963. /* Try bootstrap */
  3964. image = (__le32 *)priv->ucode_boot.v_addr;
  3965. len = priv->ucode_boot.len;
  3966. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3967. if (rc == 0) {
  3968. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  3969. return 0;
  3970. }
  3971. /* Try initialize */
  3972. image = (__le32 *)priv->ucode_init.v_addr;
  3973. len = priv->ucode_init.len;
  3974. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3975. if (rc == 0) {
  3976. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  3977. return 0;
  3978. }
  3979. /* Try runtime/protocol */
  3980. image = (__le32 *)priv->ucode_code.v_addr;
  3981. len = priv->ucode_code.len;
  3982. rc = iwl3945_verify_inst_sparse(priv, image, len);
  3983. if (rc == 0) {
  3984. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  3985. return 0;
  3986. }
  3987. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  3988. /* Since nothing seems to match, show first several data entries in
  3989. * instruction SRAM, so maybe visual inspection will give a clue.
  3990. * Selection of bootstrap image (vs. other images) is arbitrary. */
  3991. image = (__le32 *)priv->ucode_boot.v_addr;
  3992. len = priv->ucode_boot.len;
  3993. rc = iwl3945_verify_inst_full(priv, image, len);
  3994. return rc;
  3995. }
  3996. static void iwl3945_nic_start(struct iwl_priv *priv)
  3997. {
  3998. /* Remove all resets to allow NIC to operate */
  3999. iwl_write32(priv, CSR_RESET, 0);
  4000. }
  4001. /**
  4002. * iwl3945_read_ucode - Read uCode images from disk file.
  4003. *
  4004. * Copy into buffers for card to fetch via bus-mastering
  4005. */
  4006. static int iwl3945_read_ucode(struct iwl_priv *priv)
  4007. {
  4008. struct iwl_ucode *ucode;
  4009. int ret = -EINVAL, index;
  4010. const struct firmware *ucode_raw;
  4011. /* firmware file name contains uCode/driver compatibility version */
  4012. const char *name_pre = priv->cfg->fw_name_pre;
  4013. const unsigned int api_max = priv->cfg->ucode_api_max;
  4014. const unsigned int api_min = priv->cfg->ucode_api_min;
  4015. char buf[25];
  4016. u8 *src;
  4017. size_t len;
  4018. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4019. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4020. * request_firmware() is synchronous, file is in memory on return. */
  4021. for (index = api_max; index >= api_min; index--) {
  4022. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4023. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4024. if (ret < 0) {
  4025. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  4026. buf, ret);
  4027. if (ret == -ENOENT)
  4028. continue;
  4029. else
  4030. goto error;
  4031. } else {
  4032. if (index < api_max)
  4033. IWL_ERR(priv, "Loaded firmware %s, "
  4034. "which is deprecated. "
  4035. " Please use API v%u instead.\n",
  4036. buf, api_max);
  4037. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4038. buf, ucode_raw->size);
  4039. break;
  4040. }
  4041. }
  4042. if (ret < 0)
  4043. goto error;
  4044. /* Make sure that we got at least our header! */
  4045. if (ucode_raw->size < sizeof(*ucode)) {
  4046. IWL_ERR(priv, "File size way too small!\n");
  4047. ret = -EINVAL;
  4048. goto err_release;
  4049. }
  4050. /* Data from ucode file: header followed by uCode images */
  4051. ucode = (void *)ucode_raw->data;
  4052. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4053. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4054. inst_size = le32_to_cpu(ucode->inst_size);
  4055. data_size = le32_to_cpu(ucode->data_size);
  4056. init_size = le32_to_cpu(ucode->init_size);
  4057. init_data_size = le32_to_cpu(ucode->init_data_size);
  4058. boot_size = le32_to_cpu(ucode->boot_size);
  4059. /* api_ver should match the api version forming part of the
  4060. * firmware filename ... but we don't check for that and only rely
  4061. * on the API version read from firware header from here on forward */
  4062. if (api_ver < api_min || api_ver > api_max) {
  4063. IWL_ERR(priv, "Driver unable to support your firmware API. "
  4064. "Driver supports v%u, firmware is v%u.\n",
  4065. api_max, api_ver);
  4066. priv->ucode_ver = 0;
  4067. ret = -EINVAL;
  4068. goto err_release;
  4069. }
  4070. if (api_ver != api_max)
  4071. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  4072. "got %u. New firmware can be obtained "
  4073. "from http://www.intellinuxwireless.org.\n",
  4074. api_max, api_ver);
  4075. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  4076. IWL_UCODE_MAJOR(priv->ucode_ver),
  4077. IWL_UCODE_MINOR(priv->ucode_ver),
  4078. IWL_UCODE_API(priv->ucode_ver),
  4079. IWL_UCODE_SERIAL(priv->ucode_ver));
  4080. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4081. priv->ucode_ver);
  4082. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4083. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4084. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4085. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4086. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4087. /* Verify size of file vs. image size info in file's header */
  4088. if (ucode_raw->size < sizeof(*ucode) +
  4089. inst_size + data_size + init_size +
  4090. init_data_size + boot_size) {
  4091. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4092. (int)ucode_raw->size);
  4093. ret = -EINVAL;
  4094. goto err_release;
  4095. }
  4096. /* Verify that uCode images will fit in card's SRAM */
  4097. if (inst_size > IWL39_MAX_INST_SIZE) {
  4098. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4099. inst_size);
  4100. ret = -EINVAL;
  4101. goto err_release;
  4102. }
  4103. if (data_size > IWL39_MAX_DATA_SIZE) {
  4104. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4105. data_size);
  4106. ret = -EINVAL;
  4107. goto err_release;
  4108. }
  4109. if (init_size > IWL39_MAX_INST_SIZE) {
  4110. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4111. init_size);
  4112. ret = -EINVAL;
  4113. goto err_release;
  4114. }
  4115. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4116. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4117. init_data_size);
  4118. ret = -EINVAL;
  4119. goto err_release;
  4120. }
  4121. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4122. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4123. boot_size);
  4124. ret = -EINVAL;
  4125. goto err_release;
  4126. }
  4127. /* Allocate ucode buffers for card's bus-master loading ... */
  4128. /* Runtime instructions and 2 copies of data:
  4129. * 1) unmodified from disk
  4130. * 2) backup cache for save/restore during power-downs */
  4131. priv->ucode_code.len = inst_size;
  4132. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4133. priv->ucode_data.len = data_size;
  4134. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4135. priv->ucode_data_backup.len = data_size;
  4136. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4137. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4138. !priv->ucode_data_backup.v_addr)
  4139. goto err_pci_alloc;
  4140. /* Initialization instructions and data */
  4141. if (init_size && init_data_size) {
  4142. priv->ucode_init.len = init_size;
  4143. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4144. priv->ucode_init_data.len = init_data_size;
  4145. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4146. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4147. goto err_pci_alloc;
  4148. }
  4149. /* Bootstrap (instructions only, no data) */
  4150. if (boot_size) {
  4151. priv->ucode_boot.len = boot_size;
  4152. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4153. if (!priv->ucode_boot.v_addr)
  4154. goto err_pci_alloc;
  4155. }
  4156. /* Copy images into buffers for card's bus-master reads ... */
  4157. /* Runtime instructions (first block of data in file) */
  4158. src = &ucode->data[0];
  4159. len = priv->ucode_code.len;
  4160. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4161. memcpy(priv->ucode_code.v_addr, src, len);
  4162. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4163. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4164. /* Runtime data (2nd block)
  4165. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4166. src = &ucode->data[inst_size];
  4167. len = priv->ucode_data.len;
  4168. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4169. memcpy(priv->ucode_data.v_addr, src, len);
  4170. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4171. /* Initialization instructions (3rd block) */
  4172. if (init_size) {
  4173. src = &ucode->data[inst_size + data_size];
  4174. len = priv->ucode_init.len;
  4175. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4176. len);
  4177. memcpy(priv->ucode_init.v_addr, src, len);
  4178. }
  4179. /* Initialization data (4th block) */
  4180. if (init_data_size) {
  4181. src = &ucode->data[inst_size + data_size + init_size];
  4182. len = priv->ucode_init_data.len;
  4183. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4184. (int)len);
  4185. memcpy(priv->ucode_init_data.v_addr, src, len);
  4186. }
  4187. /* Bootstrap instructions (5th block) */
  4188. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4189. len = priv->ucode_boot.len;
  4190. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4191. (int)len);
  4192. memcpy(priv->ucode_boot.v_addr, src, len);
  4193. /* We have our copies now, allow OS release its copies */
  4194. release_firmware(ucode_raw);
  4195. return 0;
  4196. err_pci_alloc:
  4197. IWL_ERR(priv, "failed to allocate pci memory\n");
  4198. ret = -ENOMEM;
  4199. iwl3945_dealloc_ucode_pci(priv);
  4200. err_release:
  4201. release_firmware(ucode_raw);
  4202. error:
  4203. return ret;
  4204. }
  4205. /**
  4206. * iwl3945_set_ucode_ptrs - Set uCode address location
  4207. *
  4208. * Tell initialization uCode where to find runtime uCode.
  4209. *
  4210. * BSM registers initially contain pointers to initialization uCode.
  4211. * We need to replace them to load runtime uCode inst and data,
  4212. * and to save runtime data when powering down.
  4213. */
  4214. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  4215. {
  4216. dma_addr_t pinst;
  4217. dma_addr_t pdata;
  4218. int rc = 0;
  4219. unsigned long flags;
  4220. /* bits 31:0 for 3945 */
  4221. pinst = priv->ucode_code.p_addr;
  4222. pdata = priv->ucode_data_backup.p_addr;
  4223. spin_lock_irqsave(&priv->lock, flags);
  4224. rc = iwl_grab_nic_access(priv);
  4225. if (rc) {
  4226. spin_unlock_irqrestore(&priv->lock, flags);
  4227. return rc;
  4228. }
  4229. /* Tell bootstrap uCode where to find image to load */
  4230. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4231. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4232. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4233. priv->ucode_data.len);
  4234. /* Inst byte count must be last to set up, bit 31 signals uCode
  4235. * that all new ptr/size info is in place */
  4236. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4237. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4238. iwl_release_nic_access(priv);
  4239. spin_unlock_irqrestore(&priv->lock, flags);
  4240. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4241. return rc;
  4242. }
  4243. /**
  4244. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4245. *
  4246. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4247. *
  4248. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4249. */
  4250. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  4251. {
  4252. /* Check alive response for "valid" sign from uCode */
  4253. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4254. /* We had an error bringing up the hardware, so take it
  4255. * all the way back down so we can try again */
  4256. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4257. goto restart;
  4258. }
  4259. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4260. * This is a paranoid check, because we would not have gotten the
  4261. * "initialize" alive if code weren't properly loaded. */
  4262. if (iwl3945_verify_ucode(priv)) {
  4263. /* Runtime instruction load was bad;
  4264. * take it all the way back down so we can try again */
  4265. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4266. goto restart;
  4267. }
  4268. /* Send pointers to protocol/runtime uCode image ... init code will
  4269. * load and launch runtime uCode, which will send us another "Alive"
  4270. * notification. */
  4271. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4272. if (iwl3945_set_ucode_ptrs(priv)) {
  4273. /* Runtime instruction load won't happen;
  4274. * take it all the way back down so we can try again */
  4275. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4276. goto restart;
  4277. }
  4278. return;
  4279. restart:
  4280. queue_work(priv->workqueue, &priv->restart);
  4281. }
  4282. /* temporary */
  4283. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4284. struct sk_buff *skb);
  4285. /**
  4286. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4287. * from protocol/runtime uCode (initialization uCode's
  4288. * Alive gets handled by iwl3945_init_alive_start()).
  4289. */
  4290. static void iwl3945_alive_start(struct iwl_priv *priv)
  4291. {
  4292. int rc = 0;
  4293. int thermal_spin = 0;
  4294. u32 rfkill;
  4295. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4296. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4297. /* We had an error bringing up the hardware, so take it
  4298. * all the way back down so we can try again */
  4299. IWL_DEBUG_INFO("Alive failed.\n");
  4300. goto restart;
  4301. }
  4302. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4303. * This is a paranoid check, because we would not have gotten the
  4304. * "runtime" alive if code weren't properly loaded. */
  4305. if (iwl3945_verify_ucode(priv)) {
  4306. /* Runtime instruction load was bad;
  4307. * take it all the way back down so we can try again */
  4308. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4309. goto restart;
  4310. }
  4311. iwl3945_clear_stations_table(priv);
  4312. rc = iwl_grab_nic_access(priv);
  4313. if (rc) {
  4314. IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
  4315. return;
  4316. }
  4317. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  4318. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4319. iwl_release_nic_access(priv);
  4320. if (rfkill & 0x1) {
  4321. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4322. /* if RFKILL is not on, then wait for thermal
  4323. * sensor in adapter to kick in */
  4324. while (iwl3945_hw_get_temperature(priv) == 0) {
  4325. thermal_spin++;
  4326. udelay(10);
  4327. }
  4328. if (thermal_spin)
  4329. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4330. thermal_spin * 10);
  4331. } else
  4332. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4333. /* After the ALIVE response, we can send commands to 3945 uCode */
  4334. set_bit(STATUS_ALIVE, &priv->status);
  4335. /* Clear out the uCode error bit if it is set */
  4336. clear_bit(STATUS_FW_ERROR, &priv->status);
  4337. if (iwl_is_rfkill(priv))
  4338. return;
  4339. ieee80211_wake_queues(priv->hw);
  4340. priv->active_rate = priv->rates_mask;
  4341. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4342. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4343. if (iwl3945_is_associated(priv)) {
  4344. struct iwl3945_rxon_cmd *active_rxon =
  4345. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  4346. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  4347. sizeof(priv->staging39_rxon));
  4348. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4349. } else {
  4350. /* Initialize our rx_config data */
  4351. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4352. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4353. }
  4354. /* Configure Bluetooth device coexistence support */
  4355. iwl3945_send_bt_config(priv);
  4356. /* Configure the adapter for unassociated operation */
  4357. iwl3945_commit_rxon(priv);
  4358. iwl3945_reg_txpower_periodic(priv);
  4359. iwl3945_led_register(priv);
  4360. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4361. set_bit(STATUS_READY, &priv->status);
  4362. wake_up_interruptible(&priv->wait_command_queue);
  4363. if (priv->error_recovering)
  4364. iwl3945_error_recovery(priv);
  4365. /* reassociate for ADHOC mode */
  4366. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4367. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4368. priv->vif);
  4369. if (beacon)
  4370. iwl3945_mac_beacon_update(priv->hw, beacon);
  4371. }
  4372. return;
  4373. restart:
  4374. queue_work(priv->workqueue, &priv->restart);
  4375. }
  4376. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  4377. static void __iwl3945_down(struct iwl_priv *priv)
  4378. {
  4379. unsigned long flags;
  4380. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4381. struct ieee80211_conf *conf = NULL;
  4382. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4383. conf = ieee80211_get_hw_conf(priv->hw);
  4384. if (!exit_pending)
  4385. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4386. iwl3945_led_unregister(priv);
  4387. iwl3945_clear_stations_table(priv);
  4388. /* Unblock any waiting calls */
  4389. wake_up_interruptible_all(&priv->wait_command_queue);
  4390. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4391. * exiting the module */
  4392. if (!exit_pending)
  4393. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4394. /* stop and reset the on-board processor */
  4395. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4396. /* tell the device to stop sending interrupts */
  4397. spin_lock_irqsave(&priv->lock, flags);
  4398. iwl3945_disable_interrupts(priv);
  4399. spin_unlock_irqrestore(&priv->lock, flags);
  4400. iwl_synchronize_irq(priv);
  4401. if (priv->mac80211_registered)
  4402. ieee80211_stop_queues(priv->hw);
  4403. /* If we have not previously called iwl3945_init() then
  4404. * clear all bits but the RF Kill and SUSPEND bits and return */
  4405. if (!iwl_is_init(priv)) {
  4406. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4407. STATUS_RF_KILL_HW |
  4408. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4409. STATUS_RF_KILL_SW |
  4410. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4411. STATUS_GEO_CONFIGURED |
  4412. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4413. STATUS_IN_SUSPEND |
  4414. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4415. STATUS_EXIT_PENDING;
  4416. goto exit;
  4417. }
  4418. /* ...otherwise clear out all the status bits but the RF Kill and
  4419. * SUSPEND bits and continue taking the NIC down. */
  4420. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4421. STATUS_RF_KILL_HW |
  4422. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4423. STATUS_RF_KILL_SW |
  4424. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4425. STATUS_GEO_CONFIGURED |
  4426. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4427. STATUS_IN_SUSPEND |
  4428. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4429. STATUS_FW_ERROR |
  4430. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4431. STATUS_EXIT_PENDING;
  4432. spin_lock_irqsave(&priv->lock, flags);
  4433. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4434. spin_unlock_irqrestore(&priv->lock, flags);
  4435. iwl3945_hw_txq_ctx_stop(priv);
  4436. iwl3945_hw_rxq_stop(priv);
  4437. spin_lock_irqsave(&priv->lock, flags);
  4438. if (!iwl_grab_nic_access(priv)) {
  4439. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  4440. APMG_CLK_VAL_DMA_CLK_RQT);
  4441. iwl_release_nic_access(priv);
  4442. }
  4443. spin_unlock_irqrestore(&priv->lock, flags);
  4444. udelay(5);
  4445. priv->cfg->ops->lib->apm_ops.reset(priv);
  4446. exit:
  4447. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4448. if (priv->ibss_beacon)
  4449. dev_kfree_skb(priv->ibss_beacon);
  4450. priv->ibss_beacon = NULL;
  4451. /* clear out any free frames */
  4452. iwl3945_clear_free_frames(priv);
  4453. }
  4454. static void iwl3945_down(struct iwl_priv *priv)
  4455. {
  4456. mutex_lock(&priv->mutex);
  4457. __iwl3945_down(priv);
  4458. mutex_unlock(&priv->mutex);
  4459. iwl3945_cancel_deferred_work(priv);
  4460. }
  4461. #define MAX_HW_RESTARTS 5
  4462. static int __iwl3945_up(struct iwl_priv *priv)
  4463. {
  4464. int rc, i;
  4465. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4466. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  4467. return -EIO;
  4468. }
  4469. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4470. IWL_WARN(priv, "Radio disabled by SW RF kill (module "
  4471. "parameter)\n");
  4472. return -ENODEV;
  4473. }
  4474. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4475. IWL_ERR(priv, "ucode not available for device bring up\n");
  4476. return -EIO;
  4477. }
  4478. /* If platform's RF_KILL switch is NOT set to KILL */
  4479. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4480. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4481. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4482. else {
  4483. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4484. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4485. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  4486. return -ENODEV;
  4487. }
  4488. }
  4489. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4490. rc = iwl3945_hw_nic_init(priv);
  4491. if (rc) {
  4492. IWL_ERR(priv, "Unable to int nic\n");
  4493. return rc;
  4494. }
  4495. /* make sure rfkill handshake bits are cleared */
  4496. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4497. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4498. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4499. /* clear (again), then enable host interrupts */
  4500. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4501. iwl3945_enable_interrupts(priv);
  4502. /* really make sure rfkill handshake bits are cleared */
  4503. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4504. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4505. /* Copy original ucode data image from disk into backup cache.
  4506. * This will be used to initialize the on-board processor's
  4507. * data SRAM for a clean start when the runtime program first loads. */
  4508. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4509. priv->ucode_data.len);
  4510. /* We return success when we resume from suspend and rf_kill is on. */
  4511. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4512. return 0;
  4513. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4514. iwl3945_clear_stations_table(priv);
  4515. /* load bootstrap state machine,
  4516. * load bootstrap program into processor's memory,
  4517. * prepare to load the "initialize" uCode */
  4518. priv->cfg->ops->lib->load_ucode(priv);
  4519. if (rc) {
  4520. IWL_ERR(priv,
  4521. "Unable to set up bootstrap uCode: %d\n", rc);
  4522. continue;
  4523. }
  4524. /* start card; "initialize" will load runtime ucode */
  4525. iwl3945_nic_start(priv);
  4526. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4527. return 0;
  4528. }
  4529. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4530. __iwl3945_down(priv);
  4531. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4532. /* tried to restart and config the device for as long as our
  4533. * patience could withstand */
  4534. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  4535. return -EIO;
  4536. }
  4537. /*****************************************************************************
  4538. *
  4539. * Workqueue callbacks
  4540. *
  4541. *****************************************************************************/
  4542. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4543. {
  4544. struct iwl_priv *priv =
  4545. container_of(data, struct iwl_priv, init_alive_start.work);
  4546. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4547. return;
  4548. mutex_lock(&priv->mutex);
  4549. iwl3945_init_alive_start(priv);
  4550. mutex_unlock(&priv->mutex);
  4551. }
  4552. static void iwl3945_bg_alive_start(struct work_struct *data)
  4553. {
  4554. struct iwl_priv *priv =
  4555. container_of(data, struct iwl_priv, alive_start.work);
  4556. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4557. return;
  4558. mutex_lock(&priv->mutex);
  4559. iwl3945_alive_start(priv);
  4560. mutex_unlock(&priv->mutex);
  4561. }
  4562. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4563. {
  4564. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  4565. wake_up_interruptible(&priv->wait_command_queue);
  4566. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4567. return;
  4568. mutex_lock(&priv->mutex);
  4569. if (!iwl_is_rfkill(priv)) {
  4570. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4571. "HW and/or SW RF Kill no longer active, restarting "
  4572. "device\n");
  4573. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4574. queue_work(priv->workqueue, &priv->restart);
  4575. } else {
  4576. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4577. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4578. "disabled by SW switch\n");
  4579. else
  4580. IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
  4581. "Kill switch must be turned off for "
  4582. "wireless networking to work.\n");
  4583. }
  4584. mutex_unlock(&priv->mutex);
  4585. iwl3945_rfkill_set_hw_state(priv);
  4586. }
  4587. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4588. static void iwl3945_bg_scan_check(struct work_struct *data)
  4589. {
  4590. struct iwl_priv *priv =
  4591. container_of(data, struct iwl_priv, scan_check.work);
  4592. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4593. return;
  4594. mutex_lock(&priv->mutex);
  4595. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4596. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4597. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4598. "Scan completion watchdog resetting adapter (%dms)\n",
  4599. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4600. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4601. iwl3945_send_scan_abort(priv);
  4602. }
  4603. mutex_unlock(&priv->mutex);
  4604. }
  4605. static void iwl3945_bg_request_scan(struct work_struct *data)
  4606. {
  4607. struct iwl_priv *priv =
  4608. container_of(data, struct iwl_priv, request_scan);
  4609. struct iwl_host_cmd cmd = {
  4610. .id = REPLY_SCAN_CMD,
  4611. .len = sizeof(struct iwl3945_scan_cmd),
  4612. .meta.flags = CMD_SIZE_HUGE,
  4613. };
  4614. int rc = 0;
  4615. struct iwl3945_scan_cmd *scan;
  4616. struct ieee80211_conf *conf = NULL;
  4617. u8 n_probes = 2;
  4618. enum ieee80211_band band;
  4619. DECLARE_SSID_BUF(ssid);
  4620. conf = ieee80211_get_hw_conf(priv->hw);
  4621. mutex_lock(&priv->mutex);
  4622. if (!iwl_is_ready(priv)) {
  4623. IWL_WARN(priv, "request scan called when driver not ready.\n");
  4624. goto done;
  4625. }
  4626. /* Make sure the scan wasn't canceled before this queued work
  4627. * was given the chance to run... */
  4628. if (!test_bit(STATUS_SCANNING, &priv->status))
  4629. goto done;
  4630. /* This should never be called or scheduled if there is currently
  4631. * a scan active in the hardware. */
  4632. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  4633. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  4634. "Ignoring second request.\n");
  4635. rc = -EIO;
  4636. goto done;
  4637. }
  4638. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4639. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  4640. goto done;
  4641. }
  4642. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4643. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  4644. goto done;
  4645. }
  4646. if (iwl_is_rfkill(priv)) {
  4647. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  4648. goto done;
  4649. }
  4650. if (!test_bit(STATUS_READY, &priv->status)) {
  4651. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  4652. goto done;
  4653. }
  4654. if (!priv->scan_bands) {
  4655. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  4656. goto done;
  4657. }
  4658. if (!priv->scan39) {
  4659. priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  4660. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  4661. if (!priv->scan39) {
  4662. rc = -ENOMEM;
  4663. goto done;
  4664. }
  4665. }
  4666. scan = priv->scan39;
  4667. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  4668. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  4669. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  4670. if (iwl3945_is_associated(priv)) {
  4671. u16 interval = 0;
  4672. u32 extra;
  4673. u32 suspend_time = 100;
  4674. u32 scan_suspend_time = 100;
  4675. unsigned long flags;
  4676. IWL_DEBUG_INFO("Scanning while associated...\n");
  4677. spin_lock_irqsave(&priv->lock, flags);
  4678. interval = priv->beacon_int;
  4679. spin_unlock_irqrestore(&priv->lock, flags);
  4680. scan->suspend_time = 0;
  4681. scan->max_out_time = cpu_to_le32(200 * 1024);
  4682. if (!interval)
  4683. interval = suspend_time;
  4684. /*
  4685. * suspend time format:
  4686. * 0-19: beacon interval in usec (time before exec.)
  4687. * 20-23: 0
  4688. * 24-31: number of beacons (suspend between channels)
  4689. */
  4690. extra = (suspend_time / interval) << 24;
  4691. scan_suspend_time = 0xFF0FFFFF &
  4692. (extra | ((suspend_time % interval) * 1024));
  4693. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  4694. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  4695. scan_suspend_time, interval);
  4696. }
  4697. /* We should add the ability for user to lock to PASSIVE ONLY */
  4698. if (priv->one_direct_scan) {
  4699. IWL_DEBUG_SCAN
  4700. ("Kicking off one direct scan for '%s'\n",
  4701. print_ssid(ssid, priv->direct_ssid,
  4702. priv->direct_ssid_len));
  4703. scan->direct_scan[0].id = WLAN_EID_SSID;
  4704. scan->direct_scan[0].len = priv->direct_ssid_len;
  4705. memcpy(scan->direct_scan[0].ssid,
  4706. priv->direct_ssid, priv->direct_ssid_len);
  4707. n_probes++;
  4708. } else
  4709. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  4710. /* We don't build a direct scan probe request; the uCode will do
  4711. * that based on the direct_mask added to each channel entry */
  4712. scan->tx_cmd.len = cpu_to_le16(
  4713. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  4714. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  4715. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  4716. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  4717. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  4718. /* flags + rate selection */
  4719. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  4720. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  4721. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  4722. scan->good_CRC_th = 0;
  4723. band = IEEE80211_BAND_2GHZ;
  4724. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  4725. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  4726. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  4727. band = IEEE80211_BAND_5GHZ;
  4728. } else {
  4729. IWL_WARN(priv, "Invalid scan band count\n");
  4730. goto done;
  4731. }
  4732. /* select Rx antennas */
  4733. scan->flags |= iwl3945_get_antenna_flags(priv);
  4734. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  4735. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  4736. scan->channel_count =
  4737. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  4738. n_probes,
  4739. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  4740. if (scan->channel_count == 0) {
  4741. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  4742. goto done;
  4743. }
  4744. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  4745. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  4746. cmd.data = scan;
  4747. scan->len = cpu_to_le16(cmd.len);
  4748. set_bit(STATUS_SCAN_HW, &priv->status);
  4749. rc = iwl3945_send_cmd_sync(priv, &cmd);
  4750. if (rc)
  4751. goto done;
  4752. queue_delayed_work(priv->workqueue, &priv->scan_check,
  4753. IWL_SCAN_CHECK_WATCHDOG);
  4754. mutex_unlock(&priv->mutex);
  4755. return;
  4756. done:
  4757. /* can not perform scan make sure we clear scanning
  4758. * bits from status so next scan request can be performed.
  4759. * if we dont clear scanning status bit here all next scan
  4760. * will fail
  4761. */
  4762. clear_bit(STATUS_SCAN_HW, &priv->status);
  4763. clear_bit(STATUS_SCANNING, &priv->status);
  4764. /* inform mac80211 scan aborted */
  4765. queue_work(priv->workqueue, &priv->scan_completed);
  4766. mutex_unlock(&priv->mutex);
  4767. }
  4768. static void iwl3945_bg_up(struct work_struct *data)
  4769. {
  4770. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  4771. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4772. return;
  4773. mutex_lock(&priv->mutex);
  4774. __iwl3945_up(priv);
  4775. mutex_unlock(&priv->mutex);
  4776. iwl3945_rfkill_set_hw_state(priv);
  4777. }
  4778. static void iwl3945_bg_restart(struct work_struct *data)
  4779. {
  4780. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  4781. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4782. return;
  4783. iwl3945_down(priv);
  4784. queue_work(priv->workqueue, &priv->up);
  4785. }
  4786. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  4787. {
  4788. struct iwl_priv *priv =
  4789. container_of(data, struct iwl_priv, rx_replenish);
  4790. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4791. return;
  4792. mutex_lock(&priv->mutex);
  4793. iwl3945_rx_replenish(priv);
  4794. mutex_unlock(&priv->mutex);
  4795. }
  4796. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  4797. static void iwl3945_post_associate(struct iwl_priv *priv)
  4798. {
  4799. int rc = 0;
  4800. struct ieee80211_conf *conf = NULL;
  4801. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4802. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  4803. return;
  4804. }
  4805. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  4806. priv->assoc_id, priv->active39_rxon.bssid_addr);
  4807. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4808. return;
  4809. if (!priv->vif || !priv->is_open)
  4810. return;
  4811. iwl3945_scan_cancel_timeout(priv, 200);
  4812. conf = ieee80211_get_hw_conf(priv->hw);
  4813. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4814. iwl3945_commit_rxon(priv);
  4815. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4816. iwl3945_setup_rxon_timing(priv);
  4817. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4818. sizeof(priv->rxon_timing), &priv->rxon_timing);
  4819. if (rc)
  4820. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4821. "Attempting to continue.\n");
  4822. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4823. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4824. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  4825. priv->assoc_id, priv->beacon_int);
  4826. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4827. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4828. else
  4829. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4830. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4831. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4832. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  4833. else
  4834. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4835. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4836. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4837. }
  4838. iwl3945_commit_rxon(priv);
  4839. switch (priv->iw_mode) {
  4840. case NL80211_IFTYPE_STATION:
  4841. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  4842. break;
  4843. case NL80211_IFTYPE_ADHOC:
  4844. priv->assoc_id = 1;
  4845. iwl3945_add_station(priv, priv->bssid, 0, 0);
  4846. iwl3945_sync_sta(priv, IWL_STA_ID,
  4847. (priv->band == IEEE80211_BAND_5GHZ) ?
  4848. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  4849. CMD_ASYNC);
  4850. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  4851. iwl3945_send_beacon_cmd(priv);
  4852. break;
  4853. default:
  4854. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  4855. __func__, priv->iw_mode);
  4856. break;
  4857. }
  4858. iwl3945_activate_qos(priv, 0);
  4859. /* we have just associated, don't start scan too early */
  4860. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  4861. }
  4862. static void iwl3945_bg_abort_scan(struct work_struct *work)
  4863. {
  4864. struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
  4865. if (!iwl_is_ready(priv))
  4866. return;
  4867. mutex_lock(&priv->mutex);
  4868. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  4869. iwl3945_send_scan_abort(priv);
  4870. mutex_unlock(&priv->mutex);
  4871. }
  4872. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  4873. static void iwl3945_bg_scan_completed(struct work_struct *work)
  4874. {
  4875. struct iwl_priv *priv =
  4876. container_of(work, struct iwl_priv, scan_completed);
  4877. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  4878. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4879. return;
  4880. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  4881. iwl3945_mac_config(priv->hw, 0);
  4882. ieee80211_scan_completed(priv->hw);
  4883. /* Since setting the TXPOWER may have been deferred while
  4884. * performing the scan, fire one off */
  4885. mutex_lock(&priv->mutex);
  4886. iwl3945_hw_reg_send_txpower(priv);
  4887. mutex_unlock(&priv->mutex);
  4888. }
  4889. /*****************************************************************************
  4890. *
  4891. * mac80211 entry point functions
  4892. *
  4893. *****************************************************************************/
  4894. #define UCODE_READY_TIMEOUT (2 * HZ)
  4895. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  4896. {
  4897. struct iwl_priv *priv = hw->priv;
  4898. int ret;
  4899. IWL_DEBUG_MAC80211("enter\n");
  4900. if (pci_enable_device(priv->pci_dev)) {
  4901. IWL_ERR(priv, "Fail to pci_enable_device\n");
  4902. return -ENODEV;
  4903. }
  4904. pci_restore_state(priv->pci_dev);
  4905. pci_enable_msi(priv->pci_dev);
  4906. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  4907. DRV_NAME, priv);
  4908. if (ret) {
  4909. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  4910. goto out_disable_msi;
  4911. }
  4912. /* we should be verifying the device is ready to be opened */
  4913. mutex_lock(&priv->mutex);
  4914. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  4915. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  4916. * ucode filename and max sizes are card-specific. */
  4917. if (!priv->ucode_code.len) {
  4918. ret = iwl3945_read_ucode(priv);
  4919. if (ret) {
  4920. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  4921. mutex_unlock(&priv->mutex);
  4922. goto out_release_irq;
  4923. }
  4924. }
  4925. ret = __iwl3945_up(priv);
  4926. mutex_unlock(&priv->mutex);
  4927. iwl3945_rfkill_set_hw_state(priv);
  4928. if (ret)
  4929. goto out_release_irq;
  4930. IWL_DEBUG_INFO("Start UP work.\n");
  4931. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  4932. return 0;
  4933. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  4934. * mac80211 will not be run successfully. */
  4935. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  4936. test_bit(STATUS_READY, &priv->status),
  4937. UCODE_READY_TIMEOUT);
  4938. if (!ret) {
  4939. if (!test_bit(STATUS_READY, &priv->status)) {
  4940. IWL_ERR(priv,
  4941. "Wait for START_ALIVE timeout after %dms.\n",
  4942. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  4943. ret = -ETIMEDOUT;
  4944. goto out_release_irq;
  4945. }
  4946. }
  4947. priv->is_open = 1;
  4948. IWL_DEBUG_MAC80211("leave\n");
  4949. return 0;
  4950. out_release_irq:
  4951. free_irq(priv->pci_dev->irq, priv);
  4952. out_disable_msi:
  4953. pci_disable_msi(priv->pci_dev);
  4954. pci_disable_device(priv->pci_dev);
  4955. priv->is_open = 0;
  4956. IWL_DEBUG_MAC80211("leave - failed\n");
  4957. return ret;
  4958. }
  4959. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  4960. {
  4961. struct iwl_priv *priv = hw->priv;
  4962. IWL_DEBUG_MAC80211("enter\n");
  4963. if (!priv->is_open) {
  4964. IWL_DEBUG_MAC80211("leave - skip\n");
  4965. return;
  4966. }
  4967. priv->is_open = 0;
  4968. if (iwl_is_ready_rf(priv)) {
  4969. /* stop mac, cancel any scan request and clear
  4970. * RXON_FILTER_ASSOC_MSK BIT
  4971. */
  4972. mutex_lock(&priv->mutex);
  4973. iwl3945_scan_cancel_timeout(priv, 100);
  4974. mutex_unlock(&priv->mutex);
  4975. }
  4976. iwl3945_down(priv);
  4977. flush_workqueue(priv->workqueue);
  4978. free_irq(priv->pci_dev->irq, priv);
  4979. pci_disable_msi(priv->pci_dev);
  4980. pci_save_state(priv->pci_dev);
  4981. pci_disable_device(priv->pci_dev);
  4982. IWL_DEBUG_MAC80211("leave\n");
  4983. }
  4984. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  4985. {
  4986. struct iwl_priv *priv = hw->priv;
  4987. IWL_DEBUG_MAC80211("enter\n");
  4988. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  4989. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  4990. if (iwl3945_tx_skb(priv, skb))
  4991. dev_kfree_skb_any(skb);
  4992. IWL_DEBUG_MAC80211("leave\n");
  4993. return NETDEV_TX_OK;
  4994. }
  4995. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  4996. struct ieee80211_if_init_conf *conf)
  4997. {
  4998. struct iwl_priv *priv = hw->priv;
  4999. unsigned long flags;
  5000. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5001. if (priv->vif) {
  5002. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5003. return -EOPNOTSUPP;
  5004. }
  5005. spin_lock_irqsave(&priv->lock, flags);
  5006. priv->vif = conf->vif;
  5007. priv->iw_mode = conf->type;
  5008. spin_unlock_irqrestore(&priv->lock, flags);
  5009. mutex_lock(&priv->mutex);
  5010. if (conf->mac_addr) {
  5011. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5012. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5013. }
  5014. if (iwl_is_ready(priv))
  5015. iwl3945_set_mode(priv, conf->type);
  5016. mutex_unlock(&priv->mutex);
  5017. IWL_DEBUG_MAC80211("leave\n");
  5018. return 0;
  5019. }
  5020. /**
  5021. * iwl3945_mac_config - mac80211 config callback
  5022. *
  5023. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5024. * be set inappropriately and the driver currently sets the hardware up to
  5025. * use it whenever needed.
  5026. */
  5027. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5028. {
  5029. struct iwl_priv *priv = hw->priv;
  5030. const struct iwl_channel_info *ch_info;
  5031. struct ieee80211_conf *conf = &hw->conf;
  5032. unsigned long flags;
  5033. int ret = 0;
  5034. mutex_lock(&priv->mutex);
  5035. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5036. if (!iwl_is_ready(priv)) {
  5037. IWL_DEBUG_MAC80211("leave - not ready\n");
  5038. ret = -EIO;
  5039. goto out;
  5040. }
  5041. if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
  5042. test_bit(STATUS_SCANNING, &priv->status))) {
  5043. IWL_DEBUG_MAC80211("leave - scanning\n");
  5044. set_bit(STATUS_CONF_PENDING, &priv->status);
  5045. mutex_unlock(&priv->mutex);
  5046. return 0;
  5047. }
  5048. spin_lock_irqsave(&priv->lock, flags);
  5049. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5050. conf->channel->hw_value);
  5051. if (!is_channel_valid(ch_info)) {
  5052. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5053. conf->channel->hw_value, conf->channel->band);
  5054. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5055. spin_unlock_irqrestore(&priv->lock, flags);
  5056. ret = -EINVAL;
  5057. goto out;
  5058. }
  5059. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5060. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5061. /* The list of supported rates and rate mask can be different
  5062. * for each phymode; since the phymode may have changed, reset
  5063. * the rate mask to what mac80211 lists */
  5064. iwl3945_set_rate(priv);
  5065. spin_unlock_irqrestore(&priv->lock, flags);
  5066. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5067. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5068. iwl3945_hw_channel_switch(priv, conf->channel);
  5069. goto out;
  5070. }
  5071. #endif
  5072. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5073. if (!conf->radio_enabled) {
  5074. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5075. goto out;
  5076. }
  5077. if (iwl_is_rfkill(priv)) {
  5078. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5079. ret = -EIO;
  5080. goto out;
  5081. }
  5082. iwl3945_set_rate(priv);
  5083. if (memcmp(&priv->active39_rxon,
  5084. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  5085. iwl3945_commit_rxon(priv);
  5086. else
  5087. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5088. IWL_DEBUG_MAC80211("leave\n");
  5089. out:
  5090. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5091. mutex_unlock(&priv->mutex);
  5092. return ret;
  5093. }
  5094. static void iwl3945_config_ap(struct iwl_priv *priv)
  5095. {
  5096. int rc = 0;
  5097. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5098. return;
  5099. /* The following should be done only at AP bring up */
  5100. if (!(iwl3945_is_associated(priv))) {
  5101. /* RXON - unassoc (to set timing command) */
  5102. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5103. iwl3945_commit_rxon(priv);
  5104. /* RXON Timing */
  5105. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5106. iwl3945_setup_rxon_timing(priv);
  5107. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5108. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5109. if (rc)
  5110. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  5111. "Attempting to continue.\n");
  5112. /* FIXME: what should be the assoc_id for AP? */
  5113. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5114. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5115. priv->staging39_rxon.flags |=
  5116. RXON_FLG_SHORT_PREAMBLE_MSK;
  5117. else
  5118. priv->staging39_rxon.flags &=
  5119. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5120. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5121. if (priv->assoc_capability &
  5122. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5123. priv->staging39_rxon.flags |=
  5124. RXON_FLG_SHORT_SLOT_MSK;
  5125. else
  5126. priv->staging39_rxon.flags &=
  5127. ~RXON_FLG_SHORT_SLOT_MSK;
  5128. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5129. priv->staging39_rxon.flags &=
  5130. ~RXON_FLG_SHORT_SLOT_MSK;
  5131. }
  5132. /* restore RXON assoc */
  5133. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5134. iwl3945_commit_rxon(priv);
  5135. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  5136. }
  5137. iwl3945_send_beacon_cmd(priv);
  5138. /* FIXME - we need to add code here to detect a totally new
  5139. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5140. * clear sta table, add BCAST sta... */
  5141. }
  5142. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5143. struct ieee80211_vif *vif,
  5144. struct ieee80211_if_conf *conf)
  5145. {
  5146. struct iwl_priv *priv = hw->priv;
  5147. int rc;
  5148. if (conf == NULL)
  5149. return -EIO;
  5150. if (priv->vif != vif) {
  5151. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5152. return 0;
  5153. }
  5154. /* handle this temporarily here */
  5155. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5156. conf->changed & IEEE80211_IFCC_BEACON) {
  5157. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5158. if (!beacon)
  5159. return -ENOMEM;
  5160. mutex_lock(&priv->mutex);
  5161. rc = iwl3945_mac_beacon_update(hw, beacon);
  5162. mutex_unlock(&priv->mutex);
  5163. if (rc)
  5164. return rc;
  5165. }
  5166. if (!iwl_is_alive(priv))
  5167. return -EAGAIN;
  5168. mutex_lock(&priv->mutex);
  5169. if (conf->bssid)
  5170. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5171. /*
  5172. * very dubious code was here; the probe filtering flag is never set:
  5173. *
  5174. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5175. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5176. */
  5177. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5178. if (!conf->bssid) {
  5179. conf->bssid = priv->mac_addr;
  5180. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5181. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5182. conf->bssid);
  5183. }
  5184. if (priv->ibss_beacon)
  5185. dev_kfree_skb(priv->ibss_beacon);
  5186. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5187. }
  5188. if (iwl_is_rfkill(priv))
  5189. goto done;
  5190. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5191. !is_multicast_ether_addr(conf->bssid)) {
  5192. /* If there is currently a HW scan going on in the background
  5193. * then we need to cancel it else the RXON below will fail. */
  5194. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5195. IWL_WARN(priv, "Aborted scan still in progress "
  5196. "after 100ms\n");
  5197. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5198. mutex_unlock(&priv->mutex);
  5199. return -EAGAIN;
  5200. }
  5201. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5202. /* TODO: Audit driver for usage of these members and see
  5203. * if mac80211 deprecates them (priv->bssid looks like it
  5204. * shouldn't be there, but I haven't scanned the IBSS code
  5205. * to verify) - jpk */
  5206. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5207. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5208. iwl3945_config_ap(priv);
  5209. else {
  5210. rc = iwl3945_commit_rxon(priv);
  5211. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5212. iwl3945_add_station(priv,
  5213. priv->active39_rxon.bssid_addr, 1, 0);
  5214. }
  5215. } else {
  5216. iwl3945_scan_cancel_timeout(priv, 100);
  5217. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5218. iwl3945_commit_rxon(priv);
  5219. }
  5220. done:
  5221. IWL_DEBUG_MAC80211("leave\n");
  5222. mutex_unlock(&priv->mutex);
  5223. return 0;
  5224. }
  5225. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5226. unsigned int changed_flags,
  5227. unsigned int *total_flags,
  5228. int mc_count, struct dev_addr_list *mc_list)
  5229. {
  5230. struct iwl_priv *priv = hw->priv;
  5231. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  5232. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5233. changed_flags, *total_flags);
  5234. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5235. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5236. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5237. else
  5238. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5239. }
  5240. if (changed_flags & FIF_ALLMULTI) {
  5241. if (*total_flags & FIF_ALLMULTI)
  5242. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5243. else
  5244. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5245. }
  5246. if (changed_flags & FIF_CONTROL) {
  5247. if (*total_flags & FIF_CONTROL)
  5248. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5249. else
  5250. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5251. }
  5252. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5253. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5254. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5255. else
  5256. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5257. }
  5258. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5259. * since mac80211 will call ieee80211_hw_config immediately.
  5260. * (mc_list is not supported at this time). Otherwise, we need to
  5261. * queue a background iwl_commit_rxon work.
  5262. */
  5263. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5264. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5265. }
  5266. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5267. struct ieee80211_if_init_conf *conf)
  5268. {
  5269. struct iwl_priv *priv = hw->priv;
  5270. IWL_DEBUG_MAC80211("enter\n");
  5271. mutex_lock(&priv->mutex);
  5272. if (iwl_is_ready_rf(priv)) {
  5273. iwl3945_scan_cancel_timeout(priv, 100);
  5274. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5275. iwl3945_commit_rxon(priv);
  5276. }
  5277. if (priv->vif == conf->vif) {
  5278. priv->vif = NULL;
  5279. memset(priv->bssid, 0, ETH_ALEN);
  5280. }
  5281. mutex_unlock(&priv->mutex);
  5282. IWL_DEBUG_MAC80211("leave\n");
  5283. }
  5284. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5285. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5286. struct ieee80211_vif *vif,
  5287. struct ieee80211_bss_conf *bss_conf,
  5288. u32 changes)
  5289. {
  5290. struct iwl_priv *priv = hw->priv;
  5291. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5292. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5293. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5294. bss_conf->use_short_preamble);
  5295. if (bss_conf->use_short_preamble)
  5296. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5297. else
  5298. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5299. }
  5300. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5301. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5302. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5303. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5304. else
  5305. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5306. }
  5307. if (changes & BSS_CHANGED_ASSOC) {
  5308. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5309. /* This should never happen as this function should
  5310. * never be called from interrupt context. */
  5311. if (WARN_ON_ONCE(in_interrupt()))
  5312. return;
  5313. if (bss_conf->assoc) {
  5314. priv->assoc_id = bss_conf->aid;
  5315. priv->beacon_int = bss_conf->beacon_int;
  5316. priv->timestamp = bss_conf->timestamp;
  5317. priv->assoc_capability = bss_conf->assoc_capability;
  5318. priv->next_scan_jiffies = jiffies +
  5319. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5320. mutex_lock(&priv->mutex);
  5321. iwl3945_post_associate(priv);
  5322. mutex_unlock(&priv->mutex);
  5323. } else {
  5324. priv->assoc_id = 0;
  5325. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5326. }
  5327. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5328. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5329. iwl3945_send_rxon_assoc(priv);
  5330. }
  5331. }
  5332. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5333. {
  5334. int rc = 0;
  5335. unsigned long flags;
  5336. struct iwl_priv *priv = hw->priv;
  5337. DECLARE_SSID_BUF(ssid_buf);
  5338. IWL_DEBUG_MAC80211("enter\n");
  5339. mutex_lock(&priv->mutex);
  5340. spin_lock_irqsave(&priv->lock, flags);
  5341. if (!iwl_is_ready_rf(priv)) {
  5342. rc = -EIO;
  5343. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5344. goto out_unlock;
  5345. }
  5346. /* we don't schedule scan within next_scan_jiffies period */
  5347. if (priv->next_scan_jiffies &&
  5348. time_after(priv->next_scan_jiffies, jiffies)) {
  5349. rc = -EAGAIN;
  5350. goto out_unlock;
  5351. }
  5352. /* if we just finished scan ask for delay for a broadcast scan */
  5353. if ((len == 0) && priv->last_scan_jiffies &&
  5354. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5355. jiffies)) {
  5356. rc = -EAGAIN;
  5357. goto out_unlock;
  5358. }
  5359. if (len) {
  5360. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5361. print_ssid(ssid_buf, ssid, len), (int)len);
  5362. priv->one_direct_scan = 1;
  5363. priv->direct_ssid_len = (u8)
  5364. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5365. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5366. } else
  5367. priv->one_direct_scan = 0;
  5368. rc = iwl3945_scan_initiate(priv);
  5369. IWL_DEBUG_MAC80211("leave\n");
  5370. out_unlock:
  5371. spin_unlock_irqrestore(&priv->lock, flags);
  5372. mutex_unlock(&priv->mutex);
  5373. return rc;
  5374. }
  5375. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5376. struct ieee80211_vif *vif,
  5377. struct ieee80211_sta *sta,
  5378. struct ieee80211_key_conf *key)
  5379. {
  5380. struct iwl_priv *priv = hw->priv;
  5381. const u8 *addr;
  5382. int rc = 0;
  5383. u8 sta_id;
  5384. static const u8 bcast_addr[ETH_ALEN] =
  5385. { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  5386. IWL_DEBUG_MAC80211("enter\n");
  5387. if (iwl3945_mod_params.sw_crypto) {
  5388. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5389. return -EOPNOTSUPP;
  5390. }
  5391. addr = sta ? sta->addr : bcast_addr;
  5392. sta_id = iwl3945_hw_find_station(priv, addr);
  5393. if (sta_id == IWL_INVALID_STATION) {
  5394. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5395. addr);
  5396. return -EINVAL;
  5397. }
  5398. mutex_lock(&priv->mutex);
  5399. iwl3945_scan_cancel_timeout(priv, 100);
  5400. switch (cmd) {
  5401. case SET_KEY:
  5402. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5403. if (!rc) {
  5404. iwl3945_set_rxon_hwcrypto(priv, 1);
  5405. iwl3945_commit_rxon(priv);
  5406. key->hw_key_idx = sta_id;
  5407. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5408. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5409. }
  5410. break;
  5411. case DISABLE_KEY:
  5412. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5413. if (!rc) {
  5414. iwl3945_set_rxon_hwcrypto(priv, 0);
  5415. iwl3945_commit_rxon(priv);
  5416. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5417. }
  5418. break;
  5419. default:
  5420. rc = -EINVAL;
  5421. }
  5422. IWL_DEBUG_MAC80211("leave\n");
  5423. mutex_unlock(&priv->mutex);
  5424. return rc;
  5425. }
  5426. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5427. const struct ieee80211_tx_queue_params *params)
  5428. {
  5429. struct iwl_priv *priv = hw->priv;
  5430. unsigned long flags;
  5431. int q;
  5432. IWL_DEBUG_MAC80211("enter\n");
  5433. if (!iwl_is_ready_rf(priv)) {
  5434. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5435. return -EIO;
  5436. }
  5437. if (queue >= AC_NUM) {
  5438. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5439. return 0;
  5440. }
  5441. q = AC_NUM - 1 - queue;
  5442. spin_lock_irqsave(&priv->lock, flags);
  5443. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5444. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5445. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5446. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5447. cpu_to_le16((params->txop * 32));
  5448. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5449. priv->qos_data.qos_active = 1;
  5450. spin_unlock_irqrestore(&priv->lock, flags);
  5451. mutex_lock(&priv->mutex);
  5452. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5453. iwl3945_activate_qos(priv, 1);
  5454. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5455. iwl3945_activate_qos(priv, 0);
  5456. mutex_unlock(&priv->mutex);
  5457. IWL_DEBUG_MAC80211("leave\n");
  5458. return 0;
  5459. }
  5460. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5461. struct ieee80211_tx_queue_stats *stats)
  5462. {
  5463. struct iwl_priv *priv = hw->priv;
  5464. int i, avail;
  5465. struct iwl_tx_queue *txq;
  5466. struct iwl_queue *q;
  5467. unsigned long flags;
  5468. IWL_DEBUG_MAC80211("enter\n");
  5469. if (!iwl_is_ready_rf(priv)) {
  5470. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5471. return -EIO;
  5472. }
  5473. spin_lock_irqsave(&priv->lock, flags);
  5474. for (i = 0; i < AC_NUM; i++) {
  5475. txq = &priv->txq[i];
  5476. q = &txq->q;
  5477. avail = iwl_queue_space(q);
  5478. stats[i].len = q->n_window - avail;
  5479. stats[i].limit = q->n_window - q->high_mark;
  5480. stats[i].count = q->n_window;
  5481. }
  5482. spin_unlock_irqrestore(&priv->lock, flags);
  5483. IWL_DEBUG_MAC80211("leave\n");
  5484. return 0;
  5485. }
  5486. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5487. {
  5488. struct iwl_priv *priv = hw->priv;
  5489. unsigned long flags;
  5490. mutex_lock(&priv->mutex);
  5491. IWL_DEBUG_MAC80211("enter\n");
  5492. iwl_reset_qos(priv);
  5493. spin_lock_irqsave(&priv->lock, flags);
  5494. priv->assoc_id = 0;
  5495. priv->assoc_capability = 0;
  5496. priv->call_post_assoc_from_beacon = 0;
  5497. /* new association get rid of ibss beacon skb */
  5498. if (priv->ibss_beacon)
  5499. dev_kfree_skb(priv->ibss_beacon);
  5500. priv->ibss_beacon = NULL;
  5501. priv->beacon_int = priv->hw->conf.beacon_int;
  5502. priv->timestamp = 0;
  5503. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5504. priv->beacon_int = 0;
  5505. spin_unlock_irqrestore(&priv->lock, flags);
  5506. if (!iwl_is_ready_rf(priv)) {
  5507. IWL_DEBUG_MAC80211("leave - not ready\n");
  5508. mutex_unlock(&priv->mutex);
  5509. return;
  5510. }
  5511. /* we are restarting association process
  5512. * clear RXON_FILTER_ASSOC_MSK bit
  5513. */
  5514. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5515. iwl3945_scan_cancel_timeout(priv, 100);
  5516. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5517. iwl3945_commit_rxon(priv);
  5518. }
  5519. /* Per mac80211.h: This is only used in IBSS mode... */
  5520. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5521. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5522. mutex_unlock(&priv->mutex);
  5523. return;
  5524. }
  5525. iwl3945_set_rate(priv);
  5526. mutex_unlock(&priv->mutex);
  5527. IWL_DEBUG_MAC80211("leave\n");
  5528. }
  5529. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5530. {
  5531. struct iwl_priv *priv = hw->priv;
  5532. unsigned long flags;
  5533. IWL_DEBUG_MAC80211("enter\n");
  5534. if (!iwl_is_ready_rf(priv)) {
  5535. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5536. return -EIO;
  5537. }
  5538. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5539. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5540. return -EIO;
  5541. }
  5542. spin_lock_irqsave(&priv->lock, flags);
  5543. if (priv->ibss_beacon)
  5544. dev_kfree_skb(priv->ibss_beacon);
  5545. priv->ibss_beacon = skb;
  5546. priv->assoc_id = 0;
  5547. IWL_DEBUG_MAC80211("leave\n");
  5548. spin_unlock_irqrestore(&priv->lock, flags);
  5549. iwl_reset_qos(priv);
  5550. iwl3945_post_associate(priv);
  5551. return 0;
  5552. }
  5553. /*****************************************************************************
  5554. *
  5555. * sysfs attributes
  5556. *
  5557. *****************************************************************************/
  5558. #ifdef CONFIG_IWL3945_DEBUG
  5559. /*
  5560. * The following adds a new attribute to the sysfs representation
  5561. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5562. * used for controlling the debug level.
  5563. *
  5564. * See the level definitions in iwl for details.
  5565. */
  5566. static ssize_t show_debug_level(struct device *d,
  5567. struct device_attribute *attr, char *buf)
  5568. {
  5569. struct iwl_priv *priv = d->driver_data;
  5570. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5571. }
  5572. static ssize_t store_debug_level(struct device *d,
  5573. struct device_attribute *attr,
  5574. const char *buf, size_t count)
  5575. {
  5576. struct iwl_priv *priv = d->driver_data;
  5577. unsigned long val;
  5578. int ret;
  5579. ret = strict_strtoul(buf, 0, &val);
  5580. if (ret)
  5581. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5582. else
  5583. priv->debug_level = val;
  5584. return strnlen(buf, count);
  5585. }
  5586. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5587. show_debug_level, store_debug_level);
  5588. #endif /* CONFIG_IWL3945_DEBUG */
  5589. static ssize_t show_temperature(struct device *d,
  5590. struct device_attribute *attr, char *buf)
  5591. {
  5592. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5593. if (!iwl_is_alive(priv))
  5594. return -EAGAIN;
  5595. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5596. }
  5597. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5598. static ssize_t show_tx_power(struct device *d,
  5599. struct device_attribute *attr, char *buf)
  5600. {
  5601. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5602. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5603. }
  5604. static ssize_t store_tx_power(struct device *d,
  5605. struct device_attribute *attr,
  5606. const char *buf, size_t count)
  5607. {
  5608. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5609. char *p = (char *)buf;
  5610. u32 val;
  5611. val = simple_strtoul(p, &p, 10);
  5612. if (p == buf)
  5613. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5614. else
  5615. iwl3945_hw_reg_set_txpower(priv, val);
  5616. return count;
  5617. }
  5618. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5619. static ssize_t show_flags(struct device *d,
  5620. struct device_attribute *attr, char *buf)
  5621. {
  5622. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5623. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5624. }
  5625. static ssize_t store_flags(struct device *d,
  5626. struct device_attribute *attr,
  5627. const char *buf, size_t count)
  5628. {
  5629. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5630. u32 flags = simple_strtoul(buf, NULL, 0);
  5631. mutex_lock(&priv->mutex);
  5632. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  5633. /* Cancel any currently running scans... */
  5634. if (iwl3945_scan_cancel_timeout(priv, 100))
  5635. IWL_WARN(priv, "Could not cancel scan.\n");
  5636. else {
  5637. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  5638. flags);
  5639. priv->staging39_rxon.flags = cpu_to_le32(flags);
  5640. iwl3945_commit_rxon(priv);
  5641. }
  5642. }
  5643. mutex_unlock(&priv->mutex);
  5644. return count;
  5645. }
  5646. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  5647. static ssize_t show_filter_flags(struct device *d,
  5648. struct device_attribute *attr, char *buf)
  5649. {
  5650. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5651. return sprintf(buf, "0x%04X\n",
  5652. le32_to_cpu(priv->active39_rxon.filter_flags));
  5653. }
  5654. static ssize_t store_filter_flags(struct device *d,
  5655. struct device_attribute *attr,
  5656. const char *buf, size_t count)
  5657. {
  5658. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5659. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  5660. mutex_lock(&priv->mutex);
  5661. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  5662. /* Cancel any currently running scans... */
  5663. if (iwl3945_scan_cancel_timeout(priv, 100))
  5664. IWL_WARN(priv, "Could not cancel scan.\n");
  5665. else {
  5666. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  5667. "0x%04X\n", filter_flags);
  5668. priv->staging39_rxon.filter_flags =
  5669. cpu_to_le32(filter_flags);
  5670. iwl3945_commit_rxon(priv);
  5671. }
  5672. }
  5673. mutex_unlock(&priv->mutex);
  5674. return count;
  5675. }
  5676. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  5677. store_filter_flags);
  5678. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5679. static ssize_t show_measurement(struct device *d,
  5680. struct device_attribute *attr, char *buf)
  5681. {
  5682. struct iwl_priv *priv = dev_get_drvdata(d);
  5683. struct iwl_spectrum_notification measure_report;
  5684. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  5685. u8 *data = (u8 *)&measure_report;
  5686. unsigned long flags;
  5687. spin_lock_irqsave(&priv->lock, flags);
  5688. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  5689. spin_unlock_irqrestore(&priv->lock, flags);
  5690. return 0;
  5691. }
  5692. memcpy(&measure_report, &priv->measure_report, size);
  5693. priv->measurement_status = 0;
  5694. spin_unlock_irqrestore(&priv->lock, flags);
  5695. while (size && (PAGE_SIZE - len)) {
  5696. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5697. PAGE_SIZE - len, 1);
  5698. len = strlen(buf);
  5699. if (PAGE_SIZE - len)
  5700. buf[len++] = '\n';
  5701. ofs += 16;
  5702. size -= min(size, 16U);
  5703. }
  5704. return len;
  5705. }
  5706. static ssize_t store_measurement(struct device *d,
  5707. struct device_attribute *attr,
  5708. const char *buf, size_t count)
  5709. {
  5710. struct iwl_priv *priv = dev_get_drvdata(d);
  5711. struct ieee80211_measurement_params params = {
  5712. .channel = le16_to_cpu(priv->active39_rxon.channel),
  5713. .start_time = cpu_to_le64(priv->last_tsf),
  5714. .duration = cpu_to_le16(1),
  5715. };
  5716. u8 type = IWL_MEASURE_BASIC;
  5717. u8 buffer[32];
  5718. u8 channel;
  5719. if (count) {
  5720. char *p = buffer;
  5721. strncpy(buffer, buf, min(sizeof(buffer), count));
  5722. channel = simple_strtoul(p, NULL, 0);
  5723. if (channel)
  5724. params.channel = channel;
  5725. p = buffer;
  5726. while (*p && *p != ' ')
  5727. p++;
  5728. if (*p)
  5729. type = simple_strtoul(p + 1, NULL, 0);
  5730. }
  5731. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  5732. "channel %d (for '%s')\n", type, params.channel, buf);
  5733. iwl3945_get_measurement(priv, &params, type);
  5734. return count;
  5735. }
  5736. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  5737. show_measurement, store_measurement);
  5738. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  5739. static ssize_t store_retry_rate(struct device *d,
  5740. struct device_attribute *attr,
  5741. const char *buf, size_t count)
  5742. {
  5743. struct iwl_priv *priv = dev_get_drvdata(d);
  5744. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  5745. if (priv->retry_rate <= 0)
  5746. priv->retry_rate = 1;
  5747. return count;
  5748. }
  5749. static ssize_t show_retry_rate(struct device *d,
  5750. struct device_attribute *attr, char *buf)
  5751. {
  5752. struct iwl_priv *priv = dev_get_drvdata(d);
  5753. return sprintf(buf, "%d", priv->retry_rate);
  5754. }
  5755. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  5756. store_retry_rate);
  5757. static ssize_t store_power_level(struct device *d,
  5758. struct device_attribute *attr,
  5759. const char *buf, size_t count)
  5760. {
  5761. struct iwl_priv *priv = dev_get_drvdata(d);
  5762. int rc;
  5763. int mode;
  5764. mode = simple_strtoul(buf, NULL, 0);
  5765. mutex_lock(&priv->mutex);
  5766. if (!iwl_is_ready(priv)) {
  5767. rc = -EAGAIN;
  5768. goto out;
  5769. }
  5770. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  5771. (mode == IWL39_POWER_AC))
  5772. mode = IWL39_POWER_AC;
  5773. else
  5774. mode |= IWL_POWER_ENABLED;
  5775. if (mode != priv->power_mode) {
  5776. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  5777. if (rc) {
  5778. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  5779. goto out;
  5780. }
  5781. priv->power_mode = mode;
  5782. }
  5783. rc = count;
  5784. out:
  5785. mutex_unlock(&priv->mutex);
  5786. return rc;
  5787. }
  5788. #define MAX_WX_STRING 80
  5789. /* Values are in microsecond */
  5790. static const s32 timeout_duration[] = {
  5791. 350000,
  5792. 250000,
  5793. 75000,
  5794. 37000,
  5795. 25000,
  5796. };
  5797. static const s32 period_duration[] = {
  5798. 400000,
  5799. 700000,
  5800. 1000000,
  5801. 1000000,
  5802. 1000000
  5803. };
  5804. static ssize_t show_power_level(struct device *d,
  5805. struct device_attribute *attr, char *buf)
  5806. {
  5807. struct iwl_priv *priv = dev_get_drvdata(d);
  5808. int level = IWL_POWER_LEVEL(priv->power_mode);
  5809. char *p = buf;
  5810. p += sprintf(p, "%d ", level);
  5811. switch (level) {
  5812. case IWL_POWER_MODE_CAM:
  5813. case IWL39_POWER_AC:
  5814. p += sprintf(p, "(AC)");
  5815. break;
  5816. case IWL39_POWER_BATTERY:
  5817. p += sprintf(p, "(BATTERY)");
  5818. break;
  5819. default:
  5820. p += sprintf(p,
  5821. "(Timeout %dms, Period %dms)",
  5822. timeout_duration[level - 1] / 1000,
  5823. period_duration[level - 1] / 1000);
  5824. }
  5825. if (!(priv->power_mode & IWL_POWER_ENABLED))
  5826. p += sprintf(p, " OFF\n");
  5827. else
  5828. p += sprintf(p, " \n");
  5829. return p - buf + 1;
  5830. }
  5831. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  5832. store_power_level);
  5833. static ssize_t show_channels(struct device *d,
  5834. struct device_attribute *attr, char *buf)
  5835. {
  5836. /* all this shit doesn't belong into sysfs anyway */
  5837. return 0;
  5838. }
  5839. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  5840. static ssize_t show_statistics(struct device *d,
  5841. struct device_attribute *attr, char *buf)
  5842. {
  5843. struct iwl_priv *priv = dev_get_drvdata(d);
  5844. u32 size = sizeof(struct iwl3945_notif_statistics);
  5845. u32 len = 0, ofs = 0;
  5846. u8 *data = (u8 *)&priv->statistics_39;
  5847. int rc = 0;
  5848. if (!iwl_is_alive(priv))
  5849. return -EAGAIN;
  5850. mutex_lock(&priv->mutex);
  5851. rc = iwl3945_send_statistics_request(priv);
  5852. mutex_unlock(&priv->mutex);
  5853. if (rc) {
  5854. len = sprintf(buf,
  5855. "Error sending statistics request: 0x%08X\n", rc);
  5856. return len;
  5857. }
  5858. while (size && (PAGE_SIZE - len)) {
  5859. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5860. PAGE_SIZE - len, 1);
  5861. len = strlen(buf);
  5862. if (PAGE_SIZE - len)
  5863. buf[len++] = '\n';
  5864. ofs += 16;
  5865. size -= min(size, 16U);
  5866. }
  5867. return len;
  5868. }
  5869. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  5870. static ssize_t show_antenna(struct device *d,
  5871. struct device_attribute *attr, char *buf)
  5872. {
  5873. struct iwl_priv *priv = dev_get_drvdata(d);
  5874. if (!iwl_is_alive(priv))
  5875. return -EAGAIN;
  5876. return sprintf(buf, "%d\n", priv->antenna);
  5877. }
  5878. static ssize_t store_antenna(struct device *d,
  5879. struct device_attribute *attr,
  5880. const char *buf, size_t count)
  5881. {
  5882. int ant;
  5883. struct iwl_priv *priv = dev_get_drvdata(d);
  5884. if (count == 0)
  5885. return 0;
  5886. if (sscanf(buf, "%1i", &ant) != 1) {
  5887. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  5888. return count;
  5889. }
  5890. if ((ant >= 0) && (ant <= 2)) {
  5891. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  5892. priv->antenna = (enum iwl3945_antenna)ant;
  5893. } else
  5894. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  5895. return count;
  5896. }
  5897. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  5898. static ssize_t show_status(struct device *d,
  5899. struct device_attribute *attr, char *buf)
  5900. {
  5901. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5902. if (!iwl_is_alive(priv))
  5903. return -EAGAIN;
  5904. return sprintf(buf, "0x%08x\n", (int)priv->status);
  5905. }
  5906. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  5907. static ssize_t dump_error_log(struct device *d,
  5908. struct device_attribute *attr,
  5909. const char *buf, size_t count)
  5910. {
  5911. char *p = (char *)buf;
  5912. if (p[0] == '1')
  5913. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  5914. return strnlen(buf, count);
  5915. }
  5916. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  5917. static ssize_t dump_event_log(struct device *d,
  5918. struct device_attribute *attr,
  5919. const char *buf, size_t count)
  5920. {
  5921. char *p = (char *)buf;
  5922. if (p[0] == '1')
  5923. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  5924. return strnlen(buf, count);
  5925. }
  5926. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  5927. /*****************************************************************************
  5928. *
  5929. * driver setup and tear down
  5930. *
  5931. *****************************************************************************/
  5932. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  5933. {
  5934. priv->workqueue = create_workqueue(DRV_NAME);
  5935. init_waitqueue_head(&priv->wait_command_queue);
  5936. INIT_WORK(&priv->up, iwl3945_bg_up);
  5937. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  5938. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  5939. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  5940. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  5941. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  5942. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  5943. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  5944. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  5945. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  5946. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  5947. iwl3945_hw_setup_deferred_work(priv);
  5948. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  5949. iwl3945_irq_tasklet, (unsigned long)priv);
  5950. }
  5951. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  5952. {
  5953. iwl3945_hw_cancel_deferred_work(priv);
  5954. cancel_delayed_work_sync(&priv->init_alive_start);
  5955. cancel_delayed_work(&priv->scan_check);
  5956. cancel_delayed_work(&priv->alive_start);
  5957. cancel_work_sync(&priv->beacon_update);
  5958. }
  5959. static struct attribute *iwl3945_sysfs_entries[] = {
  5960. &dev_attr_antenna.attr,
  5961. &dev_attr_channels.attr,
  5962. &dev_attr_dump_errors.attr,
  5963. &dev_attr_dump_events.attr,
  5964. &dev_attr_flags.attr,
  5965. &dev_attr_filter_flags.attr,
  5966. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5967. &dev_attr_measurement.attr,
  5968. #endif
  5969. &dev_attr_power_level.attr,
  5970. &dev_attr_retry_rate.attr,
  5971. &dev_attr_statistics.attr,
  5972. &dev_attr_status.attr,
  5973. &dev_attr_temperature.attr,
  5974. &dev_attr_tx_power.attr,
  5975. #ifdef CONFIG_IWL3945_DEBUG
  5976. &dev_attr_debug_level.attr,
  5977. #endif
  5978. NULL
  5979. };
  5980. static struct attribute_group iwl3945_attribute_group = {
  5981. .name = NULL, /* put in device directory */
  5982. .attrs = iwl3945_sysfs_entries,
  5983. };
  5984. static struct ieee80211_ops iwl3945_hw_ops = {
  5985. .tx = iwl3945_mac_tx,
  5986. .start = iwl3945_mac_start,
  5987. .stop = iwl3945_mac_stop,
  5988. .add_interface = iwl3945_mac_add_interface,
  5989. .remove_interface = iwl3945_mac_remove_interface,
  5990. .config = iwl3945_mac_config,
  5991. .config_interface = iwl3945_mac_config_interface,
  5992. .configure_filter = iwl3945_configure_filter,
  5993. .set_key = iwl3945_mac_set_key,
  5994. .get_tx_stats = iwl3945_mac_get_tx_stats,
  5995. .conf_tx = iwl3945_mac_conf_tx,
  5996. .reset_tsf = iwl3945_mac_reset_tsf,
  5997. .bss_info_changed = iwl3945_bss_info_changed,
  5998. .hw_scan = iwl3945_mac_hw_scan
  5999. };
  6000. static int iwl3945_init_drv(struct iwl_priv *priv)
  6001. {
  6002. int ret;
  6003. priv->retry_rate = 1;
  6004. priv->ibss_beacon = NULL;
  6005. spin_lock_init(&priv->lock);
  6006. spin_lock_init(&priv->power_data.lock);
  6007. spin_lock_init(&priv->sta_lock);
  6008. spin_lock_init(&priv->hcmd_lock);
  6009. INIT_LIST_HEAD(&priv->free_frames);
  6010. mutex_init(&priv->mutex);
  6011. /* Clear the driver's (not device's) station table */
  6012. iwl3945_clear_stations_table(priv);
  6013. priv->data_retry_limit = -1;
  6014. priv->ieee_channels = NULL;
  6015. priv->ieee_rates = NULL;
  6016. priv->band = IEEE80211_BAND_2GHZ;
  6017. priv->iw_mode = NL80211_IFTYPE_STATION;
  6018. iwl_reset_qos(priv);
  6019. priv->qos_data.qos_active = 0;
  6020. priv->qos_data.qos_cap.val = 0;
  6021. priv->rates_mask = IWL_RATES_MASK;
  6022. /* If power management is turned on, default to AC mode */
  6023. priv->power_mode = IWL_POWER_AC;
  6024. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6025. ret = iwl3945_init_channel_map(priv);
  6026. if (ret) {
  6027. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  6028. goto err;
  6029. }
  6030. ret = iwl3945_init_geos(priv);
  6031. if (ret) {
  6032. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  6033. goto err_free_channel_map;
  6034. }
  6035. return 0;
  6036. err_free_channel_map:
  6037. iwl3945_free_channel_map(priv);
  6038. err:
  6039. return ret;
  6040. }
  6041. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6042. {
  6043. int err = 0;
  6044. struct iwl_priv *priv;
  6045. struct ieee80211_hw *hw;
  6046. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6047. unsigned long flags;
  6048. /***********************
  6049. * 1. Allocating HW data
  6050. * ********************/
  6051. /* mac80211 allocates memory for this device instance, including
  6052. * space for this driver's private structure */
  6053. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  6054. if (hw == NULL) {
  6055. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6056. err = -ENOMEM;
  6057. goto out;
  6058. }
  6059. priv = hw->priv;
  6060. SET_IEEE80211_DEV(hw, &pdev->dev);
  6061. if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
  6062. (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
  6063. IWL_ERR(priv,
  6064. "invalid queues_num, should be between %d and %d\n",
  6065. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6066. err = -EINVAL;
  6067. goto out;
  6068. }
  6069. /*
  6070. * Disabling hardware scan means that mac80211 will perform scans
  6071. * "the hard way", rather than using device's scan.
  6072. */
  6073. if (iwl3945_mod_params.disable_hw_scan) {
  6074. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6075. iwl3945_hw_ops.hw_scan = NULL;
  6076. }
  6077. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6078. priv->cfg = cfg;
  6079. priv->pci_dev = pdev;
  6080. #ifdef CONFIG_IWL3945_DEBUG
  6081. priv->debug_level = iwl3945_mod_params.debug;
  6082. atomic_set(&priv->restrict_refcnt, 0);
  6083. #endif
  6084. hw->rate_control_algorithm = "iwl-3945-rs";
  6085. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6086. /* Select antenna (may be helpful if only one antenna is connected) */
  6087. priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
  6088. /* Tell mac80211 our characteristics */
  6089. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6090. IEEE80211_HW_NOISE_DBM;
  6091. hw->wiphy->interface_modes =
  6092. BIT(NL80211_IFTYPE_STATION) |
  6093. BIT(NL80211_IFTYPE_ADHOC);
  6094. hw->wiphy->fw_handles_regulatory = true;
  6095. /* 4 EDCA QOS priorities */
  6096. hw->queues = 4;
  6097. /***************************
  6098. * 2. Initializing PCI bus
  6099. * *************************/
  6100. if (pci_enable_device(pdev)) {
  6101. err = -ENODEV;
  6102. goto out_ieee80211_free_hw;
  6103. }
  6104. pci_set_master(pdev);
  6105. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6106. if (!err)
  6107. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6108. if (err) {
  6109. IWL_WARN(priv, "No suitable DMA available.\n");
  6110. goto out_pci_disable_device;
  6111. }
  6112. pci_set_drvdata(pdev, priv);
  6113. err = pci_request_regions(pdev, DRV_NAME);
  6114. if (err)
  6115. goto out_pci_disable_device;
  6116. /***********************
  6117. * 3. Read REV Register
  6118. * ********************/
  6119. priv->hw_base = pci_iomap(pdev, 0, 0);
  6120. if (!priv->hw_base) {
  6121. err = -ENODEV;
  6122. goto out_pci_release_regions;
  6123. }
  6124. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6125. (unsigned long long) pci_resource_len(pdev, 0));
  6126. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6127. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6128. * PCI Tx retries from interfering with C3 CPU state */
  6129. pci_write_config_byte(pdev, 0x41, 0x00);
  6130. /* amp init */
  6131. err = priv->cfg->ops->lib->apm_ops.init(priv);
  6132. if (err < 0) {
  6133. IWL_DEBUG_INFO("Failed to init APMG\n");
  6134. goto out_iounmap;
  6135. }
  6136. /***********************
  6137. * 4. Read EEPROM
  6138. * ********************/
  6139. /* Read the EEPROM */
  6140. err = iwl3945_eeprom_init(priv);
  6141. if (err) {
  6142. IWL_ERR(priv, "Unable to init EEPROM\n");
  6143. goto out_remove_sysfs;
  6144. }
  6145. /* MAC Address location in EEPROM same for 3945/4965 */
  6146. get_eeprom_mac(priv, priv->mac_addr);
  6147. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6148. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6149. /***********************
  6150. * 5. Setup HW Constants
  6151. * ********************/
  6152. /* Device-specific setup */
  6153. if (iwl3945_hw_set_hw_params(priv)) {
  6154. IWL_ERR(priv, "failed to set hw settings\n");
  6155. goto out_iounmap;
  6156. }
  6157. /***********************
  6158. * 6. Setup priv
  6159. * ********************/
  6160. err = iwl3945_init_drv(priv);
  6161. if (err) {
  6162. IWL_ERR(priv, "initializing driver failed\n");
  6163. goto out_free_geos;
  6164. }
  6165. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  6166. priv->cfg->name);
  6167. /***********************************
  6168. * 7. Initialize Module Parameters
  6169. * **********************************/
  6170. /* Initialize module parameter values here */
  6171. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6172. if (iwl3945_mod_params.disable) {
  6173. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6174. IWL_DEBUG_INFO("Radio disabled.\n");
  6175. }
  6176. /***********************
  6177. * 8. Setup Services
  6178. * ********************/
  6179. spin_lock_irqsave(&priv->lock, flags);
  6180. iwl3945_disable_interrupts(priv);
  6181. spin_unlock_irqrestore(&priv->lock, flags);
  6182. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6183. if (err) {
  6184. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  6185. goto out_release_irq;
  6186. }
  6187. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6188. iwl3945_setup_deferred_work(priv);
  6189. iwl3945_setup_rx_handlers(priv);
  6190. /***********************
  6191. * 9. Conclude
  6192. * ********************/
  6193. pci_save_state(pdev);
  6194. pci_disable_device(pdev);
  6195. /*********************************
  6196. * 10. Setup and Register mac80211
  6197. * *******************************/
  6198. err = ieee80211_register_hw(priv->hw);
  6199. if (err) {
  6200. IWL_ERR(priv, "Failed to register network device: %d\n", err);
  6201. goto out_remove_sysfs;
  6202. }
  6203. priv->hw->conf.beacon_int = 100;
  6204. priv->mac80211_registered = 1;
  6205. err = iwl3945_rfkill_init(priv);
  6206. if (err)
  6207. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  6208. "Ignoring error: %d\n", err);
  6209. return 0;
  6210. out_remove_sysfs:
  6211. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6212. out_free_geos:
  6213. iwl3945_free_geos(priv);
  6214. out_release_irq:
  6215. destroy_workqueue(priv->workqueue);
  6216. priv->workqueue = NULL;
  6217. iwl3945_unset_hw_params(priv);
  6218. out_iounmap:
  6219. pci_iounmap(pdev, priv->hw_base);
  6220. out_pci_release_regions:
  6221. pci_release_regions(pdev);
  6222. out_pci_disable_device:
  6223. pci_disable_device(pdev);
  6224. pci_set_drvdata(pdev, NULL);
  6225. out_ieee80211_free_hw:
  6226. ieee80211_free_hw(priv->hw);
  6227. out:
  6228. return err;
  6229. }
  6230. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6231. {
  6232. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6233. unsigned long flags;
  6234. if (!priv)
  6235. return;
  6236. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6237. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6238. if (priv->mac80211_registered) {
  6239. ieee80211_unregister_hw(priv->hw);
  6240. priv->mac80211_registered = 0;
  6241. } else {
  6242. iwl3945_down(priv);
  6243. }
  6244. /* make sure we flush any pending irq or
  6245. * tasklet for the driver
  6246. */
  6247. spin_lock_irqsave(&priv->lock, flags);
  6248. iwl3945_disable_interrupts(priv);
  6249. spin_unlock_irqrestore(&priv->lock, flags);
  6250. iwl_synchronize_irq(priv);
  6251. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6252. iwl3945_rfkill_unregister(priv);
  6253. iwl3945_dealloc_ucode_pci(priv);
  6254. if (priv->rxq.bd)
  6255. iwl_rx_queue_free(priv, &priv->rxq);
  6256. iwl3945_hw_txq_ctx_free(priv);
  6257. iwl3945_unset_hw_params(priv);
  6258. iwl3945_clear_stations_table(priv);
  6259. /*netif_stop_queue(dev); */
  6260. flush_workqueue(priv->workqueue);
  6261. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6262. * priv->workqueue... so we can't take down the workqueue
  6263. * until now... */
  6264. destroy_workqueue(priv->workqueue);
  6265. priv->workqueue = NULL;
  6266. pci_iounmap(pdev, priv->hw_base);
  6267. pci_release_regions(pdev);
  6268. pci_disable_device(pdev);
  6269. pci_set_drvdata(pdev, NULL);
  6270. iwl3945_free_channel_map(priv);
  6271. iwl3945_free_geos(priv);
  6272. kfree(priv->scan39);
  6273. if (priv->ibss_beacon)
  6274. dev_kfree_skb(priv->ibss_beacon);
  6275. ieee80211_free_hw(priv->hw);
  6276. }
  6277. #ifdef CONFIG_PM
  6278. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6279. {
  6280. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6281. if (priv->is_open) {
  6282. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6283. iwl3945_mac_stop(priv->hw);
  6284. priv->is_open = 1;
  6285. }
  6286. pci_set_power_state(pdev, PCI_D3hot);
  6287. return 0;
  6288. }
  6289. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6290. {
  6291. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6292. pci_set_power_state(pdev, PCI_D0);
  6293. if (priv->is_open)
  6294. iwl3945_mac_start(priv->hw);
  6295. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6296. return 0;
  6297. }
  6298. #endif /* CONFIG_PM */
  6299. /*************** RFKILL FUNCTIONS **********/
  6300. #ifdef CONFIG_IWL3945_RFKILL
  6301. /* software rf-kill from user */
  6302. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6303. {
  6304. struct iwl_priv *priv = data;
  6305. int err = 0;
  6306. if (!priv->rfkill)
  6307. return 0;
  6308. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6309. return 0;
  6310. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6311. mutex_lock(&priv->mutex);
  6312. switch (state) {
  6313. case RFKILL_STATE_UNBLOCKED:
  6314. if (iwl_is_rfkill_hw(priv)) {
  6315. err = -EBUSY;
  6316. goto out_unlock;
  6317. }
  6318. iwl3945_radio_kill_sw(priv, 0);
  6319. break;
  6320. case RFKILL_STATE_SOFT_BLOCKED:
  6321. iwl3945_radio_kill_sw(priv, 1);
  6322. break;
  6323. default:
  6324. IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
  6325. break;
  6326. }
  6327. out_unlock:
  6328. mutex_unlock(&priv->mutex);
  6329. return err;
  6330. }
  6331. int iwl3945_rfkill_init(struct iwl_priv *priv)
  6332. {
  6333. struct device *device = wiphy_dev(priv->hw->wiphy);
  6334. int ret = 0;
  6335. BUG_ON(device == NULL);
  6336. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6337. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6338. if (!priv->rfkill) {
  6339. IWL_ERR(priv, "Unable to allocate rfkill device.\n");
  6340. ret = -ENOMEM;
  6341. goto error;
  6342. }
  6343. priv->rfkill->name = priv->cfg->name;
  6344. priv->rfkill->data = priv;
  6345. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6346. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6347. priv->rfkill->user_claim_unsupported = 1;
  6348. priv->rfkill->dev.class->suspend = NULL;
  6349. priv->rfkill->dev.class->resume = NULL;
  6350. ret = rfkill_register(priv->rfkill);
  6351. if (ret) {
  6352. IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
  6353. goto freed_rfkill;
  6354. }
  6355. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6356. return ret;
  6357. freed_rfkill:
  6358. if (priv->rfkill != NULL)
  6359. rfkill_free(priv->rfkill);
  6360. priv->rfkill = NULL;
  6361. error:
  6362. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6363. return ret;
  6364. }
  6365. void iwl3945_rfkill_unregister(struct iwl_priv *priv)
  6366. {
  6367. if (priv->rfkill)
  6368. rfkill_unregister(priv->rfkill);
  6369. priv->rfkill = NULL;
  6370. }
  6371. /* set rf-kill to the right state. */
  6372. void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
  6373. {
  6374. if (!priv->rfkill)
  6375. return;
  6376. if (iwl_is_rfkill_hw(priv)) {
  6377. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6378. return;
  6379. }
  6380. if (!iwl_is_rfkill_sw(priv))
  6381. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6382. else
  6383. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6384. }
  6385. #endif
  6386. /*****************************************************************************
  6387. *
  6388. * driver and module entry point
  6389. *
  6390. *****************************************************************************/
  6391. static struct pci_driver iwl3945_driver = {
  6392. .name = DRV_NAME,
  6393. .id_table = iwl3945_hw_card_ids,
  6394. .probe = iwl3945_pci_probe,
  6395. .remove = __devexit_p(iwl3945_pci_remove),
  6396. #ifdef CONFIG_PM
  6397. .suspend = iwl3945_pci_suspend,
  6398. .resume = iwl3945_pci_resume,
  6399. #endif
  6400. };
  6401. static int __init iwl3945_init(void)
  6402. {
  6403. int ret;
  6404. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6405. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6406. ret = iwl3945_rate_control_register();
  6407. if (ret) {
  6408. printk(KERN_ERR DRV_NAME
  6409. "Unable to register rate control algorithm: %d\n", ret);
  6410. return ret;
  6411. }
  6412. ret = pci_register_driver(&iwl3945_driver);
  6413. if (ret) {
  6414. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6415. goto error_register;
  6416. }
  6417. return ret;
  6418. error_register:
  6419. iwl3945_rate_control_unregister();
  6420. return ret;
  6421. }
  6422. static void __exit iwl3945_exit(void)
  6423. {
  6424. pci_unregister_driver(&iwl3945_driver);
  6425. iwl3945_rate_control_unregister();
  6426. }
  6427. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6428. module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
  6429. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6430. module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
  6431. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6432. module_param_named(hwcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
  6433. MODULE_PARM_DESC(hwcrypto,
  6434. "using hardware crypto engine (default 0 [software])\n");
  6435. module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
  6436. MODULE_PARM_DESC(debug, "debug output mask");
  6437. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
  6438. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6439. module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
  6440. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6441. module_exit(iwl3945_exit);
  6442. module_init(iwl3945_init);