netxen_nic_init.c 29 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ringid);
  48. static void crb_addr_transform_setup(void)
  49. {
  50. crb_addr_transform(XDMA);
  51. crb_addr_transform(TIMR);
  52. crb_addr_transform(SRE);
  53. crb_addr_transform(SQN3);
  54. crb_addr_transform(SQN2);
  55. crb_addr_transform(SQN1);
  56. crb_addr_transform(SQN0);
  57. crb_addr_transform(SQS3);
  58. crb_addr_transform(SQS2);
  59. crb_addr_transform(SQS1);
  60. crb_addr_transform(SQS0);
  61. crb_addr_transform(RPMX7);
  62. crb_addr_transform(RPMX6);
  63. crb_addr_transform(RPMX5);
  64. crb_addr_transform(RPMX4);
  65. crb_addr_transform(RPMX3);
  66. crb_addr_transform(RPMX2);
  67. crb_addr_transform(RPMX1);
  68. crb_addr_transform(RPMX0);
  69. crb_addr_transform(ROMUSB);
  70. crb_addr_transform(SN);
  71. crb_addr_transform(QMN);
  72. crb_addr_transform(QMS);
  73. crb_addr_transform(PGNI);
  74. crb_addr_transform(PGND);
  75. crb_addr_transform(PGN3);
  76. crb_addr_transform(PGN2);
  77. crb_addr_transform(PGN1);
  78. crb_addr_transform(PGN0);
  79. crb_addr_transform(PGSI);
  80. crb_addr_transform(PGSD);
  81. crb_addr_transform(PGS3);
  82. crb_addr_transform(PGS2);
  83. crb_addr_transform(PGS1);
  84. crb_addr_transform(PGS0);
  85. crb_addr_transform(PS);
  86. crb_addr_transform(PH);
  87. crb_addr_transform(NIU);
  88. crb_addr_transform(I2Q);
  89. crb_addr_transform(EG);
  90. crb_addr_transform(MN);
  91. crb_addr_transform(MS);
  92. crb_addr_transform(CAS2);
  93. crb_addr_transform(CAS1);
  94. crb_addr_transform(CAS0);
  95. crb_addr_transform(CAM);
  96. crb_addr_transform(C2C1);
  97. crb_addr_transform(C2C0);
  98. crb_addr_transform(SMB);
  99. crb_addr_transform(OCM0);
  100. crb_addr_transform(I2C0);
  101. }
  102. int netxen_init_firmware(struct netxen_adapter *adapter)
  103. {
  104. u32 state = 0, loops = 0, err = 0;
  105. /* Window 1 call */
  106. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  107. if (state == PHAN_INITIALIZE_ACK)
  108. return 0;
  109. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  110. msleep(1);
  111. /* Window 1 call */
  112. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  113. loops++;
  114. }
  115. if (loops >= 2000) {
  116. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  117. state);
  118. err = -EIO;
  119. return err;
  120. }
  121. /* Window 1 call */
  122. adapter->pci_write_normalize(adapter,
  123. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  124. adapter->pci_write_normalize(adapter,
  125. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  126. adapter->pci_write_normalize(adapter,
  127. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  128. adapter->pci_write_normalize(adapter,
  129. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  130. return err;
  131. }
  132. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  133. {
  134. struct netxen_recv_context *recv_ctx;
  135. struct nx_host_rds_ring *rds_ring;
  136. struct netxen_rx_buffer *rx_buf;
  137. int i, ring;
  138. recv_ctx = &adapter->recv_ctx;
  139. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  140. rds_ring = &recv_ctx->rds_rings[ring];
  141. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  142. rx_buf = &(rds_ring->rx_buf_arr[i]);
  143. if (rx_buf->state == NETXEN_BUFFER_FREE)
  144. continue;
  145. pci_unmap_single(adapter->pdev,
  146. rx_buf->dma,
  147. rds_ring->dma_size,
  148. PCI_DMA_FROMDEVICE);
  149. if (rx_buf->skb != NULL)
  150. dev_kfree_skb_any(rx_buf->skb);
  151. }
  152. }
  153. }
  154. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  155. {
  156. struct netxen_cmd_buffer *cmd_buf;
  157. struct netxen_skb_frag *buffrag;
  158. int i, j;
  159. cmd_buf = adapter->cmd_buf_arr;
  160. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  161. buffrag = cmd_buf->frag_array;
  162. if (buffrag->dma) {
  163. pci_unmap_single(adapter->pdev, buffrag->dma,
  164. buffrag->length, PCI_DMA_TODEVICE);
  165. buffrag->dma = 0ULL;
  166. }
  167. for (j = 0; j < cmd_buf->frag_count; j++) {
  168. buffrag++;
  169. if (buffrag->dma) {
  170. pci_unmap_page(adapter->pdev, buffrag->dma,
  171. buffrag->length,
  172. PCI_DMA_TODEVICE);
  173. buffrag->dma = 0ULL;
  174. }
  175. }
  176. /* Free the skb we received in netxen_nic_xmit_frame */
  177. if (cmd_buf->skb) {
  178. dev_kfree_skb_any(cmd_buf->skb);
  179. cmd_buf->skb = NULL;
  180. }
  181. cmd_buf++;
  182. }
  183. }
  184. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  185. {
  186. struct netxen_recv_context *recv_ctx;
  187. struct nx_host_rds_ring *rds_ring;
  188. int ring;
  189. recv_ctx = &adapter->recv_ctx;
  190. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  191. rds_ring = &recv_ctx->rds_rings[ring];
  192. if (rds_ring->rx_buf_arr) {
  193. vfree(rds_ring->rx_buf_arr);
  194. rds_ring->rx_buf_arr = NULL;
  195. }
  196. }
  197. if (adapter->cmd_buf_arr)
  198. vfree(adapter->cmd_buf_arr);
  199. return;
  200. }
  201. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  202. {
  203. struct netxen_recv_context *recv_ctx;
  204. struct nx_host_rds_ring *rds_ring;
  205. struct netxen_rx_buffer *rx_buf;
  206. int ring, i, num_rx_bufs;
  207. struct netxen_cmd_buffer *cmd_buf_arr;
  208. struct net_device *netdev = adapter->netdev;
  209. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  210. if (cmd_buf_arr == NULL) {
  211. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  212. netdev->name);
  213. return -ENOMEM;
  214. }
  215. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  216. adapter->cmd_buf_arr = cmd_buf_arr;
  217. recv_ctx = &adapter->recv_ctx;
  218. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  219. rds_ring = &recv_ctx->rds_rings[ring];
  220. switch (RCV_DESC_TYPE(ring)) {
  221. case RCV_DESC_NORMAL:
  222. rds_ring->max_rx_desc_count =
  223. adapter->max_rx_desc_count;
  224. rds_ring->flags = RCV_DESC_NORMAL;
  225. if (adapter->ahw.cut_through) {
  226. rds_ring->dma_size =
  227. NX_CT_DEFAULT_RX_BUF_LEN;
  228. rds_ring->skb_size =
  229. NX_CT_DEFAULT_RX_BUF_LEN;
  230. } else {
  231. rds_ring->dma_size = RX_DMA_MAP_LEN;
  232. rds_ring->skb_size =
  233. MAX_RX_BUFFER_LENGTH;
  234. }
  235. break;
  236. case RCV_DESC_JUMBO:
  237. rds_ring->max_rx_desc_count =
  238. adapter->max_jumbo_rx_desc_count;
  239. rds_ring->flags = RCV_DESC_JUMBO;
  240. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  241. rds_ring->dma_size =
  242. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  243. else
  244. rds_ring->dma_size =
  245. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  246. rds_ring->skb_size =
  247. rds_ring->dma_size + NET_IP_ALIGN;
  248. break;
  249. case RCV_RING_LRO:
  250. rds_ring->max_rx_desc_count =
  251. adapter->max_lro_rx_desc_count;
  252. rds_ring->flags = RCV_DESC_LRO;
  253. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  254. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  255. break;
  256. }
  257. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  258. vmalloc(RCV_BUFFSIZE);
  259. if (rds_ring->rx_buf_arr == NULL) {
  260. printk(KERN_ERR "%s: Failed to allocate "
  261. "rx buffer ring %d\n",
  262. netdev->name, ring);
  263. /* free whatever was already allocated */
  264. goto err_out;
  265. }
  266. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  267. INIT_LIST_HEAD(&rds_ring->free_list);
  268. /*
  269. * Now go through all of them, set reference handles
  270. * and put them in the queues.
  271. */
  272. num_rx_bufs = rds_ring->max_rx_desc_count;
  273. rx_buf = rds_ring->rx_buf_arr;
  274. for (i = 0; i < num_rx_bufs; i++) {
  275. list_add_tail(&rx_buf->list,
  276. &rds_ring->free_list);
  277. rx_buf->ref_handle = i;
  278. rx_buf->state = NETXEN_BUFFER_FREE;
  279. rx_buf++;
  280. }
  281. }
  282. return 0;
  283. err_out:
  284. netxen_free_sw_resources(adapter);
  285. return -ENOMEM;
  286. }
  287. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  288. {
  289. switch (adapter->ahw.port_type) {
  290. case NETXEN_NIC_GBE:
  291. adapter->enable_phy_interrupts =
  292. netxen_niu_gbe_enable_phy_interrupts;
  293. adapter->disable_phy_interrupts =
  294. netxen_niu_gbe_disable_phy_interrupts;
  295. adapter->macaddr_set = netxen_niu_macaddr_set;
  296. adapter->set_mtu = netxen_nic_set_mtu_gb;
  297. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  298. adapter->phy_read = netxen_niu_gbe_phy_read;
  299. adapter->phy_write = netxen_niu_gbe_phy_write;
  300. adapter->init_port = netxen_niu_gbe_init_port;
  301. adapter->stop_port = netxen_niu_disable_gbe_port;
  302. break;
  303. case NETXEN_NIC_XGBE:
  304. adapter->enable_phy_interrupts =
  305. netxen_niu_xgbe_enable_phy_interrupts;
  306. adapter->disable_phy_interrupts =
  307. netxen_niu_xgbe_disable_phy_interrupts;
  308. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  309. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  310. adapter->init_port = netxen_niu_xg_init_port;
  311. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  312. adapter->stop_port = netxen_niu_disable_xg_port;
  313. break;
  314. default:
  315. break;
  316. }
  317. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  318. adapter->set_mtu = nx_fw_cmd_set_mtu;
  319. adapter->set_promisc = netxen_p3_nic_set_promisc;
  320. }
  321. }
  322. /*
  323. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  324. * address to external PCI CRB address.
  325. */
  326. static u32 netxen_decode_crb_addr(u32 addr)
  327. {
  328. int i;
  329. u32 base_addr, offset, pci_base;
  330. crb_addr_transform_setup();
  331. pci_base = NETXEN_ADDR_ERROR;
  332. base_addr = addr & 0xfff00000;
  333. offset = addr & 0x000fffff;
  334. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  335. if (crb_addr_xform[i] == base_addr) {
  336. pci_base = i << 20;
  337. break;
  338. }
  339. }
  340. if (pci_base == NETXEN_ADDR_ERROR)
  341. return pci_base;
  342. else
  343. return (pci_base + offset);
  344. }
  345. static long rom_max_timeout = 100;
  346. static long rom_lock_timeout = 10000;
  347. static int rom_lock(struct netxen_adapter *adapter)
  348. {
  349. int iter;
  350. u32 done = 0;
  351. int timeout = 0;
  352. while (!done) {
  353. /* acquire semaphore2 from PCI HW block */
  354. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  355. &done);
  356. if (done == 1)
  357. break;
  358. if (timeout >= rom_lock_timeout)
  359. return -EIO;
  360. timeout++;
  361. /*
  362. * Yield CPU
  363. */
  364. if (!in_atomic())
  365. schedule();
  366. else {
  367. for (iter = 0; iter < 20; iter++)
  368. cpu_relax(); /*This a nop instr on i386 */
  369. }
  370. }
  371. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  372. return 0;
  373. }
  374. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  375. {
  376. long timeout = 0;
  377. long done = 0;
  378. cond_resched();
  379. while (done == 0) {
  380. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  381. done &= 2;
  382. timeout++;
  383. if (timeout >= rom_max_timeout) {
  384. printk("Timeout reached waiting for rom done");
  385. return -EIO;
  386. }
  387. }
  388. return 0;
  389. }
  390. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  391. {
  392. u32 val;
  393. /* release semaphore2 */
  394. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  395. }
  396. static int do_rom_fast_read(struct netxen_adapter *adapter,
  397. int addr, int *valp)
  398. {
  399. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  400. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  401. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  402. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  403. if (netxen_wait_rom_done(adapter)) {
  404. printk("Error waiting for rom done\n");
  405. return -EIO;
  406. }
  407. /* reset abyte_cnt and dummy_byte_cnt */
  408. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  409. udelay(10);
  410. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  411. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  412. return 0;
  413. }
  414. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  415. u8 *bytes, size_t size)
  416. {
  417. int addridx;
  418. int ret = 0;
  419. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  420. int v;
  421. ret = do_rom_fast_read(adapter, addridx, &v);
  422. if (ret != 0)
  423. break;
  424. *(__le32 *)bytes = cpu_to_le32(v);
  425. bytes += 4;
  426. }
  427. return ret;
  428. }
  429. int
  430. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  431. u8 *bytes, size_t size)
  432. {
  433. int ret;
  434. ret = rom_lock(adapter);
  435. if (ret < 0)
  436. return ret;
  437. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  438. netxen_rom_unlock(adapter);
  439. return ret;
  440. }
  441. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  442. {
  443. int ret;
  444. if (rom_lock(adapter) != 0)
  445. return -EIO;
  446. ret = do_rom_fast_read(adapter, addr, valp);
  447. netxen_rom_unlock(adapter);
  448. return ret;
  449. }
  450. #define NETXEN_BOARDTYPE 0x4008
  451. #define NETXEN_BOARDNUM 0x400c
  452. #define NETXEN_CHIPNUM 0x4010
  453. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  454. {
  455. int addr, val;
  456. int i, n, init_delay = 0;
  457. struct crb_addr_pair *buf;
  458. unsigned offset;
  459. u32 off;
  460. /* resetall */
  461. rom_lock(adapter);
  462. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  463. 0xffffffff);
  464. netxen_rom_unlock(adapter);
  465. if (verbose) {
  466. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  467. printk("P2 ROM board type: 0x%08x\n", val);
  468. else
  469. printk("Could not read board type\n");
  470. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  471. printk("P2 ROM board num: 0x%08x\n", val);
  472. else
  473. printk("Could not read board number\n");
  474. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  475. printk("P2 ROM chip num: 0x%08x\n", val);
  476. else
  477. printk("Could not read chip number\n");
  478. }
  479. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  480. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  481. (n != 0xcafecafe) ||
  482. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  483. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  484. "n: %08x\n", netxen_nic_driver_name, n);
  485. return -EIO;
  486. }
  487. offset = n & 0xffffU;
  488. n = (n >> 16) & 0xffffU;
  489. } else {
  490. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  491. !(n & 0x80000000)) {
  492. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  493. "n: %08x\n", netxen_nic_driver_name, n);
  494. return -EIO;
  495. }
  496. offset = 1;
  497. n &= ~0x80000000;
  498. }
  499. if (n < 1024) {
  500. if (verbose)
  501. printk(KERN_DEBUG "%s: %d CRB init values found"
  502. " in ROM.\n", netxen_nic_driver_name, n);
  503. } else {
  504. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  505. " initialized.\n", __func__, n);
  506. return -EIO;
  507. }
  508. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  509. if (buf == NULL) {
  510. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  511. netxen_nic_driver_name);
  512. return -ENOMEM;
  513. }
  514. for (i = 0; i < n; i++) {
  515. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  516. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  517. kfree(buf);
  518. return -EIO;
  519. }
  520. buf[i].addr = addr;
  521. buf[i].data = val;
  522. if (verbose)
  523. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  524. netxen_nic_driver_name,
  525. (u32)netxen_decode_crb_addr(addr), val);
  526. }
  527. for (i = 0; i < n; i++) {
  528. off = netxen_decode_crb_addr(buf[i].addr);
  529. if (off == NETXEN_ADDR_ERROR) {
  530. printk(KERN_ERR"CRB init value out of range %x\n",
  531. buf[i].addr);
  532. continue;
  533. }
  534. off += NETXEN_PCI_CRBSPACE;
  535. /* skipping cold reboot MAGIC */
  536. if (off == NETXEN_CAM_RAM(0x1fc))
  537. continue;
  538. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  539. /* do not reset PCI */
  540. if (off == (ROMUSB_GLB + 0xbc))
  541. continue;
  542. if (off == (ROMUSB_GLB + 0xa8))
  543. continue;
  544. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  545. continue;
  546. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  547. continue;
  548. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  549. continue;
  550. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  551. buf[i].data = 0x1020;
  552. /* skip the function enable register */
  553. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  554. continue;
  555. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  556. continue;
  557. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  558. continue;
  559. }
  560. if (off == NETXEN_ADDR_ERROR) {
  561. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  562. netxen_nic_driver_name, buf[i].addr);
  563. continue;
  564. }
  565. init_delay = 1;
  566. /* After writing this register, HW needs time for CRB */
  567. /* to quiet down (else crb_window returns 0xffffffff) */
  568. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  569. init_delay = 1000;
  570. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  571. /* hold xdma in reset also */
  572. buf[i].data = NETXEN_NIC_XDMA_RESET;
  573. buf[i].data = 0x8000ff;
  574. }
  575. }
  576. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  577. msleep(init_delay);
  578. }
  579. kfree(buf);
  580. /* disable_peg_cache_all */
  581. /* unreset_net_cache */
  582. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  583. adapter->hw_read_wx(adapter,
  584. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  585. netxen_crb_writelit_adapter(adapter,
  586. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  587. }
  588. /* p2dn replyCount */
  589. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  590. /* disable_peg_cache 0 */
  591. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  592. /* disable_peg_cache 1 */
  593. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  594. /* peg_clr_all */
  595. /* peg_clr 0 */
  596. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  597. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  598. /* peg_clr 1 */
  599. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  600. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  601. /* peg_clr 2 */
  602. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  603. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  604. /* peg_clr 3 */
  605. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  606. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  607. return 0;
  608. }
  609. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  610. {
  611. uint64_t addr;
  612. uint32_t hi;
  613. uint32_t lo;
  614. adapter->dummy_dma.addr =
  615. pci_alloc_consistent(adapter->pdev,
  616. NETXEN_HOST_DUMMY_DMA_SIZE,
  617. &adapter->dummy_dma.phys_addr);
  618. if (adapter->dummy_dma.addr == NULL) {
  619. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  620. __func__);
  621. return -ENOMEM;
  622. }
  623. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  624. hi = (addr >> 32) & 0xffffffff;
  625. lo = addr & 0xffffffff;
  626. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  627. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  628. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  629. uint32_t temp = 0;
  630. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  631. }
  632. return 0;
  633. }
  634. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  635. {
  636. int i = 100;
  637. if (!adapter->dummy_dma.addr)
  638. return;
  639. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  640. do {
  641. if (dma_watchdog_shutdown_request(adapter) == 1)
  642. break;
  643. msleep(50);
  644. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  645. break;
  646. } while (--i);
  647. }
  648. if (i) {
  649. pci_free_consistent(adapter->pdev,
  650. NETXEN_HOST_DUMMY_DMA_SIZE,
  651. adapter->dummy_dma.addr,
  652. adapter->dummy_dma.phys_addr);
  653. adapter->dummy_dma.addr = NULL;
  654. } else {
  655. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  656. adapter->netdev->name);
  657. }
  658. }
  659. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  660. {
  661. u32 val = 0;
  662. int retries = 60;
  663. if (!pegtune_val) {
  664. do {
  665. val = adapter->pci_read_normalize(adapter,
  666. CRB_CMDPEG_STATE);
  667. if (val == PHAN_INITIALIZE_COMPLETE ||
  668. val == PHAN_INITIALIZE_ACK)
  669. return 0;
  670. msleep(500);
  671. } while (--retries);
  672. if (!retries) {
  673. pegtune_val = adapter->pci_read_normalize(adapter,
  674. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  675. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  676. "pegtune_val=%x\n", pegtune_val);
  677. return -1;
  678. }
  679. }
  680. return 0;
  681. }
  682. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  683. {
  684. u32 val = 0;
  685. int retries = 2000;
  686. do {
  687. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  688. if (val == PHAN_PEG_RCV_INITIALIZED)
  689. return 0;
  690. msleep(10);
  691. } while (--retries);
  692. if (!retries) {
  693. printk(KERN_ERR "Receive Peg initialization not "
  694. "complete, state: 0x%x.\n", val);
  695. return -EIO;
  696. }
  697. return 0;
  698. }
  699. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  700. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  701. {
  702. struct netxen_rx_buffer *buffer;
  703. struct sk_buff *skb;
  704. buffer = &rds_ring->rx_buf_arr[index];
  705. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  706. PCI_DMA_FROMDEVICE);
  707. skb = buffer->skb;
  708. if (!skb)
  709. goto no_skb;
  710. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  711. adapter->stats.csummed++;
  712. skb->ip_summed = CHECKSUM_UNNECESSARY;
  713. } else
  714. skb->ip_summed = CHECKSUM_NONE;
  715. skb->dev = adapter->netdev;
  716. buffer->skb = NULL;
  717. no_skb:
  718. buffer->state = NETXEN_BUFFER_FREE;
  719. buffer->lro_current_frags = 0;
  720. buffer->lro_expected_frags = 0;
  721. list_add_tail(&buffer->list, &rds_ring->free_list);
  722. return skb;
  723. }
  724. static void netxen_process_rcv(struct netxen_adapter *adapter,
  725. struct status_desc *desc)
  726. {
  727. struct net_device *netdev = adapter->netdev;
  728. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  729. int index = netxen_get_sts_refhandle(sts_data);
  730. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  731. struct netxen_rx_buffer *buffer;
  732. struct sk_buff *skb;
  733. u32 length = netxen_get_sts_totallength(sts_data);
  734. u32 desc_ctx;
  735. u16 pkt_offset = 0, cksum;
  736. struct nx_host_rds_ring *rds_ring;
  737. desc_ctx = netxen_get_sts_type(sts_data);
  738. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  739. return;
  740. }
  741. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  742. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  743. return;
  744. }
  745. buffer = &rds_ring->rx_buf_arr[index];
  746. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  747. buffer->lro_current_frags++;
  748. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  749. buffer->lro_expected_frags =
  750. netxen_get_sts_desc_lro_cnt(desc);
  751. buffer->lro_length = length;
  752. }
  753. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  754. return;
  755. }
  756. }
  757. cksum = netxen_get_sts_status(sts_data);
  758. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  759. if (!skb)
  760. return;
  761. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  762. /* True length was only available on the last pkt */
  763. skb_put(skb, buffer->lro_length);
  764. } else {
  765. if (length > rds_ring->skb_size)
  766. skb_put(skb, rds_ring->skb_size);
  767. else
  768. skb_put(skb, length);
  769. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  770. if (pkt_offset)
  771. skb_pull(skb, pkt_offset);
  772. }
  773. skb->protocol = eth_type_trans(skb, netdev);
  774. netif_receive_skb(skb);
  775. adapter->stats.no_rcv++;
  776. adapter->stats.rxbytes += length;
  777. }
  778. int
  779. netxen_process_rcv_ring(struct netxen_adapter *adapter, int max)
  780. {
  781. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  782. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  783. struct status_desc *desc;
  784. u32 consumer = recv_ctx->status_rx_consumer;
  785. int count = 0, ring;
  786. u64 sts_data;
  787. u16 opcode;
  788. while (count < max) {
  789. desc = &desc_head[consumer];
  790. sts_data = le64_to_cpu(desc->status_desc_data);
  791. if (!(sts_data & STATUS_OWNER_HOST))
  792. break;
  793. opcode = netxen_get_sts_opcode(sts_data);
  794. netxen_process_rcv(adapter, desc);
  795. desc->status_desc_data = cpu_to_le64(STATUS_OWNER_PHANTOM);
  796. consumer = get_next_index(consumer,
  797. adapter->max_rx_desc_count);
  798. count++;
  799. }
  800. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  801. netxen_post_rx_buffers_nodb(adapter, ring);
  802. if (count) {
  803. recv_ctx->status_rx_consumer = consumer;
  804. adapter->pci_write_normalize(adapter,
  805. recv_ctx->crb_sts_consumer, consumer);
  806. }
  807. return count;
  808. }
  809. /* Process Command status ring */
  810. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  811. {
  812. u32 last_consumer, consumer;
  813. int count = 0, i;
  814. struct netxen_cmd_buffer *buffer;
  815. struct pci_dev *pdev = adapter->pdev;
  816. struct net_device *netdev = adapter->netdev;
  817. struct netxen_skb_frag *frag;
  818. int done = 0;
  819. last_consumer = adapter->last_cmd_consumer;
  820. barrier(); /* cmd_consumer can change underneath */
  821. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  822. while (last_consumer != consumer) {
  823. buffer = &adapter->cmd_buf_arr[last_consumer];
  824. if (buffer->skb) {
  825. frag = &buffer->frag_array[0];
  826. pci_unmap_single(pdev, frag->dma, frag->length,
  827. PCI_DMA_TODEVICE);
  828. frag->dma = 0ULL;
  829. for (i = 1; i < buffer->frag_count; i++) {
  830. frag++; /* Get the next frag */
  831. pci_unmap_page(pdev, frag->dma, frag->length,
  832. PCI_DMA_TODEVICE);
  833. frag->dma = 0ULL;
  834. }
  835. adapter->stats.xmitfinished++;
  836. dev_kfree_skb_any(buffer->skb);
  837. buffer->skb = NULL;
  838. }
  839. last_consumer = get_next_index(last_consumer,
  840. adapter->max_tx_desc_count);
  841. if (++count >= MAX_STATUS_HANDLE)
  842. break;
  843. }
  844. if (count) {
  845. adapter->last_cmd_consumer = last_consumer;
  846. smp_mb();
  847. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  848. netif_tx_lock(netdev);
  849. netif_wake_queue(netdev);
  850. smp_mb();
  851. netif_tx_unlock(netdev);
  852. }
  853. }
  854. /*
  855. * If everything is freed up to consumer then check if the ring is full
  856. * If the ring is full then check if more needs to be freed and
  857. * schedule the call back again.
  858. *
  859. * This happens when there are 2 CPUs. One could be freeing and the
  860. * other filling it. If the ring is full when we get out of here and
  861. * the card has already interrupted the host then the host can miss the
  862. * interrupt.
  863. *
  864. * There is still a possible race condition and the host could miss an
  865. * interrupt. The card has to take care of this.
  866. */
  867. barrier(); /* cmd_consumer can change underneath */
  868. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  869. done = (last_consumer == consumer);
  870. return (done);
  871. }
  872. void
  873. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid)
  874. {
  875. struct pci_dev *pdev = adapter->pdev;
  876. struct sk_buff *skb;
  877. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  878. struct nx_host_rds_ring *rds_ring = NULL;
  879. uint producer;
  880. struct rcv_desc *pdesc;
  881. struct netxen_rx_buffer *buffer;
  882. int count = 0;
  883. netxen_ctx_msg msg = 0;
  884. dma_addr_t dma;
  885. struct list_head *head;
  886. rds_ring = &recv_ctx->rds_rings[ringid];
  887. producer = rds_ring->producer;
  888. head = &rds_ring->free_list;
  889. /* We can start writing rx descriptors into the phantom memory. */
  890. while (!list_empty(head)) {
  891. skb = dev_alloc_skb(rds_ring->skb_size);
  892. if (unlikely(!skb)) {
  893. break;
  894. }
  895. if (!adapter->ahw.cut_through)
  896. skb_reserve(skb, 2);
  897. dma = pci_map_single(pdev, skb->data,
  898. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  899. if (pci_dma_mapping_error(pdev, dma)) {
  900. dev_kfree_skb_any(skb);
  901. break;
  902. }
  903. count++;
  904. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  905. list_del(&buffer->list);
  906. buffer->skb = skb;
  907. buffer->state = NETXEN_BUFFER_BUSY;
  908. buffer->dma = dma;
  909. /* make a rcv descriptor */
  910. pdesc = &rds_ring->desc_head[producer];
  911. pdesc->addr_buffer = cpu_to_le64(dma);
  912. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  913. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  914. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  915. }
  916. /* if we did allocate buffers, then write the count to Phantom */
  917. if (count) {
  918. rds_ring->producer = producer;
  919. /* Window = 1 */
  920. adapter->pci_write_normalize(adapter,
  921. rds_ring->crb_rcv_producer,
  922. (producer-1) & (rds_ring->max_rx_desc_count-1));
  923. if (adapter->fw_major < 4) {
  924. /*
  925. * Write a doorbell msg to tell phanmon of change in
  926. * receive ring producer
  927. * Only for firmware version < 4.0.0
  928. */
  929. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  930. netxen_set_msg_privid(msg);
  931. netxen_set_msg_count(msg,
  932. ((producer -
  933. 1) & (rds_ring->
  934. max_rx_desc_count - 1)));
  935. netxen_set_msg_ctxid(msg, adapter->portnum);
  936. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  937. writel(msg,
  938. DB_NORMALIZE(adapter,
  939. NETXEN_RCV_PRODUCER_OFFSET));
  940. }
  941. }
  942. }
  943. static void
  944. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ringid)
  945. {
  946. struct pci_dev *pdev = adapter->pdev;
  947. struct sk_buff *skb;
  948. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  949. struct nx_host_rds_ring *rds_ring = NULL;
  950. u32 producer;
  951. struct rcv_desc *pdesc;
  952. struct netxen_rx_buffer *buffer;
  953. int count = 0;
  954. struct list_head *head;
  955. dma_addr_t dma;
  956. rds_ring = &recv_ctx->rds_rings[ringid];
  957. producer = rds_ring->producer;
  958. head = &rds_ring->free_list;
  959. /* We can start writing rx descriptors into the phantom memory. */
  960. while (!list_empty(head)) {
  961. skb = dev_alloc_skb(rds_ring->skb_size);
  962. if (unlikely(!skb)) {
  963. break;
  964. }
  965. if (!adapter->ahw.cut_through)
  966. skb_reserve(skb, 2);
  967. dma = pci_map_single(pdev, skb->data,
  968. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  969. if (pci_dma_mapping_error(pdev, dma)) {
  970. dev_kfree_skb_any(skb);
  971. break;
  972. }
  973. count++;
  974. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  975. list_del(&buffer->list);
  976. buffer->skb = skb;
  977. buffer->state = NETXEN_BUFFER_BUSY;
  978. buffer->dma = dma;
  979. /* make a rcv descriptor */
  980. pdesc = &rds_ring->desc_head[producer];
  981. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  982. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  983. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  984. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  985. }
  986. /* if we did allocate buffers, then write the count to Phantom */
  987. if (count) {
  988. rds_ring->producer = producer;
  989. /* Window = 1 */
  990. adapter->pci_write_normalize(adapter,
  991. rds_ring->crb_rcv_producer,
  992. (producer-1) & (rds_ring->max_rx_desc_count-1));
  993. wmb();
  994. }
  995. }
  996. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  997. {
  998. memset(&adapter->stats, 0, sizeof(adapter->stats));
  999. return;
  1000. }