rtc-s3c.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650
  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <mach/hardware.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <plat/regs-rtc.h>
  32. enum s3c_cpu_type {
  33. TYPE_S3C2410,
  34. TYPE_S3C64XX,
  35. };
  36. /* I have yet to find an S3C implementation with more than one
  37. * of these rtc blocks in */
  38. static struct resource *s3c_rtc_mem;
  39. static struct clk *rtc_clk;
  40. static void __iomem *s3c_rtc_base;
  41. static int s3c_rtc_alarmno = NO_IRQ;
  42. static int s3c_rtc_tickno = NO_IRQ;
  43. static bool wake_en;
  44. static enum s3c_cpu_type s3c_rtc_cpu_type;
  45. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  46. /* IRQ Handlers */
  47. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  48. {
  49. struct rtc_device *rdev = id;
  50. clk_enable(rtc_clk);
  51. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  52. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  53. writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
  54. clk_disable(rtc_clk);
  55. return IRQ_HANDLED;
  56. }
  57. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  58. {
  59. struct rtc_device *rdev = id;
  60. clk_enable(rtc_clk);
  61. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  62. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  63. writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
  64. clk_disable(rtc_clk);
  65. return IRQ_HANDLED;
  66. }
  67. /* Update control registers */
  68. static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
  69. {
  70. unsigned int tmp;
  71. pr_debug("%s: aie=%d\n", __func__, enabled);
  72. clk_enable(rtc_clk);
  73. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  74. if (enabled)
  75. tmp |= S3C2410_RTCALM_ALMEN;
  76. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  77. clk_disable(rtc_clk);
  78. return 0;
  79. }
  80. static int s3c_rtc_setfreq(struct device *dev, int freq)
  81. {
  82. struct platform_device *pdev = to_platform_device(dev);
  83. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  84. unsigned int tmp = 0;
  85. if (!is_power_of_2(freq))
  86. return -EINVAL;
  87. clk_enable(rtc_clk);
  88. spin_lock_irq(&s3c_rtc_pie_lock);
  89. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  90. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  91. tmp &= S3C2410_TICNT_ENABLE;
  92. }
  93. tmp |= (rtc_dev->max_user_freq / freq)-1;
  94. writel(tmp, s3c_rtc_base + S3C2410_TICNT);
  95. spin_unlock_irq(&s3c_rtc_pie_lock);
  96. clk_disable(rtc_clk);
  97. return 0;
  98. }
  99. /* Time read/write */
  100. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  101. {
  102. unsigned int have_retried = 0;
  103. void __iomem *base = s3c_rtc_base;
  104. clk_enable(rtc_clk);
  105. retry_get_time:
  106. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  107. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  108. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  109. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  110. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  111. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  112. /* the only way to work out wether the system was mid-update
  113. * when we read it is to check the second counter, and if it
  114. * is zero, then we re-try the entire read
  115. */
  116. if (rtc_tm->tm_sec == 0 && !have_retried) {
  117. have_retried = 1;
  118. goto retry_get_time;
  119. }
  120. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  121. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  122. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  123. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  124. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  125. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  126. rtc_tm->tm_year += 100;
  127. pr_debug("read time %04d.%02d.%02d %02d:%02d:%02d\n",
  128. 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  129. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  130. rtc_tm->tm_mon -= 1;
  131. clk_disable(rtc_clk);
  132. return rtc_valid_tm(rtc_tm);
  133. }
  134. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  135. {
  136. void __iomem *base = s3c_rtc_base;
  137. int year = tm->tm_year - 100;
  138. clk_enable(rtc_clk);
  139. pr_debug("set time %04d.%02d.%02d %02d:%02d:%02d\n",
  140. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  141. tm->tm_hour, tm->tm_min, tm->tm_sec);
  142. /* we get around y2k by simply not supporting it */
  143. if (year < 0 || year >= 100) {
  144. dev_err(dev, "rtc only supports 100 years\n");
  145. return -EINVAL;
  146. }
  147. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  148. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  149. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  150. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  151. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  152. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  153. clk_disable(rtc_clk);
  154. return 0;
  155. }
  156. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  157. {
  158. struct rtc_time *alm_tm = &alrm->time;
  159. void __iomem *base = s3c_rtc_base;
  160. unsigned int alm_en;
  161. clk_enable(rtc_clk);
  162. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  163. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  164. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  165. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  166. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  167. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  168. alm_en = readb(base + S3C2410_RTCALM);
  169. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  170. pr_debug("read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  171. alm_en,
  172. 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  173. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  174. /* decode the alarm enable field */
  175. if (alm_en & S3C2410_RTCALM_SECEN)
  176. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  177. else
  178. alm_tm->tm_sec = -1;
  179. if (alm_en & S3C2410_RTCALM_MINEN)
  180. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  181. else
  182. alm_tm->tm_min = -1;
  183. if (alm_en & S3C2410_RTCALM_HOUREN)
  184. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  185. else
  186. alm_tm->tm_hour = -1;
  187. if (alm_en & S3C2410_RTCALM_DAYEN)
  188. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  189. else
  190. alm_tm->tm_mday = -1;
  191. if (alm_en & S3C2410_RTCALM_MONEN) {
  192. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  193. alm_tm->tm_mon -= 1;
  194. } else {
  195. alm_tm->tm_mon = -1;
  196. }
  197. if (alm_en & S3C2410_RTCALM_YEAREN)
  198. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  199. else
  200. alm_tm->tm_year = -1;
  201. clk_disable(rtc_clk);
  202. return 0;
  203. }
  204. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  205. {
  206. struct rtc_time *tm = &alrm->time;
  207. void __iomem *base = s3c_rtc_base;
  208. unsigned int alrm_en;
  209. clk_enable(rtc_clk);
  210. pr_debug("s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  211. alrm->enabled,
  212. 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
  213. tm->tm_hour, tm->tm_min, tm->tm_sec);
  214. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  215. writeb(0x00, base + S3C2410_RTCALM);
  216. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  217. alrm_en |= S3C2410_RTCALM_SECEN;
  218. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  219. }
  220. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  221. alrm_en |= S3C2410_RTCALM_MINEN;
  222. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  223. }
  224. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  225. alrm_en |= S3C2410_RTCALM_HOUREN;
  226. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  227. }
  228. pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en);
  229. writeb(alrm_en, base + S3C2410_RTCALM);
  230. s3c_rtc_setaie(dev, alrm->enabled);
  231. clk_disable(rtc_clk);
  232. return 0;
  233. }
  234. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  235. {
  236. unsigned int ticnt;
  237. clk_enable(rtc_clk);
  238. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  239. ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
  240. ticnt &= S3C64XX_RTCCON_TICEN;
  241. } else {
  242. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  243. ticnt &= S3C2410_TICNT_ENABLE;
  244. }
  245. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  246. clk_disable(rtc_clk);
  247. return 0;
  248. }
  249. static const struct rtc_class_ops s3c_rtcops = {
  250. .read_time = s3c_rtc_gettime,
  251. .set_time = s3c_rtc_settime,
  252. .read_alarm = s3c_rtc_getalarm,
  253. .set_alarm = s3c_rtc_setalarm,
  254. .proc = s3c_rtc_proc,
  255. .alarm_irq_enable = s3c_rtc_setaie,
  256. };
  257. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  258. {
  259. void __iomem *base = s3c_rtc_base;
  260. unsigned int tmp;
  261. if (s3c_rtc_base == NULL)
  262. return;
  263. clk_enable(rtc_clk);
  264. if (!en) {
  265. tmp = readw(base + S3C2410_RTCCON);
  266. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  267. tmp &= ~S3C64XX_RTCCON_TICEN;
  268. tmp &= ~S3C2410_RTCCON_RTCEN;
  269. writew(tmp, base + S3C2410_RTCCON);
  270. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  271. tmp = readb(base + S3C2410_TICNT);
  272. tmp &= ~S3C2410_TICNT_ENABLE;
  273. writeb(tmp, base + S3C2410_TICNT);
  274. }
  275. } else {
  276. /* re-enable the device, and check it is ok */
  277. if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
  278. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  279. tmp = readw(base + S3C2410_RTCCON);
  280. writew(tmp | S3C2410_RTCCON_RTCEN,
  281. base + S3C2410_RTCCON);
  282. }
  283. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
  284. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  285. tmp = readw(base + S3C2410_RTCCON);
  286. writew(tmp & ~S3C2410_RTCCON_CNTSEL,
  287. base + S3C2410_RTCCON);
  288. }
  289. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
  290. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  291. tmp = readw(base + S3C2410_RTCCON);
  292. writew(tmp & ~S3C2410_RTCCON_CLKRST,
  293. base + S3C2410_RTCCON);
  294. }
  295. }
  296. clk_disable(rtc_clk);
  297. }
  298. static int __devexit s3c_rtc_remove(struct platform_device *dev)
  299. {
  300. struct rtc_device *rtc = platform_get_drvdata(dev);
  301. free_irq(s3c_rtc_alarmno, rtc);
  302. free_irq(s3c_rtc_tickno, rtc);
  303. platform_set_drvdata(dev, NULL);
  304. rtc_device_unregister(rtc);
  305. s3c_rtc_setaie(&dev->dev, 0);
  306. clk_put(rtc_clk);
  307. rtc_clk = NULL;
  308. iounmap(s3c_rtc_base);
  309. release_resource(s3c_rtc_mem);
  310. kfree(s3c_rtc_mem);
  311. return 0;
  312. }
  313. static int __devinit s3c_rtc_probe(struct platform_device *pdev)
  314. {
  315. struct rtc_device *rtc;
  316. struct rtc_time rtc_tm;
  317. struct resource *res;
  318. int ret;
  319. pr_debug("%s: probe=%p\n", __func__, pdev);
  320. /* find the IRQs */
  321. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  322. if (s3c_rtc_tickno < 0) {
  323. dev_err(&pdev->dev, "no irq for rtc tick\n");
  324. return -ENOENT;
  325. }
  326. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  327. if (s3c_rtc_alarmno < 0) {
  328. dev_err(&pdev->dev, "no irq for alarm\n");
  329. return -ENOENT;
  330. }
  331. pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n",
  332. s3c_rtc_tickno, s3c_rtc_alarmno);
  333. /* get the memory region */
  334. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  335. if (res == NULL) {
  336. dev_err(&pdev->dev, "failed to get memory region resource\n");
  337. return -ENOENT;
  338. }
  339. s3c_rtc_mem = request_mem_region(res->start, resource_size(res),
  340. pdev->name);
  341. if (s3c_rtc_mem == NULL) {
  342. dev_err(&pdev->dev, "failed to reserve memory region\n");
  343. ret = -ENOENT;
  344. goto err_nores;
  345. }
  346. s3c_rtc_base = ioremap(res->start, resource_size(res));
  347. if (s3c_rtc_base == NULL) {
  348. dev_err(&pdev->dev, "failed ioremap()\n");
  349. ret = -EINVAL;
  350. goto err_nomap;
  351. }
  352. rtc_clk = clk_get(&pdev->dev, "rtc");
  353. if (IS_ERR(rtc_clk)) {
  354. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  355. ret = PTR_ERR(rtc_clk);
  356. rtc_clk = NULL;
  357. goto err_clk;
  358. }
  359. clk_enable(rtc_clk);
  360. /* check to see if everything is setup correctly */
  361. s3c_rtc_enable(pdev, 1);
  362. pr_debug("s3c2410_rtc: RTCCON=%02x\n",
  363. readw(s3c_rtc_base + S3C2410_RTCCON));
  364. device_init_wakeup(&pdev->dev, 1);
  365. /* register RTC and exit */
  366. rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
  367. THIS_MODULE);
  368. if (IS_ERR(rtc)) {
  369. dev_err(&pdev->dev, "cannot attach rtc\n");
  370. ret = PTR_ERR(rtc);
  371. goto err_nortc;
  372. }
  373. s3c_rtc_cpu_type = platform_get_device_id(pdev)->driver_data;
  374. /* Check RTC Time */
  375. s3c_rtc_gettime(NULL, &rtc_tm);
  376. if (rtc_valid_tm(&rtc_tm)) {
  377. rtc_tm.tm_year = 100;
  378. rtc_tm.tm_mon = 0;
  379. rtc_tm.tm_mday = 1;
  380. rtc_tm.tm_hour = 0;
  381. rtc_tm.tm_min = 0;
  382. rtc_tm.tm_sec = 0;
  383. s3c_rtc_settime(NULL, &rtc_tm);
  384. dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
  385. }
  386. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  387. rtc->max_user_freq = 32768;
  388. else
  389. rtc->max_user_freq = 128;
  390. platform_set_drvdata(pdev, rtc);
  391. s3c_rtc_setfreq(&pdev->dev, 1);
  392. ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq,
  393. IRQF_DISABLED, "s3c2410-rtc alarm", rtc);
  394. if (ret) {
  395. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  396. goto err_alarm_irq;
  397. }
  398. ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq,
  399. IRQF_DISABLED, "s3c2410-rtc tick", rtc);
  400. if (ret) {
  401. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  402. free_irq(s3c_rtc_alarmno, rtc);
  403. goto err_tick_irq;
  404. }
  405. clk_disable(rtc_clk);
  406. return 0;
  407. err_tick_irq:
  408. free_irq(s3c_rtc_alarmno, rtc);
  409. err_alarm_irq:
  410. platform_set_drvdata(pdev, NULL);
  411. rtc_device_unregister(rtc);
  412. err_nortc:
  413. s3c_rtc_enable(pdev, 0);
  414. clk_disable(rtc_clk);
  415. clk_put(rtc_clk);
  416. err_clk:
  417. iounmap(s3c_rtc_base);
  418. err_nomap:
  419. release_resource(s3c_rtc_mem);
  420. err_nores:
  421. return ret;
  422. }
  423. #ifdef CONFIG_PM
  424. /* RTC Power management control */
  425. static int ticnt_save, ticnt_en_save;
  426. static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  427. {
  428. clk_enable(rtc_clk);
  429. /* save TICNT for anyone using periodic interrupts */
  430. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  431. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  432. ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
  433. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  434. }
  435. s3c_rtc_enable(pdev, 0);
  436. if (device_may_wakeup(&pdev->dev) && !wake_en) {
  437. if (enable_irq_wake(s3c_rtc_alarmno) == 0)
  438. wake_en = true;
  439. else
  440. dev_err(&pdev->dev, "enable_irq_wake failed\n");
  441. }
  442. clk_disable(rtc_clk);
  443. return 0;
  444. }
  445. static int s3c_rtc_resume(struct platform_device *pdev)
  446. {
  447. unsigned int tmp;
  448. clk_enable(rtc_clk);
  449. s3c_rtc_enable(pdev, 1);
  450. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  451. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  452. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  453. writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  454. }
  455. if (device_may_wakeup(&pdev->dev) && wake_en) {
  456. disable_irq_wake(s3c_rtc_alarmno);
  457. wake_en = false;
  458. }
  459. clk_disable(rtc_clk);
  460. return 0;
  461. }
  462. #else
  463. #define s3c_rtc_suspend NULL
  464. #define s3c_rtc_resume NULL
  465. #endif
  466. static struct platform_device_id s3c_rtc_driver_ids[] = {
  467. {
  468. .name = "s3c2410-rtc",
  469. .driver_data = TYPE_S3C2410,
  470. }, {
  471. .name = "s3c64xx-rtc",
  472. .driver_data = TYPE_S3C64XX,
  473. },
  474. { }
  475. };
  476. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  477. static struct platform_driver s3c_rtc_driver = {
  478. .probe = s3c_rtc_probe,
  479. .remove = __devexit_p(s3c_rtc_remove),
  480. .suspend = s3c_rtc_suspend,
  481. .resume = s3c_rtc_resume,
  482. .id_table = s3c_rtc_driver_ids,
  483. .driver = {
  484. .name = "s3c-rtc",
  485. .owner = THIS_MODULE,
  486. },
  487. };
  488. static char __initdata banner[] = "S3C24XX RTC, (c) 2004,2006 Simtec Electronics\n";
  489. static int __init s3c_rtc_init(void)
  490. {
  491. printk(banner);
  492. return platform_driver_register(&s3c_rtc_driver);
  493. }
  494. static void __exit s3c_rtc_exit(void)
  495. {
  496. platform_driver_unregister(&s3c_rtc_driver);
  497. }
  498. module_init(s3c_rtc_init);
  499. module_exit(s3c_rtc_exit);
  500. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  501. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  502. MODULE_LICENSE("GPL");
  503. MODULE_ALIAS("platform:s3c2410-rtc");