sdhci-esdhc-imx.c 15 KB

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  1. /*
  2. * Freescale eSDHC i.MX controller driver for the platform bus.
  3. *
  4. * derived from the OF-version.
  5. *
  6. * Copyright (c) 2010 Pengutronix e.K.
  7. * Author: Wolfram Sang <w.sang@pengutronix.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/io.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/gpio.h>
  18. #include <linux/module.h>
  19. #include <linux/slab.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/mmc/mmc.h>
  22. #include <linux/mmc/sdio.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/of_gpio.h>
  26. #include <mach/esdhc.h>
  27. #include "sdhci-pltfm.h"
  28. #include "sdhci-esdhc.h"
  29. #define SDHCI_CTRL_D3CD 0x08
  30. /* VENDOR SPEC register */
  31. #define SDHCI_VENDOR_SPEC 0xC0
  32. #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
  33. /*
  34. * The CMDTYPE of the CMD register (offset 0xE) should be set to
  35. * "11" when the STOP CMD12 is issued on imx53 to abort one
  36. * open ended multi-blk IO. Otherwise the TC INT wouldn't
  37. * be generated.
  38. * In exact block transfer, the controller doesn't complete the
  39. * operations automatically as required at the end of the
  40. * transfer and remains on hold if the abort command is not sent.
  41. * As a result, the TC flag is not asserted and SW received timeout
  42. * exeception. Bit1 of Vendor Spec registor is used to fix it.
  43. */
  44. #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
  45. enum imx_esdhc_type {
  46. IMX25_ESDHC,
  47. IMX35_ESDHC,
  48. IMX51_ESDHC,
  49. IMX53_ESDHC,
  50. };
  51. struct pltfm_imx_data {
  52. int flags;
  53. u32 scratchpad;
  54. enum imx_esdhc_type devtype;
  55. struct esdhc_platform_data boarddata;
  56. };
  57. static struct platform_device_id imx_esdhc_devtype[] = {
  58. {
  59. .name = "sdhci-esdhc-imx25",
  60. .driver_data = IMX25_ESDHC,
  61. }, {
  62. .name = "sdhci-esdhc-imx35",
  63. .driver_data = IMX35_ESDHC,
  64. }, {
  65. .name = "sdhci-esdhc-imx51",
  66. .driver_data = IMX51_ESDHC,
  67. }, {
  68. .name = "sdhci-esdhc-imx53",
  69. .driver_data = IMX53_ESDHC,
  70. }, {
  71. /* sentinel */
  72. }
  73. };
  74. MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
  75. static const struct of_device_id imx_esdhc_dt_ids[] = {
  76. { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
  77. { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
  78. { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
  79. { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
  80. { /* sentinel */ }
  81. };
  82. MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
  83. static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
  84. {
  85. return data->devtype == IMX25_ESDHC;
  86. }
  87. static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
  88. {
  89. return data->devtype == IMX35_ESDHC;
  90. }
  91. static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
  92. {
  93. return data->devtype == IMX51_ESDHC;
  94. }
  95. static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
  96. {
  97. return data->devtype == IMX53_ESDHC;
  98. }
  99. static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
  100. {
  101. void __iomem *base = host->ioaddr + (reg & ~0x3);
  102. u32 shift = (reg & 0x3) * 8;
  103. writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
  104. }
  105. static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
  106. {
  107. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  108. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  109. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  110. /* fake CARD_PRESENT flag */
  111. u32 val = readl(host->ioaddr + reg);
  112. if (unlikely((reg == SDHCI_PRESENT_STATE)
  113. && gpio_is_valid(boarddata->cd_gpio))) {
  114. if (gpio_get_value(boarddata->cd_gpio))
  115. /* no card, if a valid gpio says so... */
  116. val &= ~SDHCI_CARD_PRESENT;
  117. else
  118. /* ... in all other cases assume card is present */
  119. val |= SDHCI_CARD_PRESENT;
  120. }
  121. return val;
  122. }
  123. static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
  124. {
  125. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  126. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  127. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  128. u32 data;
  129. if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
  130. if (boarddata->cd_type == ESDHC_CD_GPIO)
  131. /*
  132. * These interrupts won't work with a custom
  133. * card_detect gpio (only applied to mx25/35)
  134. */
  135. val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
  136. if (val & SDHCI_INT_CARD_INT) {
  137. /*
  138. * Clear and then set D3CD bit to avoid missing the
  139. * card interrupt. This is a eSDHC controller problem
  140. * so we need to apply the following workaround: clear
  141. * and set D3CD bit will make eSDHC re-sample the card
  142. * interrupt. In case a card interrupt was lost,
  143. * re-sample it by the following steps.
  144. */
  145. data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
  146. data &= ~SDHCI_CTRL_D3CD;
  147. writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
  148. data |= SDHCI_CTRL_D3CD;
  149. writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
  150. }
  151. }
  152. if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  153. && (reg == SDHCI_INT_STATUS)
  154. && (val & SDHCI_INT_DATA_END))) {
  155. u32 v;
  156. v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
  157. v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
  158. writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
  159. }
  160. writel(val, host->ioaddr + reg);
  161. }
  162. static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
  163. {
  164. if (unlikely(reg == SDHCI_HOST_VERSION))
  165. reg ^= 2;
  166. return readw(host->ioaddr + reg);
  167. }
  168. static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
  169. {
  170. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  171. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  172. switch (reg) {
  173. case SDHCI_TRANSFER_MODE:
  174. /*
  175. * Postpone this write, we must do it together with a
  176. * command write that is down below.
  177. */
  178. if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  179. && (host->cmd->opcode == SD_IO_RW_EXTENDED)
  180. && (host->cmd->data->blocks > 1)
  181. && (host->cmd->data->flags & MMC_DATA_READ)) {
  182. u32 v;
  183. v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
  184. v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
  185. writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
  186. }
  187. imx_data->scratchpad = val;
  188. return;
  189. case SDHCI_COMMAND:
  190. if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
  191. && (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
  192. val |= SDHCI_CMD_ABORTCMD;
  193. writel(val << 16 | imx_data->scratchpad,
  194. host->ioaddr + SDHCI_TRANSFER_MODE);
  195. return;
  196. case SDHCI_BLOCK_SIZE:
  197. val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  198. break;
  199. }
  200. esdhc_clrset_le(host, 0xffff, val, reg);
  201. }
  202. static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
  203. {
  204. u32 new_val;
  205. switch (reg) {
  206. case SDHCI_POWER_CONTROL:
  207. /*
  208. * FSL put some DMA bits here
  209. * If your board has a regulator, code should be here
  210. */
  211. return;
  212. case SDHCI_HOST_CONTROL:
  213. /* FSL messed up here, so we can just keep those three */
  214. new_val = val & (SDHCI_CTRL_LED | \
  215. SDHCI_CTRL_4BITBUS | \
  216. SDHCI_CTRL_D3CD);
  217. /* ensure the endianess */
  218. new_val |= ESDHC_HOST_CONTROL_LE;
  219. /* DMA mode bits are shifted */
  220. new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
  221. esdhc_clrset_le(host, 0xffff, new_val, reg);
  222. return;
  223. }
  224. esdhc_clrset_le(host, 0xff, val, reg);
  225. /*
  226. * The esdhc has a design violation to SDHC spec which tells
  227. * that software reset should not affect card detection circuit.
  228. * But esdhc clears its SYSCTL register bits [0..2] during the
  229. * software reset. This will stop those clocks that card detection
  230. * circuit relies on. To work around it, we turn the clocks on back
  231. * to keep card detection circuit functional.
  232. */
  233. if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1))
  234. esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
  235. }
  236. static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
  237. {
  238. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  239. return clk_get_rate(pltfm_host->clk);
  240. }
  241. static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
  242. {
  243. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  244. return clk_get_rate(pltfm_host->clk) / 256 / 16;
  245. }
  246. static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
  247. {
  248. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  249. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  250. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  251. switch (boarddata->wp_type) {
  252. case ESDHC_WP_GPIO:
  253. if (gpio_is_valid(boarddata->wp_gpio))
  254. return gpio_get_value(boarddata->wp_gpio);
  255. case ESDHC_WP_CONTROLLER:
  256. return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  257. SDHCI_WRITE_PROTECT);
  258. case ESDHC_WP_NONE:
  259. break;
  260. }
  261. return -ENOSYS;
  262. }
  263. static struct sdhci_ops sdhci_esdhc_ops = {
  264. .read_l = esdhc_readl_le,
  265. .read_w = esdhc_readw_le,
  266. .write_l = esdhc_writel_le,
  267. .write_w = esdhc_writew_le,
  268. .write_b = esdhc_writeb_le,
  269. .set_clock = esdhc_set_clock,
  270. .get_max_clock = esdhc_pltfm_get_max_clock,
  271. .get_min_clock = esdhc_pltfm_get_min_clock,
  272. .get_ro = esdhc_pltfm_get_ro,
  273. };
  274. static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
  275. .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA
  276. | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  277. /* ADMA has issues. Might be fixable */
  278. .ops = &sdhci_esdhc_ops,
  279. };
  280. static irqreturn_t cd_irq(int irq, void *data)
  281. {
  282. struct sdhci_host *sdhost = (struct sdhci_host *)data;
  283. tasklet_schedule(&sdhost->card_tasklet);
  284. return IRQ_HANDLED;
  285. };
  286. #ifdef CONFIG_OF
  287. static int __devinit
  288. sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
  289. struct esdhc_platform_data *boarddata)
  290. {
  291. struct device_node *np = pdev->dev.of_node;
  292. if (!np)
  293. return -ENODEV;
  294. if (of_get_property(np, "fsl,card-wired", NULL))
  295. boarddata->cd_type = ESDHC_CD_PERMANENT;
  296. if (of_get_property(np, "fsl,cd-controller", NULL))
  297. boarddata->cd_type = ESDHC_CD_CONTROLLER;
  298. if (of_get_property(np, "fsl,wp-controller", NULL))
  299. boarddata->wp_type = ESDHC_WP_CONTROLLER;
  300. boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
  301. if (gpio_is_valid(boarddata->cd_gpio))
  302. boarddata->cd_type = ESDHC_CD_GPIO;
  303. boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
  304. if (gpio_is_valid(boarddata->wp_gpio))
  305. boarddata->wp_type = ESDHC_WP_GPIO;
  306. return 0;
  307. }
  308. #else
  309. static inline int
  310. sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
  311. struct esdhc_platform_data *boarddata)
  312. {
  313. return -ENODEV;
  314. }
  315. #endif
  316. static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
  317. {
  318. const struct of_device_id *of_id =
  319. of_match_device(imx_esdhc_dt_ids, &pdev->dev);
  320. struct sdhci_pltfm_host *pltfm_host;
  321. struct sdhci_host *host;
  322. struct esdhc_platform_data *boarddata;
  323. struct clk *clk;
  324. int err;
  325. struct pltfm_imx_data *imx_data;
  326. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
  327. if (IS_ERR(host))
  328. return PTR_ERR(host);
  329. pltfm_host = sdhci_priv(host);
  330. imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
  331. if (!imx_data) {
  332. err = -ENOMEM;
  333. goto err_imx_data;
  334. }
  335. if (of_id)
  336. pdev->id_entry = of_id->data;
  337. imx_data->devtype = pdev->id_entry->driver_data;
  338. pltfm_host->priv = imx_data;
  339. clk = clk_get(mmc_dev(host->mmc), NULL);
  340. if (IS_ERR(clk)) {
  341. dev_err(mmc_dev(host->mmc), "clk err\n");
  342. err = PTR_ERR(clk);
  343. goto err_clk_get;
  344. }
  345. clk_enable(clk);
  346. pltfm_host->clk = clk;
  347. if (!is_imx25_esdhc(imx_data))
  348. host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
  349. if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
  350. /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
  351. host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
  352. if (is_imx53_esdhc(imx_data))
  353. imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
  354. boarddata = &imx_data->boarddata;
  355. if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
  356. if (!host->mmc->parent->platform_data) {
  357. dev_err(mmc_dev(host->mmc), "no board data!\n");
  358. err = -EINVAL;
  359. goto no_board_data;
  360. }
  361. imx_data->boarddata = *((struct esdhc_platform_data *)
  362. host->mmc->parent->platform_data);
  363. }
  364. /* write_protect */
  365. if (boarddata->wp_type == ESDHC_WP_GPIO) {
  366. err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP");
  367. if (err) {
  368. dev_warn(mmc_dev(host->mmc),
  369. "no write-protect pin available!\n");
  370. boarddata->wp_gpio = -EINVAL;
  371. }
  372. } else {
  373. boarddata->wp_gpio = -EINVAL;
  374. }
  375. /* card_detect */
  376. if (boarddata->cd_type != ESDHC_CD_GPIO)
  377. boarddata->cd_gpio = -EINVAL;
  378. switch (boarddata->cd_type) {
  379. case ESDHC_CD_GPIO:
  380. err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD");
  381. if (err) {
  382. dev_err(mmc_dev(host->mmc),
  383. "no card-detect pin available!\n");
  384. goto no_card_detect_pin;
  385. }
  386. err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq,
  387. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  388. mmc_hostname(host->mmc), host);
  389. if (err) {
  390. dev_err(mmc_dev(host->mmc), "request irq error\n");
  391. goto no_card_detect_irq;
  392. }
  393. /* fall through */
  394. case ESDHC_CD_CONTROLLER:
  395. /* we have a working card_detect back */
  396. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  397. break;
  398. case ESDHC_CD_PERMANENT:
  399. host->mmc->caps = MMC_CAP_NONREMOVABLE;
  400. break;
  401. case ESDHC_CD_NONE:
  402. break;
  403. }
  404. err = sdhci_add_host(host);
  405. if (err)
  406. goto err_add_host;
  407. return 0;
  408. err_add_host:
  409. if (gpio_is_valid(boarddata->cd_gpio))
  410. free_irq(gpio_to_irq(boarddata->cd_gpio), host);
  411. no_card_detect_irq:
  412. if (gpio_is_valid(boarddata->cd_gpio))
  413. gpio_free(boarddata->cd_gpio);
  414. if (gpio_is_valid(boarddata->wp_gpio))
  415. gpio_free(boarddata->wp_gpio);
  416. no_card_detect_pin:
  417. no_board_data:
  418. clk_disable(pltfm_host->clk);
  419. clk_put(pltfm_host->clk);
  420. err_clk_get:
  421. kfree(imx_data);
  422. err_imx_data:
  423. sdhci_pltfm_free(pdev);
  424. return err;
  425. }
  426. static int __devexit sdhci_esdhc_imx_remove(struct platform_device *pdev)
  427. {
  428. struct sdhci_host *host = platform_get_drvdata(pdev);
  429. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  430. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  431. struct esdhc_platform_data *boarddata = &imx_data->boarddata;
  432. int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  433. sdhci_remove_host(host, dead);
  434. if (gpio_is_valid(boarddata->wp_gpio))
  435. gpio_free(boarddata->wp_gpio);
  436. if (gpio_is_valid(boarddata->cd_gpio)) {
  437. free_irq(gpio_to_irq(boarddata->cd_gpio), host);
  438. gpio_free(boarddata->cd_gpio);
  439. }
  440. clk_disable(pltfm_host->clk);
  441. clk_put(pltfm_host->clk);
  442. kfree(imx_data);
  443. sdhci_pltfm_free(pdev);
  444. return 0;
  445. }
  446. static struct platform_driver sdhci_esdhc_imx_driver = {
  447. .driver = {
  448. .name = "sdhci-esdhc-imx",
  449. .owner = THIS_MODULE,
  450. .of_match_table = imx_esdhc_dt_ids,
  451. },
  452. .id_table = imx_esdhc_devtype,
  453. .probe = sdhci_esdhc_imx_probe,
  454. .remove = __devexit_p(sdhci_esdhc_imx_remove),
  455. #ifdef CONFIG_PM
  456. .suspend = sdhci_pltfm_suspend,
  457. .resume = sdhci_pltfm_resume,
  458. #endif
  459. };
  460. static int __init sdhci_esdhc_imx_init(void)
  461. {
  462. return platform_driver_register(&sdhci_esdhc_imx_driver);
  463. }
  464. module_init(sdhci_esdhc_imx_init);
  465. static void __exit sdhci_esdhc_imx_exit(void)
  466. {
  467. platform_driver_unregister(&sdhci_esdhc_imx_driver);
  468. }
  469. module_exit(sdhci_esdhc_imx_exit);
  470. MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
  471. MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
  472. MODULE_LICENSE("GPL v2");