i2c-tegra.c 21 KB

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  1. /*
  2. * drivers/i2c/busses/i2c-tegra.c
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. * Author: Colin Cross <ccross@android.com>
  6. *
  7. * This software is licensed under the terms of the GNU General Public
  8. * License version 2, as published by the Free Software Foundation, and
  9. * may be copied, distributed, and modified under those terms.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/clk.h>
  21. #include <linux/err.h>
  22. #include <linux/i2c.h>
  23. #include <linux/io.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <linux/i2c-tegra.h>
  28. #include <linux/of_i2c.h>
  29. #include <asm/unaligned.h>
  30. #include <mach/clk.h>
  31. #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  32. #define BYTES_PER_FIFO_WORD 4
  33. #define I2C_CNFG 0x000
  34. #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
  35. #define I2C_CNFG_PACKET_MODE_EN (1<<10)
  36. #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
  37. #define I2C_STATUS 0x01C
  38. #define I2C_SL_CNFG 0x020
  39. #define I2C_SL_CNFG_NACK (1<<1)
  40. #define I2C_SL_CNFG_NEWSL (1<<2)
  41. #define I2C_SL_ADDR1 0x02c
  42. #define I2C_SL_ADDR2 0x030
  43. #define I2C_TX_FIFO 0x050
  44. #define I2C_RX_FIFO 0x054
  45. #define I2C_PACKET_TRANSFER_STATUS 0x058
  46. #define I2C_FIFO_CONTROL 0x05c
  47. #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
  48. #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
  49. #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
  50. #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
  51. #define I2C_FIFO_STATUS 0x060
  52. #define I2C_FIFO_STATUS_TX_MASK 0xF0
  53. #define I2C_FIFO_STATUS_TX_SHIFT 4
  54. #define I2C_FIFO_STATUS_RX_MASK 0x0F
  55. #define I2C_FIFO_STATUS_RX_SHIFT 0
  56. #define I2C_INT_MASK 0x064
  57. #define I2C_INT_STATUS 0x068
  58. #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
  59. #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
  60. #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
  61. #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
  62. #define I2C_INT_NO_ACK (1<<3)
  63. #define I2C_INT_ARBITRATION_LOST (1<<2)
  64. #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
  65. #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
  66. #define I2C_CLK_DIVISOR 0x06c
  67. #define DVC_CTRL_REG1 0x000
  68. #define DVC_CTRL_REG1_INTR_EN (1<<10)
  69. #define DVC_CTRL_REG2 0x004
  70. #define DVC_CTRL_REG3 0x008
  71. #define DVC_CTRL_REG3_SW_PROG (1<<26)
  72. #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
  73. #define DVC_STATUS 0x00c
  74. #define DVC_STATUS_I2C_DONE_INTR (1<<30)
  75. #define I2C_ERR_NONE 0x00
  76. #define I2C_ERR_NO_ACK 0x01
  77. #define I2C_ERR_ARBITRATION_LOST 0x02
  78. #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
  79. #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
  80. #define PACKET_HEADER0_PACKET_ID_SHIFT 16
  81. #define PACKET_HEADER0_CONT_ID_SHIFT 12
  82. #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
  83. #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
  84. #define I2C_HEADER_CONT_ON_NAK (1<<21)
  85. #define I2C_HEADER_SEND_START_BYTE (1<<20)
  86. #define I2C_HEADER_READ (1<<19)
  87. #define I2C_HEADER_10BIT_ADDR (1<<18)
  88. #define I2C_HEADER_IE_ENABLE (1<<17)
  89. #define I2C_HEADER_REPEAT_START (1<<16)
  90. #define I2C_HEADER_MASTER_ADDR_SHIFT 12
  91. #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
  92. /**
  93. * struct tegra_i2c_dev - per device i2c context
  94. * @dev: device reference for power management
  95. * @adapter: core i2c layer adapter information
  96. * @clk: clock reference for i2c controller
  97. * @i2c_clk: clock reference for i2c bus
  98. * @iomem: memory resource for registers
  99. * @base: ioremapped registers cookie
  100. * @cont_id: i2c controller id, used for for packet header
  101. * @irq: irq number of transfer complete interrupt
  102. * @is_dvc: identifies the DVC i2c controller, has a different register layout
  103. * @msg_complete: transfer completion notifier
  104. * @msg_err: error code for completed message
  105. * @msg_buf: pointer to current message data
  106. * @msg_buf_remaining: size of unsent data in the message buffer
  107. * @msg_read: identifies read transfers
  108. * @bus_clk_rate: current i2c bus clock rate
  109. * @is_suspended: prevents i2c controller accesses after suspend is called
  110. */
  111. struct tegra_i2c_dev {
  112. struct device *dev;
  113. struct i2c_adapter adapter;
  114. struct clk *clk;
  115. struct clk *i2c_clk;
  116. struct resource *iomem;
  117. void __iomem *base;
  118. int cont_id;
  119. int irq;
  120. bool irq_disabled;
  121. int is_dvc;
  122. struct completion msg_complete;
  123. int msg_err;
  124. u8 *msg_buf;
  125. size_t msg_buf_remaining;
  126. int msg_read;
  127. unsigned long bus_clk_rate;
  128. bool is_suspended;
  129. };
  130. static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
  131. {
  132. writel(val, i2c_dev->base + reg);
  133. }
  134. static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
  135. {
  136. return readl(i2c_dev->base + reg);
  137. }
  138. /*
  139. * i2c_writel and i2c_readl will offset the register if necessary to talk
  140. * to the I2C block inside the DVC block
  141. */
  142. static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
  143. unsigned long reg)
  144. {
  145. if (i2c_dev->is_dvc)
  146. reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
  147. return reg;
  148. }
  149. static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
  150. unsigned long reg)
  151. {
  152. writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
  153. }
  154. static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
  155. {
  156. return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
  157. }
  158. static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
  159. unsigned long reg, int len)
  160. {
  161. writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
  162. }
  163. static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
  164. unsigned long reg, int len)
  165. {
  166. readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
  167. }
  168. static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
  169. {
  170. u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
  171. int_mask &= ~mask;
  172. i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
  173. }
  174. static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
  175. {
  176. u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
  177. int_mask |= mask;
  178. i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
  179. }
  180. static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
  181. {
  182. unsigned long timeout = jiffies + HZ;
  183. u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
  184. val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
  185. i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
  186. while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
  187. (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
  188. if (time_after(jiffies, timeout)) {
  189. dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
  190. return -ETIMEDOUT;
  191. }
  192. msleep(1);
  193. }
  194. return 0;
  195. }
  196. static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
  197. {
  198. u32 val;
  199. int rx_fifo_avail;
  200. u8 *buf = i2c_dev->msg_buf;
  201. size_t buf_remaining = i2c_dev->msg_buf_remaining;
  202. int words_to_transfer;
  203. val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
  204. rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
  205. I2C_FIFO_STATUS_RX_SHIFT;
  206. /* Rounds down to not include partial word at the end of buf */
  207. words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
  208. if (words_to_transfer > rx_fifo_avail)
  209. words_to_transfer = rx_fifo_avail;
  210. i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
  211. buf += words_to_transfer * BYTES_PER_FIFO_WORD;
  212. buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
  213. rx_fifo_avail -= words_to_transfer;
  214. /*
  215. * If there is a partial word at the end of buf, handle it manually to
  216. * prevent overwriting past the end of buf
  217. */
  218. if (rx_fifo_avail > 0 && buf_remaining > 0) {
  219. BUG_ON(buf_remaining > 3);
  220. val = i2c_readl(i2c_dev, I2C_RX_FIFO);
  221. memcpy(buf, &val, buf_remaining);
  222. buf_remaining = 0;
  223. rx_fifo_avail--;
  224. }
  225. BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
  226. i2c_dev->msg_buf_remaining = buf_remaining;
  227. i2c_dev->msg_buf = buf;
  228. return 0;
  229. }
  230. static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
  231. {
  232. u32 val;
  233. int tx_fifo_avail;
  234. u8 *buf = i2c_dev->msg_buf;
  235. size_t buf_remaining = i2c_dev->msg_buf_remaining;
  236. int words_to_transfer;
  237. val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
  238. tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
  239. I2C_FIFO_STATUS_TX_SHIFT;
  240. /* Rounds down to not include partial word at the end of buf */
  241. words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
  242. /* It's very common to have < 4 bytes, so optimize that case. */
  243. if (words_to_transfer) {
  244. if (words_to_transfer > tx_fifo_avail)
  245. words_to_transfer = tx_fifo_avail;
  246. /*
  247. * Update state before writing to FIFO. If this casues us
  248. * to finish writing all bytes (AKA buf_remaining goes to 0) we
  249. * have a potential for an interrupt (PACKET_XFER_COMPLETE is
  250. * not maskable). We need to make sure that the isr sees
  251. * buf_remaining as 0 and doesn't call us back re-entrantly.
  252. */
  253. buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
  254. tx_fifo_avail -= words_to_transfer;
  255. i2c_dev->msg_buf_remaining = buf_remaining;
  256. i2c_dev->msg_buf = buf +
  257. words_to_transfer * BYTES_PER_FIFO_WORD;
  258. barrier();
  259. i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
  260. buf += words_to_transfer * BYTES_PER_FIFO_WORD;
  261. }
  262. /*
  263. * If there is a partial word at the end of buf, handle it manually to
  264. * prevent reading past the end of buf, which could cross a page
  265. * boundary and fault.
  266. */
  267. if (tx_fifo_avail > 0 && buf_remaining > 0) {
  268. BUG_ON(buf_remaining > 3);
  269. memcpy(&val, buf, buf_remaining);
  270. /* Again update before writing to FIFO to make sure isr sees. */
  271. i2c_dev->msg_buf_remaining = 0;
  272. i2c_dev->msg_buf = NULL;
  273. barrier();
  274. i2c_writel(i2c_dev, val, I2C_TX_FIFO);
  275. }
  276. return 0;
  277. }
  278. /*
  279. * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
  280. * block. This block is identical to the rest of the I2C blocks, except that
  281. * it only supports master mode, it has registers moved around, and it needs
  282. * some extra init to get it into I2C mode. The register moves are handled
  283. * by i2c_readl and i2c_writel
  284. */
  285. static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
  286. {
  287. u32 val = 0;
  288. val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
  289. val |= DVC_CTRL_REG3_SW_PROG;
  290. val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
  291. dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
  292. val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
  293. val |= DVC_CTRL_REG1_INTR_EN;
  294. dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
  295. }
  296. static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
  297. {
  298. u32 val;
  299. int err = 0;
  300. clk_enable(i2c_dev->clk);
  301. tegra_periph_reset_assert(i2c_dev->clk);
  302. udelay(2);
  303. tegra_periph_reset_deassert(i2c_dev->clk);
  304. if (i2c_dev->is_dvc)
  305. tegra_dvc_init(i2c_dev);
  306. val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
  307. (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
  308. i2c_writel(i2c_dev, val, I2C_CNFG);
  309. i2c_writel(i2c_dev, 0, I2C_INT_MASK);
  310. clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
  311. if (!i2c_dev->is_dvc) {
  312. u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
  313. sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
  314. i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
  315. i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
  316. i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
  317. }
  318. val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
  319. 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
  320. i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
  321. if (tegra_i2c_flush_fifos(i2c_dev))
  322. err = -ETIMEDOUT;
  323. clk_disable(i2c_dev->clk);
  324. if (i2c_dev->irq_disabled) {
  325. i2c_dev->irq_disabled = 0;
  326. enable_irq(i2c_dev->irq);
  327. }
  328. return err;
  329. }
  330. static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
  331. {
  332. u32 status;
  333. const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
  334. struct tegra_i2c_dev *i2c_dev = dev_id;
  335. status = i2c_readl(i2c_dev, I2C_INT_STATUS);
  336. if (status == 0) {
  337. dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
  338. i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
  339. i2c_readl(i2c_dev, I2C_STATUS),
  340. i2c_readl(i2c_dev, I2C_CNFG));
  341. i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
  342. if (!i2c_dev->irq_disabled) {
  343. disable_irq_nosync(i2c_dev->irq);
  344. i2c_dev->irq_disabled = 1;
  345. }
  346. complete(&i2c_dev->msg_complete);
  347. goto err;
  348. }
  349. if (unlikely(status & status_err)) {
  350. if (status & I2C_INT_NO_ACK)
  351. i2c_dev->msg_err |= I2C_ERR_NO_ACK;
  352. if (status & I2C_INT_ARBITRATION_LOST)
  353. i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
  354. complete(&i2c_dev->msg_complete);
  355. goto err;
  356. }
  357. if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
  358. if (i2c_dev->msg_buf_remaining)
  359. tegra_i2c_empty_rx_fifo(i2c_dev);
  360. else
  361. BUG();
  362. }
  363. if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
  364. if (i2c_dev->msg_buf_remaining)
  365. tegra_i2c_fill_tx_fifo(i2c_dev);
  366. else
  367. tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
  368. }
  369. if (status & I2C_INT_PACKET_XFER_COMPLETE) {
  370. BUG_ON(i2c_dev->msg_buf_remaining);
  371. complete(&i2c_dev->msg_complete);
  372. }
  373. i2c_writel(i2c_dev, status, I2C_INT_STATUS);
  374. if (i2c_dev->is_dvc)
  375. dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
  376. return IRQ_HANDLED;
  377. err:
  378. /* An error occurred, mask all interrupts */
  379. tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
  380. I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
  381. I2C_INT_RX_FIFO_DATA_REQ);
  382. i2c_writel(i2c_dev, status, I2C_INT_STATUS);
  383. if (i2c_dev->is_dvc)
  384. dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
  385. return IRQ_HANDLED;
  386. }
  387. static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
  388. struct i2c_msg *msg, int stop)
  389. {
  390. u32 packet_header;
  391. u32 int_mask;
  392. int ret;
  393. tegra_i2c_flush_fifos(i2c_dev);
  394. i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
  395. if (msg->len == 0)
  396. return -EINVAL;
  397. i2c_dev->msg_buf = msg->buf;
  398. i2c_dev->msg_buf_remaining = msg->len;
  399. i2c_dev->msg_err = I2C_ERR_NONE;
  400. i2c_dev->msg_read = (msg->flags & I2C_M_RD);
  401. INIT_COMPLETION(i2c_dev->msg_complete);
  402. packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
  403. PACKET_HEADER0_PROTOCOL_I2C |
  404. (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
  405. (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
  406. i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
  407. packet_header = msg->len - 1;
  408. i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
  409. packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
  410. packet_header |= I2C_HEADER_IE_ENABLE;
  411. if (!stop)
  412. packet_header |= I2C_HEADER_REPEAT_START;
  413. if (msg->flags & I2C_M_TEN)
  414. packet_header |= I2C_HEADER_10BIT_ADDR;
  415. if (msg->flags & I2C_M_IGNORE_NAK)
  416. packet_header |= I2C_HEADER_CONT_ON_NAK;
  417. if (msg->flags & I2C_M_RD)
  418. packet_header |= I2C_HEADER_READ;
  419. i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
  420. if (!(msg->flags & I2C_M_RD))
  421. tegra_i2c_fill_tx_fifo(i2c_dev);
  422. int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
  423. if (msg->flags & I2C_M_RD)
  424. int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
  425. else if (i2c_dev->msg_buf_remaining)
  426. int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
  427. tegra_i2c_unmask_irq(i2c_dev, int_mask);
  428. dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
  429. i2c_readl(i2c_dev, I2C_INT_MASK));
  430. ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
  431. tegra_i2c_mask_irq(i2c_dev, int_mask);
  432. if (WARN_ON(ret == 0)) {
  433. dev_err(i2c_dev->dev, "i2c transfer timed out\n");
  434. tegra_i2c_init(i2c_dev);
  435. return -ETIMEDOUT;
  436. }
  437. dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
  438. ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
  439. if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
  440. return 0;
  441. tegra_i2c_init(i2c_dev);
  442. if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
  443. if (msg->flags & I2C_M_IGNORE_NAK)
  444. return 0;
  445. return -EREMOTEIO;
  446. }
  447. return -EIO;
  448. }
  449. static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
  450. int num)
  451. {
  452. struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
  453. int i;
  454. int ret = 0;
  455. if (i2c_dev->is_suspended)
  456. return -EBUSY;
  457. clk_enable(i2c_dev->clk);
  458. for (i = 0; i < num; i++) {
  459. int stop = (i == (num - 1)) ? 1 : 0;
  460. ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
  461. if (ret)
  462. break;
  463. }
  464. clk_disable(i2c_dev->clk);
  465. return ret ?: i;
  466. }
  467. static u32 tegra_i2c_func(struct i2c_adapter *adap)
  468. {
  469. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  470. }
  471. static const struct i2c_algorithm tegra_i2c_algo = {
  472. .master_xfer = tegra_i2c_xfer,
  473. .functionality = tegra_i2c_func,
  474. };
  475. static int tegra_i2c_probe(struct platform_device *pdev)
  476. {
  477. struct tegra_i2c_dev *i2c_dev;
  478. struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
  479. struct resource *res;
  480. struct resource *iomem;
  481. struct clk *clk;
  482. struct clk *i2c_clk;
  483. const unsigned int *prop;
  484. void *base;
  485. int irq;
  486. int ret = 0;
  487. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  488. if (!res) {
  489. dev_err(&pdev->dev, "no mem resource\n");
  490. return -EINVAL;
  491. }
  492. iomem = request_mem_region(res->start, resource_size(res), pdev->name);
  493. if (!iomem) {
  494. dev_err(&pdev->dev, "I2C region already claimed\n");
  495. return -EBUSY;
  496. }
  497. base = ioremap(iomem->start, resource_size(iomem));
  498. if (!base) {
  499. dev_err(&pdev->dev, "Cannot ioremap I2C region\n");
  500. return -ENOMEM;
  501. }
  502. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  503. if (!res) {
  504. dev_err(&pdev->dev, "no irq resource\n");
  505. ret = -EINVAL;
  506. goto err_iounmap;
  507. }
  508. irq = res->start;
  509. clk = clk_get(&pdev->dev, NULL);
  510. if (IS_ERR(clk)) {
  511. dev_err(&pdev->dev, "missing controller clock");
  512. ret = PTR_ERR(clk);
  513. goto err_release_region;
  514. }
  515. i2c_clk = clk_get(&pdev->dev, "i2c");
  516. if (IS_ERR(i2c_clk)) {
  517. dev_err(&pdev->dev, "missing bus clock");
  518. ret = PTR_ERR(i2c_clk);
  519. goto err_clk_put;
  520. }
  521. i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
  522. if (!i2c_dev) {
  523. ret = -ENOMEM;
  524. goto err_i2c_clk_put;
  525. }
  526. i2c_dev->base = base;
  527. i2c_dev->clk = clk;
  528. i2c_dev->i2c_clk = i2c_clk;
  529. i2c_dev->iomem = iomem;
  530. i2c_dev->adapter.algo = &tegra_i2c_algo;
  531. i2c_dev->irq = irq;
  532. i2c_dev->cont_id = pdev->id;
  533. i2c_dev->dev = &pdev->dev;
  534. i2c_dev->bus_clk_rate = 100000; /* default clock rate */
  535. if (pdata) {
  536. i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
  537. } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
  538. prop = of_get_property(i2c_dev->dev->of_node,
  539. "clock-frequency", NULL);
  540. if (prop)
  541. i2c_dev->bus_clk_rate = be32_to_cpup(prop);
  542. }
  543. if (pdev->id == 3)
  544. i2c_dev->is_dvc = 1;
  545. init_completion(&i2c_dev->msg_complete);
  546. platform_set_drvdata(pdev, i2c_dev);
  547. ret = tegra_i2c_init(i2c_dev);
  548. if (ret) {
  549. dev_err(&pdev->dev, "Failed to initialize i2c controller");
  550. goto err_free;
  551. }
  552. ret = request_irq(i2c_dev->irq, tegra_i2c_isr, 0, pdev->name, i2c_dev);
  553. if (ret) {
  554. dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
  555. goto err_free;
  556. }
  557. clk_enable(i2c_dev->i2c_clk);
  558. i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
  559. i2c_dev->adapter.owner = THIS_MODULE;
  560. i2c_dev->adapter.class = I2C_CLASS_HWMON;
  561. strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
  562. sizeof(i2c_dev->adapter.name));
  563. i2c_dev->adapter.algo = &tegra_i2c_algo;
  564. i2c_dev->adapter.dev.parent = &pdev->dev;
  565. i2c_dev->adapter.nr = pdev->id;
  566. i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
  567. ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
  568. if (ret) {
  569. dev_err(&pdev->dev, "Failed to add I2C adapter\n");
  570. goto err_free_irq;
  571. }
  572. of_i2c_register_devices(&i2c_dev->adapter);
  573. return 0;
  574. err_free_irq:
  575. free_irq(i2c_dev->irq, i2c_dev);
  576. err_free:
  577. kfree(i2c_dev);
  578. err_i2c_clk_put:
  579. clk_put(i2c_clk);
  580. err_clk_put:
  581. clk_put(clk);
  582. err_release_region:
  583. release_mem_region(iomem->start, resource_size(iomem));
  584. err_iounmap:
  585. iounmap(base);
  586. return ret;
  587. }
  588. static int tegra_i2c_remove(struct platform_device *pdev)
  589. {
  590. struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
  591. i2c_del_adapter(&i2c_dev->adapter);
  592. free_irq(i2c_dev->irq, i2c_dev);
  593. clk_put(i2c_dev->i2c_clk);
  594. clk_put(i2c_dev->clk);
  595. release_mem_region(i2c_dev->iomem->start,
  596. resource_size(i2c_dev->iomem));
  597. iounmap(i2c_dev->base);
  598. kfree(i2c_dev);
  599. return 0;
  600. }
  601. #ifdef CONFIG_PM
  602. static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
  603. {
  604. struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
  605. i2c_lock_adapter(&i2c_dev->adapter);
  606. i2c_dev->is_suspended = true;
  607. i2c_unlock_adapter(&i2c_dev->adapter);
  608. return 0;
  609. }
  610. static int tegra_i2c_resume(struct platform_device *pdev)
  611. {
  612. struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
  613. int ret;
  614. i2c_lock_adapter(&i2c_dev->adapter);
  615. ret = tegra_i2c_init(i2c_dev);
  616. if (ret) {
  617. i2c_unlock_adapter(&i2c_dev->adapter);
  618. return ret;
  619. }
  620. i2c_dev->is_suspended = false;
  621. i2c_unlock_adapter(&i2c_dev->adapter);
  622. return 0;
  623. }
  624. #endif
  625. #if defined(CONFIG_OF)
  626. /* Match table for of_platform binding */
  627. static const struct of_device_id tegra_i2c_of_match[] __devinitconst = {
  628. { .compatible = "nvidia,tegra20-i2c", },
  629. {},
  630. };
  631. MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
  632. #else
  633. #define tegra_i2c_of_match NULL
  634. #endif
  635. static struct platform_driver tegra_i2c_driver = {
  636. .probe = tegra_i2c_probe,
  637. .remove = tegra_i2c_remove,
  638. #ifdef CONFIG_PM
  639. .suspend = tegra_i2c_suspend,
  640. .resume = tegra_i2c_resume,
  641. #endif
  642. .driver = {
  643. .name = "tegra-i2c",
  644. .owner = THIS_MODULE,
  645. .of_match_table = tegra_i2c_of_match,
  646. },
  647. };
  648. static int __init tegra_i2c_init_driver(void)
  649. {
  650. return platform_driver_register(&tegra_i2c_driver);
  651. }
  652. static void __exit tegra_i2c_exit_driver(void)
  653. {
  654. platform_driver_unregister(&tegra_i2c_driver);
  655. }
  656. subsys_initcall(tegra_i2c_init_driver);
  657. module_exit(tegra_i2c_exit_driver);
  658. MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
  659. MODULE_AUTHOR("Colin Cross");
  660. MODULE_LICENSE("GPL v2");