radeonfb.h 15 KB

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  1. #ifndef __RADEONFB_H__
  2. #define __RADEONFB_H__
  3. #ifdef CONFIG_FB_RADEON_DEBUG
  4. #define DEBUG 1
  5. #endif
  6. #include <linux/module.h>
  7. #include <linux/kernel.h>
  8. #include <linux/sched.h>
  9. #include <linux/delay.h>
  10. #include <linux/pci.h>
  11. #include <linux/fb.h>
  12. #ifdef CONFIG_FB_RADEON_I2C
  13. #include <linux/i2c.h>
  14. #include <linux/i2c-algo-bit.h>
  15. #endif
  16. #include <asm/io.h>
  17. #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
  18. #include <asm/prom.h>
  19. #endif
  20. #include <video/radeon.h>
  21. /***************************************************************
  22. * Most of the definitions here are adapted right from XFree86 *
  23. ***************************************************************/
  24. /*
  25. * Chip families. Must fit in the low 16 bits of a long word
  26. */
  27. enum radeon_family {
  28. CHIP_FAMILY_UNKNOW,
  29. CHIP_FAMILY_LEGACY,
  30. CHIP_FAMILY_RADEON,
  31. CHIP_FAMILY_RV100,
  32. CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
  33. CHIP_FAMILY_RV200,
  34. CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
  35. RS250 (IGP 7000) */
  36. CHIP_FAMILY_R200,
  37. CHIP_FAMILY_RV250,
  38. CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
  39. CHIP_FAMILY_RV280,
  40. CHIP_FAMILY_R300,
  41. CHIP_FAMILY_R350,
  42. CHIP_FAMILY_RV350,
  43. CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
  44. CHIP_FAMILY_R420, /* R420/R423/M18 */
  45. CHIP_FAMILY_RC410,
  46. CHIP_FAMILY_RS400,
  47. CHIP_FAMILY_RS480,
  48. CHIP_FAMILY_LAST,
  49. };
  50. #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
  51. ((rinfo)->family == CHIP_FAMILY_RV200) || \
  52. ((rinfo)->family == CHIP_FAMILY_RS100) || \
  53. ((rinfo)->family == CHIP_FAMILY_RS200) || \
  54. ((rinfo)->family == CHIP_FAMILY_RV250) || \
  55. ((rinfo)->family == CHIP_FAMILY_RV280) || \
  56. ((rinfo)->family == CHIP_FAMILY_RS300))
  57. #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
  58. ((rinfo)->family == CHIP_FAMILY_RV350) || \
  59. ((rinfo)->family == CHIP_FAMILY_R350) || \
  60. ((rinfo)->family == CHIP_FAMILY_RV380) || \
  61. ((rinfo)->family == CHIP_FAMILY_R420) || \
  62. ((rinfo)->family == CHIP_FAMILY_RC410) || \
  63. ((rinfo)->family == CHIP_FAMILY_RS480))
  64. /*
  65. * Chip flags
  66. */
  67. enum radeon_chip_flags {
  68. CHIP_FAMILY_MASK = 0x0000ffffUL,
  69. CHIP_FLAGS_MASK = 0xffff0000UL,
  70. CHIP_IS_MOBILITY = 0x00010000UL,
  71. CHIP_IS_IGP = 0x00020000UL,
  72. CHIP_HAS_CRTC2 = 0x00040000UL,
  73. };
  74. /*
  75. * Errata workarounds
  76. */
  77. enum radeon_errata {
  78. CHIP_ERRATA_R300_CG = 0x00000001,
  79. CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
  80. CHIP_ERRATA_PLL_DELAY = 0x00000004,
  81. };
  82. /*
  83. * Monitor types
  84. */
  85. enum radeon_montype {
  86. MT_NONE = 0,
  87. MT_CRT, /* CRT */
  88. MT_LCD, /* LCD */
  89. MT_DFP, /* DVI */
  90. MT_CTV, /* composite TV */
  91. MT_STV /* S-Video out */
  92. };
  93. /*
  94. * DDC i2c ports
  95. */
  96. enum ddc_type {
  97. ddc_none,
  98. ddc_monid,
  99. ddc_dvi,
  100. ddc_vga,
  101. ddc_crt2,
  102. };
  103. /*
  104. * Connector types
  105. */
  106. enum conn_type {
  107. conn_none,
  108. conn_proprietary,
  109. conn_crt,
  110. conn_DVI_I,
  111. conn_DVI_D,
  112. };
  113. /*
  114. * PLL infos
  115. */
  116. struct pll_info {
  117. int ppll_max;
  118. int ppll_min;
  119. int sclk, mclk;
  120. int ref_div;
  121. int ref_clk;
  122. };
  123. /*
  124. * This structure contains the various registers manipulated by this
  125. * driver for setting or restoring a mode. It's mostly copied from
  126. * XFree's RADEONSaveRec structure. A few chip settings might still be
  127. * tweaked without beeing reflected or saved in these registers though
  128. */
  129. struct radeon_regs {
  130. /* Common registers */
  131. u32 ovr_clr;
  132. u32 ovr_wid_left_right;
  133. u32 ovr_wid_top_bottom;
  134. u32 ov0_scale_cntl;
  135. u32 mpp_tb_config;
  136. u32 mpp_gp_config;
  137. u32 subpic_cntl;
  138. u32 viph_control;
  139. u32 i2c_cntl_1;
  140. u32 gen_int_cntl;
  141. u32 cap0_trig_cntl;
  142. u32 cap1_trig_cntl;
  143. u32 bus_cntl;
  144. u32 surface_cntl;
  145. u32 bios_5_scratch;
  146. /* Other registers to save for VT switches or driver load/unload */
  147. u32 dp_datatype;
  148. u32 rbbm_soft_reset;
  149. u32 clock_cntl_index;
  150. u32 amcgpio_en_reg;
  151. u32 amcgpio_mask;
  152. /* Surface/tiling registers */
  153. u32 surf_lower_bound[8];
  154. u32 surf_upper_bound[8];
  155. u32 surf_info[8];
  156. /* CRTC registers */
  157. u32 crtc_gen_cntl;
  158. u32 crtc_ext_cntl;
  159. u32 dac_cntl;
  160. u32 crtc_h_total_disp;
  161. u32 crtc_h_sync_strt_wid;
  162. u32 crtc_v_total_disp;
  163. u32 crtc_v_sync_strt_wid;
  164. u32 crtc_offset;
  165. u32 crtc_offset_cntl;
  166. u32 crtc_pitch;
  167. u32 disp_merge_cntl;
  168. u32 grph_buffer_cntl;
  169. u32 crtc_more_cntl;
  170. /* CRTC2 registers */
  171. u32 crtc2_gen_cntl;
  172. u32 dac2_cntl;
  173. u32 disp_output_cntl;
  174. u32 disp_hw_debug;
  175. u32 disp2_merge_cntl;
  176. u32 grph2_buffer_cntl;
  177. u32 crtc2_h_total_disp;
  178. u32 crtc2_h_sync_strt_wid;
  179. u32 crtc2_v_total_disp;
  180. u32 crtc2_v_sync_strt_wid;
  181. u32 crtc2_offset;
  182. u32 crtc2_offset_cntl;
  183. u32 crtc2_pitch;
  184. /* Flat panel regs */
  185. u32 fp_crtc_h_total_disp;
  186. u32 fp_crtc_v_total_disp;
  187. u32 fp_gen_cntl;
  188. u32 fp2_gen_cntl;
  189. u32 fp_h_sync_strt_wid;
  190. u32 fp2_h_sync_strt_wid;
  191. u32 fp_horz_stretch;
  192. u32 fp_panel_cntl;
  193. u32 fp_v_sync_strt_wid;
  194. u32 fp2_v_sync_strt_wid;
  195. u32 fp_vert_stretch;
  196. u32 lvds_gen_cntl;
  197. u32 lvds_pll_cntl;
  198. u32 tmds_crc;
  199. u32 tmds_transmitter_cntl;
  200. /* Computed values for PLL */
  201. u32 dot_clock_freq;
  202. int feedback_div;
  203. int post_div;
  204. /* PLL registers */
  205. u32 ppll_div_3;
  206. u32 ppll_ref_div;
  207. u32 vclk_ecp_cntl;
  208. u32 clk_cntl_index;
  209. /* Computed values for PLL2 */
  210. u32 dot_clock_freq_2;
  211. int feedback_div_2;
  212. int post_div_2;
  213. /* PLL2 registers */
  214. u32 p2pll_ref_div;
  215. u32 p2pll_div_0;
  216. u32 htotal_cntl2;
  217. /* Palette */
  218. int palette_valid;
  219. };
  220. struct panel_info {
  221. int xres, yres;
  222. int valid;
  223. int clock;
  224. int hOver_plus, hSync_width, hblank;
  225. int vOver_plus, vSync_width, vblank;
  226. int hAct_high, vAct_high, interlaced;
  227. int pwr_delay;
  228. int use_bios_dividers;
  229. int ref_divider;
  230. int post_divider;
  231. int fbk_divider;
  232. };
  233. struct radeonfb_info;
  234. #ifdef CONFIG_FB_RADEON_I2C
  235. struct radeon_i2c_chan {
  236. struct radeonfb_info *rinfo;
  237. u32 ddc_reg;
  238. struct i2c_adapter adapter;
  239. struct i2c_algo_bit_data algo;
  240. };
  241. #endif
  242. enum radeon_pm_mode {
  243. radeon_pm_none = 0, /* Nothing supported */
  244. radeon_pm_d2 = 0x00000001, /* Can do D2 state */
  245. radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
  246. };
  247. typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
  248. struct radeonfb_info {
  249. struct fb_info *info;
  250. struct radeon_regs state;
  251. struct radeon_regs init_state;
  252. char name[50];
  253. unsigned long mmio_base_phys;
  254. unsigned long fb_base_phys;
  255. void __iomem *mmio_base;
  256. void __iomem *fb_base;
  257. unsigned long fb_local_base;
  258. struct pci_dev *pdev;
  259. #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
  260. struct device_node *of_node;
  261. #endif
  262. void __iomem *bios_seg;
  263. int fp_bios_start;
  264. u32 pseudo_palette[16];
  265. struct { u8 red, green, blue, pad; }
  266. palette[256];
  267. int chipset;
  268. u8 family;
  269. u8 rev;
  270. unsigned int errata;
  271. unsigned long video_ram;
  272. unsigned long mapped_vram;
  273. int vram_width;
  274. int vram_ddr;
  275. int pitch, bpp, depth;
  276. int has_CRTC2;
  277. int is_mobility;
  278. int is_IGP;
  279. int reversed_DAC;
  280. int reversed_TMDS;
  281. struct panel_info panel_info;
  282. int mon1_type;
  283. u8 *mon1_EDID;
  284. struct fb_videomode *mon1_modedb;
  285. int mon1_dbsize;
  286. int mon2_type;
  287. u8 *mon2_EDID;
  288. /* accel bits */
  289. u32 dp_gui_mc_base;
  290. u32 dp_gui_mc_cache;
  291. u32 dp_cntl_cache;
  292. u32 dp_brush_fg_cache;
  293. u32 dp_brush_bg_cache;
  294. u32 dp_src_fg_cache;
  295. u32 dp_src_bg_cache;
  296. u32 fifo_free;
  297. struct pll_info pll;
  298. int mtrr_hdl;
  299. int pm_reg;
  300. u32 save_regs[100];
  301. int asleep;
  302. int lock_blank;
  303. int dynclk;
  304. int no_schedule;
  305. int gfx_mode;
  306. enum radeon_pm_mode pm_mode;
  307. reinit_function_ptr reinit_func;
  308. /* Lock on register access */
  309. spinlock_t reg_lock;
  310. /* Timer used for delayed LVDS operations */
  311. struct timer_list lvds_timer;
  312. u32 pending_lvds_gen_cntl;
  313. #ifdef CONFIG_FB_RADEON_I2C
  314. struct radeon_i2c_chan i2c[4];
  315. #endif
  316. u32 cfg_save[64];
  317. };
  318. #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
  319. /*
  320. * IO macros
  321. */
  322. /* Note about this function: we have some rare cases where we must not schedule,
  323. * this typically happen with our special "wake up early" hook which allows us to
  324. * wake up the graphic chip (and thus get the console back) before everything else
  325. * on some machines that support that mechanism. At this point, interrupts are off
  326. * and scheduling is not permitted
  327. */
  328. static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
  329. {
  330. if (rinfo->no_schedule || oops_in_progress)
  331. mdelay(ms);
  332. else
  333. msleep(ms);
  334. }
  335. #define INREG8(addr) readb((rinfo->mmio_base)+addr)
  336. #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
  337. #define INREG16(addr) readw((rinfo->mmio_base)+addr)
  338. #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
  339. #ifdef CONFIG_PPC
  340. #define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
  341. #define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
  342. #else
  343. #define INREG(addr) readl((rinfo->mmio_base)+addr)
  344. #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
  345. #endif
  346. static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
  347. u32 val, u32 mask)
  348. {
  349. unsigned long flags;
  350. unsigned int tmp;
  351. spin_lock_irqsave(&rinfo->reg_lock, flags);
  352. tmp = INREG(addr);
  353. tmp &= (mask);
  354. tmp |= (val);
  355. OUTREG(addr, tmp);
  356. spin_unlock_irqrestore(&rinfo->reg_lock, flags);
  357. }
  358. #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
  359. /*
  360. * Note about PLL register accesses:
  361. *
  362. * I have removed the spinlock on them on purpose. The driver now
  363. * expects that it will only manipulate the PLL registers in normal
  364. * task environment, where radeon_msleep() will be called, protected
  365. * by a semaphore (currently the console semaphore) so that no conflict
  366. * will happen on the PLL register index.
  367. *
  368. * With the latest changes to the VT layer, this is guaranteed for all
  369. * calls except the actual drawing/blits which aren't supposed to use
  370. * the PLL registers anyway
  371. *
  372. * This is very important for the workarounds to work properly. The only
  373. * possible exception to this rule is the call to unblank(), which may
  374. * be done at irq time if an oops is in progress.
  375. */
  376. static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
  377. {
  378. if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
  379. return;
  380. (void)INREG(CLOCK_CNTL_DATA);
  381. (void)INREG(CRTC_GEN_CNTL);
  382. }
  383. static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
  384. {
  385. if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
  386. /* we can't deal with posted writes here ... */
  387. _radeon_msleep(rinfo, 5);
  388. }
  389. if (rinfo->errata & CHIP_ERRATA_R300_CG) {
  390. u32 save, tmp;
  391. save = INREG(CLOCK_CNTL_INDEX);
  392. tmp = save & ~(0x3f | PLL_WR_EN);
  393. OUTREG(CLOCK_CNTL_INDEX, tmp);
  394. tmp = INREG(CLOCK_CNTL_DATA);
  395. OUTREG(CLOCK_CNTL_INDEX, save);
  396. }
  397. }
  398. static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
  399. {
  400. u32 data;
  401. OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
  402. radeon_pll_errata_after_index(rinfo);
  403. data = INREG(CLOCK_CNTL_DATA);
  404. radeon_pll_errata_after_data(rinfo);
  405. return data;
  406. }
  407. static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
  408. u32 val)
  409. {
  410. OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
  411. radeon_pll_errata_after_index(rinfo);
  412. OUTREG(CLOCK_CNTL_DATA, val);
  413. radeon_pll_errata_after_data(rinfo);
  414. }
  415. static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
  416. u32 val, u32 mask)
  417. {
  418. unsigned int tmp;
  419. tmp = __INPLL(rinfo, index);
  420. tmp &= (mask);
  421. tmp |= (val);
  422. __OUTPLL(rinfo, index, tmp);
  423. }
  424. #define INPLL(addr) __INPLL(rinfo, addr)
  425. #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
  426. #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
  427. #define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
  428. #define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
  429. (readb(rinfo->bios_seg + (v) + 1) << 8))
  430. #define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
  431. (readb(rinfo->bios_seg + (v) + 1) << 8) | \
  432. (readb(rinfo->bios_seg + (v) + 2) << 16) | \
  433. (readb(rinfo->bios_seg + (v) + 3) << 24))
  434. /*
  435. * Inline utilities
  436. */
  437. static inline int round_div(int num, int den)
  438. {
  439. return (num + (den / 2)) / den;
  440. }
  441. static inline int var_to_depth(const struct fb_var_screeninfo *var)
  442. {
  443. if (var->bits_per_pixel != 16)
  444. return var->bits_per_pixel;
  445. return (var->green.length == 5) ? 15 : 16;
  446. }
  447. static inline u32 radeon_get_dstbpp(u16 depth)
  448. {
  449. switch (depth) {
  450. case 8:
  451. return DST_8BPP;
  452. case 15:
  453. return DST_15BPP;
  454. case 16:
  455. return DST_16BPP;
  456. case 32:
  457. return DST_32BPP;
  458. default:
  459. return 0;
  460. }
  461. }
  462. /*
  463. * 2D Engine helper routines
  464. */
  465. extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries);
  466. static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
  467. {
  468. int i;
  469. /* Initiate flush */
  470. OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
  471. ~RB2D_DC_FLUSH_ALL);
  472. /* Ensure FIFO is empty, ie, make sure the flush commands
  473. * has reached the cache
  474. */
  475. radeon_fifo_update_and_wait(rinfo, 64);
  476. /* Wait for the flush to complete */
  477. for (i=0; i < 2000000; i++) {
  478. if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
  479. return;
  480. udelay(1);
  481. }
  482. printk(KERN_ERR "radeonfb: Flush Timeout !\n");
  483. }
  484. static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
  485. {
  486. int i;
  487. /* ensure FIFO is empty before waiting for idle */
  488. radeon_fifo_update_and_wait (rinfo, 64);
  489. for (i=0; i<2000000; i++) {
  490. if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
  491. radeon_engine_flush (rinfo);
  492. return;
  493. }
  494. udelay(1);
  495. }
  496. printk(KERN_ERR "radeonfb: Idle Timeout !\n");
  497. }
  498. #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
  499. /* I2C Functions */
  500. extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
  501. extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
  502. extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
  503. /* PM Functions */
  504. extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
  505. extern int radeonfb_pci_resume(struct pci_dev *pdev);
  506. extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
  507. extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
  508. /* Monitor probe functions */
  509. extern void radeon_probe_screens(struct radeonfb_info *rinfo,
  510. const char *monitor_layout, int ignore_edid);
  511. extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
  512. extern int radeon_match_mode(struct radeonfb_info *rinfo,
  513. struct fb_var_screeninfo *dest,
  514. const struct fb_var_screeninfo *src);
  515. /* Accel functions */
  516. extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
  517. extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
  518. extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
  519. extern int radeonfb_sync(struct fb_info *info);
  520. extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
  521. extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
  522. extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
  523. /* Other functions */
  524. extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
  525. extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
  526. int reg_only);
  527. /* Backlight functions */
  528. #ifdef CONFIG_FB_RADEON_BACKLIGHT
  529. extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
  530. extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
  531. #else
  532. static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
  533. static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
  534. #endif
  535. #endif /* __RADEONFB_H__ */