access.c 8.3 KB

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  1. #include <linux/delay.h>
  2. #include <linux/pci.h>
  3. #include <linux/module.h>
  4. #include <linux/sched.h>
  5. #include <linux/ioport.h>
  6. #include <linux/wait.h>
  7. #include "pci.h"
  8. /*
  9. * This interrupt-safe spinlock protects all accesses to PCI
  10. * configuration space.
  11. */
  12. static DEFINE_SPINLOCK(pci_lock);
  13. /*
  14. * Wrappers for all PCI configuration access functions. They just check
  15. * alignment, do locking and call the low-level functions pointed to
  16. * by pci_dev->ops.
  17. */
  18. #define PCI_byte_BAD 0
  19. #define PCI_word_BAD (pos & 1)
  20. #define PCI_dword_BAD (pos & 3)
  21. #define PCI_OP_READ(size,type,len) \
  22. int pci_bus_read_config_##size \
  23. (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
  24. { \
  25. int res; \
  26. unsigned long flags; \
  27. u32 data = 0; \
  28. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  29. spin_lock_irqsave(&pci_lock, flags); \
  30. res = bus->ops->read(bus, devfn, pos, len, &data); \
  31. *value = (type)data; \
  32. spin_unlock_irqrestore(&pci_lock, flags); \
  33. return res; \
  34. }
  35. #define PCI_OP_WRITE(size,type,len) \
  36. int pci_bus_write_config_##size \
  37. (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
  38. { \
  39. int res; \
  40. unsigned long flags; \
  41. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  42. spin_lock_irqsave(&pci_lock, flags); \
  43. res = bus->ops->write(bus, devfn, pos, len, value); \
  44. spin_unlock_irqrestore(&pci_lock, flags); \
  45. return res; \
  46. }
  47. PCI_OP_READ(byte, u8, 1)
  48. PCI_OP_READ(word, u16, 2)
  49. PCI_OP_READ(dword, u32, 4)
  50. PCI_OP_WRITE(byte, u8, 1)
  51. PCI_OP_WRITE(word, u16, 2)
  52. PCI_OP_WRITE(dword, u32, 4)
  53. EXPORT_SYMBOL(pci_bus_read_config_byte);
  54. EXPORT_SYMBOL(pci_bus_read_config_word);
  55. EXPORT_SYMBOL(pci_bus_read_config_dword);
  56. EXPORT_SYMBOL(pci_bus_write_config_byte);
  57. EXPORT_SYMBOL(pci_bus_write_config_word);
  58. EXPORT_SYMBOL(pci_bus_write_config_dword);
  59. /*
  60. * The following routines are to prevent the user from accessing PCI config
  61. * space when it's unsafe to do so. Some devices require this during BIST and
  62. * we're required to prevent it during D-state transitions.
  63. *
  64. * We have a bit per device to indicate it's blocked and a global wait queue
  65. * for callers to sleep on until devices are unblocked.
  66. */
  67. static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
  68. static noinline void pci_wait_ucfg(struct pci_dev *dev)
  69. {
  70. DECLARE_WAITQUEUE(wait, current);
  71. __add_wait_queue(&pci_ucfg_wait, &wait);
  72. do {
  73. set_current_state(TASK_UNINTERRUPTIBLE);
  74. spin_unlock_irq(&pci_lock);
  75. schedule();
  76. spin_lock_irq(&pci_lock);
  77. } while (dev->block_ucfg_access);
  78. __remove_wait_queue(&pci_ucfg_wait, &wait);
  79. }
  80. #define PCI_USER_READ_CONFIG(size,type) \
  81. int pci_user_read_config_##size \
  82. (struct pci_dev *dev, int pos, type *val) \
  83. { \
  84. int ret = 0; \
  85. u32 data = -1; \
  86. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  87. spin_lock_irq(&pci_lock); \
  88. if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
  89. ret = dev->bus->ops->read(dev->bus, dev->devfn, \
  90. pos, sizeof(type), &data); \
  91. spin_unlock_irq(&pci_lock); \
  92. *val = (type)data; \
  93. return ret; \
  94. }
  95. #define PCI_USER_WRITE_CONFIG(size,type) \
  96. int pci_user_write_config_##size \
  97. (struct pci_dev *dev, int pos, type val) \
  98. { \
  99. int ret = -EIO; \
  100. if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
  101. spin_lock_irq(&pci_lock); \
  102. if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
  103. ret = dev->bus->ops->write(dev->bus, dev->devfn, \
  104. pos, sizeof(type), val); \
  105. spin_unlock_irq(&pci_lock); \
  106. return ret; \
  107. }
  108. PCI_USER_READ_CONFIG(byte, u8)
  109. PCI_USER_READ_CONFIG(word, u16)
  110. PCI_USER_READ_CONFIG(dword, u32)
  111. PCI_USER_WRITE_CONFIG(byte, u8)
  112. PCI_USER_WRITE_CONFIG(word, u16)
  113. PCI_USER_WRITE_CONFIG(dword, u32)
  114. /* VPD access through PCI 2.2+ VPD capability */
  115. #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
  116. struct pci_vpd_pci22 {
  117. struct pci_vpd base;
  118. spinlock_t lock; /* controls access to hardware and the flags */
  119. u8 cap;
  120. bool busy;
  121. bool flag; /* value of F bit to wait for */
  122. };
  123. /* Wait for last operation to complete */
  124. static int pci_vpd_pci22_wait(struct pci_dev *dev)
  125. {
  126. struct pci_vpd_pci22 *vpd =
  127. container_of(dev->vpd, struct pci_vpd_pci22, base);
  128. u16 flag, status;
  129. int wait;
  130. int ret;
  131. if (!vpd->busy)
  132. return 0;
  133. flag = vpd->flag ? PCI_VPD_ADDR_F : 0;
  134. wait = vpd->flag ? 10 : 1000; /* read: 100 us; write: 10 ms */
  135. for (;;) {
  136. ret = pci_user_read_config_word(dev,
  137. vpd->cap + PCI_VPD_ADDR,
  138. &status);
  139. if (ret < 0)
  140. return ret;
  141. if ((status & PCI_VPD_ADDR_F) == flag) {
  142. vpd->busy = false;
  143. return 0;
  144. }
  145. if (wait-- == 0)
  146. return -ETIMEDOUT;
  147. udelay(10);
  148. }
  149. }
  150. static int pci_vpd_pci22_read(struct pci_dev *dev, int pos, int size,
  151. char *buf)
  152. {
  153. struct pci_vpd_pci22 *vpd =
  154. container_of(dev->vpd, struct pci_vpd_pci22, base);
  155. u32 val;
  156. int ret;
  157. int begin, end, i;
  158. if (pos < 0 || pos > vpd->base.len || size > vpd->base.len - pos)
  159. return -EINVAL;
  160. if (size == 0)
  161. return 0;
  162. spin_lock_irq(&vpd->lock);
  163. ret = pci_vpd_pci22_wait(dev);
  164. if (ret < 0)
  165. goto out;
  166. ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  167. pos & ~3);
  168. if (ret < 0)
  169. goto out;
  170. vpd->busy = true;
  171. vpd->flag = 1;
  172. ret = pci_vpd_pci22_wait(dev);
  173. if (ret < 0)
  174. goto out;
  175. ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA,
  176. &val);
  177. out:
  178. spin_unlock_irq(&vpd->lock);
  179. if (ret < 0)
  180. return ret;
  181. /* Convert to bytes */
  182. begin = pos & 3;
  183. end = min(4, begin + size);
  184. for (i = 0; i < end; ++i) {
  185. if (i >= begin)
  186. *buf++ = val;
  187. val >>= 8;
  188. }
  189. return end - begin;
  190. }
  191. static int pci_vpd_pci22_write(struct pci_dev *dev, int pos, int size,
  192. const char *buf)
  193. {
  194. struct pci_vpd_pci22 *vpd =
  195. container_of(dev->vpd, struct pci_vpd_pci22, base);
  196. u32 val;
  197. int ret;
  198. if (pos < 0 || pos > vpd->base.len || pos & 3 ||
  199. size > vpd->base.len - pos || size < 4)
  200. return -EINVAL;
  201. val = (u8) *buf++;
  202. val |= ((u8) *buf++) << 8;
  203. val |= ((u8) *buf++) << 16;
  204. val |= ((u32)(u8) *buf++) << 24;
  205. spin_lock_irq(&vpd->lock);
  206. ret = pci_vpd_pci22_wait(dev);
  207. if (ret < 0)
  208. goto out;
  209. ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
  210. val);
  211. if (ret < 0)
  212. goto out;
  213. ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
  214. pos | PCI_VPD_ADDR_F);
  215. if (ret < 0)
  216. goto out;
  217. vpd->busy = true;
  218. vpd->flag = 0;
  219. ret = pci_vpd_pci22_wait(dev);
  220. out:
  221. spin_unlock_irq(&vpd->lock);
  222. if (ret < 0)
  223. return ret;
  224. return 4;
  225. }
  226. static void pci_vpd_pci22_release(struct pci_dev *dev)
  227. {
  228. kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
  229. }
  230. static struct pci_vpd_ops pci_vpd_pci22_ops = {
  231. .read = pci_vpd_pci22_read,
  232. .write = pci_vpd_pci22_write,
  233. .release = pci_vpd_pci22_release,
  234. };
  235. int pci_vpd_pci22_init(struct pci_dev *dev)
  236. {
  237. struct pci_vpd_pci22 *vpd;
  238. u8 cap;
  239. cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
  240. if (!cap)
  241. return -ENODEV;
  242. vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
  243. if (!vpd)
  244. return -ENOMEM;
  245. vpd->base.len = PCI_VPD_PCI22_SIZE;
  246. vpd->base.ops = &pci_vpd_pci22_ops;
  247. spin_lock_init(&vpd->lock);
  248. vpd->cap = cap;
  249. vpd->busy = false;
  250. dev->vpd = &vpd->base;
  251. return 0;
  252. }
  253. /**
  254. * pci_block_user_cfg_access - Block userspace PCI config reads/writes
  255. * @dev: pci device struct
  256. *
  257. * When user access is blocked, any reads or writes to config space will
  258. * sleep until access is unblocked again. We don't allow nesting of
  259. * block/unblock calls.
  260. */
  261. void pci_block_user_cfg_access(struct pci_dev *dev)
  262. {
  263. unsigned long flags;
  264. int was_blocked;
  265. spin_lock_irqsave(&pci_lock, flags);
  266. was_blocked = dev->block_ucfg_access;
  267. dev->block_ucfg_access = 1;
  268. spin_unlock_irqrestore(&pci_lock, flags);
  269. /* If we BUG() inside the pci_lock, we're guaranteed to hose
  270. * the machine */
  271. BUG_ON(was_blocked);
  272. }
  273. EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
  274. /**
  275. * pci_unblock_user_cfg_access - Unblock userspace PCI config reads/writes
  276. * @dev: pci device struct
  277. *
  278. * This function allows userspace PCI config accesses to resume.
  279. */
  280. void pci_unblock_user_cfg_access(struct pci_dev *dev)
  281. {
  282. unsigned long flags;
  283. spin_lock_irqsave(&pci_lock, flags);
  284. /* This indicates a problem in the caller, but we don't need
  285. * to kill them, unlike a double-block above. */
  286. WARN_ON(!dev->block_ucfg_access);
  287. dev->block_ucfg_access = 0;
  288. wake_up_all(&pci_ucfg_wait);
  289. spin_unlock_irqrestore(&pci_lock, flags);
  290. }
  291. EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);