rt2x00queue.c 21 KB

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  1. /*
  2. Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00lib
  19. Abstract: rt2x00 queue specific routines.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/dma-mapping.h>
  24. #include "rt2x00.h"
  25. #include "rt2x00lib.h"
  26. struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
  27. struct queue_entry *entry)
  28. {
  29. struct sk_buff *skb;
  30. struct skb_frame_desc *skbdesc;
  31. unsigned int frame_size;
  32. unsigned int head_size = 0;
  33. unsigned int tail_size = 0;
  34. /*
  35. * The frame size includes descriptor size, because the
  36. * hardware directly receive the frame into the skbuffer.
  37. */
  38. frame_size = entry->queue->data_size + entry->queue->desc_size;
  39. /*
  40. * The payload should be aligned to a 4-byte boundary,
  41. * this means we need at least 3 bytes for moving the frame
  42. * into the correct offset.
  43. */
  44. head_size = 4;
  45. /*
  46. * For IV/EIV/ICV assembly we must make sure there is
  47. * at least 8 bytes bytes available in headroom for IV/EIV
  48. * and 4 bytes for ICV data as tailroon.
  49. */
  50. #ifdef CONFIG_RT2X00_LIB_CRYPTO
  51. if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
  52. head_size += 8;
  53. tail_size += 4;
  54. }
  55. #endif /* CONFIG_RT2X00_LIB_CRYPTO */
  56. /*
  57. * Allocate skbuffer.
  58. */
  59. skb = dev_alloc_skb(frame_size + head_size + tail_size);
  60. if (!skb)
  61. return NULL;
  62. /*
  63. * Make sure we not have a frame with the requested bytes
  64. * available in the head and tail.
  65. */
  66. skb_reserve(skb, head_size);
  67. skb_put(skb, frame_size);
  68. /*
  69. * Populate skbdesc.
  70. */
  71. skbdesc = get_skb_frame_desc(skb);
  72. memset(skbdesc, 0, sizeof(*skbdesc));
  73. skbdesc->entry = entry;
  74. if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
  75. skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
  76. skb->data,
  77. skb->len,
  78. DMA_FROM_DEVICE);
  79. skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
  80. }
  81. return skb;
  82. }
  83. void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  84. {
  85. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  86. /*
  87. * If device has requested headroom, we should make sure that
  88. * is also mapped to the DMA so it can be used for transfering
  89. * additional descriptor information to the hardware.
  90. */
  91. skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
  92. skbdesc->skb_dma =
  93. dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
  94. /*
  95. * Restore data pointer to original location again.
  96. */
  97. skb_pull(skb, rt2x00dev->hw->extra_tx_headroom);
  98. skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
  99. }
  100. EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
  101. void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  102. {
  103. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  104. if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
  105. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
  106. DMA_FROM_DEVICE);
  107. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
  108. }
  109. if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
  110. /*
  111. * Add headroom to the skb length, it has been removed
  112. * by the driver, but it was actually mapped to DMA.
  113. */
  114. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
  115. skb->len + rt2x00dev->hw->extra_tx_headroom,
  116. DMA_TO_DEVICE);
  117. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
  118. }
  119. }
  120. void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  121. {
  122. if (!skb)
  123. return;
  124. rt2x00queue_unmap_skb(rt2x00dev, skb);
  125. dev_kfree_skb_any(skb);
  126. }
  127. static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
  128. struct txentry_desc *txdesc)
  129. {
  130. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  131. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
  132. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
  133. struct ieee80211_rate *rate =
  134. ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
  135. const struct rt2x00_rate *hwrate;
  136. unsigned int data_length;
  137. unsigned int duration;
  138. unsigned int residual;
  139. unsigned long irqflags;
  140. memset(txdesc, 0, sizeof(*txdesc));
  141. /*
  142. * Initialize information from queue
  143. */
  144. txdesc->queue = entry->queue->qid;
  145. txdesc->cw_min = entry->queue->cw_min;
  146. txdesc->cw_max = entry->queue->cw_max;
  147. txdesc->aifs = entry->queue->aifs;
  148. /* Data length + CRC + IV/EIV/ICV/MMIC (when using encryption) */
  149. data_length = entry->skb->len + 4;
  150. /*
  151. * Check whether this frame is to be acked.
  152. */
  153. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
  154. __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
  155. #ifdef CONFIG_RT2X00_LIB_CRYPTO
  156. if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags) &&
  157. !entry->skb->do_not_encrypt) {
  158. struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
  159. __set_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags);
  160. txdesc->cipher = rt2x00crypto_key_to_cipher(hw_key);
  161. if (hw_key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
  162. __set_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags);
  163. txdesc->key_idx = hw_key->hw_key_idx;
  164. txdesc->iv_offset = ieee80211_get_hdrlen_from_skb(entry->skb);
  165. /*
  166. * Extend frame length to include all encryption overhead
  167. * that will be added by the hardware.
  168. */
  169. data_length += rt2x00crypto_tx_overhead(tx_info);
  170. if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_IV))
  171. __set_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags);
  172. if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_MMIC))
  173. __set_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags);
  174. }
  175. #endif /* CONFIG_RT2X00_LIB_CRYPTO */
  176. /*
  177. * Check if this is a RTS/CTS frame
  178. */
  179. if (ieee80211_is_rts(hdr->frame_control) ||
  180. ieee80211_is_cts(hdr->frame_control)) {
  181. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  182. if (ieee80211_is_rts(hdr->frame_control))
  183. __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
  184. else
  185. __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
  186. if (tx_info->control.rts_cts_rate_idx >= 0)
  187. rate =
  188. ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
  189. }
  190. /*
  191. * Determine retry information.
  192. */
  193. txdesc->retry_limit = tx_info->control.retry_limit;
  194. if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
  195. __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
  196. /*
  197. * Check if more fragments are pending
  198. */
  199. if (ieee80211_has_morefrags(hdr->frame_control)) {
  200. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  201. __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
  202. }
  203. /*
  204. * Beacons and probe responses require the tsf timestamp
  205. * to be inserted into the frame.
  206. */
  207. if (ieee80211_is_beacon(hdr->frame_control) ||
  208. ieee80211_is_probe_resp(hdr->frame_control))
  209. __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
  210. /*
  211. * Determine with what IFS priority this frame should be send.
  212. * Set ifs to IFS_SIFS when the this is not the first fragment,
  213. * or this fragment came after RTS/CTS.
  214. */
  215. if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
  216. txdesc->ifs = IFS_SIFS;
  217. } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
  218. __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
  219. txdesc->ifs = IFS_BACKOFF;
  220. } else {
  221. txdesc->ifs = IFS_SIFS;
  222. }
  223. /*
  224. * Hardware should insert sequence counter.
  225. * FIXME: We insert a software sequence counter first for
  226. * hardware that doesn't support hardware sequence counting.
  227. *
  228. * This is wrong because beacons are not getting sequence
  229. * numbers assigned properly.
  230. *
  231. * A secondary problem exists for drivers that cannot toggle
  232. * sequence counting per-frame, since those will override the
  233. * sequence counter given by mac80211.
  234. */
  235. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  236. if (likely(tx_info->control.vif)) {
  237. struct rt2x00_intf *intf;
  238. intf = vif_to_intf(tx_info->control.vif);
  239. spin_lock_irqsave(&intf->seqlock, irqflags);
  240. if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
  241. intf->seqno += 0x10;
  242. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  243. hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
  244. spin_unlock_irqrestore(&intf->seqlock, irqflags);
  245. __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
  246. }
  247. }
  248. /*
  249. * PLCP setup
  250. * Length calculation depends on OFDM/CCK rate.
  251. */
  252. hwrate = rt2x00_get_rate(rate->hw_value);
  253. txdesc->signal = hwrate->plcp;
  254. txdesc->service = 0x04;
  255. if (hwrate->flags & DEV_RATE_OFDM) {
  256. __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags);
  257. txdesc->length_high = (data_length >> 6) & 0x3f;
  258. txdesc->length_low = data_length & 0x3f;
  259. } else {
  260. /*
  261. * Convert length to microseconds.
  262. */
  263. residual = get_duration_res(data_length, hwrate->bitrate);
  264. duration = get_duration(data_length, hwrate->bitrate);
  265. if (residual != 0) {
  266. duration++;
  267. /*
  268. * Check if we need to set the Length Extension
  269. */
  270. if (hwrate->bitrate == 110 && residual <= 30)
  271. txdesc->service |= 0x80;
  272. }
  273. txdesc->length_high = (duration >> 8) & 0xff;
  274. txdesc->length_low = duration & 0xff;
  275. /*
  276. * When preamble is enabled we should set the
  277. * preamble bit for the signal.
  278. */
  279. if (rt2x00_get_rate_preamble(rate->hw_value))
  280. txdesc->signal |= 0x08;
  281. }
  282. }
  283. static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
  284. struct txentry_desc *txdesc)
  285. {
  286. struct data_queue *queue = entry->queue;
  287. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  288. rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
  289. /*
  290. * All processing on the frame has been completed, this means
  291. * it is now ready to be dumped to userspace through debugfs.
  292. */
  293. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
  294. /*
  295. * Check if we need to kick the queue, there are however a few rules
  296. * 1) Don't kick beacon queue
  297. * 2) Don't kick unless this is the last in frame in a burst.
  298. * When the burst flag is set, this frame is always followed
  299. * by another frame which in some way are related to eachother.
  300. * This is true for fragments, RTS or CTS-to-self frames.
  301. * 3) Rule 2 can be broken when the available entries
  302. * in the queue are less then a certain threshold.
  303. */
  304. if (entry->queue->qid == QID_BEACON)
  305. return;
  306. if (rt2x00queue_threshold(queue) ||
  307. !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
  308. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
  309. }
  310. int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
  311. {
  312. struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
  313. struct txentry_desc txdesc;
  314. struct skb_frame_desc *skbdesc;
  315. unsigned int iv_len = 0;
  316. if (unlikely(rt2x00queue_full(queue)))
  317. return -EINVAL;
  318. if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
  319. ERROR(queue->rt2x00dev,
  320. "Arrived at non-free entry in the non-full queue %d.\n"
  321. "Please file bug report to %s.\n",
  322. queue->qid, DRV_PROJECT);
  323. return -EINVAL;
  324. }
  325. /*
  326. * Copy all TX descriptor information into txdesc,
  327. * after that we are free to use the skb->cb array
  328. * for our information.
  329. */
  330. entry->skb = skb;
  331. rt2x00queue_create_tx_descriptor(entry, &txdesc);
  332. if (IEEE80211_SKB_CB(skb)->control.hw_key != NULL)
  333. iv_len = IEEE80211_SKB_CB(skb)->control.hw_key->iv_len;
  334. /*
  335. * All information is retreived from the skb->cb array,
  336. * now we should claim ownership of the driver part of that
  337. * array.
  338. */
  339. skbdesc = get_skb_frame_desc(entry->skb);
  340. memset(skbdesc, 0, sizeof(*skbdesc));
  341. skbdesc->entry = entry;
  342. /*
  343. * When hardware encryption is supported, and this frame
  344. * is to be encrypted, we should strip the IV/EIV data from
  345. * the frame so we can provide it to the driver seperately.
  346. */
  347. if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
  348. !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
  349. rt2x00crypto_tx_remove_iv(skb, iv_len);
  350. }
  351. /*
  352. * It could be possible that the queue was corrupted and this
  353. * call failed. Just drop the frame, we cannot rollback and pass
  354. * the frame to mac80211 because the skb->cb has now been tainted.
  355. */
  356. if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
  357. clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
  358. dev_kfree_skb_any(entry->skb);
  359. entry->skb = NULL;
  360. return 0;
  361. }
  362. if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
  363. rt2x00queue_map_txskb(queue->rt2x00dev, skb);
  364. set_bit(ENTRY_DATA_PENDING, &entry->flags);
  365. rt2x00queue_index_inc(queue, Q_INDEX);
  366. rt2x00queue_write_tx_descriptor(entry, &txdesc);
  367. return 0;
  368. }
  369. int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
  370. struct ieee80211_vif *vif)
  371. {
  372. struct rt2x00_intf *intf = vif_to_intf(vif);
  373. struct skb_frame_desc *skbdesc;
  374. struct txentry_desc txdesc;
  375. __le32 desc[16];
  376. if (unlikely(!intf->beacon))
  377. return -ENOBUFS;
  378. intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
  379. if (!intf->beacon->skb)
  380. return -ENOMEM;
  381. /*
  382. * Copy all TX descriptor information into txdesc,
  383. * after that we are free to use the skb->cb array
  384. * for our information.
  385. */
  386. rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
  387. /*
  388. * For the descriptor we use a local array from where the
  389. * driver can move it to the correct location required for
  390. * the hardware.
  391. */
  392. memset(desc, 0, sizeof(desc));
  393. /*
  394. * Fill in skb descriptor
  395. */
  396. skbdesc = get_skb_frame_desc(intf->beacon->skb);
  397. memset(skbdesc, 0, sizeof(*skbdesc));
  398. skbdesc->desc = desc;
  399. skbdesc->desc_len = intf->beacon->queue->desc_size;
  400. skbdesc->entry = intf->beacon;
  401. /*
  402. * Write TX descriptor into reserved room in front of the beacon.
  403. */
  404. rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
  405. /*
  406. * Send beacon to hardware.
  407. * Also enable beacon generation, which might have been disabled
  408. * by the driver during the config_beacon() callback function.
  409. */
  410. rt2x00dev->ops->lib->write_beacon(intf->beacon);
  411. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
  412. return 0;
  413. }
  414. struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
  415. const enum data_queue_qid queue)
  416. {
  417. int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  418. if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
  419. return &rt2x00dev->tx[queue];
  420. if (!rt2x00dev->bcn)
  421. return NULL;
  422. if (queue == QID_BEACON)
  423. return &rt2x00dev->bcn[0];
  424. else if (queue == QID_ATIM && atim)
  425. return &rt2x00dev->bcn[1];
  426. return NULL;
  427. }
  428. EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
  429. struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
  430. enum queue_index index)
  431. {
  432. struct queue_entry *entry;
  433. unsigned long irqflags;
  434. if (unlikely(index >= Q_INDEX_MAX)) {
  435. ERROR(queue->rt2x00dev,
  436. "Entry requested from invalid index type (%d)\n", index);
  437. return NULL;
  438. }
  439. spin_lock_irqsave(&queue->lock, irqflags);
  440. entry = &queue->entries[queue->index[index]];
  441. spin_unlock_irqrestore(&queue->lock, irqflags);
  442. return entry;
  443. }
  444. EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
  445. void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
  446. {
  447. unsigned long irqflags;
  448. if (unlikely(index >= Q_INDEX_MAX)) {
  449. ERROR(queue->rt2x00dev,
  450. "Index change on invalid index type (%d)\n", index);
  451. return;
  452. }
  453. spin_lock_irqsave(&queue->lock, irqflags);
  454. queue->index[index]++;
  455. if (queue->index[index] >= queue->limit)
  456. queue->index[index] = 0;
  457. if (index == Q_INDEX) {
  458. queue->length++;
  459. } else if (index == Q_INDEX_DONE) {
  460. queue->length--;
  461. queue->count ++;
  462. }
  463. spin_unlock_irqrestore(&queue->lock, irqflags);
  464. }
  465. static void rt2x00queue_reset(struct data_queue *queue)
  466. {
  467. unsigned long irqflags;
  468. spin_lock_irqsave(&queue->lock, irqflags);
  469. queue->count = 0;
  470. queue->length = 0;
  471. memset(queue->index, 0, sizeof(queue->index));
  472. spin_unlock_irqrestore(&queue->lock, irqflags);
  473. }
  474. void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev)
  475. {
  476. struct data_queue *queue = rt2x00dev->rx;
  477. unsigned int i;
  478. rt2x00queue_reset(queue);
  479. if (!rt2x00dev->ops->lib->init_rxentry)
  480. return;
  481. for (i = 0; i < queue->limit; i++) {
  482. queue->entries[i].flags = 0;
  483. rt2x00dev->ops->lib->init_rxentry(rt2x00dev,
  484. &queue->entries[i]);
  485. }
  486. }
  487. void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev)
  488. {
  489. struct data_queue *queue;
  490. unsigned int i;
  491. txall_queue_for_each(rt2x00dev, queue) {
  492. rt2x00queue_reset(queue);
  493. if (!rt2x00dev->ops->lib->init_txentry)
  494. continue;
  495. for (i = 0; i < queue->limit; i++) {
  496. queue->entries[i].flags = 0;
  497. rt2x00dev->ops->lib->init_txentry(rt2x00dev,
  498. &queue->entries[i]);
  499. }
  500. }
  501. }
  502. static int rt2x00queue_alloc_entries(struct data_queue *queue,
  503. const struct data_queue_desc *qdesc)
  504. {
  505. struct queue_entry *entries;
  506. unsigned int entry_size;
  507. unsigned int i;
  508. rt2x00queue_reset(queue);
  509. queue->limit = qdesc->entry_num;
  510. queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
  511. queue->data_size = qdesc->data_size;
  512. queue->desc_size = qdesc->desc_size;
  513. /*
  514. * Allocate all queue entries.
  515. */
  516. entry_size = sizeof(*entries) + qdesc->priv_size;
  517. entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
  518. if (!entries)
  519. return -ENOMEM;
  520. #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
  521. ( ((char *)(__base)) + ((__limit) * (__esize)) + \
  522. ((__index) * (__psize)) )
  523. for (i = 0; i < queue->limit; i++) {
  524. entries[i].flags = 0;
  525. entries[i].queue = queue;
  526. entries[i].skb = NULL;
  527. entries[i].entry_idx = i;
  528. entries[i].priv_data =
  529. QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
  530. sizeof(*entries), qdesc->priv_size);
  531. }
  532. #undef QUEUE_ENTRY_PRIV_OFFSET
  533. queue->entries = entries;
  534. return 0;
  535. }
  536. static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
  537. struct data_queue *queue)
  538. {
  539. unsigned int i;
  540. if (!queue->entries)
  541. return;
  542. for (i = 0; i < queue->limit; i++) {
  543. if (queue->entries[i].skb)
  544. rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
  545. }
  546. }
  547. static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
  548. struct data_queue *queue)
  549. {
  550. unsigned int i;
  551. struct sk_buff *skb;
  552. for (i = 0; i < queue->limit; i++) {
  553. skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
  554. if (!skb)
  555. return -ENOMEM;
  556. queue->entries[i].skb = skb;
  557. }
  558. return 0;
  559. }
  560. int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
  561. {
  562. struct data_queue *queue;
  563. int status;
  564. status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
  565. if (status)
  566. goto exit;
  567. tx_queue_for_each(rt2x00dev, queue) {
  568. status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
  569. if (status)
  570. goto exit;
  571. }
  572. status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
  573. if (status)
  574. goto exit;
  575. if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
  576. status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
  577. rt2x00dev->ops->atim);
  578. if (status)
  579. goto exit;
  580. }
  581. status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
  582. if (status)
  583. goto exit;
  584. return 0;
  585. exit:
  586. ERROR(rt2x00dev, "Queue entries allocation failed.\n");
  587. rt2x00queue_uninitialize(rt2x00dev);
  588. return status;
  589. }
  590. void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
  591. {
  592. struct data_queue *queue;
  593. rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
  594. queue_for_each(rt2x00dev, queue) {
  595. kfree(queue->entries);
  596. queue->entries = NULL;
  597. }
  598. }
  599. static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
  600. struct data_queue *queue, enum data_queue_qid qid)
  601. {
  602. spin_lock_init(&queue->lock);
  603. queue->rt2x00dev = rt2x00dev;
  604. queue->qid = qid;
  605. queue->txop = 0;
  606. queue->aifs = 2;
  607. queue->cw_min = 5;
  608. queue->cw_max = 10;
  609. }
  610. int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
  611. {
  612. struct data_queue *queue;
  613. enum data_queue_qid qid;
  614. unsigned int req_atim =
  615. !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  616. /*
  617. * We need the following queues:
  618. * RX: 1
  619. * TX: ops->tx_queues
  620. * Beacon: 1
  621. * Atim: 1 (if required)
  622. */
  623. rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
  624. queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
  625. if (!queue) {
  626. ERROR(rt2x00dev, "Queue allocation failed.\n");
  627. return -ENOMEM;
  628. }
  629. /*
  630. * Initialize pointers
  631. */
  632. rt2x00dev->rx = queue;
  633. rt2x00dev->tx = &queue[1];
  634. rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
  635. /*
  636. * Initialize queue parameters.
  637. * RX: qid = QID_RX
  638. * TX: qid = QID_AC_BE + index
  639. * TX: cw_min: 2^5 = 32.
  640. * TX: cw_max: 2^10 = 1024.
  641. * BCN: qid = QID_BEACON
  642. * ATIM: qid = QID_ATIM
  643. */
  644. rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
  645. qid = QID_AC_BE;
  646. tx_queue_for_each(rt2x00dev, queue)
  647. rt2x00queue_init(rt2x00dev, queue, qid++);
  648. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
  649. if (req_atim)
  650. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
  651. return 0;
  652. }
  653. void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
  654. {
  655. kfree(rt2x00dev->rx);
  656. rt2x00dev->rx = NULL;
  657. rt2x00dev->tx = NULL;
  658. rt2x00dev->bcn = NULL;
  659. }