iwl3945-base.c 234 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #include "iwl-3945-core.h"
  45. #include "iwl-3945.h"
  46. #include "iwl-helpers.h"
  47. #ifdef CONFIG_IWL3945_DEBUG
  48. u32 iwl3945_debug_level;
  49. #endif
  50. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  51. struct iwl3945_tx_queue *txq);
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /* module parameters */
  58. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  59. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  60. static int iwl3945_param_disable; /* def: 0 = enable radio */
  61. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  62. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  63. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  64. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWLWIFI_VERSION "1.2.26k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  83. #define DRV_VERSION IWLWIFI_VERSION
  84. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85. MODULE_VERSION(DRV_VERSION);
  86. MODULE_AUTHOR(DRV_COPYRIGHT);
  87. MODULE_LICENSE("GPL");
  88. static const struct ieee80211_supported_band *iwl3945_get_band(
  89. struct iwl3945_priv *priv, enum ieee80211_band band)
  90. {
  91. return priv->hw->wiphy->bands[band];
  92. }
  93. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  94. {
  95. /* Single white space is for Linksys APs */
  96. if (essid_len == 1 && essid[0] == ' ')
  97. return 1;
  98. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  99. while (essid_len) {
  100. essid_len--;
  101. if (essid[essid_len] != '\0')
  102. return 0;
  103. }
  104. return 1;
  105. }
  106. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  107. {
  108. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  109. const char *s = essid;
  110. char *d = escaped;
  111. if (iwl3945_is_empty_essid(essid, essid_len)) {
  112. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  113. return escaped;
  114. }
  115. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  116. while (essid_len--) {
  117. if (*s == '\0') {
  118. *d++ = '\\';
  119. *d++ = '0';
  120. s++;
  121. } else
  122. *d++ = *s++;
  123. }
  124. *d = '\0';
  125. return escaped;
  126. }
  127. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  128. * DMA services
  129. *
  130. * Theory of operation
  131. *
  132. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  133. * of buffer descriptors, each of which points to one or more data buffers for
  134. * the device to read from or fill. Driver and device exchange status of each
  135. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  136. * entries in each circular buffer, to protect against confusing empty and full
  137. * queue states.
  138. *
  139. * The device reads or writes the data in the queues via the device's several
  140. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  141. *
  142. * For Tx queue, there are low mark and high mark limits. If, after queuing
  143. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  144. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  145. * Tx queue resumed.
  146. *
  147. * The 3945 operates with six queues: One receive queue, one transmit queue
  148. * (#4) for sending commands to the device firmware, and four transmit queues
  149. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  150. ***************************************************/
  151. int iwl3945_queue_space(const struct iwl3945_queue *q)
  152. {
  153. int s = q->read_ptr - q->write_ptr;
  154. if (q->read_ptr > q->write_ptr)
  155. s -= q->n_bd;
  156. if (s <= 0)
  157. s += q->n_window;
  158. /* keep some reserve to not confuse empty and full situations */
  159. s -= 2;
  160. if (s < 0)
  161. s = 0;
  162. return s;
  163. }
  164. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  165. {
  166. return q->write_ptr > q->read_ptr ?
  167. (i >= q->read_ptr && i < q->write_ptr) :
  168. !(i < q->read_ptr && i >= q->write_ptr);
  169. }
  170. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  171. {
  172. /* This is for scan command, the big buffer at end of command array */
  173. if (is_huge)
  174. return q->n_window; /* must be power of 2 */
  175. /* Otherwise, use normal size buffers */
  176. return index & (q->n_window - 1);
  177. }
  178. /**
  179. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  180. */
  181. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  182. int count, int slots_num, u32 id)
  183. {
  184. q->n_bd = count;
  185. q->n_window = slots_num;
  186. q->id = id;
  187. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  188. * and iwl_queue_dec_wrap are broken. */
  189. BUG_ON(!is_power_of_2(count));
  190. /* slots_num must be power-of-two size, otherwise
  191. * get_cmd_index is broken. */
  192. BUG_ON(!is_power_of_2(slots_num));
  193. q->low_mark = q->n_window / 4;
  194. if (q->low_mark < 4)
  195. q->low_mark = 4;
  196. q->high_mark = q->n_window / 8;
  197. if (q->high_mark < 2)
  198. q->high_mark = 2;
  199. q->write_ptr = q->read_ptr = 0;
  200. return 0;
  201. }
  202. /**
  203. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  204. */
  205. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  206. struct iwl3945_tx_queue *txq, u32 id)
  207. {
  208. struct pci_dev *dev = priv->pci_dev;
  209. /* Driver private data, only for Tx (not command) queues,
  210. * not shared with device. */
  211. if (id != IWL_CMD_QUEUE_NUM) {
  212. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  213. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  214. if (!txq->txb) {
  215. IWL_ERROR("kmalloc for auxiliary BD "
  216. "structures failed\n");
  217. goto error;
  218. }
  219. } else
  220. txq->txb = NULL;
  221. /* Circular buffer of transmit frame descriptors (TFDs),
  222. * shared with device */
  223. txq->bd = pci_alloc_consistent(dev,
  224. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  225. &txq->q.dma_addr);
  226. if (!txq->bd) {
  227. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  228. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  229. goto error;
  230. }
  231. txq->q.id = id;
  232. return 0;
  233. error:
  234. kfree(txq->txb);
  235. txq->txb = NULL;
  236. return -ENOMEM;
  237. }
  238. /**
  239. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  240. */
  241. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  242. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  243. {
  244. struct pci_dev *dev = priv->pci_dev;
  245. int len;
  246. int rc = 0;
  247. /*
  248. * Alloc buffer array for commands (Tx or other types of commands).
  249. * For the command queue (#4), allocate command space + one big
  250. * command for scan, since scan command is very huge; the system will
  251. * not have two scans at the same time, so only one is needed.
  252. * For data Tx queues (all other queues), no super-size command
  253. * space is needed.
  254. */
  255. len = sizeof(struct iwl3945_cmd) * slots_num;
  256. if (txq_id == IWL_CMD_QUEUE_NUM)
  257. len += IWL_MAX_SCAN_SIZE;
  258. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  259. if (!txq->cmd)
  260. return -ENOMEM;
  261. /* Alloc driver data array and TFD circular buffer */
  262. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  263. if (rc) {
  264. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  265. return -ENOMEM;
  266. }
  267. txq->need_update = 0;
  268. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  269. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  270. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  271. /* Initialize queue high/low-water, head/tail indexes */
  272. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  273. /* Tell device where to find queue, enable DMA channel. */
  274. iwl3945_hw_tx_queue_init(priv, txq);
  275. return 0;
  276. }
  277. /**
  278. * iwl3945_tx_queue_free - Deallocate DMA queue.
  279. * @txq: Transmit queue to deallocate.
  280. *
  281. * Empty queue by removing and destroying all BD's.
  282. * Free all buffers.
  283. * 0-fill, but do not free "txq" descriptor structure.
  284. */
  285. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  286. {
  287. struct iwl3945_queue *q = &txq->q;
  288. struct pci_dev *dev = priv->pci_dev;
  289. int len;
  290. if (q->n_bd == 0)
  291. return;
  292. /* first, empty all BD's */
  293. for (; q->write_ptr != q->read_ptr;
  294. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  295. iwl3945_hw_txq_free_tfd(priv, txq);
  296. len = sizeof(struct iwl3945_cmd) * q->n_window;
  297. if (q->id == IWL_CMD_QUEUE_NUM)
  298. len += IWL_MAX_SCAN_SIZE;
  299. /* De-alloc array of command/tx buffers */
  300. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  301. /* De-alloc circular buffer of TFDs */
  302. if (txq->q.n_bd)
  303. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  304. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  305. /* De-alloc array of per-TFD driver data */
  306. kfree(txq->txb);
  307. txq->txb = NULL;
  308. /* 0-fill queue descriptor structure */
  309. memset(txq, 0, sizeof(*txq));
  310. }
  311. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  312. /*************** STATION TABLE MANAGEMENT ****
  313. * mac80211 should be examined to determine if sta_info is duplicating
  314. * the functionality provided here
  315. */
  316. /**************************************************************/
  317. #if 0 /* temporary disable till we add real remove station */
  318. /**
  319. * iwl3945_remove_station - Remove driver's knowledge of station.
  320. *
  321. * NOTE: This does not remove station from device's station table.
  322. */
  323. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  324. {
  325. int index = IWL_INVALID_STATION;
  326. int i;
  327. unsigned long flags;
  328. spin_lock_irqsave(&priv->sta_lock, flags);
  329. if (is_ap)
  330. index = IWL_AP_ID;
  331. else if (is_broadcast_ether_addr(addr))
  332. index = priv->hw_setting.bcast_sta_id;
  333. else
  334. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  335. if (priv->stations[i].used &&
  336. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  337. addr)) {
  338. index = i;
  339. break;
  340. }
  341. if (unlikely(index == IWL_INVALID_STATION))
  342. goto out;
  343. if (priv->stations[index].used) {
  344. priv->stations[index].used = 0;
  345. priv->num_stations--;
  346. }
  347. BUG_ON(priv->num_stations < 0);
  348. out:
  349. spin_unlock_irqrestore(&priv->sta_lock, flags);
  350. return 0;
  351. }
  352. #endif
  353. /**
  354. * iwl3945_clear_stations_table - Clear the driver's station table
  355. *
  356. * NOTE: This does not clear or otherwise alter the device's station table.
  357. */
  358. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  359. {
  360. unsigned long flags;
  361. spin_lock_irqsave(&priv->sta_lock, flags);
  362. priv->num_stations = 0;
  363. memset(priv->stations, 0, sizeof(priv->stations));
  364. spin_unlock_irqrestore(&priv->sta_lock, flags);
  365. }
  366. /**
  367. * iwl3945_add_station - Add station to station tables in driver and device
  368. */
  369. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  370. {
  371. int i;
  372. int index = IWL_INVALID_STATION;
  373. struct iwl3945_station_entry *station;
  374. unsigned long flags_spin;
  375. DECLARE_MAC_BUF(mac);
  376. u8 rate;
  377. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  378. if (is_ap)
  379. index = IWL_AP_ID;
  380. else if (is_broadcast_ether_addr(addr))
  381. index = priv->hw_setting.bcast_sta_id;
  382. else
  383. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  384. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  385. addr)) {
  386. index = i;
  387. break;
  388. }
  389. if (!priv->stations[i].used &&
  390. index == IWL_INVALID_STATION)
  391. index = i;
  392. }
  393. /* These two conditions has the same outcome but keep them separate
  394. since they have different meaning */
  395. if (unlikely(index == IWL_INVALID_STATION)) {
  396. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  397. return index;
  398. }
  399. if (priv->stations[index].used &&
  400. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  401. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  402. return index;
  403. }
  404. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  405. station = &priv->stations[index];
  406. station->used = 1;
  407. priv->num_stations++;
  408. /* Set up the REPLY_ADD_STA command to send to device */
  409. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  410. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  411. station->sta.mode = 0;
  412. station->sta.sta.sta_id = index;
  413. station->sta.station_flags = 0;
  414. if (priv->band == IEEE80211_BAND_5GHZ)
  415. rate = IWL_RATE_6M_PLCP;
  416. else
  417. rate = IWL_RATE_1M_PLCP;
  418. /* Turn on both antennas for the station... */
  419. station->sta.rate_n_flags =
  420. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  421. station->current_rate.rate_n_flags =
  422. le16_to_cpu(station->sta.rate_n_flags);
  423. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  424. /* Add station to device's station table */
  425. iwl3945_send_add_station(priv, &station->sta, flags);
  426. return index;
  427. }
  428. /*************** DRIVER STATUS FUNCTIONS *****/
  429. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  430. {
  431. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  432. * set but EXIT_PENDING is not */
  433. return test_bit(STATUS_READY, &priv->status) &&
  434. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  435. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  436. }
  437. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  438. {
  439. return test_bit(STATUS_ALIVE, &priv->status);
  440. }
  441. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  442. {
  443. return test_bit(STATUS_INIT, &priv->status);
  444. }
  445. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  446. {
  447. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  448. }
  449. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  450. {
  451. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  452. }
  453. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  454. {
  455. return iwl3945_is_rfkill_hw(priv) ||
  456. iwl3945_is_rfkill_sw(priv);
  457. }
  458. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  459. {
  460. if (iwl3945_is_rfkill(priv))
  461. return 0;
  462. return iwl3945_is_ready(priv);
  463. }
  464. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  465. #define IWL_CMD(x) case x : return #x
  466. static const char *get_cmd_string(u8 cmd)
  467. {
  468. switch (cmd) {
  469. IWL_CMD(REPLY_ALIVE);
  470. IWL_CMD(REPLY_ERROR);
  471. IWL_CMD(REPLY_RXON);
  472. IWL_CMD(REPLY_RXON_ASSOC);
  473. IWL_CMD(REPLY_QOS_PARAM);
  474. IWL_CMD(REPLY_RXON_TIMING);
  475. IWL_CMD(REPLY_ADD_STA);
  476. IWL_CMD(REPLY_REMOVE_STA);
  477. IWL_CMD(REPLY_REMOVE_ALL_STA);
  478. IWL_CMD(REPLY_3945_RX);
  479. IWL_CMD(REPLY_TX);
  480. IWL_CMD(REPLY_RATE_SCALE);
  481. IWL_CMD(REPLY_LEDS_CMD);
  482. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  483. IWL_CMD(RADAR_NOTIFICATION);
  484. IWL_CMD(REPLY_QUIET_CMD);
  485. IWL_CMD(REPLY_CHANNEL_SWITCH);
  486. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  487. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  488. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  489. IWL_CMD(POWER_TABLE_CMD);
  490. IWL_CMD(PM_SLEEP_NOTIFICATION);
  491. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  492. IWL_CMD(REPLY_SCAN_CMD);
  493. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  494. IWL_CMD(SCAN_START_NOTIFICATION);
  495. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  496. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  497. IWL_CMD(BEACON_NOTIFICATION);
  498. IWL_CMD(REPLY_TX_BEACON);
  499. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  500. IWL_CMD(QUIET_NOTIFICATION);
  501. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  502. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  503. IWL_CMD(REPLY_BT_CONFIG);
  504. IWL_CMD(REPLY_STATISTICS_CMD);
  505. IWL_CMD(STATISTICS_NOTIFICATION);
  506. IWL_CMD(REPLY_CARD_STATE_CMD);
  507. IWL_CMD(CARD_STATE_NOTIFICATION);
  508. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  509. default:
  510. return "UNKNOWN";
  511. }
  512. }
  513. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  514. /**
  515. * iwl3945_enqueue_hcmd - enqueue a uCode command
  516. * @priv: device private data point
  517. * @cmd: a point to the ucode command structure
  518. *
  519. * The function returns < 0 values to indicate the operation is
  520. * failed. On success, it turns the index (> 0) of command in the
  521. * command queue.
  522. */
  523. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  524. {
  525. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  526. struct iwl3945_queue *q = &txq->q;
  527. struct iwl3945_tfd_frame *tfd;
  528. u32 *control_flags;
  529. struct iwl3945_cmd *out_cmd;
  530. u32 idx;
  531. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  532. dma_addr_t phys_addr;
  533. int pad;
  534. u16 count;
  535. int ret;
  536. unsigned long flags;
  537. /* If any of the command structures end up being larger than
  538. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  539. * we will need to increase the size of the TFD entries */
  540. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  541. !(cmd->meta.flags & CMD_SIZE_HUGE));
  542. if (iwl3945_is_rfkill(priv)) {
  543. IWL_DEBUG_INFO("Not sending command - RF KILL");
  544. return -EIO;
  545. }
  546. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  547. IWL_ERROR("No space for Tx\n");
  548. return -ENOSPC;
  549. }
  550. spin_lock_irqsave(&priv->hcmd_lock, flags);
  551. tfd = &txq->bd[q->write_ptr];
  552. memset(tfd, 0, sizeof(*tfd));
  553. control_flags = (u32 *) tfd;
  554. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  555. out_cmd = &txq->cmd[idx];
  556. out_cmd->hdr.cmd = cmd->id;
  557. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  558. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  559. /* At this point, the out_cmd now has all of the incoming cmd
  560. * information */
  561. out_cmd->hdr.flags = 0;
  562. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  563. INDEX_TO_SEQ(q->write_ptr));
  564. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  565. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  566. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  567. offsetof(struct iwl3945_cmd, hdr);
  568. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  569. pad = U32_PAD(cmd->len);
  570. count = TFD_CTL_COUNT_GET(*control_flags);
  571. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  572. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  573. "%d bytes at %d[%d]:%d\n",
  574. get_cmd_string(out_cmd->hdr.cmd),
  575. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  576. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  577. txq->need_update = 1;
  578. /* Increment and update queue's write index */
  579. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  580. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  581. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  582. return ret ? ret : idx;
  583. }
  584. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  585. {
  586. int ret;
  587. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  588. /* An asynchronous command can not expect an SKB to be set. */
  589. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  590. /* An asynchronous command MUST have a callback. */
  591. BUG_ON(!cmd->meta.u.callback);
  592. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  593. return -EBUSY;
  594. ret = iwl3945_enqueue_hcmd(priv, cmd);
  595. if (ret < 0) {
  596. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  597. get_cmd_string(cmd->id), ret);
  598. return ret;
  599. }
  600. return 0;
  601. }
  602. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  603. {
  604. int cmd_idx;
  605. int ret;
  606. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  607. /* A synchronous command can not have a callback set. */
  608. BUG_ON(cmd->meta.u.callback != NULL);
  609. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  610. IWL_ERROR("Error sending %s: Already sending a host command\n",
  611. get_cmd_string(cmd->id));
  612. ret = -EBUSY;
  613. goto out;
  614. }
  615. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  616. if (cmd->meta.flags & CMD_WANT_SKB)
  617. cmd->meta.source = &cmd->meta;
  618. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  619. if (cmd_idx < 0) {
  620. ret = cmd_idx;
  621. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  622. get_cmd_string(cmd->id), ret);
  623. goto out;
  624. }
  625. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  626. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  627. HOST_COMPLETE_TIMEOUT);
  628. if (!ret) {
  629. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  630. IWL_ERROR("Error sending %s: time out after %dms.\n",
  631. get_cmd_string(cmd->id),
  632. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  633. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  634. ret = -ETIMEDOUT;
  635. goto cancel;
  636. }
  637. }
  638. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  639. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  640. get_cmd_string(cmd->id));
  641. ret = -ECANCELED;
  642. goto fail;
  643. }
  644. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  645. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  646. get_cmd_string(cmd->id));
  647. ret = -EIO;
  648. goto fail;
  649. }
  650. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  651. IWL_ERROR("Error: Response NULL in '%s'\n",
  652. get_cmd_string(cmd->id));
  653. ret = -EIO;
  654. goto out;
  655. }
  656. ret = 0;
  657. goto out;
  658. cancel:
  659. if (cmd->meta.flags & CMD_WANT_SKB) {
  660. struct iwl3945_cmd *qcmd;
  661. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  662. * TX cmd queue. Otherwise in case the cmd comes
  663. * in later, it will possibly set an invalid
  664. * address (cmd->meta.source). */
  665. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  666. qcmd->meta.flags &= ~CMD_WANT_SKB;
  667. }
  668. fail:
  669. if (cmd->meta.u.skb) {
  670. dev_kfree_skb_any(cmd->meta.u.skb);
  671. cmd->meta.u.skb = NULL;
  672. }
  673. out:
  674. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  675. return ret;
  676. }
  677. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  678. {
  679. if (cmd->meta.flags & CMD_ASYNC)
  680. return iwl3945_send_cmd_async(priv, cmd);
  681. return iwl3945_send_cmd_sync(priv, cmd);
  682. }
  683. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  684. {
  685. struct iwl3945_host_cmd cmd = {
  686. .id = id,
  687. .len = len,
  688. .data = data,
  689. };
  690. return iwl3945_send_cmd_sync(priv, &cmd);
  691. }
  692. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  693. {
  694. struct iwl3945_host_cmd cmd = {
  695. .id = id,
  696. .len = sizeof(val),
  697. .data = &val,
  698. };
  699. return iwl3945_send_cmd_sync(priv, &cmd);
  700. }
  701. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  702. {
  703. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  704. }
  705. /**
  706. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  707. * @band: 2.4 or 5 GHz band
  708. * @channel: Any channel valid for the requested band
  709. * In addition to setting the staging RXON, priv->band is also set.
  710. *
  711. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  712. * in the staging RXON flag structure based on the band
  713. */
  714. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  715. enum ieee80211_band band,
  716. u16 channel)
  717. {
  718. if (!iwl3945_get_channel_info(priv, band, channel)) {
  719. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  720. channel, band);
  721. return -EINVAL;
  722. }
  723. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  724. (priv->band == band))
  725. return 0;
  726. priv->staging_rxon.channel = cpu_to_le16(channel);
  727. if (band == IEEE80211_BAND_5GHZ)
  728. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  729. else
  730. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  731. priv->band = band;
  732. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  733. return 0;
  734. }
  735. /**
  736. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  737. *
  738. * NOTE: This is really only useful during development and can eventually
  739. * be #ifdef'd out once the driver is stable and folks aren't actively
  740. * making changes
  741. */
  742. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  743. {
  744. int error = 0;
  745. int counter = 1;
  746. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  747. error |= le32_to_cpu(rxon->flags &
  748. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  749. RXON_FLG_RADAR_DETECT_MSK));
  750. if (error)
  751. IWL_WARNING("check 24G fields %d | %d\n",
  752. counter++, error);
  753. } else {
  754. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  755. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  756. if (error)
  757. IWL_WARNING("check 52 fields %d | %d\n",
  758. counter++, error);
  759. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  760. if (error)
  761. IWL_WARNING("check 52 CCK %d | %d\n",
  762. counter++, error);
  763. }
  764. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  765. if (error)
  766. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  767. /* make sure basic rates 6Mbps and 1Mbps are supported */
  768. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  769. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  770. if (error)
  771. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  772. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  773. if (error)
  774. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  775. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  776. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  777. if (error)
  778. IWL_WARNING("check CCK and short slot %d | %d\n",
  779. counter++, error);
  780. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  781. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  782. if (error)
  783. IWL_WARNING("check CCK & auto detect %d | %d\n",
  784. counter++, error);
  785. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  786. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  787. if (error)
  788. IWL_WARNING("check TGG and auto detect %d | %d\n",
  789. counter++, error);
  790. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  791. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  792. RXON_FLG_ANT_A_MSK)) == 0);
  793. if (error)
  794. IWL_WARNING("check antenna %d %d\n", counter++, error);
  795. if (error)
  796. IWL_WARNING("Tuning to channel %d\n",
  797. le16_to_cpu(rxon->channel));
  798. if (error) {
  799. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  800. return -1;
  801. }
  802. return 0;
  803. }
  804. /**
  805. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  806. * @priv: staging_rxon is compared to active_rxon
  807. *
  808. * If the RXON structure is changing enough to require a new tune,
  809. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  810. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  811. */
  812. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  813. {
  814. /* These items are only settable from the full RXON command */
  815. if (!(iwl3945_is_associated(priv)) ||
  816. compare_ether_addr(priv->staging_rxon.bssid_addr,
  817. priv->active_rxon.bssid_addr) ||
  818. compare_ether_addr(priv->staging_rxon.node_addr,
  819. priv->active_rxon.node_addr) ||
  820. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  821. priv->active_rxon.wlap_bssid_addr) ||
  822. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  823. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  824. (priv->staging_rxon.air_propagation !=
  825. priv->active_rxon.air_propagation) ||
  826. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  827. return 1;
  828. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  829. * be updated with the RXON_ASSOC command -- however only some
  830. * flag transitions are allowed using RXON_ASSOC */
  831. /* Check if we are not switching bands */
  832. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  833. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  834. return 1;
  835. /* Check if we are switching association toggle */
  836. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  837. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  838. return 1;
  839. return 0;
  840. }
  841. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  842. {
  843. int rc = 0;
  844. struct iwl3945_rx_packet *res = NULL;
  845. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  846. struct iwl3945_host_cmd cmd = {
  847. .id = REPLY_RXON_ASSOC,
  848. .len = sizeof(rxon_assoc),
  849. .meta.flags = CMD_WANT_SKB,
  850. .data = &rxon_assoc,
  851. };
  852. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  853. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  854. if ((rxon1->flags == rxon2->flags) &&
  855. (rxon1->filter_flags == rxon2->filter_flags) &&
  856. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  857. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  858. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  859. return 0;
  860. }
  861. rxon_assoc.flags = priv->staging_rxon.flags;
  862. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  863. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  864. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  865. rxon_assoc.reserved = 0;
  866. rc = iwl3945_send_cmd_sync(priv, &cmd);
  867. if (rc)
  868. return rc;
  869. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  870. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  871. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  872. rc = -EIO;
  873. }
  874. priv->alloc_rxb_skb--;
  875. dev_kfree_skb_any(cmd.meta.u.skb);
  876. return rc;
  877. }
  878. /**
  879. * iwl3945_commit_rxon - commit staging_rxon to hardware
  880. *
  881. * The RXON command in staging_rxon is committed to the hardware and
  882. * the active_rxon structure is updated with the new data. This
  883. * function correctly transitions out of the RXON_ASSOC_MSK state if
  884. * a HW tune is required based on the RXON structure changes.
  885. */
  886. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  887. {
  888. /* cast away the const for active_rxon in this function */
  889. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  890. int rc = 0;
  891. DECLARE_MAC_BUF(mac);
  892. if (!iwl3945_is_alive(priv))
  893. return -1;
  894. /* always get timestamp with Rx frame */
  895. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  896. /* select antenna */
  897. priv->staging_rxon.flags &=
  898. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  899. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  900. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  901. if (rc) {
  902. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  903. return -EINVAL;
  904. }
  905. /* If we don't need to send a full RXON, we can use
  906. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  907. * and other flags for the current radio configuration. */
  908. if (!iwl3945_full_rxon_required(priv)) {
  909. rc = iwl3945_send_rxon_assoc(priv);
  910. if (rc) {
  911. IWL_ERROR("Error setting RXON_ASSOC "
  912. "configuration (%d).\n", rc);
  913. return rc;
  914. }
  915. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  916. return 0;
  917. }
  918. /* If we are currently associated and the new config requires
  919. * an RXON_ASSOC and the new config wants the associated mask enabled,
  920. * we must clear the associated from the active configuration
  921. * before we apply the new config */
  922. if (iwl3945_is_associated(priv) &&
  923. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  924. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  925. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  926. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  927. sizeof(struct iwl3945_rxon_cmd),
  928. &priv->active_rxon);
  929. /* If the mask clearing failed then we set
  930. * active_rxon back to what it was previously */
  931. if (rc) {
  932. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  933. IWL_ERROR("Error clearing ASSOC_MSK on current "
  934. "configuration (%d).\n", rc);
  935. return rc;
  936. }
  937. }
  938. IWL_DEBUG_INFO("Sending RXON\n"
  939. "* with%s RXON_FILTER_ASSOC_MSK\n"
  940. "* channel = %d\n"
  941. "* bssid = %s\n",
  942. ((priv->staging_rxon.filter_flags &
  943. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  944. le16_to_cpu(priv->staging_rxon.channel),
  945. print_mac(mac, priv->staging_rxon.bssid_addr));
  946. /* Apply the new configuration */
  947. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  948. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  949. if (rc) {
  950. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  951. return rc;
  952. }
  953. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  954. iwl3945_clear_stations_table(priv);
  955. /* If we issue a new RXON command which required a tune then we must
  956. * send a new TXPOWER command or we won't be able to Tx any frames */
  957. rc = iwl3945_hw_reg_send_txpower(priv);
  958. if (rc) {
  959. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  960. return rc;
  961. }
  962. /* Add the broadcast address so we can send broadcast frames */
  963. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  964. IWL_INVALID_STATION) {
  965. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  966. return -EIO;
  967. }
  968. /* If we have set the ASSOC_MSK and we are in BSS mode then
  969. * add the IWL_AP_ID to the station rate table */
  970. if (iwl3945_is_associated(priv) &&
  971. (priv->iw_mode == NL80211_IFTYPE_STATION))
  972. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  973. == IWL_INVALID_STATION) {
  974. IWL_ERROR("Error adding AP address for transmit.\n");
  975. return -EIO;
  976. }
  977. /* Init the hardware's rate fallback order based on the band */
  978. rc = iwl3945_init_hw_rate_table(priv);
  979. if (rc) {
  980. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  981. return -EIO;
  982. }
  983. return 0;
  984. }
  985. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  986. {
  987. struct iwl3945_bt_cmd bt_cmd = {
  988. .flags = 3,
  989. .lead_time = 0xAA,
  990. .max_kill = 1,
  991. .kill_ack_mask = 0,
  992. .kill_cts_mask = 0,
  993. };
  994. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  995. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  996. }
  997. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  998. {
  999. int rc = 0;
  1000. struct iwl3945_rx_packet *res;
  1001. struct iwl3945_host_cmd cmd = {
  1002. .id = REPLY_SCAN_ABORT_CMD,
  1003. .meta.flags = CMD_WANT_SKB,
  1004. };
  1005. /* If there isn't a scan actively going on in the hardware
  1006. * then we are in between scan bands and not actually
  1007. * actively scanning, so don't send the abort command */
  1008. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1009. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1010. return 0;
  1011. }
  1012. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1013. if (rc) {
  1014. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1015. return rc;
  1016. }
  1017. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1018. if (res->u.status != CAN_ABORT_STATUS) {
  1019. /* The scan abort will return 1 for success or
  1020. * 2 for "failure". A failure condition can be
  1021. * due to simply not being in an active scan which
  1022. * can occur if we send the scan abort before we
  1023. * the microcode has notified us that a scan is
  1024. * completed. */
  1025. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1026. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1027. clear_bit(STATUS_SCAN_HW, &priv->status);
  1028. }
  1029. dev_kfree_skb_any(cmd.meta.u.skb);
  1030. return rc;
  1031. }
  1032. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1033. struct iwl3945_cmd *cmd,
  1034. struct sk_buff *skb)
  1035. {
  1036. return 1;
  1037. }
  1038. /*
  1039. * CARD_STATE_CMD
  1040. *
  1041. * Use: Sets the device's internal card state to enable, disable, or halt
  1042. *
  1043. * When in the 'enable' state the card operates as normal.
  1044. * When in the 'disable' state, the card enters into a low power mode.
  1045. * When in the 'halt' state, the card is shut down and must be fully
  1046. * restarted to come back on.
  1047. */
  1048. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1049. {
  1050. struct iwl3945_host_cmd cmd = {
  1051. .id = REPLY_CARD_STATE_CMD,
  1052. .len = sizeof(u32),
  1053. .data = &flags,
  1054. .meta.flags = meta_flag,
  1055. };
  1056. if (meta_flag & CMD_ASYNC)
  1057. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1058. return iwl3945_send_cmd(priv, &cmd);
  1059. }
  1060. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1061. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1062. {
  1063. struct iwl3945_rx_packet *res = NULL;
  1064. if (!skb) {
  1065. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1066. return 1;
  1067. }
  1068. res = (struct iwl3945_rx_packet *)skb->data;
  1069. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1070. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1071. res->hdr.flags);
  1072. return 1;
  1073. }
  1074. switch (res->u.add_sta.status) {
  1075. case ADD_STA_SUCCESS_MSK:
  1076. break;
  1077. default:
  1078. break;
  1079. }
  1080. /* We didn't cache the SKB; let the caller free it */
  1081. return 1;
  1082. }
  1083. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1084. struct iwl3945_addsta_cmd *sta, u8 flags)
  1085. {
  1086. struct iwl3945_rx_packet *res = NULL;
  1087. int rc = 0;
  1088. struct iwl3945_host_cmd cmd = {
  1089. .id = REPLY_ADD_STA,
  1090. .len = sizeof(struct iwl3945_addsta_cmd),
  1091. .meta.flags = flags,
  1092. .data = sta,
  1093. };
  1094. if (flags & CMD_ASYNC)
  1095. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1096. else
  1097. cmd.meta.flags |= CMD_WANT_SKB;
  1098. rc = iwl3945_send_cmd(priv, &cmd);
  1099. if (rc || (flags & CMD_ASYNC))
  1100. return rc;
  1101. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1102. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1103. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1104. res->hdr.flags);
  1105. rc = -EIO;
  1106. }
  1107. if (rc == 0) {
  1108. switch (res->u.add_sta.status) {
  1109. case ADD_STA_SUCCESS_MSK:
  1110. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1111. break;
  1112. default:
  1113. rc = -EIO;
  1114. IWL_WARNING("REPLY_ADD_STA failed\n");
  1115. break;
  1116. }
  1117. }
  1118. priv->alloc_rxb_skb--;
  1119. dev_kfree_skb_any(cmd.meta.u.skb);
  1120. return rc;
  1121. }
  1122. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1123. struct ieee80211_key_conf *keyconf,
  1124. u8 sta_id)
  1125. {
  1126. unsigned long flags;
  1127. __le16 key_flags = 0;
  1128. switch (keyconf->alg) {
  1129. case ALG_CCMP:
  1130. key_flags |= STA_KEY_FLG_CCMP;
  1131. key_flags |= cpu_to_le16(
  1132. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1133. key_flags &= ~STA_KEY_FLG_INVALID;
  1134. break;
  1135. case ALG_TKIP:
  1136. case ALG_WEP:
  1137. default:
  1138. return -EINVAL;
  1139. }
  1140. spin_lock_irqsave(&priv->sta_lock, flags);
  1141. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1142. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1143. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1144. keyconf->keylen);
  1145. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1146. keyconf->keylen);
  1147. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1148. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1149. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1150. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1151. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1152. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1153. return 0;
  1154. }
  1155. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1156. {
  1157. unsigned long flags;
  1158. spin_lock_irqsave(&priv->sta_lock, flags);
  1159. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1160. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1161. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1162. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1163. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1164. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1165. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1166. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1167. return 0;
  1168. }
  1169. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1170. {
  1171. struct list_head *element;
  1172. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1173. priv->frames_count);
  1174. while (!list_empty(&priv->free_frames)) {
  1175. element = priv->free_frames.next;
  1176. list_del(element);
  1177. kfree(list_entry(element, struct iwl3945_frame, list));
  1178. priv->frames_count--;
  1179. }
  1180. if (priv->frames_count) {
  1181. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1182. priv->frames_count);
  1183. priv->frames_count = 0;
  1184. }
  1185. }
  1186. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1187. {
  1188. struct iwl3945_frame *frame;
  1189. struct list_head *element;
  1190. if (list_empty(&priv->free_frames)) {
  1191. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1192. if (!frame) {
  1193. IWL_ERROR("Could not allocate frame!\n");
  1194. return NULL;
  1195. }
  1196. priv->frames_count++;
  1197. return frame;
  1198. }
  1199. element = priv->free_frames.next;
  1200. list_del(element);
  1201. return list_entry(element, struct iwl3945_frame, list);
  1202. }
  1203. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1204. {
  1205. memset(frame, 0, sizeof(*frame));
  1206. list_add(&frame->list, &priv->free_frames);
  1207. }
  1208. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1209. struct ieee80211_hdr *hdr,
  1210. const u8 *dest, int left)
  1211. {
  1212. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1213. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1214. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1215. return 0;
  1216. if (priv->ibss_beacon->len > left)
  1217. return 0;
  1218. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1219. return priv->ibss_beacon->len;
  1220. }
  1221. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1222. {
  1223. u8 i;
  1224. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1225. i = iwl3945_rates[i].next_ieee) {
  1226. if (rate_mask & (1 << i))
  1227. return iwl3945_rates[i].plcp;
  1228. }
  1229. return IWL_RATE_INVALID;
  1230. }
  1231. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1232. {
  1233. struct iwl3945_frame *frame;
  1234. unsigned int frame_size;
  1235. int rc;
  1236. u8 rate;
  1237. frame = iwl3945_get_free_frame(priv);
  1238. if (!frame) {
  1239. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1240. "command.\n");
  1241. return -ENOMEM;
  1242. }
  1243. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1244. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1245. 0xFF0);
  1246. if (rate == IWL_INVALID_RATE)
  1247. rate = IWL_RATE_6M_PLCP;
  1248. } else {
  1249. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1250. if (rate == IWL_INVALID_RATE)
  1251. rate = IWL_RATE_1M_PLCP;
  1252. }
  1253. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1254. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1255. &frame->u.cmd[0]);
  1256. iwl3945_free_frame(priv, frame);
  1257. return rc;
  1258. }
  1259. /******************************************************************************
  1260. *
  1261. * EEPROM related functions
  1262. *
  1263. ******************************************************************************/
  1264. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1265. {
  1266. memcpy(mac, priv->eeprom.mac_address, 6);
  1267. }
  1268. /*
  1269. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1270. * embedded controller) as EEPROM reader; each read is a series of pulses
  1271. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1272. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1273. * simply claims ownership, which should be safe when this function is called
  1274. * (i.e. before loading uCode!).
  1275. */
  1276. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1277. {
  1278. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1279. return 0;
  1280. }
  1281. /**
  1282. * iwl3945_eeprom_init - read EEPROM contents
  1283. *
  1284. * Load the EEPROM contents from adapter into priv->eeprom
  1285. *
  1286. * NOTE: This routine uses the non-debug IO access functions.
  1287. */
  1288. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1289. {
  1290. u16 *e = (u16 *)&priv->eeprom;
  1291. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1292. u32 r;
  1293. int sz = sizeof(priv->eeprom);
  1294. int rc;
  1295. int i;
  1296. u16 addr;
  1297. /* The EEPROM structure has several padding buffers within it
  1298. * and when adding new EEPROM maps is subject to programmer errors
  1299. * which may be very difficult to identify without explicitly
  1300. * checking the resulting size of the eeprom map. */
  1301. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1302. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1303. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1304. return -ENOENT;
  1305. }
  1306. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1307. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1308. if (rc < 0) {
  1309. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1310. return -ENOENT;
  1311. }
  1312. /* eeprom is an array of 16bit values */
  1313. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1314. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1315. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1316. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1317. i += IWL_EEPROM_ACCESS_DELAY) {
  1318. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1319. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1320. break;
  1321. udelay(IWL_EEPROM_ACCESS_DELAY);
  1322. }
  1323. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1324. IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
  1325. return -ETIMEDOUT;
  1326. }
  1327. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1328. }
  1329. return 0;
  1330. }
  1331. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1332. {
  1333. if (priv->hw_setting.shared_virt)
  1334. pci_free_consistent(priv->pci_dev,
  1335. sizeof(struct iwl3945_shared),
  1336. priv->hw_setting.shared_virt,
  1337. priv->hw_setting.shared_phys);
  1338. }
  1339. /**
  1340. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1341. *
  1342. * return : set the bit for each supported rate insert in ie
  1343. */
  1344. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1345. u16 basic_rate, int *left)
  1346. {
  1347. u16 ret_rates = 0, bit;
  1348. int i;
  1349. u8 *cnt = ie;
  1350. u8 *rates = ie + 1;
  1351. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1352. if (bit & supported_rate) {
  1353. ret_rates |= bit;
  1354. rates[*cnt] = iwl3945_rates[i].ieee |
  1355. ((bit & basic_rate) ? 0x80 : 0x00);
  1356. (*cnt)++;
  1357. (*left)--;
  1358. if ((*left <= 0) ||
  1359. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1360. break;
  1361. }
  1362. }
  1363. return ret_rates;
  1364. }
  1365. /**
  1366. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1367. */
  1368. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1369. struct ieee80211_mgmt *frame,
  1370. int left, int is_direct)
  1371. {
  1372. int len = 0;
  1373. u8 *pos = NULL;
  1374. u16 active_rates, ret_rates, cck_rates;
  1375. /* Make sure there is enough space for the probe request,
  1376. * two mandatory IEs and the data */
  1377. left -= 24;
  1378. if (left < 0)
  1379. return 0;
  1380. len += 24;
  1381. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1382. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1383. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1384. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1385. frame->seq_ctrl = 0;
  1386. /* fill in our indirect SSID IE */
  1387. /* ...next IE... */
  1388. left -= 2;
  1389. if (left < 0)
  1390. return 0;
  1391. len += 2;
  1392. pos = &(frame->u.probe_req.variable[0]);
  1393. *pos++ = WLAN_EID_SSID;
  1394. *pos++ = 0;
  1395. /* fill in our direct SSID IE... */
  1396. if (is_direct) {
  1397. /* ...next IE... */
  1398. left -= 2 + priv->essid_len;
  1399. if (left < 0)
  1400. return 0;
  1401. /* ... fill it in... */
  1402. *pos++ = WLAN_EID_SSID;
  1403. *pos++ = priv->essid_len;
  1404. memcpy(pos, priv->essid, priv->essid_len);
  1405. pos += priv->essid_len;
  1406. len += 2 + priv->essid_len;
  1407. }
  1408. /* fill in supported rate */
  1409. /* ...next IE... */
  1410. left -= 2;
  1411. if (left < 0)
  1412. return 0;
  1413. /* ... fill it in... */
  1414. *pos++ = WLAN_EID_SUPP_RATES;
  1415. *pos = 0;
  1416. priv->active_rate = priv->rates_mask;
  1417. active_rates = priv->active_rate;
  1418. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1419. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1420. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1421. priv->active_rate_basic, &left);
  1422. active_rates &= ~ret_rates;
  1423. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1424. priv->active_rate_basic, &left);
  1425. active_rates &= ~ret_rates;
  1426. len += 2 + *pos;
  1427. pos += (*pos) + 1;
  1428. if (active_rates == 0)
  1429. goto fill_end;
  1430. /* fill in supported extended rate */
  1431. /* ...next IE... */
  1432. left -= 2;
  1433. if (left < 0)
  1434. return 0;
  1435. /* ... fill it in... */
  1436. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1437. *pos = 0;
  1438. iwl3945_supported_rate_to_ie(pos, active_rates,
  1439. priv->active_rate_basic, &left);
  1440. if (*pos > 0)
  1441. len += 2 + *pos;
  1442. fill_end:
  1443. return (u16)len;
  1444. }
  1445. /*
  1446. * QoS support
  1447. */
  1448. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1449. struct iwl3945_qosparam_cmd *qos)
  1450. {
  1451. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1452. sizeof(struct iwl3945_qosparam_cmd), qos);
  1453. }
  1454. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1455. {
  1456. u16 cw_min = 15;
  1457. u16 cw_max = 1023;
  1458. u8 aifs = 2;
  1459. u8 is_legacy = 0;
  1460. unsigned long flags;
  1461. int i;
  1462. spin_lock_irqsave(&priv->lock, flags);
  1463. priv->qos_data.qos_active = 0;
  1464. if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
  1465. if (priv->qos_data.qos_enable)
  1466. priv->qos_data.qos_active = 1;
  1467. if (!(priv->active_rate & 0xfff0)) {
  1468. cw_min = 31;
  1469. is_legacy = 1;
  1470. }
  1471. } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1472. if (priv->qos_data.qos_enable)
  1473. priv->qos_data.qos_active = 1;
  1474. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1475. cw_min = 31;
  1476. is_legacy = 1;
  1477. }
  1478. if (priv->qos_data.qos_active)
  1479. aifs = 3;
  1480. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1481. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1482. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1483. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1484. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1485. if (priv->qos_data.qos_active) {
  1486. i = 1;
  1487. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1488. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1489. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1490. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1491. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1492. i = 2;
  1493. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1494. cpu_to_le16((cw_min + 1) / 2 - 1);
  1495. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1496. cpu_to_le16(cw_max);
  1497. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1498. if (is_legacy)
  1499. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1500. cpu_to_le16(6016);
  1501. else
  1502. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1503. cpu_to_le16(3008);
  1504. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1505. i = 3;
  1506. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1507. cpu_to_le16((cw_min + 1) / 4 - 1);
  1508. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1509. cpu_to_le16((cw_max + 1) / 2 - 1);
  1510. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1511. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1512. if (is_legacy)
  1513. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1514. cpu_to_le16(3264);
  1515. else
  1516. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1517. cpu_to_le16(1504);
  1518. } else {
  1519. for (i = 1; i < 4; i++) {
  1520. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1521. cpu_to_le16(cw_min);
  1522. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1523. cpu_to_le16(cw_max);
  1524. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1525. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1526. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1527. }
  1528. }
  1529. IWL_DEBUG_QOS("set QoS to default \n");
  1530. spin_unlock_irqrestore(&priv->lock, flags);
  1531. }
  1532. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1533. {
  1534. unsigned long flags;
  1535. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1536. return;
  1537. if (!priv->qos_data.qos_enable)
  1538. return;
  1539. spin_lock_irqsave(&priv->lock, flags);
  1540. priv->qos_data.def_qos_parm.qos_flags = 0;
  1541. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1542. !priv->qos_data.qos_cap.q_AP.txop_request)
  1543. priv->qos_data.def_qos_parm.qos_flags |=
  1544. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1545. if (priv->qos_data.qos_active)
  1546. priv->qos_data.def_qos_parm.qos_flags |=
  1547. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1548. spin_unlock_irqrestore(&priv->lock, flags);
  1549. if (force || iwl3945_is_associated(priv)) {
  1550. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1551. priv->qos_data.qos_active);
  1552. iwl3945_send_qos_params_command(priv,
  1553. &(priv->qos_data.def_qos_parm));
  1554. }
  1555. }
  1556. /*
  1557. * Power management (not Tx power!) functions
  1558. */
  1559. #define MSEC_TO_USEC 1024
  1560. #define NOSLP __constant_cpu_to_le32(0)
  1561. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1562. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1563. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1564. __constant_cpu_to_le32(X1), \
  1565. __constant_cpu_to_le32(X2), \
  1566. __constant_cpu_to_le32(X3), \
  1567. __constant_cpu_to_le32(X4)}
  1568. /* default power management (not Tx power) table values */
  1569. /* for tim 0-10 */
  1570. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1571. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1572. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1573. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1574. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1575. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1576. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1577. };
  1578. /* for tim > 10 */
  1579. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1580. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1581. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1582. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1583. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1584. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1585. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1586. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1587. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1588. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1589. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1590. };
  1591. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1592. {
  1593. int rc = 0, i;
  1594. struct iwl3945_power_mgr *pow_data;
  1595. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1596. u16 pci_pm;
  1597. IWL_DEBUG_POWER("Initialize power \n");
  1598. pow_data = &(priv->power_data);
  1599. memset(pow_data, 0, sizeof(*pow_data));
  1600. pow_data->active_index = IWL_POWER_RANGE_0;
  1601. pow_data->dtim_val = 0xffff;
  1602. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1603. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1604. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1605. if (rc != 0)
  1606. return 0;
  1607. else {
  1608. struct iwl3945_powertable_cmd *cmd;
  1609. IWL_DEBUG_POWER("adjust power command flags\n");
  1610. for (i = 0; i < IWL_POWER_AC; i++) {
  1611. cmd = &pow_data->pwr_range_0[i].cmd;
  1612. if (pci_pm & 0x1)
  1613. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1614. else
  1615. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1616. }
  1617. }
  1618. return rc;
  1619. }
  1620. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1621. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1622. {
  1623. int rc = 0, i;
  1624. u8 skip;
  1625. u32 max_sleep = 0;
  1626. struct iwl3945_power_vec_entry *range;
  1627. u8 period = 0;
  1628. struct iwl3945_power_mgr *pow_data;
  1629. if (mode > IWL_POWER_INDEX_5) {
  1630. IWL_DEBUG_POWER("Error invalid power mode \n");
  1631. return -1;
  1632. }
  1633. pow_data = &(priv->power_data);
  1634. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1635. range = &pow_data->pwr_range_0[0];
  1636. else
  1637. range = &pow_data->pwr_range_1[1];
  1638. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1639. #ifdef IWL_MAC80211_DISABLE
  1640. if (priv->assoc_network != NULL) {
  1641. unsigned long flags;
  1642. period = priv->assoc_network->tim.tim_period;
  1643. }
  1644. #endif /*IWL_MAC80211_DISABLE */
  1645. skip = range[mode].no_dtim;
  1646. if (period == 0) {
  1647. period = 1;
  1648. skip = 0;
  1649. }
  1650. if (skip == 0) {
  1651. max_sleep = period;
  1652. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1653. } else {
  1654. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1655. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1656. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1657. }
  1658. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1659. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1660. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1661. }
  1662. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1663. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1664. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1665. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1666. le32_to_cpu(cmd->sleep_interval[0]),
  1667. le32_to_cpu(cmd->sleep_interval[1]),
  1668. le32_to_cpu(cmd->sleep_interval[2]),
  1669. le32_to_cpu(cmd->sleep_interval[3]),
  1670. le32_to_cpu(cmd->sleep_interval[4]));
  1671. return rc;
  1672. }
  1673. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1674. {
  1675. u32 uninitialized_var(final_mode);
  1676. int rc;
  1677. struct iwl3945_powertable_cmd cmd;
  1678. /* If on battery, set to 3,
  1679. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1680. * else user level */
  1681. switch (mode) {
  1682. case IWL_POWER_BATTERY:
  1683. final_mode = IWL_POWER_INDEX_3;
  1684. break;
  1685. case IWL_POWER_AC:
  1686. final_mode = IWL_POWER_MODE_CAM;
  1687. break;
  1688. default:
  1689. final_mode = mode;
  1690. break;
  1691. }
  1692. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1693. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1694. if (final_mode == IWL_POWER_MODE_CAM)
  1695. clear_bit(STATUS_POWER_PMI, &priv->status);
  1696. else
  1697. set_bit(STATUS_POWER_PMI, &priv->status);
  1698. return rc;
  1699. }
  1700. /**
  1701. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1702. *
  1703. * NOTE: priv->mutex is not required before calling this function
  1704. */
  1705. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1706. {
  1707. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1708. clear_bit(STATUS_SCANNING, &priv->status);
  1709. return 0;
  1710. }
  1711. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1712. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1713. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1714. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1715. queue_work(priv->workqueue, &priv->abort_scan);
  1716. } else
  1717. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1718. return test_bit(STATUS_SCANNING, &priv->status);
  1719. }
  1720. return 0;
  1721. }
  1722. /**
  1723. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1724. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1725. *
  1726. * NOTE: priv->mutex must be held before calling this function
  1727. */
  1728. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1729. {
  1730. unsigned long now = jiffies;
  1731. int ret;
  1732. ret = iwl3945_scan_cancel(priv);
  1733. if (ret && ms) {
  1734. mutex_unlock(&priv->mutex);
  1735. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1736. test_bit(STATUS_SCANNING, &priv->status))
  1737. msleep(1);
  1738. mutex_lock(&priv->mutex);
  1739. return test_bit(STATUS_SCANNING, &priv->status);
  1740. }
  1741. return ret;
  1742. }
  1743. #define MAX_UCODE_BEACON_INTERVAL 1024
  1744. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1745. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1746. {
  1747. u16 new_val = 0;
  1748. u16 beacon_factor = 0;
  1749. beacon_factor =
  1750. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1751. / MAX_UCODE_BEACON_INTERVAL;
  1752. new_val = beacon_val / beacon_factor;
  1753. return cpu_to_le16(new_val);
  1754. }
  1755. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1756. {
  1757. u64 interval_tm_unit;
  1758. u64 tsf, result;
  1759. unsigned long flags;
  1760. struct ieee80211_conf *conf = NULL;
  1761. u16 beacon_int = 0;
  1762. conf = ieee80211_get_hw_conf(priv->hw);
  1763. spin_lock_irqsave(&priv->lock, flags);
  1764. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1765. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1766. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1767. tsf = priv->timestamp1;
  1768. tsf = ((tsf << 32) | priv->timestamp0);
  1769. beacon_int = priv->beacon_int;
  1770. spin_unlock_irqrestore(&priv->lock, flags);
  1771. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1772. if (beacon_int == 0) {
  1773. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1774. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1775. } else {
  1776. priv->rxon_timing.beacon_interval =
  1777. cpu_to_le16(beacon_int);
  1778. priv->rxon_timing.beacon_interval =
  1779. iwl3945_adjust_beacon_interval(
  1780. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1781. }
  1782. priv->rxon_timing.atim_window = 0;
  1783. } else {
  1784. priv->rxon_timing.beacon_interval =
  1785. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1786. /* TODO: we need to get atim_window from upper stack
  1787. * for now we set to 0 */
  1788. priv->rxon_timing.atim_window = 0;
  1789. }
  1790. interval_tm_unit =
  1791. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1792. result = do_div(tsf, interval_tm_unit);
  1793. priv->rxon_timing.beacon_init_val =
  1794. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1795. IWL_DEBUG_ASSOC
  1796. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1797. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1798. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1799. le16_to_cpu(priv->rxon_timing.atim_window));
  1800. }
  1801. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1802. {
  1803. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1804. IWL_ERROR("APs don't scan.\n");
  1805. return 0;
  1806. }
  1807. if (!iwl3945_is_ready_rf(priv)) {
  1808. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1809. return -EIO;
  1810. }
  1811. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1812. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1813. return -EAGAIN;
  1814. }
  1815. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1816. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1817. "Queuing.\n");
  1818. return -EAGAIN;
  1819. }
  1820. IWL_DEBUG_INFO("Starting scan...\n");
  1821. if (priv->cfg->sku & IWL_SKU_G)
  1822. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1823. if (priv->cfg->sku & IWL_SKU_A)
  1824. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1825. set_bit(STATUS_SCANNING, &priv->status);
  1826. priv->scan_start = jiffies;
  1827. priv->scan_pass_start = priv->scan_start;
  1828. queue_work(priv->workqueue, &priv->request_scan);
  1829. return 0;
  1830. }
  1831. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1832. {
  1833. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1834. if (hw_decrypt)
  1835. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1836. else
  1837. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1838. return 0;
  1839. }
  1840. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1841. enum ieee80211_band band)
  1842. {
  1843. if (band == IEEE80211_BAND_5GHZ) {
  1844. priv->staging_rxon.flags &=
  1845. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1846. | RXON_FLG_CCK_MSK);
  1847. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1848. } else {
  1849. /* Copied from iwl3945_bg_post_associate() */
  1850. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1851. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1852. else
  1853. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1854. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1855. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1856. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1857. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1858. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1859. }
  1860. }
  1861. /*
  1862. * initialize rxon structure with default values from eeprom
  1863. */
  1864. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1865. {
  1866. const struct iwl3945_channel_info *ch_info;
  1867. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1868. switch (priv->iw_mode) {
  1869. case NL80211_IFTYPE_AP:
  1870. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1871. break;
  1872. case NL80211_IFTYPE_STATION:
  1873. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1874. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1875. break;
  1876. case NL80211_IFTYPE_ADHOC:
  1877. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1878. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1879. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1880. RXON_FILTER_ACCEPT_GRP_MSK;
  1881. break;
  1882. case NL80211_IFTYPE_MONITOR:
  1883. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1884. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1885. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1886. break;
  1887. default:
  1888. IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
  1889. break;
  1890. }
  1891. #if 0
  1892. /* TODO: Figure out when short_preamble would be set and cache from
  1893. * that */
  1894. if (!hw_to_local(priv->hw)->short_preamble)
  1895. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1896. else
  1897. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1898. #endif
  1899. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1900. le16_to_cpu(priv->active_rxon.channel));
  1901. if (!ch_info)
  1902. ch_info = &priv->channel_info[0];
  1903. /*
  1904. * in some case A channels are all non IBSS
  1905. * in this case force B/G channel
  1906. */
  1907. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1908. !(is_channel_ibss(ch_info)))
  1909. ch_info = &priv->channel_info[0];
  1910. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1911. if (is_channel_a_band(ch_info))
  1912. priv->band = IEEE80211_BAND_5GHZ;
  1913. else
  1914. priv->band = IEEE80211_BAND_2GHZ;
  1915. iwl3945_set_flags_for_phymode(priv, priv->band);
  1916. priv->staging_rxon.ofdm_basic_rates =
  1917. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1918. priv->staging_rxon.cck_basic_rates =
  1919. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1920. }
  1921. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1922. {
  1923. if (mode == NL80211_IFTYPE_ADHOC) {
  1924. const struct iwl3945_channel_info *ch_info;
  1925. ch_info = iwl3945_get_channel_info(priv,
  1926. priv->band,
  1927. le16_to_cpu(priv->staging_rxon.channel));
  1928. if (!ch_info || !is_channel_ibss(ch_info)) {
  1929. IWL_ERROR("channel %d not IBSS channel\n",
  1930. le16_to_cpu(priv->staging_rxon.channel));
  1931. return -EINVAL;
  1932. }
  1933. }
  1934. priv->iw_mode = mode;
  1935. iwl3945_connection_init_rx_config(priv);
  1936. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1937. iwl3945_clear_stations_table(priv);
  1938. /* dont commit rxon if rf-kill is on*/
  1939. if (!iwl3945_is_ready_rf(priv))
  1940. return -EAGAIN;
  1941. cancel_delayed_work(&priv->scan_check);
  1942. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1943. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1944. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1945. return -EAGAIN;
  1946. }
  1947. iwl3945_commit_rxon(priv);
  1948. return 0;
  1949. }
  1950. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1951. struct ieee80211_tx_info *info,
  1952. struct iwl3945_cmd *cmd,
  1953. struct sk_buff *skb_frag,
  1954. int last_frag)
  1955. {
  1956. struct iwl3945_hw_key *keyinfo =
  1957. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1958. switch (keyinfo->alg) {
  1959. case ALG_CCMP:
  1960. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1961. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1962. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  1963. break;
  1964. case ALG_TKIP:
  1965. #if 0
  1966. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1967. if (last_frag)
  1968. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1969. 8);
  1970. else
  1971. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1972. #endif
  1973. break;
  1974. case ALG_WEP:
  1975. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1976. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1977. if (keyinfo->keylen == 13)
  1978. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1979. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1980. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1981. "with key %d\n", info->control.hw_key->hw_key_idx);
  1982. break;
  1983. default:
  1984. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  1985. break;
  1986. }
  1987. }
  1988. /*
  1989. * handle build REPLY_TX command notification.
  1990. */
  1991. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  1992. struct iwl3945_cmd *cmd,
  1993. struct ieee80211_tx_info *info,
  1994. struct ieee80211_hdr *hdr,
  1995. int is_unicast, u8 std_id)
  1996. {
  1997. __le16 fc = hdr->frame_control;
  1998. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1999. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2000. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  2001. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2002. if (ieee80211_is_mgmt(fc))
  2003. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2004. if (ieee80211_is_probe_resp(fc) &&
  2005. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2006. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2007. } else {
  2008. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2009. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2010. }
  2011. cmd->cmd.tx.sta_id = std_id;
  2012. if (ieee80211_has_morefrags(fc))
  2013. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2014. if (ieee80211_is_data_qos(fc)) {
  2015. u8 *qc = ieee80211_get_qos_ctl(hdr);
  2016. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  2017. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2018. } else {
  2019. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2020. }
  2021. if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
  2022. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2023. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2024. } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
  2025. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2026. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2027. }
  2028. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2029. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2030. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2031. if (ieee80211_is_mgmt(fc)) {
  2032. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  2033. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2034. else
  2035. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2036. } else {
  2037. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2038. #ifdef CONFIG_IWL3945_LEDS
  2039. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  2040. #endif
  2041. }
  2042. cmd->cmd.tx.driver_txop = 0;
  2043. cmd->cmd.tx.tx_flags = tx_flags;
  2044. cmd->cmd.tx.next_frame_len = 0;
  2045. }
  2046. /**
  2047. * iwl3945_get_sta_id - Find station's index within station table
  2048. */
  2049. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2050. {
  2051. int sta_id;
  2052. u16 fc = le16_to_cpu(hdr->frame_control);
  2053. /* If this frame is broadcast or management, use broadcast station id */
  2054. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2055. is_multicast_ether_addr(hdr->addr1))
  2056. return priv->hw_setting.bcast_sta_id;
  2057. switch (priv->iw_mode) {
  2058. /* If we are a client station in a BSS network, use the special
  2059. * AP station entry (that's the only station we communicate with) */
  2060. case NL80211_IFTYPE_STATION:
  2061. return IWL_AP_ID;
  2062. /* If we are an AP, then find the station, or use BCAST */
  2063. case NL80211_IFTYPE_AP:
  2064. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2065. if (sta_id != IWL_INVALID_STATION)
  2066. return sta_id;
  2067. return priv->hw_setting.bcast_sta_id;
  2068. /* If this frame is going out to an IBSS network, find the station,
  2069. * or create a new station table entry */
  2070. case NL80211_IFTYPE_ADHOC: {
  2071. DECLARE_MAC_BUF(mac);
  2072. /* Create new station table entry */
  2073. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2074. if (sta_id != IWL_INVALID_STATION)
  2075. return sta_id;
  2076. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2077. if (sta_id != IWL_INVALID_STATION)
  2078. return sta_id;
  2079. IWL_DEBUG_DROP("Station %s not in station map. "
  2080. "Defaulting to broadcast...\n",
  2081. print_mac(mac, hdr->addr1));
  2082. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2083. return priv->hw_setting.bcast_sta_id;
  2084. }
  2085. /* If we are in monitor mode, use BCAST. This is required for
  2086. * packet injection. */
  2087. case NL80211_IFTYPE_MONITOR:
  2088. return priv->hw_setting.bcast_sta_id;
  2089. default:
  2090. IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
  2091. return priv->hw_setting.bcast_sta_id;
  2092. }
  2093. }
  2094. /*
  2095. * start REPLY_TX command process
  2096. */
  2097. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2098. {
  2099. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2100. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2101. struct iwl3945_tfd_frame *tfd;
  2102. u32 *control_flags;
  2103. int txq_id = skb_get_queue_mapping(skb);
  2104. struct iwl3945_tx_queue *txq = NULL;
  2105. struct iwl3945_queue *q = NULL;
  2106. dma_addr_t phys_addr;
  2107. dma_addr_t txcmd_phys;
  2108. struct iwl3945_cmd *out_cmd = NULL;
  2109. u16 len, idx, len_org, hdr_len;
  2110. u8 id;
  2111. u8 unicast;
  2112. u8 sta_id;
  2113. u8 tid = 0;
  2114. u16 seq_number = 0;
  2115. __le16 fc;
  2116. u8 wait_write_ptr = 0;
  2117. u8 *qc = NULL;
  2118. unsigned long flags;
  2119. int rc;
  2120. spin_lock_irqsave(&priv->lock, flags);
  2121. if (iwl3945_is_rfkill(priv)) {
  2122. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2123. goto drop_unlock;
  2124. }
  2125. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2126. IWL_ERROR("ERROR: No TX rate available.\n");
  2127. goto drop_unlock;
  2128. }
  2129. unicast = !is_multicast_ether_addr(hdr->addr1);
  2130. id = 0;
  2131. fc = hdr->frame_control;
  2132. #ifdef CONFIG_IWL3945_DEBUG
  2133. if (ieee80211_is_auth(fc))
  2134. IWL_DEBUG_TX("Sending AUTH frame\n");
  2135. else if (ieee80211_is_assoc_req(fc))
  2136. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2137. else if (ieee80211_is_reassoc_req(fc))
  2138. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2139. #endif
  2140. /* drop all data frame if we are not associated */
  2141. if (ieee80211_is_data(fc) &&
  2142. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  2143. (!iwl3945_is_associated(priv) ||
  2144. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  2145. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2146. goto drop_unlock;
  2147. }
  2148. spin_unlock_irqrestore(&priv->lock, flags);
  2149. hdr_len = ieee80211_hdrlen(fc);
  2150. /* Find (or create) index into station table for destination station */
  2151. sta_id = iwl3945_get_sta_id(priv, hdr);
  2152. if (sta_id == IWL_INVALID_STATION) {
  2153. DECLARE_MAC_BUF(mac);
  2154. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2155. print_mac(mac, hdr->addr1));
  2156. goto drop;
  2157. }
  2158. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2159. if (ieee80211_is_data_qos(fc)) {
  2160. qc = ieee80211_get_qos_ctl(hdr);
  2161. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  2162. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2163. IEEE80211_SCTL_SEQ;
  2164. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2165. (hdr->seq_ctrl &
  2166. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2167. seq_number += 0x10;
  2168. }
  2169. /* Descriptor for chosen Tx queue */
  2170. txq = &priv->txq[txq_id];
  2171. q = &txq->q;
  2172. spin_lock_irqsave(&priv->lock, flags);
  2173. /* Set up first empty TFD within this queue's circular TFD buffer */
  2174. tfd = &txq->bd[q->write_ptr];
  2175. memset(tfd, 0, sizeof(*tfd));
  2176. control_flags = (u32 *) tfd;
  2177. idx = get_cmd_index(q, q->write_ptr, 0);
  2178. /* Set up driver data for this TFD */
  2179. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2180. txq->txb[q->write_ptr].skb[0] = skb;
  2181. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2182. out_cmd = &txq->cmd[idx];
  2183. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2184. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2185. /*
  2186. * Set up the Tx-command (not MAC!) header.
  2187. * Store the chosen Tx queue and TFD index within the sequence field;
  2188. * after Tx, uCode's Tx response will return this value so driver can
  2189. * locate the frame within the tx queue and do post-tx processing.
  2190. */
  2191. out_cmd->hdr.cmd = REPLY_TX;
  2192. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2193. INDEX_TO_SEQ(q->write_ptr)));
  2194. /* Copy MAC header from skb into command buffer */
  2195. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2196. /*
  2197. * Use the first empty entry in this queue's command buffer array
  2198. * to contain the Tx command and MAC header concatenated together
  2199. * (payload data will be in another buffer).
  2200. * Size of this varies, due to varying MAC header length.
  2201. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2202. * of the MAC header (device reads on dword boundaries).
  2203. * We'll tell device about this padding later.
  2204. */
  2205. len = priv->hw_setting.tx_cmd_len +
  2206. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2207. len_org = len;
  2208. len = (len + 3) & ~3;
  2209. if (len_org != len)
  2210. len_org = 1;
  2211. else
  2212. len_org = 0;
  2213. /* Physical address of this Tx command's header (not MAC header!),
  2214. * within command buffer array. */
  2215. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2216. offsetof(struct iwl3945_cmd, hdr);
  2217. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2218. * first entry */
  2219. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2220. if (info->control.hw_key)
  2221. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2222. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2223. * if any (802.11 null frames have no payload). */
  2224. len = skb->len - hdr_len;
  2225. if (len) {
  2226. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2227. len, PCI_DMA_TODEVICE);
  2228. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2229. }
  2230. if (!len)
  2231. /* If there is no payload, then we use only one Tx buffer */
  2232. *control_flags = TFD_CTL_COUNT_SET(1);
  2233. else
  2234. /* Else use 2 buffers.
  2235. * Tell 3945 about any padding after MAC header */
  2236. *control_flags = TFD_CTL_COUNT_SET(2) |
  2237. TFD_CTL_PAD_SET(U32_PAD(len));
  2238. /* Total # bytes to be transmitted */
  2239. len = (u16)skb->len;
  2240. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2241. /* TODO need this for burst mode later on */
  2242. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2243. /* set is_hcca to 0; it probably will never be implemented */
  2244. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2245. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2246. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2247. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2248. txq->need_update = 1;
  2249. if (qc)
  2250. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2251. } else {
  2252. wait_write_ptr = 1;
  2253. txq->need_update = 0;
  2254. }
  2255. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2256. sizeof(out_cmd->cmd.tx));
  2257. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2258. ieee80211_hdrlen(fc));
  2259. /* Tell device the write index *just past* this latest filled TFD */
  2260. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2261. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2262. spin_unlock_irqrestore(&priv->lock, flags);
  2263. if (rc)
  2264. return rc;
  2265. if ((iwl3945_queue_space(q) < q->high_mark)
  2266. && priv->mac80211_registered) {
  2267. if (wait_write_ptr) {
  2268. spin_lock_irqsave(&priv->lock, flags);
  2269. txq->need_update = 1;
  2270. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2271. spin_unlock_irqrestore(&priv->lock, flags);
  2272. }
  2273. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2274. }
  2275. return 0;
  2276. drop_unlock:
  2277. spin_unlock_irqrestore(&priv->lock, flags);
  2278. drop:
  2279. return -1;
  2280. }
  2281. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2282. {
  2283. const struct ieee80211_supported_band *sband = NULL;
  2284. struct ieee80211_rate *rate;
  2285. int i;
  2286. sband = iwl3945_get_band(priv, priv->band);
  2287. if (!sband) {
  2288. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2289. return;
  2290. }
  2291. priv->active_rate = 0;
  2292. priv->active_rate_basic = 0;
  2293. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2294. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2295. for (i = 0; i < sband->n_bitrates; i++) {
  2296. rate = &sband->bitrates[i];
  2297. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2298. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2299. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2300. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2301. priv->active_rate |= (1 << rate->hw_value);
  2302. }
  2303. }
  2304. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2305. priv->active_rate, priv->active_rate_basic);
  2306. /*
  2307. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2308. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2309. * OFDM
  2310. */
  2311. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2312. priv->staging_rxon.cck_basic_rates =
  2313. ((priv->active_rate_basic &
  2314. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2315. else
  2316. priv->staging_rxon.cck_basic_rates =
  2317. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2318. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2319. priv->staging_rxon.ofdm_basic_rates =
  2320. ((priv->active_rate_basic &
  2321. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2322. IWL_FIRST_OFDM_RATE) & 0xFF;
  2323. else
  2324. priv->staging_rxon.ofdm_basic_rates =
  2325. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2326. }
  2327. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2328. {
  2329. unsigned long flags;
  2330. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2331. return;
  2332. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2333. disable_radio ? "OFF" : "ON");
  2334. if (disable_radio) {
  2335. iwl3945_scan_cancel(priv);
  2336. /* FIXME: This is a workaround for AP */
  2337. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2338. spin_lock_irqsave(&priv->lock, flags);
  2339. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2340. CSR_UCODE_SW_BIT_RFKILL);
  2341. spin_unlock_irqrestore(&priv->lock, flags);
  2342. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2343. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2344. }
  2345. return;
  2346. }
  2347. spin_lock_irqsave(&priv->lock, flags);
  2348. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2349. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2350. spin_unlock_irqrestore(&priv->lock, flags);
  2351. /* wake up ucode */
  2352. msleep(10);
  2353. spin_lock_irqsave(&priv->lock, flags);
  2354. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2355. if (!iwl3945_grab_nic_access(priv))
  2356. iwl3945_release_nic_access(priv);
  2357. spin_unlock_irqrestore(&priv->lock, flags);
  2358. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2359. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2360. "disabled by HW switch\n");
  2361. return;
  2362. }
  2363. if (priv->is_open)
  2364. queue_work(priv->workqueue, &priv->restart);
  2365. return;
  2366. }
  2367. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2368. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2369. {
  2370. u16 fc =
  2371. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2372. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2373. return;
  2374. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2375. return;
  2376. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2377. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2378. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2379. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2380. RX_RES_STATUS_BAD_ICV_MIC)
  2381. stats->flag |= RX_FLAG_MMIC_ERROR;
  2382. case RX_RES_STATUS_SEC_TYPE_WEP:
  2383. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2384. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2385. RX_RES_STATUS_DECRYPT_OK) {
  2386. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2387. stats->flag |= RX_FLAG_DECRYPTED;
  2388. }
  2389. break;
  2390. default:
  2391. break;
  2392. }
  2393. }
  2394. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2395. #include "iwl-spectrum.h"
  2396. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2397. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2398. #define TIME_UNIT 1024
  2399. /*
  2400. * extended beacon time format
  2401. * time in usec will be changed into a 32-bit value in 8:24 format
  2402. * the high 1 byte is the beacon counts
  2403. * the lower 3 bytes is the time in usec within one beacon interval
  2404. */
  2405. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2406. {
  2407. u32 quot;
  2408. u32 rem;
  2409. u32 interval = beacon_interval * 1024;
  2410. if (!interval || !usec)
  2411. return 0;
  2412. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2413. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2414. return (quot << 24) + rem;
  2415. }
  2416. /* base is usually what we get from ucode with each received frame,
  2417. * the same as HW timer counter counting down
  2418. */
  2419. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2420. {
  2421. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2422. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2423. u32 interval = beacon_interval * TIME_UNIT;
  2424. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2425. (addon & BEACON_TIME_MASK_HIGH);
  2426. if (base_low > addon_low)
  2427. res += base_low - addon_low;
  2428. else if (base_low < addon_low) {
  2429. res += interval + base_low - addon_low;
  2430. res += (1 << 24);
  2431. } else
  2432. res += (1 << 24);
  2433. return cpu_to_le32(res);
  2434. }
  2435. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2436. struct ieee80211_measurement_params *params,
  2437. u8 type)
  2438. {
  2439. struct iwl3945_spectrum_cmd spectrum;
  2440. struct iwl3945_rx_packet *res;
  2441. struct iwl3945_host_cmd cmd = {
  2442. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2443. .data = (void *)&spectrum,
  2444. .meta.flags = CMD_WANT_SKB,
  2445. };
  2446. u32 add_time = le64_to_cpu(params->start_time);
  2447. int rc;
  2448. int spectrum_resp_status;
  2449. int duration = le16_to_cpu(params->duration);
  2450. if (iwl3945_is_associated(priv))
  2451. add_time =
  2452. iwl3945_usecs_to_beacons(
  2453. le64_to_cpu(params->start_time) - priv->last_tsf,
  2454. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2455. memset(&spectrum, 0, sizeof(spectrum));
  2456. spectrum.channel_count = cpu_to_le16(1);
  2457. spectrum.flags =
  2458. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2459. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2460. cmd.len = sizeof(spectrum);
  2461. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2462. if (iwl3945_is_associated(priv))
  2463. spectrum.start_time =
  2464. iwl3945_add_beacon_time(priv->last_beacon_time,
  2465. add_time,
  2466. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2467. else
  2468. spectrum.start_time = 0;
  2469. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2470. spectrum.channels[0].channel = params->channel;
  2471. spectrum.channels[0].type = type;
  2472. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2473. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2474. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2475. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2476. if (rc)
  2477. return rc;
  2478. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2479. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2480. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2481. rc = -EIO;
  2482. }
  2483. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2484. switch (spectrum_resp_status) {
  2485. case 0: /* Command will be handled */
  2486. if (res->u.spectrum.id != 0xff) {
  2487. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2488. res->u.spectrum.id);
  2489. priv->measurement_status &= ~MEASUREMENT_READY;
  2490. }
  2491. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2492. rc = 0;
  2493. break;
  2494. case 1: /* Command will not be handled */
  2495. rc = -EAGAIN;
  2496. break;
  2497. }
  2498. dev_kfree_skb_any(cmd.meta.u.skb);
  2499. return rc;
  2500. }
  2501. #endif
  2502. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2503. struct iwl3945_rx_mem_buffer *rxb)
  2504. {
  2505. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2506. struct iwl3945_alive_resp *palive;
  2507. struct delayed_work *pwork;
  2508. palive = &pkt->u.alive_frame;
  2509. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2510. "0x%01X 0x%01X\n",
  2511. palive->is_valid, palive->ver_type,
  2512. palive->ver_subtype);
  2513. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2514. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2515. memcpy(&priv->card_alive_init,
  2516. &pkt->u.alive_frame,
  2517. sizeof(struct iwl3945_init_alive_resp));
  2518. pwork = &priv->init_alive_start;
  2519. } else {
  2520. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2521. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2522. sizeof(struct iwl3945_alive_resp));
  2523. pwork = &priv->alive_start;
  2524. iwl3945_disable_events(priv);
  2525. }
  2526. /* We delay the ALIVE response by 5ms to
  2527. * give the HW RF Kill time to activate... */
  2528. if (palive->is_valid == UCODE_VALID_OK)
  2529. queue_delayed_work(priv->workqueue, pwork,
  2530. msecs_to_jiffies(5));
  2531. else
  2532. IWL_WARNING("uCode did not respond OK.\n");
  2533. }
  2534. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2535. struct iwl3945_rx_mem_buffer *rxb)
  2536. {
  2537. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2538. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2539. return;
  2540. }
  2541. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2542. struct iwl3945_rx_mem_buffer *rxb)
  2543. {
  2544. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2545. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2546. "seq 0x%04X ser 0x%08X\n",
  2547. le32_to_cpu(pkt->u.err_resp.error_type),
  2548. get_cmd_string(pkt->u.err_resp.cmd_id),
  2549. pkt->u.err_resp.cmd_id,
  2550. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2551. le32_to_cpu(pkt->u.err_resp.error_info));
  2552. }
  2553. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2554. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2555. {
  2556. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2557. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2558. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2559. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2560. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2561. rxon->channel = csa->channel;
  2562. priv->staging_rxon.channel = csa->channel;
  2563. }
  2564. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2565. struct iwl3945_rx_mem_buffer *rxb)
  2566. {
  2567. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2568. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2569. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2570. if (!report->state) {
  2571. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2572. "Spectrum Measure Notification: Start\n");
  2573. return;
  2574. }
  2575. memcpy(&priv->measure_report, report, sizeof(*report));
  2576. priv->measurement_status |= MEASUREMENT_READY;
  2577. #endif
  2578. }
  2579. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2580. struct iwl3945_rx_mem_buffer *rxb)
  2581. {
  2582. #ifdef CONFIG_IWL3945_DEBUG
  2583. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2584. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2585. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2586. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2587. #endif
  2588. }
  2589. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2590. struct iwl3945_rx_mem_buffer *rxb)
  2591. {
  2592. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2593. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2594. "notification for %s:\n",
  2595. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2596. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2597. }
  2598. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2599. {
  2600. struct iwl3945_priv *priv =
  2601. container_of(work, struct iwl3945_priv, beacon_update);
  2602. struct sk_buff *beacon;
  2603. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2604. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2605. if (!beacon) {
  2606. IWL_ERROR("update beacon failed\n");
  2607. return;
  2608. }
  2609. mutex_lock(&priv->mutex);
  2610. /* new beacon skb is allocated every time; dispose previous.*/
  2611. if (priv->ibss_beacon)
  2612. dev_kfree_skb(priv->ibss_beacon);
  2613. priv->ibss_beacon = beacon;
  2614. mutex_unlock(&priv->mutex);
  2615. iwl3945_send_beacon_cmd(priv);
  2616. }
  2617. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2618. struct iwl3945_rx_mem_buffer *rxb)
  2619. {
  2620. #ifdef CONFIG_IWL3945_DEBUG
  2621. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2622. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2623. u8 rate = beacon->beacon_notify_hdr.rate;
  2624. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2625. "tsf %d %d rate %d\n",
  2626. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2627. beacon->beacon_notify_hdr.failure_frame,
  2628. le32_to_cpu(beacon->ibss_mgr_status),
  2629. le32_to_cpu(beacon->high_tsf),
  2630. le32_to_cpu(beacon->low_tsf), rate);
  2631. #endif
  2632. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2633. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2634. queue_work(priv->workqueue, &priv->beacon_update);
  2635. }
  2636. /* Service response to REPLY_SCAN_CMD (0x80) */
  2637. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2638. struct iwl3945_rx_mem_buffer *rxb)
  2639. {
  2640. #ifdef CONFIG_IWL3945_DEBUG
  2641. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2642. struct iwl3945_scanreq_notification *notif =
  2643. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2644. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2645. #endif
  2646. }
  2647. /* Service SCAN_START_NOTIFICATION (0x82) */
  2648. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2649. struct iwl3945_rx_mem_buffer *rxb)
  2650. {
  2651. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2652. struct iwl3945_scanstart_notification *notif =
  2653. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2654. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2655. IWL_DEBUG_SCAN("Scan start: "
  2656. "%d [802.11%s] "
  2657. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2658. notif->channel,
  2659. notif->band ? "bg" : "a",
  2660. notif->tsf_high,
  2661. notif->tsf_low, notif->status, notif->beacon_timer);
  2662. }
  2663. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2664. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2665. struct iwl3945_rx_mem_buffer *rxb)
  2666. {
  2667. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2668. struct iwl3945_scanresults_notification *notif =
  2669. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2670. IWL_DEBUG_SCAN("Scan ch.res: "
  2671. "%d [802.11%s] "
  2672. "(TSF: 0x%08X:%08X) - %d "
  2673. "elapsed=%lu usec (%dms since last)\n",
  2674. notif->channel,
  2675. notif->band ? "bg" : "a",
  2676. le32_to_cpu(notif->tsf_high),
  2677. le32_to_cpu(notif->tsf_low),
  2678. le32_to_cpu(notif->statistics[0]),
  2679. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2680. jiffies_to_msecs(elapsed_jiffies
  2681. (priv->last_scan_jiffies, jiffies)));
  2682. priv->last_scan_jiffies = jiffies;
  2683. priv->next_scan_jiffies = 0;
  2684. }
  2685. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2686. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2687. struct iwl3945_rx_mem_buffer *rxb)
  2688. {
  2689. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2690. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2691. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2692. scan_notif->scanned_channels,
  2693. scan_notif->tsf_low,
  2694. scan_notif->tsf_high, scan_notif->status);
  2695. /* The HW is no longer scanning */
  2696. clear_bit(STATUS_SCAN_HW, &priv->status);
  2697. /* The scan completion notification came in, so kill that timer... */
  2698. cancel_delayed_work(&priv->scan_check);
  2699. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2700. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2701. "2.4" : "5.2",
  2702. jiffies_to_msecs(elapsed_jiffies
  2703. (priv->scan_pass_start, jiffies)));
  2704. /* Remove this scanned band from the list of pending
  2705. * bands to scan, band G precedes A in order of scanning
  2706. * as seen in iwl3945_bg_request_scan */
  2707. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2708. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2709. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2710. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2711. /* If a request to abort was given, or the scan did not succeed
  2712. * then we reset the scan state machine and terminate,
  2713. * re-queuing another scan if one has been requested */
  2714. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2715. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2716. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2717. } else {
  2718. /* If there are more bands on this scan pass reschedule */
  2719. if (priv->scan_bands > 0)
  2720. goto reschedule;
  2721. }
  2722. priv->last_scan_jiffies = jiffies;
  2723. priv->next_scan_jiffies = 0;
  2724. IWL_DEBUG_INFO("Setting scan to off\n");
  2725. clear_bit(STATUS_SCANNING, &priv->status);
  2726. IWL_DEBUG_INFO("Scan took %dms\n",
  2727. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2728. queue_work(priv->workqueue, &priv->scan_completed);
  2729. return;
  2730. reschedule:
  2731. priv->scan_pass_start = jiffies;
  2732. queue_work(priv->workqueue, &priv->request_scan);
  2733. }
  2734. /* Handle notification from uCode that card's power state is changing
  2735. * due to software, hardware, or critical temperature RFKILL */
  2736. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2737. struct iwl3945_rx_mem_buffer *rxb)
  2738. {
  2739. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2740. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2741. unsigned long status = priv->status;
  2742. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2743. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2744. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2745. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2746. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2747. if (flags & HW_CARD_DISABLED)
  2748. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2749. else
  2750. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2751. if (flags & SW_CARD_DISABLED)
  2752. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2753. else
  2754. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2755. iwl3945_scan_cancel(priv);
  2756. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2757. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2758. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2759. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2760. queue_work(priv->workqueue, &priv->rf_kill);
  2761. else
  2762. wake_up_interruptible(&priv->wait_command_queue);
  2763. }
  2764. /**
  2765. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2766. *
  2767. * Setup the RX handlers for each of the reply types sent from the uCode
  2768. * to the host.
  2769. *
  2770. * This function chains into the hardware specific files for them to setup
  2771. * any hardware specific handlers as well.
  2772. */
  2773. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2774. {
  2775. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2776. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2777. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2778. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2779. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2780. iwl3945_rx_spectrum_measure_notif;
  2781. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2782. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2783. iwl3945_rx_pm_debug_statistics_notif;
  2784. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2785. /*
  2786. * The same handler is used for both the REPLY to a discrete
  2787. * statistics request from the host as well as for the periodic
  2788. * statistics notifications (after received beacons) from the uCode.
  2789. */
  2790. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2791. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2792. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2793. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2794. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2795. iwl3945_rx_scan_results_notif;
  2796. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2797. iwl3945_rx_scan_complete_notif;
  2798. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2799. /* Set up hardware specific Rx handlers */
  2800. iwl3945_hw_rx_handler_setup(priv);
  2801. }
  2802. /**
  2803. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2804. * When FW advances 'R' index, all entries between old and new 'R' index
  2805. * need to be reclaimed.
  2806. */
  2807. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2808. int txq_id, int index)
  2809. {
  2810. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2811. struct iwl3945_queue *q = &txq->q;
  2812. int nfreed = 0;
  2813. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2814. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2815. "is out of range [0-%d] %d %d.\n", txq_id,
  2816. index, q->n_bd, q->write_ptr, q->read_ptr);
  2817. return;
  2818. }
  2819. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2820. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2821. if (nfreed > 1) {
  2822. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2823. q->write_ptr, q->read_ptr);
  2824. queue_work(priv->workqueue, &priv->restart);
  2825. break;
  2826. }
  2827. nfreed++;
  2828. }
  2829. }
  2830. /**
  2831. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2832. * @rxb: Rx buffer to reclaim
  2833. *
  2834. * If an Rx buffer has an async callback associated with it the callback
  2835. * will be executed. The attached skb (if present) will only be freed
  2836. * if the callback returns 1
  2837. */
  2838. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2839. struct iwl3945_rx_mem_buffer *rxb)
  2840. {
  2841. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2842. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2843. int txq_id = SEQ_TO_QUEUE(sequence);
  2844. int index = SEQ_TO_INDEX(sequence);
  2845. int huge = sequence & SEQ_HUGE_FRAME;
  2846. int cmd_index;
  2847. struct iwl3945_cmd *cmd;
  2848. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2849. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2850. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2851. /* Input error checking is done when commands are added to queue. */
  2852. if (cmd->meta.flags & CMD_WANT_SKB) {
  2853. cmd->meta.source->u.skb = rxb->skb;
  2854. rxb->skb = NULL;
  2855. } else if (cmd->meta.u.callback &&
  2856. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2857. rxb->skb = NULL;
  2858. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2859. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2860. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2861. wake_up_interruptible(&priv->wait_command_queue);
  2862. }
  2863. }
  2864. /************************** RX-FUNCTIONS ****************************/
  2865. /*
  2866. * Rx theory of operation
  2867. *
  2868. * The host allocates 32 DMA target addresses and passes the host address
  2869. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2870. * 0 to 31
  2871. *
  2872. * Rx Queue Indexes
  2873. * The host/firmware share two index registers for managing the Rx buffers.
  2874. *
  2875. * The READ index maps to the first position that the firmware may be writing
  2876. * to -- the driver can read up to (but not including) this position and get
  2877. * good data.
  2878. * The READ index is managed by the firmware once the card is enabled.
  2879. *
  2880. * The WRITE index maps to the last position the driver has read from -- the
  2881. * position preceding WRITE is the last slot the firmware can place a packet.
  2882. *
  2883. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2884. * WRITE = READ.
  2885. *
  2886. * During initialization, the host sets up the READ queue position to the first
  2887. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2888. *
  2889. * When the firmware places a packet in a buffer, it will advance the READ index
  2890. * and fire the RX interrupt. The driver can then query the READ index and
  2891. * process as many packets as possible, moving the WRITE index forward as it
  2892. * resets the Rx queue buffers with new memory.
  2893. *
  2894. * The management in the driver is as follows:
  2895. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2896. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2897. * to replenish the iwl->rxq->rx_free.
  2898. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2899. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2900. * 'processed' and 'read' driver indexes as well)
  2901. * + A received packet is processed and handed to the kernel network stack,
  2902. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2903. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2904. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2905. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2906. * were enough free buffers and RX_STALLED is set it is cleared.
  2907. *
  2908. *
  2909. * Driver sequence:
  2910. *
  2911. * iwl3945_rx_queue_alloc() Allocates rx_free
  2912. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2913. * iwl3945_rx_queue_restock
  2914. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2915. * queue, updates firmware pointers, and updates
  2916. * the WRITE index. If insufficient rx_free buffers
  2917. * are available, schedules iwl3945_rx_replenish
  2918. *
  2919. * -- enable interrupts --
  2920. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  2921. * READ INDEX, detaching the SKB from the pool.
  2922. * Moves the packet buffer from queue to rx_used.
  2923. * Calls iwl3945_rx_queue_restock to refill any empty
  2924. * slots.
  2925. * ...
  2926. *
  2927. */
  2928. /**
  2929. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2930. */
  2931. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  2932. {
  2933. int s = q->read - q->write;
  2934. if (s <= 0)
  2935. s += RX_QUEUE_SIZE;
  2936. /* keep some buffer to not confuse full and empty queue */
  2937. s -= 2;
  2938. if (s < 0)
  2939. s = 0;
  2940. return s;
  2941. }
  2942. /**
  2943. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2944. */
  2945. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  2946. {
  2947. u32 reg = 0;
  2948. int rc = 0;
  2949. unsigned long flags;
  2950. spin_lock_irqsave(&q->lock, flags);
  2951. if (q->need_update == 0)
  2952. goto exit_unlock;
  2953. /* If power-saving is in use, make sure device is awake */
  2954. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2955. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2956. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2957. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  2958. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2959. goto exit_unlock;
  2960. }
  2961. rc = iwl3945_grab_nic_access(priv);
  2962. if (rc)
  2963. goto exit_unlock;
  2964. /* Device expects a multiple of 8 */
  2965. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  2966. q->write & ~0x7);
  2967. iwl3945_release_nic_access(priv);
  2968. /* Else device is assumed to be awake */
  2969. } else
  2970. /* Device expects a multiple of 8 */
  2971. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2972. q->need_update = 0;
  2973. exit_unlock:
  2974. spin_unlock_irqrestore(&q->lock, flags);
  2975. return rc;
  2976. }
  2977. /**
  2978. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2979. */
  2980. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  2981. dma_addr_t dma_addr)
  2982. {
  2983. return cpu_to_le32((u32)dma_addr);
  2984. }
  2985. /**
  2986. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2987. *
  2988. * If there are slots in the RX queue that need to be restocked,
  2989. * and we have free pre-allocated buffers, fill the ranks as much
  2990. * as we can, pulling from rx_free.
  2991. *
  2992. * This moves the 'write' index forward to catch up with 'processed', and
  2993. * also updates the memory address in the firmware to reference the new
  2994. * target buffer.
  2995. */
  2996. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  2997. {
  2998. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2999. struct list_head *element;
  3000. struct iwl3945_rx_mem_buffer *rxb;
  3001. unsigned long flags;
  3002. int write, rc;
  3003. spin_lock_irqsave(&rxq->lock, flags);
  3004. write = rxq->write & ~0x7;
  3005. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3006. /* Get next free Rx buffer, remove from free list */
  3007. element = rxq->rx_free.next;
  3008. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3009. list_del(element);
  3010. /* Point to Rx buffer via next RBD in circular buffer */
  3011. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3012. rxq->queue[rxq->write] = rxb;
  3013. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3014. rxq->free_count--;
  3015. }
  3016. spin_unlock_irqrestore(&rxq->lock, flags);
  3017. /* If the pre-allocated buffer pool is dropping low, schedule to
  3018. * refill it */
  3019. if (rxq->free_count <= RX_LOW_WATERMARK)
  3020. queue_work(priv->workqueue, &priv->rx_replenish);
  3021. /* If we've added more space for the firmware to place data, tell it.
  3022. * Increment device's write pointer in multiples of 8. */
  3023. if ((write != (rxq->write & ~0x7))
  3024. || (abs(rxq->write - rxq->read) > 7)) {
  3025. spin_lock_irqsave(&rxq->lock, flags);
  3026. rxq->need_update = 1;
  3027. spin_unlock_irqrestore(&rxq->lock, flags);
  3028. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3029. if (rc)
  3030. return rc;
  3031. }
  3032. return 0;
  3033. }
  3034. /**
  3035. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3036. *
  3037. * When moving to rx_free an SKB is allocated for the slot.
  3038. *
  3039. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3040. * This is called as a scheduled work item (except for during initialization)
  3041. */
  3042. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3043. {
  3044. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3045. struct list_head *element;
  3046. struct iwl3945_rx_mem_buffer *rxb;
  3047. unsigned long flags;
  3048. spin_lock_irqsave(&rxq->lock, flags);
  3049. while (!list_empty(&rxq->rx_used)) {
  3050. element = rxq->rx_used.next;
  3051. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3052. /* Alloc a new receive buffer */
  3053. rxb->skb =
  3054. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3055. if (!rxb->skb) {
  3056. if (net_ratelimit())
  3057. printk(KERN_CRIT DRV_NAME
  3058. ": Can not allocate SKB buffers\n");
  3059. /* We don't reschedule replenish work here -- we will
  3060. * call the restock method and if it still needs
  3061. * more buffers it will schedule replenish */
  3062. break;
  3063. }
  3064. /* If radiotap head is required, reserve some headroom here.
  3065. * The physical head count is a variable rx_stats->phy_count.
  3066. * We reserve 4 bytes here. Plus these extra bytes, the
  3067. * headroom of the physical head should be enough for the
  3068. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3069. */
  3070. skb_reserve(rxb->skb, 4);
  3071. priv->alloc_rxb_skb++;
  3072. list_del(element);
  3073. /* Get physical address of RB/SKB */
  3074. rxb->dma_addr =
  3075. pci_map_single(priv->pci_dev, rxb->skb->data,
  3076. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3077. list_add_tail(&rxb->list, &rxq->rx_free);
  3078. rxq->free_count++;
  3079. }
  3080. spin_unlock_irqrestore(&rxq->lock, flags);
  3081. }
  3082. /*
  3083. * this should be called while priv->lock is locked
  3084. */
  3085. static void __iwl3945_rx_replenish(void *data)
  3086. {
  3087. struct iwl3945_priv *priv = data;
  3088. iwl3945_rx_allocate(priv);
  3089. iwl3945_rx_queue_restock(priv);
  3090. }
  3091. void iwl3945_rx_replenish(void *data)
  3092. {
  3093. struct iwl3945_priv *priv = data;
  3094. unsigned long flags;
  3095. iwl3945_rx_allocate(priv);
  3096. spin_lock_irqsave(&priv->lock, flags);
  3097. iwl3945_rx_queue_restock(priv);
  3098. spin_unlock_irqrestore(&priv->lock, flags);
  3099. }
  3100. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3101. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3102. * This free routine walks the list of POOL entries and if SKB is set to
  3103. * non NULL it is unmapped and freed
  3104. */
  3105. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3106. {
  3107. int i;
  3108. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3109. if (rxq->pool[i].skb != NULL) {
  3110. pci_unmap_single(priv->pci_dev,
  3111. rxq->pool[i].dma_addr,
  3112. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3113. dev_kfree_skb(rxq->pool[i].skb);
  3114. }
  3115. }
  3116. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3117. rxq->dma_addr);
  3118. rxq->bd = NULL;
  3119. }
  3120. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3121. {
  3122. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3123. struct pci_dev *dev = priv->pci_dev;
  3124. int i;
  3125. spin_lock_init(&rxq->lock);
  3126. INIT_LIST_HEAD(&rxq->rx_free);
  3127. INIT_LIST_HEAD(&rxq->rx_used);
  3128. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3129. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3130. if (!rxq->bd)
  3131. return -ENOMEM;
  3132. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3133. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3134. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3135. /* Set us so that we have processed and used all buffers, but have
  3136. * not restocked the Rx queue with fresh buffers */
  3137. rxq->read = rxq->write = 0;
  3138. rxq->free_count = 0;
  3139. rxq->need_update = 0;
  3140. return 0;
  3141. }
  3142. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3143. {
  3144. unsigned long flags;
  3145. int i;
  3146. spin_lock_irqsave(&rxq->lock, flags);
  3147. INIT_LIST_HEAD(&rxq->rx_free);
  3148. INIT_LIST_HEAD(&rxq->rx_used);
  3149. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3150. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3151. /* In the reset function, these buffers may have been allocated
  3152. * to an SKB, so we need to unmap and free potential storage */
  3153. if (rxq->pool[i].skb != NULL) {
  3154. pci_unmap_single(priv->pci_dev,
  3155. rxq->pool[i].dma_addr,
  3156. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3157. priv->alloc_rxb_skb--;
  3158. dev_kfree_skb(rxq->pool[i].skb);
  3159. rxq->pool[i].skb = NULL;
  3160. }
  3161. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3162. }
  3163. /* Set us so that we have processed and used all buffers, but have
  3164. * not restocked the Rx queue with fresh buffers */
  3165. rxq->read = rxq->write = 0;
  3166. rxq->free_count = 0;
  3167. spin_unlock_irqrestore(&rxq->lock, flags);
  3168. }
  3169. /* Convert linear signal-to-noise ratio into dB */
  3170. static u8 ratio2dB[100] = {
  3171. /* 0 1 2 3 4 5 6 7 8 9 */
  3172. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3173. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3174. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3175. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3176. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3177. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3178. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3179. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3180. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3181. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3182. };
  3183. /* Calculates a relative dB value from a ratio of linear
  3184. * (i.e. not dB) signal levels.
  3185. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3186. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3187. {
  3188. /* 1000:1 or higher just report as 60 dB */
  3189. if (sig_ratio >= 1000)
  3190. return 60;
  3191. /* 100:1 or higher, divide by 10 and use table,
  3192. * add 20 dB to make up for divide by 10 */
  3193. if (sig_ratio >= 100)
  3194. return 20 + (int)ratio2dB[sig_ratio/10];
  3195. /* We shouldn't see this */
  3196. if (sig_ratio < 1)
  3197. return 0;
  3198. /* Use table for ratios 1:1 - 99:1 */
  3199. return (int)ratio2dB[sig_ratio];
  3200. }
  3201. #define PERFECT_RSSI (-20) /* dBm */
  3202. #define WORST_RSSI (-95) /* dBm */
  3203. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3204. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3205. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3206. * about formulas used below. */
  3207. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3208. {
  3209. int sig_qual;
  3210. int degradation = PERFECT_RSSI - rssi_dbm;
  3211. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3212. * as indicator; formula is (signal dbm - noise dbm).
  3213. * SNR at or above 40 is a great signal (100%).
  3214. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3215. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3216. if (noise_dbm) {
  3217. if (rssi_dbm - noise_dbm >= 40)
  3218. return 100;
  3219. else if (rssi_dbm < noise_dbm)
  3220. return 0;
  3221. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3222. /* Else use just the signal level.
  3223. * This formula is a least squares fit of data points collected and
  3224. * compared with a reference system that had a percentage (%) display
  3225. * for signal quality. */
  3226. } else
  3227. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3228. (15 * RSSI_RANGE + 62 * degradation)) /
  3229. (RSSI_RANGE * RSSI_RANGE);
  3230. if (sig_qual > 100)
  3231. sig_qual = 100;
  3232. else if (sig_qual < 1)
  3233. sig_qual = 0;
  3234. return sig_qual;
  3235. }
  3236. /**
  3237. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3238. *
  3239. * Uses the priv->rx_handlers callback function array to invoke
  3240. * the appropriate handlers, including command responses,
  3241. * frame-received notifications, and other notifications.
  3242. */
  3243. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3244. {
  3245. struct iwl3945_rx_mem_buffer *rxb;
  3246. struct iwl3945_rx_packet *pkt;
  3247. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3248. u32 r, i;
  3249. int reclaim;
  3250. unsigned long flags;
  3251. u8 fill_rx = 0;
  3252. u32 count = 8;
  3253. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3254. * buffer that the driver may process (last buffer filled by ucode). */
  3255. r = iwl3945_hw_get_rx_read(priv);
  3256. i = rxq->read;
  3257. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3258. fill_rx = 1;
  3259. /* Rx interrupt, but nothing sent from uCode */
  3260. if (i == r)
  3261. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3262. while (i != r) {
  3263. rxb = rxq->queue[i];
  3264. /* If an RXB doesn't have a Rx queue slot associated with it,
  3265. * then a bug has been introduced in the queue refilling
  3266. * routines -- catch it here */
  3267. BUG_ON(rxb == NULL);
  3268. rxq->queue[i] = NULL;
  3269. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3270. IWL_RX_BUF_SIZE,
  3271. PCI_DMA_FROMDEVICE);
  3272. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3273. /* Reclaim a command buffer only if this packet is a response
  3274. * to a (driver-originated) command.
  3275. * If the packet (e.g. Rx frame) originated from uCode,
  3276. * there is no command buffer to reclaim.
  3277. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3278. * but apparently a few don't get set; catch them here. */
  3279. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3280. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3281. (pkt->hdr.cmd != REPLY_TX);
  3282. /* Based on type of command response or notification,
  3283. * handle those that need handling via function in
  3284. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3285. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3286. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3287. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3288. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3289. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3290. } else {
  3291. /* No handling needed */
  3292. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3293. "r %d i %d No handler needed for %s, 0x%02x\n",
  3294. r, i, get_cmd_string(pkt->hdr.cmd),
  3295. pkt->hdr.cmd);
  3296. }
  3297. if (reclaim) {
  3298. /* Invoke any callbacks, transfer the skb to caller, and
  3299. * fire off the (possibly) blocking iwl3945_send_cmd()
  3300. * as we reclaim the driver command queue */
  3301. if (rxb && rxb->skb)
  3302. iwl3945_tx_cmd_complete(priv, rxb);
  3303. else
  3304. IWL_WARNING("Claim null rxb?\n");
  3305. }
  3306. /* For now we just don't re-use anything. We can tweak this
  3307. * later to try and re-use notification packets and SKBs that
  3308. * fail to Rx correctly */
  3309. if (rxb->skb != NULL) {
  3310. priv->alloc_rxb_skb--;
  3311. dev_kfree_skb_any(rxb->skb);
  3312. rxb->skb = NULL;
  3313. }
  3314. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3315. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3316. spin_lock_irqsave(&rxq->lock, flags);
  3317. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3318. spin_unlock_irqrestore(&rxq->lock, flags);
  3319. i = (i + 1) & RX_QUEUE_MASK;
  3320. /* If there are a lot of unused frames,
  3321. * restock the Rx queue so ucode won't assert. */
  3322. if (fill_rx) {
  3323. count++;
  3324. if (count >= 8) {
  3325. priv->rxq.read = i;
  3326. __iwl3945_rx_replenish(priv);
  3327. count = 0;
  3328. }
  3329. }
  3330. }
  3331. /* Backtrack one entry */
  3332. priv->rxq.read = i;
  3333. iwl3945_rx_queue_restock(priv);
  3334. }
  3335. /**
  3336. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3337. */
  3338. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3339. struct iwl3945_tx_queue *txq)
  3340. {
  3341. u32 reg = 0;
  3342. int rc = 0;
  3343. int txq_id = txq->q.id;
  3344. if (txq->need_update == 0)
  3345. return rc;
  3346. /* if we're trying to save power */
  3347. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3348. /* wake up nic if it's powered down ...
  3349. * uCode will wake up, and interrupt us again, so next
  3350. * time we'll skip this part. */
  3351. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3352. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3353. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3354. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3355. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3356. return rc;
  3357. }
  3358. /* restore this queue's parameters in nic hardware. */
  3359. rc = iwl3945_grab_nic_access(priv);
  3360. if (rc)
  3361. return rc;
  3362. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3363. txq->q.write_ptr | (txq_id << 8));
  3364. iwl3945_release_nic_access(priv);
  3365. /* else not in power-save mode, uCode will never sleep when we're
  3366. * trying to tx (during RFKILL, we're not trying to tx). */
  3367. } else
  3368. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3369. txq->q.write_ptr | (txq_id << 8));
  3370. txq->need_update = 0;
  3371. return rc;
  3372. }
  3373. #ifdef CONFIG_IWL3945_DEBUG
  3374. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3375. {
  3376. DECLARE_MAC_BUF(mac);
  3377. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3378. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3379. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3380. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3381. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3382. le32_to_cpu(rxon->filter_flags));
  3383. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3384. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3385. rxon->ofdm_basic_rates);
  3386. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3387. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3388. print_mac(mac, rxon->node_addr));
  3389. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3390. print_mac(mac, rxon->bssid_addr));
  3391. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3392. }
  3393. #endif
  3394. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3395. {
  3396. IWL_DEBUG_ISR("Enabling interrupts\n");
  3397. set_bit(STATUS_INT_ENABLED, &priv->status);
  3398. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3399. }
  3400. /* call this function to flush any scheduled tasklet */
  3401. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3402. {
  3403. /* wait to make sure we flush pedding tasklet*/
  3404. synchronize_irq(priv->pci_dev->irq);
  3405. tasklet_kill(&priv->irq_tasklet);
  3406. }
  3407. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3408. {
  3409. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3410. /* disable interrupts from uCode/NIC to host */
  3411. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3412. /* acknowledge/clear/reset any interrupts still pending
  3413. * from uCode or flow handler (Rx/Tx DMA) */
  3414. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3415. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3416. IWL_DEBUG_ISR("Disabled interrupts\n");
  3417. }
  3418. static const char *desc_lookup(int i)
  3419. {
  3420. switch (i) {
  3421. case 1:
  3422. return "FAIL";
  3423. case 2:
  3424. return "BAD_PARAM";
  3425. case 3:
  3426. return "BAD_CHECKSUM";
  3427. case 4:
  3428. return "NMI_INTERRUPT";
  3429. case 5:
  3430. return "SYSASSERT";
  3431. case 6:
  3432. return "FATAL_ERROR";
  3433. }
  3434. return "UNKNOWN";
  3435. }
  3436. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3437. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3438. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3439. {
  3440. u32 i;
  3441. u32 desc, time, count, base, data1;
  3442. u32 blink1, blink2, ilink1, ilink2;
  3443. int rc;
  3444. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3445. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3446. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3447. return;
  3448. }
  3449. rc = iwl3945_grab_nic_access(priv);
  3450. if (rc) {
  3451. IWL_WARNING("Can not read from adapter at this time.\n");
  3452. return;
  3453. }
  3454. count = iwl3945_read_targ_mem(priv, base);
  3455. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3456. IWL_ERROR("Start IWL Error Log Dump:\n");
  3457. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3458. }
  3459. IWL_ERROR("Desc Time asrtPC blink2 "
  3460. "ilink1 nmiPC Line\n");
  3461. for (i = ERROR_START_OFFSET;
  3462. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3463. i += ERROR_ELEM_SIZE) {
  3464. desc = iwl3945_read_targ_mem(priv, base + i);
  3465. time =
  3466. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3467. blink1 =
  3468. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3469. blink2 =
  3470. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3471. ilink1 =
  3472. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3473. ilink2 =
  3474. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3475. data1 =
  3476. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3477. IWL_ERROR
  3478. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3479. desc_lookup(desc), desc, time, blink1, blink2,
  3480. ilink1, ilink2, data1);
  3481. }
  3482. iwl3945_release_nic_access(priv);
  3483. }
  3484. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3485. /**
  3486. * iwl3945_print_event_log - Dump error event log to syslog
  3487. *
  3488. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3489. */
  3490. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3491. u32 num_events, u32 mode)
  3492. {
  3493. u32 i;
  3494. u32 base; /* SRAM byte address of event log header */
  3495. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3496. u32 ptr; /* SRAM byte address of log data */
  3497. u32 ev, time, data; /* event log data */
  3498. if (num_events == 0)
  3499. return;
  3500. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3501. if (mode == 0)
  3502. event_size = 2 * sizeof(u32);
  3503. else
  3504. event_size = 3 * sizeof(u32);
  3505. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3506. /* "time" is actually "data" for mode 0 (no timestamp).
  3507. * place event id # at far right for easier visual parsing. */
  3508. for (i = 0; i < num_events; i++) {
  3509. ev = iwl3945_read_targ_mem(priv, ptr);
  3510. ptr += sizeof(u32);
  3511. time = iwl3945_read_targ_mem(priv, ptr);
  3512. ptr += sizeof(u32);
  3513. if (mode == 0)
  3514. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3515. else {
  3516. data = iwl3945_read_targ_mem(priv, ptr);
  3517. ptr += sizeof(u32);
  3518. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3519. }
  3520. }
  3521. }
  3522. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3523. {
  3524. int rc;
  3525. u32 base; /* SRAM byte address of event log header */
  3526. u32 capacity; /* event log capacity in # entries */
  3527. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3528. u32 num_wraps; /* # times uCode wrapped to top of log */
  3529. u32 next_entry; /* index of next entry to be written by uCode */
  3530. u32 size; /* # entries that we'll print */
  3531. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3532. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3533. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3534. return;
  3535. }
  3536. rc = iwl3945_grab_nic_access(priv);
  3537. if (rc) {
  3538. IWL_WARNING("Can not read from adapter at this time.\n");
  3539. return;
  3540. }
  3541. /* event log header */
  3542. capacity = iwl3945_read_targ_mem(priv, base);
  3543. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3544. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3545. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3546. size = num_wraps ? capacity : next_entry;
  3547. /* bail out if nothing in log */
  3548. if (size == 0) {
  3549. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3550. iwl3945_release_nic_access(priv);
  3551. return;
  3552. }
  3553. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3554. size, num_wraps);
  3555. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3556. * i.e the next one that uCode would fill. */
  3557. if (num_wraps)
  3558. iwl3945_print_event_log(priv, next_entry,
  3559. capacity - next_entry, mode);
  3560. /* (then/else) start at top of log */
  3561. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3562. iwl3945_release_nic_access(priv);
  3563. }
  3564. /**
  3565. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3566. */
  3567. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3568. {
  3569. /* Set the FW error flag -- cleared on iwl3945_down */
  3570. set_bit(STATUS_FW_ERROR, &priv->status);
  3571. /* Cancel currently queued command. */
  3572. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3573. #ifdef CONFIG_IWL3945_DEBUG
  3574. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3575. iwl3945_dump_nic_error_log(priv);
  3576. iwl3945_dump_nic_event_log(priv);
  3577. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3578. }
  3579. #endif
  3580. wake_up_interruptible(&priv->wait_command_queue);
  3581. /* Keep the restart process from trying to send host
  3582. * commands by clearing the INIT status bit */
  3583. clear_bit(STATUS_READY, &priv->status);
  3584. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3585. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3586. "Restarting adapter due to uCode error.\n");
  3587. if (iwl3945_is_associated(priv)) {
  3588. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3589. sizeof(priv->recovery_rxon));
  3590. priv->error_recovering = 1;
  3591. }
  3592. queue_work(priv->workqueue, &priv->restart);
  3593. }
  3594. }
  3595. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3596. {
  3597. unsigned long flags;
  3598. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3599. sizeof(priv->staging_rxon));
  3600. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3601. iwl3945_commit_rxon(priv);
  3602. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3603. spin_lock_irqsave(&priv->lock, flags);
  3604. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3605. priv->error_recovering = 0;
  3606. spin_unlock_irqrestore(&priv->lock, flags);
  3607. }
  3608. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3609. {
  3610. u32 inta, handled = 0;
  3611. u32 inta_fh;
  3612. unsigned long flags;
  3613. #ifdef CONFIG_IWL3945_DEBUG
  3614. u32 inta_mask;
  3615. #endif
  3616. spin_lock_irqsave(&priv->lock, flags);
  3617. /* Ack/clear/reset pending uCode interrupts.
  3618. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3619. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3620. inta = iwl3945_read32(priv, CSR_INT);
  3621. iwl3945_write32(priv, CSR_INT, inta);
  3622. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3623. * Any new interrupts that happen after this, either while we're
  3624. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3625. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3626. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3627. #ifdef CONFIG_IWL3945_DEBUG
  3628. if (iwl3945_debug_level & IWL_DL_ISR) {
  3629. /* just for debug */
  3630. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3631. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3632. inta, inta_mask, inta_fh);
  3633. }
  3634. #endif
  3635. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3636. * atomic, make sure that inta covers all the interrupts that
  3637. * we've discovered, even if FH interrupt came in just after
  3638. * reading CSR_INT. */
  3639. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3640. inta |= CSR_INT_BIT_FH_RX;
  3641. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3642. inta |= CSR_INT_BIT_FH_TX;
  3643. /* Now service all interrupt bits discovered above. */
  3644. if (inta & CSR_INT_BIT_HW_ERR) {
  3645. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3646. /* Tell the device to stop sending interrupts */
  3647. iwl3945_disable_interrupts(priv);
  3648. iwl3945_irq_handle_error(priv);
  3649. handled |= CSR_INT_BIT_HW_ERR;
  3650. spin_unlock_irqrestore(&priv->lock, flags);
  3651. return;
  3652. }
  3653. #ifdef CONFIG_IWL3945_DEBUG
  3654. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3655. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3656. if (inta & CSR_INT_BIT_SCD)
  3657. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3658. "the frame/frames.\n");
  3659. /* Alive notification via Rx interrupt will do the real work */
  3660. if (inta & CSR_INT_BIT_ALIVE)
  3661. IWL_DEBUG_ISR("Alive interrupt\n");
  3662. }
  3663. #endif
  3664. /* Safely ignore these bits for debug checks below */
  3665. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3666. /* HW RF KILL switch toggled (4965 only) */
  3667. if (inta & CSR_INT_BIT_RF_KILL) {
  3668. int hw_rf_kill = 0;
  3669. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3670. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3671. hw_rf_kill = 1;
  3672. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3673. "RF_KILL bit toggled to %s.\n",
  3674. hw_rf_kill ? "disable radio":"enable radio");
  3675. /* Queue restart only if RF_KILL switch was set to "kill"
  3676. * when we loaded driver, and is now set to "enable".
  3677. * After we're Alive, RF_KILL gets handled by
  3678. * iwl3945_rx_card_state_notif() */
  3679. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3680. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3681. queue_work(priv->workqueue, &priv->restart);
  3682. }
  3683. handled |= CSR_INT_BIT_RF_KILL;
  3684. }
  3685. /* Chip got too hot and stopped itself (4965 only) */
  3686. if (inta & CSR_INT_BIT_CT_KILL) {
  3687. IWL_ERROR("Microcode CT kill error detected.\n");
  3688. handled |= CSR_INT_BIT_CT_KILL;
  3689. }
  3690. /* Error detected by uCode */
  3691. if (inta & CSR_INT_BIT_SW_ERR) {
  3692. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3693. inta);
  3694. iwl3945_irq_handle_error(priv);
  3695. handled |= CSR_INT_BIT_SW_ERR;
  3696. }
  3697. /* uCode wakes up after power-down sleep */
  3698. if (inta & CSR_INT_BIT_WAKEUP) {
  3699. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3700. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3701. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3702. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3703. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3704. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3705. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3706. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3707. handled |= CSR_INT_BIT_WAKEUP;
  3708. }
  3709. /* All uCode command responses, including Tx command responses,
  3710. * Rx "responses" (frame-received notification), and other
  3711. * notifications from uCode come through here*/
  3712. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3713. iwl3945_rx_handle(priv);
  3714. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3715. }
  3716. if (inta & CSR_INT_BIT_FH_TX) {
  3717. IWL_DEBUG_ISR("Tx interrupt\n");
  3718. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3719. if (!iwl3945_grab_nic_access(priv)) {
  3720. iwl3945_write_direct32(priv,
  3721. FH_TCSR_CREDIT
  3722. (ALM_FH_SRVC_CHNL), 0x0);
  3723. iwl3945_release_nic_access(priv);
  3724. }
  3725. handled |= CSR_INT_BIT_FH_TX;
  3726. }
  3727. if (inta & ~handled)
  3728. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3729. if (inta & ~CSR_INI_SET_MASK) {
  3730. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3731. inta & ~CSR_INI_SET_MASK);
  3732. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3733. }
  3734. /* Re-enable all interrupts */
  3735. /* only Re-enable if disabled by irq */
  3736. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3737. iwl3945_enable_interrupts(priv);
  3738. #ifdef CONFIG_IWL3945_DEBUG
  3739. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3740. inta = iwl3945_read32(priv, CSR_INT);
  3741. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3742. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3743. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3744. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3745. }
  3746. #endif
  3747. spin_unlock_irqrestore(&priv->lock, flags);
  3748. }
  3749. static irqreturn_t iwl3945_isr(int irq, void *data)
  3750. {
  3751. struct iwl3945_priv *priv = data;
  3752. u32 inta, inta_mask;
  3753. u32 inta_fh;
  3754. if (!priv)
  3755. return IRQ_NONE;
  3756. spin_lock(&priv->lock);
  3757. /* Disable (but don't clear!) interrupts here to avoid
  3758. * back-to-back ISRs and sporadic interrupts from our NIC.
  3759. * If we have something to service, the tasklet will re-enable ints.
  3760. * If we *don't* have something, we'll re-enable before leaving here. */
  3761. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3762. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3763. /* Discover which interrupts are active/pending */
  3764. inta = iwl3945_read32(priv, CSR_INT);
  3765. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3766. /* Ignore interrupt if there's nothing in NIC to service.
  3767. * This may be due to IRQ shared with another device,
  3768. * or due to sporadic interrupts thrown from our NIC. */
  3769. if (!inta && !inta_fh) {
  3770. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3771. goto none;
  3772. }
  3773. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3774. /* Hardware disappeared */
  3775. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3776. goto unplugged;
  3777. }
  3778. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3779. inta, inta_mask, inta_fh);
  3780. inta &= ~CSR_INT_BIT_SCD;
  3781. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3782. if (likely(inta || inta_fh))
  3783. tasklet_schedule(&priv->irq_tasklet);
  3784. unplugged:
  3785. spin_unlock(&priv->lock);
  3786. return IRQ_HANDLED;
  3787. none:
  3788. /* re-enable interrupts here since we don't have anything to service. */
  3789. /* only Re-enable if disabled by irq */
  3790. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3791. iwl3945_enable_interrupts(priv);
  3792. spin_unlock(&priv->lock);
  3793. return IRQ_NONE;
  3794. }
  3795. /************************** EEPROM BANDS ****************************
  3796. *
  3797. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3798. * EEPROM contents to the specific channel number supported for each
  3799. * band.
  3800. *
  3801. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3802. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3803. * The specific geography and calibration information for that channel
  3804. * is contained in the eeprom map itself.
  3805. *
  3806. * During init, we copy the eeprom information and channel map
  3807. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3808. *
  3809. * channel_map_24/52 provides the index in the channel_info array for a
  3810. * given channel. We have to have two separate maps as there is channel
  3811. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3812. * band_2
  3813. *
  3814. * A value of 0xff stored in the channel_map indicates that the channel
  3815. * is not supported by the hardware at all.
  3816. *
  3817. * A value of 0xfe in the channel_map indicates that the channel is not
  3818. * valid for Tx with the current hardware. This means that
  3819. * while the system can tune and receive on a given channel, it may not
  3820. * be able to associate or transmit any frames on that
  3821. * channel. There is no corresponding channel information for that
  3822. * entry.
  3823. *
  3824. *********************************************************************/
  3825. /* 2.4 GHz */
  3826. static const u8 iwl3945_eeprom_band_1[14] = {
  3827. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3828. };
  3829. /* 5.2 GHz bands */
  3830. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3831. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3832. };
  3833. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3834. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3835. };
  3836. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3837. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3838. };
  3839. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3840. 145, 149, 153, 157, 161, 165
  3841. };
  3842. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3843. int *eeprom_ch_count,
  3844. const struct iwl3945_eeprom_channel
  3845. **eeprom_ch_info,
  3846. const u8 **eeprom_ch_index)
  3847. {
  3848. switch (band) {
  3849. case 1: /* 2.4GHz band */
  3850. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3851. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3852. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3853. break;
  3854. case 2: /* 4.9GHz band */
  3855. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3856. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3857. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3858. break;
  3859. case 3: /* 5.2GHz band */
  3860. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3861. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3862. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3863. break;
  3864. case 4: /* 5.5GHz band */
  3865. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3866. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3867. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3868. break;
  3869. case 5: /* 5.7GHz band */
  3870. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3871. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3872. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3873. break;
  3874. default:
  3875. BUG();
  3876. return;
  3877. }
  3878. }
  3879. /**
  3880. * iwl3945_get_channel_info - Find driver's private channel info
  3881. *
  3882. * Based on band and channel number.
  3883. */
  3884. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3885. enum ieee80211_band band, u16 channel)
  3886. {
  3887. int i;
  3888. switch (band) {
  3889. case IEEE80211_BAND_5GHZ:
  3890. for (i = 14; i < priv->channel_count; i++) {
  3891. if (priv->channel_info[i].channel == channel)
  3892. return &priv->channel_info[i];
  3893. }
  3894. break;
  3895. case IEEE80211_BAND_2GHZ:
  3896. if (channel >= 1 && channel <= 14)
  3897. return &priv->channel_info[channel - 1];
  3898. break;
  3899. case IEEE80211_NUM_BANDS:
  3900. WARN_ON(1);
  3901. }
  3902. return NULL;
  3903. }
  3904. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3905. ? # x " " : "")
  3906. /**
  3907. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3908. */
  3909. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3910. {
  3911. int eeprom_ch_count = 0;
  3912. const u8 *eeprom_ch_index = NULL;
  3913. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  3914. int band, ch;
  3915. struct iwl3945_channel_info *ch_info;
  3916. if (priv->channel_count) {
  3917. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3918. return 0;
  3919. }
  3920. if (priv->eeprom.version < 0x2f) {
  3921. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3922. priv->eeprom.version);
  3923. return -EINVAL;
  3924. }
  3925. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3926. priv->channel_count =
  3927. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3928. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3929. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3930. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3931. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3932. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3933. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  3934. priv->channel_count, GFP_KERNEL);
  3935. if (!priv->channel_info) {
  3936. IWL_ERROR("Could not allocate channel_info\n");
  3937. priv->channel_count = 0;
  3938. return -ENOMEM;
  3939. }
  3940. ch_info = priv->channel_info;
  3941. /* Loop through the 5 EEPROM bands adding them in order to the
  3942. * channel map we maintain (that contains additional information than
  3943. * what just in the EEPROM) */
  3944. for (band = 1; band <= 5; band++) {
  3945. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3946. &eeprom_ch_info, &eeprom_ch_index);
  3947. /* Loop through each band adding each of the channels */
  3948. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3949. ch_info->channel = eeprom_ch_index[ch];
  3950. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3951. IEEE80211_BAND_5GHZ;
  3952. /* permanently store EEPROM's channel regulatory flags
  3953. * and max power in channel info database. */
  3954. ch_info->eeprom = eeprom_ch_info[ch];
  3955. /* Copy the run-time flags so they are there even on
  3956. * invalid channels */
  3957. ch_info->flags = eeprom_ch_info[ch].flags;
  3958. if (!(is_channel_valid(ch_info))) {
  3959. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3960. "No traffic\n",
  3961. ch_info->channel,
  3962. ch_info->flags,
  3963. is_channel_a_band(ch_info) ?
  3964. "5.2" : "2.4");
  3965. ch_info++;
  3966. continue;
  3967. }
  3968. /* Initialize regulatory-based run-time data */
  3969. ch_info->max_power_avg = ch_info->curr_txpow =
  3970. eeprom_ch_info[ch].max_power_avg;
  3971. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3972. ch_info->min_power = 0;
  3973. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3974. " %ddBm): Ad-Hoc %ssupported\n",
  3975. ch_info->channel,
  3976. is_channel_a_band(ch_info) ?
  3977. "5.2" : "2.4",
  3978. CHECK_AND_PRINT(VALID),
  3979. CHECK_AND_PRINT(IBSS),
  3980. CHECK_AND_PRINT(ACTIVE),
  3981. CHECK_AND_PRINT(RADAR),
  3982. CHECK_AND_PRINT(WIDE),
  3983. CHECK_AND_PRINT(DFS),
  3984. eeprom_ch_info[ch].flags,
  3985. eeprom_ch_info[ch].max_power_avg,
  3986. ((eeprom_ch_info[ch].
  3987. flags & EEPROM_CHANNEL_IBSS)
  3988. && !(eeprom_ch_info[ch].
  3989. flags & EEPROM_CHANNEL_RADAR))
  3990. ? "" : "not ");
  3991. /* Set the user_txpower_limit to the highest power
  3992. * supported by any channel */
  3993. if (eeprom_ch_info[ch].max_power_avg >
  3994. priv->user_txpower_limit)
  3995. priv->user_txpower_limit =
  3996. eeprom_ch_info[ch].max_power_avg;
  3997. ch_info++;
  3998. }
  3999. }
  4000. /* Set up txpower settings in driver for all channels */
  4001. if (iwl3945_txpower_set_from_eeprom(priv))
  4002. return -EIO;
  4003. return 0;
  4004. }
  4005. /*
  4006. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4007. */
  4008. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4009. {
  4010. kfree(priv->channel_info);
  4011. priv->channel_count = 0;
  4012. }
  4013. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4014. * sending probe req. This should be set long enough to hear probe responses
  4015. * from more than one AP. */
  4016. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  4017. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  4018. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  4019. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  4020. /* For faster active scanning, scan will move to the next channel if fewer than
  4021. * PLCP_QUIET_THRESH packets are heard on this channel within
  4022. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4023. * time if it's a quiet channel (nothing responded to our probe, and there's
  4024. * no other traffic).
  4025. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4026. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4027. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  4028. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4029. * Must be set longer than active dwell time.
  4030. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4031. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4032. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4033. #define IWL_PASSIVE_DWELL_BASE (100)
  4034. #define IWL_CHANNEL_TUNE_TIME 5
  4035. #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
  4036. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4037. enum ieee80211_band band,
  4038. u8 n_probes)
  4039. {
  4040. if (band == IEEE80211_BAND_5GHZ)
  4041. return IWL_ACTIVE_DWELL_TIME_52 +
  4042. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  4043. else
  4044. return IWL_ACTIVE_DWELL_TIME_24 +
  4045. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  4046. }
  4047. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4048. enum ieee80211_band band)
  4049. {
  4050. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4051. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4052. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4053. if (iwl3945_is_associated(priv)) {
  4054. /* If we're associated, we clamp the maximum passive
  4055. * dwell time to be 98% of the beacon interval (minus
  4056. * 2 * channel tune time) */
  4057. passive = priv->beacon_int;
  4058. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4059. passive = IWL_PASSIVE_DWELL_BASE;
  4060. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4061. }
  4062. return passive;
  4063. }
  4064. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4065. enum ieee80211_band band,
  4066. u8 is_active, u8 n_probes,
  4067. struct iwl3945_scan_channel *scan_ch)
  4068. {
  4069. const struct ieee80211_channel *channels = NULL;
  4070. const struct ieee80211_supported_band *sband;
  4071. const struct iwl3945_channel_info *ch_info;
  4072. u16 passive_dwell = 0;
  4073. u16 active_dwell = 0;
  4074. int added, i;
  4075. sband = iwl3945_get_band(priv, band);
  4076. if (!sband)
  4077. return 0;
  4078. channels = sband->channels;
  4079. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  4080. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4081. if (passive_dwell <= active_dwell)
  4082. passive_dwell = active_dwell + 1;
  4083. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4084. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4085. continue;
  4086. scan_ch->channel = channels[i].hw_value;
  4087. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4088. if (!is_channel_valid(ch_info)) {
  4089. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4090. scan_ch->channel);
  4091. continue;
  4092. }
  4093. if (!is_active || is_channel_passive(ch_info) ||
  4094. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4095. scan_ch->type = 0; /* passive */
  4096. else
  4097. scan_ch->type = 1; /* active */
  4098. if ((scan_ch->type & 1) && n_probes)
  4099. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4100. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4101. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4102. /* Set txpower levels to defaults */
  4103. scan_ch->tpc.dsp_atten = 110;
  4104. /* scan_pwr_info->tpc.dsp_atten; */
  4105. /*scan_pwr_info->tpc.tx_gain; */
  4106. if (band == IEEE80211_BAND_5GHZ)
  4107. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4108. else {
  4109. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4110. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4111. * power level:
  4112. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4113. */
  4114. }
  4115. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4116. scan_ch->channel,
  4117. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4118. (scan_ch->type & 1) ?
  4119. active_dwell : passive_dwell);
  4120. scan_ch++;
  4121. added++;
  4122. }
  4123. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4124. return added;
  4125. }
  4126. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4127. struct ieee80211_rate *rates)
  4128. {
  4129. int i;
  4130. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4131. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4132. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4133. rates[i].hw_value_short = i;
  4134. rates[i].flags = 0;
  4135. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4136. /*
  4137. * If CCK != 1M then set short preamble rate flag.
  4138. */
  4139. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4140. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4141. }
  4142. }
  4143. }
  4144. /**
  4145. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4146. */
  4147. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4148. {
  4149. struct iwl3945_channel_info *ch;
  4150. struct ieee80211_supported_band *sband;
  4151. struct ieee80211_channel *channels;
  4152. struct ieee80211_channel *geo_ch;
  4153. struct ieee80211_rate *rates;
  4154. int i = 0;
  4155. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4156. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4157. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4158. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4159. return 0;
  4160. }
  4161. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4162. priv->channel_count, GFP_KERNEL);
  4163. if (!channels)
  4164. return -ENOMEM;
  4165. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4166. GFP_KERNEL);
  4167. if (!rates) {
  4168. kfree(channels);
  4169. return -ENOMEM;
  4170. }
  4171. /* 5.2GHz channels start after the 2.4GHz channels */
  4172. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4173. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4174. /* just OFDM */
  4175. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4176. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4177. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4178. sband->channels = channels;
  4179. /* OFDM & CCK */
  4180. sband->bitrates = rates;
  4181. sband->n_bitrates = IWL_RATE_COUNT;
  4182. priv->ieee_channels = channels;
  4183. priv->ieee_rates = rates;
  4184. iwl3945_init_hw_rates(priv, rates);
  4185. for (i = 0; i < priv->channel_count; i++) {
  4186. ch = &priv->channel_info[i];
  4187. /* FIXME: might be removed if scan is OK*/
  4188. if (!is_channel_valid(ch))
  4189. continue;
  4190. if (is_channel_a_band(ch))
  4191. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4192. else
  4193. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4194. geo_ch = &sband->channels[sband->n_channels++];
  4195. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4196. geo_ch->max_power = ch->max_power_avg;
  4197. geo_ch->max_antenna_gain = 0xff;
  4198. geo_ch->hw_value = ch->channel;
  4199. if (is_channel_valid(ch)) {
  4200. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4201. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4202. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4203. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4204. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4205. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4206. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4207. priv->max_channel_txpower_limit =
  4208. ch->max_power_avg;
  4209. } else {
  4210. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4211. }
  4212. /* Save flags for reg domain usage */
  4213. geo_ch->orig_flags = geo_ch->flags;
  4214. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4215. ch->channel, geo_ch->center_freq,
  4216. is_channel_a_band(ch) ? "5.2" : "2.4",
  4217. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4218. "restricted" : "valid",
  4219. geo_ch->flags);
  4220. }
  4221. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4222. priv->cfg->sku & IWL_SKU_A) {
  4223. printk(KERN_INFO DRV_NAME
  4224. ": Incorrectly detected BG card as ABG. Please send "
  4225. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4226. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4227. priv->cfg->sku &= ~IWL_SKU_A;
  4228. }
  4229. printk(KERN_INFO DRV_NAME
  4230. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4231. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4232. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4233. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4234. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4235. &priv->bands[IEEE80211_BAND_2GHZ];
  4236. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4237. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4238. &priv->bands[IEEE80211_BAND_5GHZ];
  4239. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4240. return 0;
  4241. }
  4242. /*
  4243. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4244. */
  4245. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4246. {
  4247. kfree(priv->ieee_channels);
  4248. kfree(priv->ieee_rates);
  4249. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4250. }
  4251. /******************************************************************************
  4252. *
  4253. * uCode download functions
  4254. *
  4255. ******************************************************************************/
  4256. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4257. {
  4258. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4259. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4260. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4261. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4262. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4263. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4264. }
  4265. /**
  4266. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4267. * looking at all data.
  4268. */
  4269. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4270. {
  4271. u32 val;
  4272. u32 save_len = len;
  4273. int rc = 0;
  4274. u32 errcnt;
  4275. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4276. rc = iwl3945_grab_nic_access(priv);
  4277. if (rc)
  4278. return rc;
  4279. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4280. errcnt = 0;
  4281. for (; len > 0; len -= sizeof(u32), image++) {
  4282. /* read data comes through single port, auto-incr addr */
  4283. /* NOTE: Use the debugless read so we don't flood kernel log
  4284. * if IWL_DL_IO is set */
  4285. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4286. if (val != le32_to_cpu(*image)) {
  4287. IWL_ERROR("uCode INST section is invalid at "
  4288. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4289. save_len - len, val, le32_to_cpu(*image));
  4290. rc = -EIO;
  4291. errcnt++;
  4292. if (errcnt >= 20)
  4293. break;
  4294. }
  4295. }
  4296. iwl3945_release_nic_access(priv);
  4297. if (!errcnt)
  4298. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4299. return rc;
  4300. }
  4301. /**
  4302. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4303. * using sample data 100 bytes apart. If these sample points are good,
  4304. * it's a pretty good bet that everything between them is good, too.
  4305. */
  4306. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4307. {
  4308. u32 val;
  4309. int rc = 0;
  4310. u32 errcnt = 0;
  4311. u32 i;
  4312. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4313. rc = iwl3945_grab_nic_access(priv);
  4314. if (rc)
  4315. return rc;
  4316. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4317. /* read data comes through single port, auto-incr addr */
  4318. /* NOTE: Use the debugless read so we don't flood kernel log
  4319. * if IWL_DL_IO is set */
  4320. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4321. i + RTC_INST_LOWER_BOUND);
  4322. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4323. if (val != le32_to_cpu(*image)) {
  4324. #if 0 /* Enable this if you want to see details */
  4325. IWL_ERROR("uCode INST section is invalid at "
  4326. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4327. i, val, *image);
  4328. #endif
  4329. rc = -EIO;
  4330. errcnt++;
  4331. if (errcnt >= 3)
  4332. break;
  4333. }
  4334. }
  4335. iwl3945_release_nic_access(priv);
  4336. return rc;
  4337. }
  4338. /**
  4339. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4340. * and verify its contents
  4341. */
  4342. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4343. {
  4344. __le32 *image;
  4345. u32 len;
  4346. int rc = 0;
  4347. /* Try bootstrap */
  4348. image = (__le32 *)priv->ucode_boot.v_addr;
  4349. len = priv->ucode_boot.len;
  4350. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4351. if (rc == 0) {
  4352. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4353. return 0;
  4354. }
  4355. /* Try initialize */
  4356. image = (__le32 *)priv->ucode_init.v_addr;
  4357. len = priv->ucode_init.len;
  4358. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4359. if (rc == 0) {
  4360. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4361. return 0;
  4362. }
  4363. /* Try runtime/protocol */
  4364. image = (__le32 *)priv->ucode_code.v_addr;
  4365. len = priv->ucode_code.len;
  4366. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4367. if (rc == 0) {
  4368. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4369. return 0;
  4370. }
  4371. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4372. /* Since nothing seems to match, show first several data entries in
  4373. * instruction SRAM, so maybe visual inspection will give a clue.
  4374. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4375. image = (__le32 *)priv->ucode_boot.v_addr;
  4376. len = priv->ucode_boot.len;
  4377. rc = iwl3945_verify_inst_full(priv, image, len);
  4378. return rc;
  4379. }
  4380. /* check contents of special bootstrap uCode SRAM */
  4381. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4382. {
  4383. __le32 *image = priv->ucode_boot.v_addr;
  4384. u32 len = priv->ucode_boot.len;
  4385. u32 reg;
  4386. u32 val;
  4387. IWL_DEBUG_INFO("Begin verify bsm\n");
  4388. /* verify BSM SRAM contents */
  4389. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4390. for (reg = BSM_SRAM_LOWER_BOUND;
  4391. reg < BSM_SRAM_LOWER_BOUND + len;
  4392. reg += sizeof(u32), image++) {
  4393. val = iwl3945_read_prph(priv, reg);
  4394. if (val != le32_to_cpu(*image)) {
  4395. IWL_ERROR("BSM uCode verification failed at "
  4396. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4397. BSM_SRAM_LOWER_BOUND,
  4398. reg - BSM_SRAM_LOWER_BOUND, len,
  4399. val, le32_to_cpu(*image));
  4400. return -EIO;
  4401. }
  4402. }
  4403. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4404. return 0;
  4405. }
  4406. /**
  4407. * iwl3945_load_bsm - Load bootstrap instructions
  4408. *
  4409. * BSM operation:
  4410. *
  4411. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4412. * in special SRAM that does not power down during RFKILL. When powering back
  4413. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4414. * the bootstrap program into the on-board processor, and starts it.
  4415. *
  4416. * The bootstrap program loads (via DMA) instructions and data for a new
  4417. * program from host DRAM locations indicated by the host driver in the
  4418. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4419. * automatically.
  4420. *
  4421. * When initializing the NIC, the host driver points the BSM to the
  4422. * "initialize" uCode image. This uCode sets up some internal data, then
  4423. * notifies host via "initialize alive" that it is complete.
  4424. *
  4425. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4426. * normal runtime uCode instructions and a backup uCode data cache buffer
  4427. * (filled initially with starting data values for the on-board processor),
  4428. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4429. * which begins normal operation.
  4430. *
  4431. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4432. * the backup data cache in DRAM before SRAM is powered down.
  4433. *
  4434. * When powering back up, the BSM loads the bootstrap program. This reloads
  4435. * the runtime uCode instructions and the backup data cache into SRAM,
  4436. * and re-launches the runtime uCode from where it left off.
  4437. */
  4438. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4439. {
  4440. __le32 *image = priv->ucode_boot.v_addr;
  4441. u32 len = priv->ucode_boot.len;
  4442. dma_addr_t pinst;
  4443. dma_addr_t pdata;
  4444. u32 inst_len;
  4445. u32 data_len;
  4446. int rc;
  4447. int i;
  4448. u32 done;
  4449. u32 reg_offset;
  4450. IWL_DEBUG_INFO("Begin load bsm\n");
  4451. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4452. if (len > IWL_MAX_BSM_SIZE)
  4453. return -EINVAL;
  4454. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4455. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4456. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4457. * after the "initialize" uCode has run, to point to
  4458. * runtime/protocol instructions and backup data cache. */
  4459. pinst = priv->ucode_init.p_addr;
  4460. pdata = priv->ucode_init_data.p_addr;
  4461. inst_len = priv->ucode_init.len;
  4462. data_len = priv->ucode_init_data.len;
  4463. rc = iwl3945_grab_nic_access(priv);
  4464. if (rc)
  4465. return rc;
  4466. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4467. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4468. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4469. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4470. /* Fill BSM memory with bootstrap instructions */
  4471. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4472. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4473. reg_offset += sizeof(u32), image++)
  4474. _iwl3945_write_prph(priv, reg_offset,
  4475. le32_to_cpu(*image));
  4476. rc = iwl3945_verify_bsm(priv);
  4477. if (rc) {
  4478. iwl3945_release_nic_access(priv);
  4479. return rc;
  4480. }
  4481. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4482. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4483. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4484. RTC_INST_LOWER_BOUND);
  4485. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4486. /* Load bootstrap code into instruction SRAM now,
  4487. * to prepare to load "initialize" uCode */
  4488. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4489. BSM_WR_CTRL_REG_BIT_START);
  4490. /* Wait for load of bootstrap uCode to finish */
  4491. for (i = 0; i < 100; i++) {
  4492. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4493. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4494. break;
  4495. udelay(10);
  4496. }
  4497. if (i < 100)
  4498. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4499. else {
  4500. IWL_ERROR("BSM write did not complete!\n");
  4501. return -EIO;
  4502. }
  4503. /* Enable future boot loads whenever power management unit triggers it
  4504. * (e.g. when powering back up after power-save shutdown) */
  4505. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4506. BSM_WR_CTRL_REG_BIT_START_EN);
  4507. iwl3945_release_nic_access(priv);
  4508. return 0;
  4509. }
  4510. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4511. {
  4512. /* Remove all resets to allow NIC to operate */
  4513. iwl3945_write32(priv, CSR_RESET, 0);
  4514. }
  4515. /**
  4516. * iwl3945_read_ucode - Read uCode images from disk file.
  4517. *
  4518. * Copy into buffers for card to fetch via bus-mastering
  4519. */
  4520. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4521. {
  4522. struct iwl3945_ucode *ucode;
  4523. int ret = 0;
  4524. const struct firmware *ucode_raw;
  4525. /* firmware file name contains uCode/driver compatibility version */
  4526. const char *name = priv->cfg->fw_name;
  4527. u8 *src;
  4528. size_t len;
  4529. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4530. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4531. * request_firmware() is synchronous, file is in memory on return. */
  4532. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4533. if (ret < 0) {
  4534. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4535. name, ret);
  4536. goto error;
  4537. }
  4538. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4539. name, ucode_raw->size);
  4540. /* Make sure that we got at least our header! */
  4541. if (ucode_raw->size < sizeof(*ucode)) {
  4542. IWL_ERROR("File size way too small!\n");
  4543. ret = -EINVAL;
  4544. goto err_release;
  4545. }
  4546. /* Data from ucode file: header followed by uCode images */
  4547. ucode = (void *)ucode_raw->data;
  4548. ver = le32_to_cpu(ucode->ver);
  4549. inst_size = le32_to_cpu(ucode->inst_size);
  4550. data_size = le32_to_cpu(ucode->data_size);
  4551. init_size = le32_to_cpu(ucode->init_size);
  4552. init_data_size = le32_to_cpu(ucode->init_data_size);
  4553. boot_size = le32_to_cpu(ucode->boot_size);
  4554. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4555. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4556. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4557. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4558. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4559. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4560. /* Verify size of file vs. image size info in file's header */
  4561. if (ucode_raw->size < sizeof(*ucode) +
  4562. inst_size + data_size + init_size +
  4563. init_data_size + boot_size) {
  4564. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4565. (int)ucode_raw->size);
  4566. ret = -EINVAL;
  4567. goto err_release;
  4568. }
  4569. /* Verify that uCode images will fit in card's SRAM */
  4570. if (inst_size > IWL_MAX_INST_SIZE) {
  4571. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4572. inst_size);
  4573. ret = -EINVAL;
  4574. goto err_release;
  4575. }
  4576. if (data_size > IWL_MAX_DATA_SIZE) {
  4577. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4578. data_size);
  4579. ret = -EINVAL;
  4580. goto err_release;
  4581. }
  4582. if (init_size > IWL_MAX_INST_SIZE) {
  4583. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4584. init_size);
  4585. ret = -EINVAL;
  4586. goto err_release;
  4587. }
  4588. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4589. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4590. init_data_size);
  4591. ret = -EINVAL;
  4592. goto err_release;
  4593. }
  4594. if (boot_size > IWL_MAX_BSM_SIZE) {
  4595. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4596. boot_size);
  4597. ret = -EINVAL;
  4598. goto err_release;
  4599. }
  4600. /* Allocate ucode buffers for card's bus-master loading ... */
  4601. /* Runtime instructions and 2 copies of data:
  4602. * 1) unmodified from disk
  4603. * 2) backup cache for save/restore during power-downs */
  4604. priv->ucode_code.len = inst_size;
  4605. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4606. priv->ucode_data.len = data_size;
  4607. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4608. priv->ucode_data_backup.len = data_size;
  4609. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4610. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4611. !priv->ucode_data_backup.v_addr)
  4612. goto err_pci_alloc;
  4613. /* Initialization instructions and data */
  4614. if (init_size && init_data_size) {
  4615. priv->ucode_init.len = init_size;
  4616. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4617. priv->ucode_init_data.len = init_data_size;
  4618. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4619. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4620. goto err_pci_alloc;
  4621. }
  4622. /* Bootstrap (instructions only, no data) */
  4623. if (boot_size) {
  4624. priv->ucode_boot.len = boot_size;
  4625. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4626. if (!priv->ucode_boot.v_addr)
  4627. goto err_pci_alloc;
  4628. }
  4629. /* Copy images into buffers for card's bus-master reads ... */
  4630. /* Runtime instructions (first block of data in file) */
  4631. src = &ucode->data[0];
  4632. len = priv->ucode_code.len;
  4633. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4634. memcpy(priv->ucode_code.v_addr, src, len);
  4635. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4636. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4637. /* Runtime data (2nd block)
  4638. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4639. src = &ucode->data[inst_size];
  4640. len = priv->ucode_data.len;
  4641. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4642. memcpy(priv->ucode_data.v_addr, src, len);
  4643. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4644. /* Initialization instructions (3rd block) */
  4645. if (init_size) {
  4646. src = &ucode->data[inst_size + data_size];
  4647. len = priv->ucode_init.len;
  4648. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4649. len);
  4650. memcpy(priv->ucode_init.v_addr, src, len);
  4651. }
  4652. /* Initialization data (4th block) */
  4653. if (init_data_size) {
  4654. src = &ucode->data[inst_size + data_size + init_size];
  4655. len = priv->ucode_init_data.len;
  4656. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4657. (int)len);
  4658. memcpy(priv->ucode_init_data.v_addr, src, len);
  4659. }
  4660. /* Bootstrap instructions (5th block) */
  4661. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4662. len = priv->ucode_boot.len;
  4663. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4664. (int)len);
  4665. memcpy(priv->ucode_boot.v_addr, src, len);
  4666. /* We have our copies now, allow OS release its copies */
  4667. release_firmware(ucode_raw);
  4668. return 0;
  4669. err_pci_alloc:
  4670. IWL_ERROR("failed to allocate pci memory\n");
  4671. ret = -ENOMEM;
  4672. iwl3945_dealloc_ucode_pci(priv);
  4673. err_release:
  4674. release_firmware(ucode_raw);
  4675. error:
  4676. return ret;
  4677. }
  4678. /**
  4679. * iwl3945_set_ucode_ptrs - Set uCode address location
  4680. *
  4681. * Tell initialization uCode where to find runtime uCode.
  4682. *
  4683. * BSM registers initially contain pointers to initialization uCode.
  4684. * We need to replace them to load runtime uCode inst and data,
  4685. * and to save runtime data when powering down.
  4686. */
  4687. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4688. {
  4689. dma_addr_t pinst;
  4690. dma_addr_t pdata;
  4691. int rc = 0;
  4692. unsigned long flags;
  4693. /* bits 31:0 for 3945 */
  4694. pinst = priv->ucode_code.p_addr;
  4695. pdata = priv->ucode_data_backup.p_addr;
  4696. spin_lock_irqsave(&priv->lock, flags);
  4697. rc = iwl3945_grab_nic_access(priv);
  4698. if (rc) {
  4699. spin_unlock_irqrestore(&priv->lock, flags);
  4700. return rc;
  4701. }
  4702. /* Tell bootstrap uCode where to find image to load */
  4703. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4704. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4705. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4706. priv->ucode_data.len);
  4707. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4708. * that all new ptr/size info is in place */
  4709. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4710. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4711. iwl3945_release_nic_access(priv);
  4712. spin_unlock_irqrestore(&priv->lock, flags);
  4713. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4714. return rc;
  4715. }
  4716. /**
  4717. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4718. *
  4719. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4720. *
  4721. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4722. */
  4723. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4724. {
  4725. /* Check alive response for "valid" sign from uCode */
  4726. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4727. /* We had an error bringing up the hardware, so take it
  4728. * all the way back down so we can try again */
  4729. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4730. goto restart;
  4731. }
  4732. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4733. * This is a paranoid check, because we would not have gotten the
  4734. * "initialize" alive if code weren't properly loaded. */
  4735. if (iwl3945_verify_ucode(priv)) {
  4736. /* Runtime instruction load was bad;
  4737. * take it all the way back down so we can try again */
  4738. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4739. goto restart;
  4740. }
  4741. /* Send pointers to protocol/runtime uCode image ... init code will
  4742. * load and launch runtime uCode, which will send us another "Alive"
  4743. * notification. */
  4744. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4745. if (iwl3945_set_ucode_ptrs(priv)) {
  4746. /* Runtime instruction load won't happen;
  4747. * take it all the way back down so we can try again */
  4748. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4749. goto restart;
  4750. }
  4751. return;
  4752. restart:
  4753. queue_work(priv->workqueue, &priv->restart);
  4754. }
  4755. /**
  4756. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4757. * from protocol/runtime uCode (initialization uCode's
  4758. * Alive gets handled by iwl3945_init_alive_start()).
  4759. */
  4760. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4761. {
  4762. int rc = 0;
  4763. int thermal_spin = 0;
  4764. u32 rfkill;
  4765. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4766. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4767. /* We had an error bringing up the hardware, so take it
  4768. * all the way back down so we can try again */
  4769. IWL_DEBUG_INFO("Alive failed.\n");
  4770. goto restart;
  4771. }
  4772. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4773. * This is a paranoid check, because we would not have gotten the
  4774. * "runtime" alive if code weren't properly loaded. */
  4775. if (iwl3945_verify_ucode(priv)) {
  4776. /* Runtime instruction load was bad;
  4777. * take it all the way back down so we can try again */
  4778. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4779. goto restart;
  4780. }
  4781. iwl3945_clear_stations_table(priv);
  4782. rc = iwl3945_grab_nic_access(priv);
  4783. if (rc) {
  4784. IWL_WARNING("Can not read rfkill status from adapter\n");
  4785. return;
  4786. }
  4787. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4788. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4789. iwl3945_release_nic_access(priv);
  4790. if (rfkill & 0x1) {
  4791. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4792. /* if rfkill is not on, then wait for thermal
  4793. * sensor in adapter to kick in */
  4794. while (iwl3945_hw_get_temperature(priv) == 0) {
  4795. thermal_spin++;
  4796. udelay(10);
  4797. }
  4798. if (thermal_spin)
  4799. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4800. thermal_spin * 10);
  4801. } else
  4802. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4803. /* After the ALIVE response, we can send commands to 3945 uCode */
  4804. set_bit(STATUS_ALIVE, &priv->status);
  4805. /* Clear out the uCode error bit if it is set */
  4806. clear_bit(STATUS_FW_ERROR, &priv->status);
  4807. if (iwl3945_is_rfkill(priv))
  4808. return;
  4809. ieee80211_wake_queues(priv->hw);
  4810. priv->active_rate = priv->rates_mask;
  4811. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4812. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4813. if (iwl3945_is_associated(priv)) {
  4814. struct iwl3945_rxon_cmd *active_rxon =
  4815. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4816. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4817. sizeof(priv->staging_rxon));
  4818. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4819. } else {
  4820. /* Initialize our rx_config data */
  4821. iwl3945_connection_init_rx_config(priv);
  4822. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4823. }
  4824. /* Configure Bluetooth device coexistence support */
  4825. iwl3945_send_bt_config(priv);
  4826. /* Configure the adapter for unassociated operation */
  4827. iwl3945_commit_rxon(priv);
  4828. iwl3945_reg_txpower_periodic(priv);
  4829. iwl3945_led_register(priv);
  4830. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4831. set_bit(STATUS_READY, &priv->status);
  4832. wake_up_interruptible(&priv->wait_command_queue);
  4833. if (priv->error_recovering)
  4834. iwl3945_error_recovery(priv);
  4835. return;
  4836. restart:
  4837. queue_work(priv->workqueue, &priv->restart);
  4838. }
  4839. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4840. static void __iwl3945_down(struct iwl3945_priv *priv)
  4841. {
  4842. unsigned long flags;
  4843. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4844. struct ieee80211_conf *conf = NULL;
  4845. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4846. conf = ieee80211_get_hw_conf(priv->hw);
  4847. if (!exit_pending)
  4848. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4849. iwl3945_led_unregister(priv);
  4850. iwl3945_clear_stations_table(priv);
  4851. /* Unblock any waiting calls */
  4852. wake_up_interruptible_all(&priv->wait_command_queue);
  4853. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4854. * exiting the module */
  4855. if (!exit_pending)
  4856. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4857. /* stop and reset the on-board processor */
  4858. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4859. /* tell the device to stop sending interrupts */
  4860. spin_lock_irqsave(&priv->lock, flags);
  4861. iwl3945_disable_interrupts(priv);
  4862. spin_unlock_irqrestore(&priv->lock, flags);
  4863. iwl_synchronize_irq(priv);
  4864. if (priv->mac80211_registered)
  4865. ieee80211_stop_queues(priv->hw);
  4866. /* If we have not previously called iwl3945_init() then
  4867. * clear all bits but the RF Kill and SUSPEND bits and return */
  4868. if (!iwl3945_is_init(priv)) {
  4869. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4870. STATUS_RF_KILL_HW |
  4871. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4872. STATUS_RF_KILL_SW |
  4873. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4874. STATUS_GEO_CONFIGURED |
  4875. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4876. STATUS_IN_SUSPEND |
  4877. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4878. STATUS_EXIT_PENDING;
  4879. goto exit;
  4880. }
  4881. /* ...otherwise clear out all the status bits but the RF Kill and
  4882. * SUSPEND bits and continue taking the NIC down. */
  4883. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4884. STATUS_RF_KILL_HW |
  4885. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4886. STATUS_RF_KILL_SW |
  4887. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4888. STATUS_GEO_CONFIGURED |
  4889. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4890. STATUS_IN_SUSPEND |
  4891. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4892. STATUS_FW_ERROR |
  4893. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4894. STATUS_EXIT_PENDING;
  4895. spin_lock_irqsave(&priv->lock, flags);
  4896. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4897. spin_unlock_irqrestore(&priv->lock, flags);
  4898. iwl3945_hw_txq_ctx_stop(priv);
  4899. iwl3945_hw_rxq_stop(priv);
  4900. spin_lock_irqsave(&priv->lock, flags);
  4901. if (!iwl3945_grab_nic_access(priv)) {
  4902. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4903. APMG_CLK_VAL_DMA_CLK_RQT);
  4904. iwl3945_release_nic_access(priv);
  4905. }
  4906. spin_unlock_irqrestore(&priv->lock, flags);
  4907. udelay(5);
  4908. iwl3945_hw_nic_stop_master(priv);
  4909. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4910. iwl3945_hw_nic_reset(priv);
  4911. exit:
  4912. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  4913. if (priv->ibss_beacon)
  4914. dev_kfree_skb(priv->ibss_beacon);
  4915. priv->ibss_beacon = NULL;
  4916. /* clear out any free frames */
  4917. iwl3945_clear_free_frames(priv);
  4918. }
  4919. static void iwl3945_down(struct iwl3945_priv *priv)
  4920. {
  4921. mutex_lock(&priv->mutex);
  4922. __iwl3945_down(priv);
  4923. mutex_unlock(&priv->mutex);
  4924. iwl3945_cancel_deferred_work(priv);
  4925. }
  4926. #define MAX_HW_RESTARTS 5
  4927. static int __iwl3945_up(struct iwl3945_priv *priv)
  4928. {
  4929. int rc, i;
  4930. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4931. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4932. return -EIO;
  4933. }
  4934. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4935. IWL_WARNING("Radio disabled by SW RF kill (module "
  4936. "parameter)\n");
  4937. return -ENODEV;
  4938. }
  4939. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4940. IWL_ERROR("ucode not available for device bringup\n");
  4941. return -EIO;
  4942. }
  4943. /* If platform's RF_KILL switch is NOT set to KILL */
  4944. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  4945. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4946. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4947. else {
  4948. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4949. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4950. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4951. return -ENODEV;
  4952. }
  4953. }
  4954. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4955. rc = iwl3945_hw_nic_init(priv);
  4956. if (rc) {
  4957. IWL_ERROR("Unable to int nic\n");
  4958. return rc;
  4959. }
  4960. /* make sure rfkill handshake bits are cleared */
  4961. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4962. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4963. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4964. /* clear (again), then enable host interrupts */
  4965. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4966. iwl3945_enable_interrupts(priv);
  4967. /* really make sure rfkill handshake bits are cleared */
  4968. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4969. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4970. /* Copy original ucode data image from disk into backup cache.
  4971. * This will be used to initialize the on-board processor's
  4972. * data SRAM for a clean start when the runtime program first loads. */
  4973. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4974. priv->ucode_data.len);
  4975. /* We return success when we resume from suspend and rf_kill is on. */
  4976. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4977. return 0;
  4978. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4979. iwl3945_clear_stations_table(priv);
  4980. /* load bootstrap state machine,
  4981. * load bootstrap program into processor's memory,
  4982. * prepare to load the "initialize" uCode */
  4983. rc = iwl3945_load_bsm(priv);
  4984. if (rc) {
  4985. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4986. continue;
  4987. }
  4988. /* start card; "initialize" will load runtime ucode */
  4989. iwl3945_nic_start(priv);
  4990. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4991. return 0;
  4992. }
  4993. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4994. __iwl3945_down(priv);
  4995. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4996. /* tried to restart and config the device for as long as our
  4997. * patience could withstand */
  4998. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4999. return -EIO;
  5000. }
  5001. /*****************************************************************************
  5002. *
  5003. * Workqueue callbacks
  5004. *
  5005. *****************************************************************************/
  5006. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5007. {
  5008. struct iwl3945_priv *priv =
  5009. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5010. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5011. return;
  5012. mutex_lock(&priv->mutex);
  5013. iwl3945_init_alive_start(priv);
  5014. mutex_unlock(&priv->mutex);
  5015. }
  5016. static void iwl3945_bg_alive_start(struct work_struct *data)
  5017. {
  5018. struct iwl3945_priv *priv =
  5019. container_of(data, struct iwl3945_priv, alive_start.work);
  5020. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5021. return;
  5022. mutex_lock(&priv->mutex);
  5023. iwl3945_alive_start(priv);
  5024. mutex_unlock(&priv->mutex);
  5025. ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
  5026. }
  5027. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5028. {
  5029. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5030. wake_up_interruptible(&priv->wait_command_queue);
  5031. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5032. return;
  5033. mutex_lock(&priv->mutex);
  5034. if (!iwl3945_is_rfkill(priv)) {
  5035. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5036. "HW and/or SW RF Kill no longer active, restarting "
  5037. "device\n");
  5038. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5039. queue_work(priv->workqueue, &priv->restart);
  5040. } else {
  5041. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5042. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5043. "disabled by SW switch\n");
  5044. else
  5045. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5046. "Kill switch must be turned off for "
  5047. "wireless networking to work.\n");
  5048. }
  5049. mutex_unlock(&priv->mutex);
  5050. iwl3945_rfkill_set_hw_state(priv);
  5051. }
  5052. static void iwl3945_bg_set_monitor(struct work_struct *work)
  5053. {
  5054. struct iwl3945_priv *priv = container_of(work,
  5055. struct iwl3945_priv, set_monitor);
  5056. IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
  5057. mutex_lock(&priv->mutex);
  5058. if (!iwl3945_is_ready(priv))
  5059. IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
  5060. else
  5061. if (iwl3945_set_mode(priv, NL80211_IFTYPE_MONITOR) != 0)
  5062. IWL_ERROR("iwl3945_set_mode() failed\n");
  5063. mutex_unlock(&priv->mutex);
  5064. }
  5065. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5066. static void iwl3945_bg_scan_check(struct work_struct *data)
  5067. {
  5068. struct iwl3945_priv *priv =
  5069. container_of(data, struct iwl3945_priv, scan_check.work);
  5070. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5071. return;
  5072. mutex_lock(&priv->mutex);
  5073. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5074. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5075. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5076. "Scan completion watchdog resetting adapter (%dms)\n",
  5077. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5078. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5079. iwl3945_send_scan_abort(priv);
  5080. }
  5081. mutex_unlock(&priv->mutex);
  5082. }
  5083. static void iwl3945_bg_request_scan(struct work_struct *data)
  5084. {
  5085. struct iwl3945_priv *priv =
  5086. container_of(data, struct iwl3945_priv, request_scan);
  5087. struct iwl3945_host_cmd cmd = {
  5088. .id = REPLY_SCAN_CMD,
  5089. .len = sizeof(struct iwl3945_scan_cmd),
  5090. .meta.flags = CMD_SIZE_HUGE,
  5091. };
  5092. int rc = 0;
  5093. struct iwl3945_scan_cmd *scan;
  5094. struct ieee80211_conf *conf = NULL;
  5095. u8 n_probes = 2;
  5096. enum ieee80211_band band;
  5097. conf = ieee80211_get_hw_conf(priv->hw);
  5098. mutex_lock(&priv->mutex);
  5099. if (!iwl3945_is_ready(priv)) {
  5100. IWL_WARNING("request scan called when driver not ready.\n");
  5101. goto done;
  5102. }
  5103. /* Make sure the scan wasn't cancelled before this queued work
  5104. * was given the chance to run... */
  5105. if (!test_bit(STATUS_SCANNING, &priv->status))
  5106. goto done;
  5107. /* This should never be called or scheduled if there is currently
  5108. * a scan active in the hardware. */
  5109. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5110. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5111. "Ignoring second request.\n");
  5112. rc = -EIO;
  5113. goto done;
  5114. }
  5115. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5116. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5117. goto done;
  5118. }
  5119. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5120. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5121. goto done;
  5122. }
  5123. if (iwl3945_is_rfkill(priv)) {
  5124. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5125. goto done;
  5126. }
  5127. if (!test_bit(STATUS_READY, &priv->status)) {
  5128. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5129. goto done;
  5130. }
  5131. if (!priv->scan_bands) {
  5132. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5133. goto done;
  5134. }
  5135. if (!priv->scan) {
  5136. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5137. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5138. if (!priv->scan) {
  5139. rc = -ENOMEM;
  5140. goto done;
  5141. }
  5142. }
  5143. scan = priv->scan;
  5144. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5145. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5146. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5147. if (iwl3945_is_associated(priv)) {
  5148. u16 interval = 0;
  5149. u32 extra;
  5150. u32 suspend_time = 100;
  5151. u32 scan_suspend_time = 100;
  5152. unsigned long flags;
  5153. IWL_DEBUG_INFO("Scanning while associated...\n");
  5154. spin_lock_irqsave(&priv->lock, flags);
  5155. interval = priv->beacon_int;
  5156. spin_unlock_irqrestore(&priv->lock, flags);
  5157. scan->suspend_time = 0;
  5158. scan->max_out_time = cpu_to_le32(200 * 1024);
  5159. if (!interval)
  5160. interval = suspend_time;
  5161. /*
  5162. * suspend time format:
  5163. * 0-19: beacon interval in usec (time before exec.)
  5164. * 20-23: 0
  5165. * 24-31: number of beacons (suspend between channels)
  5166. */
  5167. extra = (suspend_time / interval) << 24;
  5168. scan_suspend_time = 0xFF0FFFFF &
  5169. (extra | ((suspend_time % interval) * 1024));
  5170. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5171. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5172. scan_suspend_time, interval);
  5173. }
  5174. /* We should add the ability for user to lock to PASSIVE ONLY */
  5175. if (priv->one_direct_scan) {
  5176. IWL_DEBUG_SCAN
  5177. ("Kicking off one direct scan for '%s'\n",
  5178. iwl3945_escape_essid(priv->direct_ssid,
  5179. priv->direct_ssid_len));
  5180. scan->direct_scan[0].id = WLAN_EID_SSID;
  5181. scan->direct_scan[0].len = priv->direct_ssid_len;
  5182. memcpy(scan->direct_scan[0].ssid,
  5183. priv->direct_ssid, priv->direct_ssid_len);
  5184. n_probes++;
  5185. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5186. IWL_DEBUG_SCAN
  5187. ("Kicking off one direct scan for '%s' when not associated\n",
  5188. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5189. scan->direct_scan[0].id = WLAN_EID_SSID;
  5190. scan->direct_scan[0].len = priv->essid_len;
  5191. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5192. n_probes++;
  5193. } else
  5194. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5195. /* We don't build a direct scan probe request; the uCode will do
  5196. * that based on the direct_mask added to each channel entry */
  5197. scan->tx_cmd.len = cpu_to_le16(
  5198. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5199. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5200. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5201. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5202. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5203. /* flags + rate selection */
  5204. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5205. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5206. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5207. scan->good_CRC_th = 0;
  5208. band = IEEE80211_BAND_2GHZ;
  5209. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5210. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5211. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5212. band = IEEE80211_BAND_5GHZ;
  5213. } else {
  5214. IWL_WARNING("Invalid scan band count\n");
  5215. goto done;
  5216. }
  5217. /* select Rx antennas */
  5218. scan->flags |= iwl3945_get_antenna_flags(priv);
  5219. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  5220. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5221. scan->channel_count =
  5222. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  5223. n_probes,
  5224. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5225. if (scan->channel_count == 0) {
  5226. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  5227. goto done;
  5228. }
  5229. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5230. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5231. cmd.data = scan;
  5232. scan->len = cpu_to_le16(cmd.len);
  5233. set_bit(STATUS_SCAN_HW, &priv->status);
  5234. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5235. if (rc)
  5236. goto done;
  5237. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5238. IWL_SCAN_CHECK_WATCHDOG);
  5239. mutex_unlock(&priv->mutex);
  5240. return;
  5241. done:
  5242. /* can not perform scan make sure we clear scanning
  5243. * bits from status so next scan request can be performed.
  5244. * if we dont clear scanning status bit here all next scan
  5245. * will fail
  5246. */
  5247. clear_bit(STATUS_SCAN_HW, &priv->status);
  5248. clear_bit(STATUS_SCANNING, &priv->status);
  5249. /* inform mac80211 scan aborted */
  5250. queue_work(priv->workqueue, &priv->scan_completed);
  5251. mutex_unlock(&priv->mutex);
  5252. }
  5253. static void iwl3945_bg_up(struct work_struct *data)
  5254. {
  5255. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5256. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5257. return;
  5258. mutex_lock(&priv->mutex);
  5259. __iwl3945_up(priv);
  5260. mutex_unlock(&priv->mutex);
  5261. iwl3945_rfkill_set_hw_state(priv);
  5262. }
  5263. static void iwl3945_bg_restart(struct work_struct *data)
  5264. {
  5265. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5266. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5267. return;
  5268. iwl3945_down(priv);
  5269. queue_work(priv->workqueue, &priv->up);
  5270. }
  5271. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5272. {
  5273. struct iwl3945_priv *priv =
  5274. container_of(data, struct iwl3945_priv, rx_replenish);
  5275. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5276. return;
  5277. mutex_lock(&priv->mutex);
  5278. iwl3945_rx_replenish(priv);
  5279. mutex_unlock(&priv->mutex);
  5280. }
  5281. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5282. static void iwl3945_post_associate(struct iwl3945_priv *priv)
  5283. {
  5284. int rc = 0;
  5285. struct ieee80211_conf *conf = NULL;
  5286. DECLARE_MAC_BUF(mac);
  5287. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5288. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5289. return;
  5290. }
  5291. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5292. priv->assoc_id,
  5293. print_mac(mac, priv->active_rxon.bssid_addr));
  5294. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5295. return;
  5296. if (!priv->vif || !priv->is_open)
  5297. return;
  5298. iwl3945_scan_cancel_timeout(priv, 200);
  5299. conf = ieee80211_get_hw_conf(priv->hw);
  5300. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5301. iwl3945_commit_rxon(priv);
  5302. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5303. iwl3945_setup_rxon_timing(priv);
  5304. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5305. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5306. if (rc)
  5307. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5308. "Attempting to continue.\n");
  5309. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5310. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5311. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5312. priv->assoc_id, priv->beacon_int);
  5313. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5314. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5315. else
  5316. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5317. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5318. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5319. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5320. else
  5321. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5322. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5323. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5324. }
  5325. iwl3945_commit_rxon(priv);
  5326. switch (priv->iw_mode) {
  5327. case NL80211_IFTYPE_STATION:
  5328. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5329. break;
  5330. case NL80211_IFTYPE_ADHOC:
  5331. /* clear out the station table */
  5332. iwl3945_clear_stations_table(priv);
  5333. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5334. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5335. iwl3945_sync_sta(priv, IWL_STA_ID,
  5336. (priv->band == IEEE80211_BAND_5GHZ) ?
  5337. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5338. CMD_ASYNC);
  5339. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5340. iwl3945_send_beacon_cmd(priv);
  5341. break;
  5342. default:
  5343. IWL_ERROR("%s Should not be called in %d mode\n",
  5344. __func__, priv->iw_mode);
  5345. break;
  5346. }
  5347. iwl3945_activate_qos(priv, 0);
  5348. /* we have just associated, don't start scan too early */
  5349. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5350. }
  5351. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5352. {
  5353. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5354. if (!iwl3945_is_ready(priv))
  5355. return;
  5356. mutex_lock(&priv->mutex);
  5357. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5358. iwl3945_send_scan_abort(priv);
  5359. mutex_unlock(&priv->mutex);
  5360. }
  5361. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5362. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5363. {
  5364. struct iwl3945_priv *priv =
  5365. container_of(work, struct iwl3945_priv, scan_completed);
  5366. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5367. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5368. return;
  5369. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5370. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5371. ieee80211_scan_completed(priv->hw);
  5372. /* Since setting the TXPOWER may have been deferred while
  5373. * performing the scan, fire one off */
  5374. mutex_lock(&priv->mutex);
  5375. iwl3945_hw_reg_send_txpower(priv);
  5376. mutex_unlock(&priv->mutex);
  5377. }
  5378. /*****************************************************************************
  5379. *
  5380. * mac80211 entry point functions
  5381. *
  5382. *****************************************************************************/
  5383. #define UCODE_READY_TIMEOUT (2 * HZ)
  5384. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5385. {
  5386. struct iwl3945_priv *priv = hw->priv;
  5387. int ret;
  5388. IWL_DEBUG_MAC80211("enter\n");
  5389. if (pci_enable_device(priv->pci_dev)) {
  5390. IWL_ERROR("Fail to pci_enable_device\n");
  5391. return -ENODEV;
  5392. }
  5393. pci_restore_state(priv->pci_dev);
  5394. pci_enable_msi(priv->pci_dev);
  5395. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5396. DRV_NAME, priv);
  5397. if (ret) {
  5398. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5399. goto out_disable_msi;
  5400. }
  5401. /* we should be verifying the device is ready to be opened */
  5402. mutex_lock(&priv->mutex);
  5403. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5404. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5405. * ucode filename and max sizes are card-specific. */
  5406. if (!priv->ucode_code.len) {
  5407. ret = iwl3945_read_ucode(priv);
  5408. if (ret) {
  5409. IWL_ERROR("Could not read microcode: %d\n", ret);
  5410. mutex_unlock(&priv->mutex);
  5411. goto out_release_irq;
  5412. }
  5413. }
  5414. ret = __iwl3945_up(priv);
  5415. mutex_unlock(&priv->mutex);
  5416. iwl3945_rfkill_set_hw_state(priv);
  5417. if (ret)
  5418. goto out_release_irq;
  5419. IWL_DEBUG_INFO("Start UP work.\n");
  5420. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5421. return 0;
  5422. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5423. * mac80211 will not be run successfully. */
  5424. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5425. test_bit(STATUS_READY, &priv->status),
  5426. UCODE_READY_TIMEOUT);
  5427. if (!ret) {
  5428. if (!test_bit(STATUS_READY, &priv->status)) {
  5429. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5430. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5431. ret = -ETIMEDOUT;
  5432. goto out_release_irq;
  5433. }
  5434. }
  5435. priv->is_open = 1;
  5436. IWL_DEBUG_MAC80211("leave\n");
  5437. return 0;
  5438. out_release_irq:
  5439. free_irq(priv->pci_dev->irq, priv);
  5440. out_disable_msi:
  5441. pci_disable_msi(priv->pci_dev);
  5442. pci_disable_device(priv->pci_dev);
  5443. priv->is_open = 0;
  5444. IWL_DEBUG_MAC80211("leave - failed\n");
  5445. return ret;
  5446. }
  5447. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5448. {
  5449. struct iwl3945_priv *priv = hw->priv;
  5450. IWL_DEBUG_MAC80211("enter\n");
  5451. if (!priv->is_open) {
  5452. IWL_DEBUG_MAC80211("leave - skip\n");
  5453. return;
  5454. }
  5455. priv->is_open = 0;
  5456. if (iwl3945_is_ready_rf(priv)) {
  5457. /* stop mac, cancel any scan request and clear
  5458. * RXON_FILTER_ASSOC_MSK BIT
  5459. */
  5460. mutex_lock(&priv->mutex);
  5461. iwl3945_scan_cancel_timeout(priv, 100);
  5462. mutex_unlock(&priv->mutex);
  5463. }
  5464. iwl3945_down(priv);
  5465. flush_workqueue(priv->workqueue);
  5466. free_irq(priv->pci_dev->irq, priv);
  5467. pci_disable_msi(priv->pci_dev);
  5468. pci_save_state(priv->pci_dev);
  5469. pci_disable_device(priv->pci_dev);
  5470. IWL_DEBUG_MAC80211("leave\n");
  5471. }
  5472. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5473. {
  5474. struct iwl3945_priv *priv = hw->priv;
  5475. IWL_DEBUG_MAC80211("enter\n");
  5476. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5477. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5478. if (iwl3945_tx_skb(priv, skb))
  5479. dev_kfree_skb_any(skb);
  5480. IWL_DEBUG_MAC80211("leave\n");
  5481. return 0;
  5482. }
  5483. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5484. struct ieee80211_if_init_conf *conf)
  5485. {
  5486. struct iwl3945_priv *priv = hw->priv;
  5487. unsigned long flags;
  5488. DECLARE_MAC_BUF(mac);
  5489. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5490. if (priv->vif) {
  5491. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5492. return -EOPNOTSUPP;
  5493. }
  5494. spin_lock_irqsave(&priv->lock, flags);
  5495. priv->vif = conf->vif;
  5496. spin_unlock_irqrestore(&priv->lock, flags);
  5497. mutex_lock(&priv->mutex);
  5498. if (conf->mac_addr) {
  5499. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5500. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5501. }
  5502. if (iwl3945_is_ready(priv))
  5503. iwl3945_set_mode(priv, conf->type);
  5504. mutex_unlock(&priv->mutex);
  5505. IWL_DEBUG_MAC80211("leave\n");
  5506. return 0;
  5507. }
  5508. /**
  5509. * iwl3945_mac_config - mac80211 config callback
  5510. *
  5511. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5512. * be set inappropriately and the driver currently sets the hardware up to
  5513. * use it whenever needed.
  5514. */
  5515. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5516. {
  5517. struct iwl3945_priv *priv = hw->priv;
  5518. const struct iwl3945_channel_info *ch_info;
  5519. unsigned long flags;
  5520. int ret = 0;
  5521. mutex_lock(&priv->mutex);
  5522. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5523. if (!iwl3945_is_ready(priv)) {
  5524. IWL_DEBUG_MAC80211("leave - not ready\n");
  5525. ret = -EIO;
  5526. goto out;
  5527. }
  5528. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5529. test_bit(STATUS_SCANNING, &priv->status))) {
  5530. IWL_DEBUG_MAC80211("leave - scanning\n");
  5531. set_bit(STATUS_CONF_PENDING, &priv->status);
  5532. mutex_unlock(&priv->mutex);
  5533. return 0;
  5534. }
  5535. spin_lock_irqsave(&priv->lock, flags);
  5536. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5537. conf->channel->hw_value);
  5538. if (!is_channel_valid(ch_info)) {
  5539. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5540. conf->channel->hw_value, conf->channel->band);
  5541. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5542. spin_unlock_irqrestore(&priv->lock, flags);
  5543. ret = -EINVAL;
  5544. goto out;
  5545. }
  5546. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5547. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5548. /* The list of supported rates and rate mask can be different
  5549. * for each phymode; since the phymode may have changed, reset
  5550. * the rate mask to what mac80211 lists */
  5551. iwl3945_set_rate(priv);
  5552. spin_unlock_irqrestore(&priv->lock, flags);
  5553. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5554. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5555. iwl3945_hw_channel_switch(priv, conf->channel);
  5556. goto out;
  5557. }
  5558. #endif
  5559. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5560. if (!conf->radio_enabled) {
  5561. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5562. goto out;
  5563. }
  5564. if (iwl3945_is_rfkill(priv)) {
  5565. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5566. ret = -EIO;
  5567. goto out;
  5568. }
  5569. iwl3945_set_rate(priv);
  5570. if (memcmp(&priv->active_rxon,
  5571. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5572. iwl3945_commit_rxon(priv);
  5573. else
  5574. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5575. IWL_DEBUG_MAC80211("leave\n");
  5576. out:
  5577. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5578. mutex_unlock(&priv->mutex);
  5579. return ret;
  5580. }
  5581. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5582. {
  5583. int rc = 0;
  5584. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5585. return;
  5586. /* The following should be done only at AP bring up */
  5587. if (!(iwl3945_is_associated(priv))) {
  5588. /* RXON - unassoc (to set timing command) */
  5589. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5590. iwl3945_commit_rxon(priv);
  5591. /* RXON Timing */
  5592. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5593. iwl3945_setup_rxon_timing(priv);
  5594. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5595. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5596. if (rc)
  5597. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5598. "Attempting to continue.\n");
  5599. /* FIXME: what should be the assoc_id for AP? */
  5600. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5601. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5602. priv->staging_rxon.flags |=
  5603. RXON_FLG_SHORT_PREAMBLE_MSK;
  5604. else
  5605. priv->staging_rxon.flags &=
  5606. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5607. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5608. if (priv->assoc_capability &
  5609. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5610. priv->staging_rxon.flags |=
  5611. RXON_FLG_SHORT_SLOT_MSK;
  5612. else
  5613. priv->staging_rxon.flags &=
  5614. ~RXON_FLG_SHORT_SLOT_MSK;
  5615. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5616. priv->staging_rxon.flags &=
  5617. ~RXON_FLG_SHORT_SLOT_MSK;
  5618. }
  5619. /* restore RXON assoc */
  5620. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5621. iwl3945_commit_rxon(priv);
  5622. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5623. }
  5624. iwl3945_send_beacon_cmd(priv);
  5625. /* FIXME - we need to add code here to detect a totally new
  5626. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5627. * clear sta table, add BCAST sta... */
  5628. }
  5629. /* temporary */
  5630. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
  5631. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5632. struct ieee80211_vif *vif,
  5633. struct ieee80211_if_conf *conf)
  5634. {
  5635. struct iwl3945_priv *priv = hw->priv;
  5636. DECLARE_MAC_BUF(mac);
  5637. unsigned long flags;
  5638. int rc;
  5639. if (conf == NULL)
  5640. return -EIO;
  5641. if (priv->vif != vif) {
  5642. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5643. return 0;
  5644. }
  5645. /* handle this temporarily here */
  5646. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5647. conf->changed & IEEE80211_IFCC_BEACON) {
  5648. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5649. if (!beacon)
  5650. return -ENOMEM;
  5651. rc = iwl3945_mac_beacon_update(hw, beacon);
  5652. if (rc)
  5653. return rc;
  5654. }
  5655. /* XXX: this MUST use conf->mac_addr */
  5656. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  5657. (!conf->ssid_len)) {
  5658. IWL_DEBUG_MAC80211
  5659. ("Leaving in AP mode because HostAPD is not ready.\n");
  5660. return 0;
  5661. }
  5662. if (!iwl3945_is_alive(priv))
  5663. return -EAGAIN;
  5664. mutex_lock(&priv->mutex);
  5665. if (conf->bssid)
  5666. IWL_DEBUG_MAC80211("bssid: %s\n",
  5667. print_mac(mac, conf->bssid));
  5668. /*
  5669. * very dubious code was here; the probe filtering flag is never set:
  5670. *
  5671. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5672. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5673. */
  5674. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5675. if (!conf->bssid) {
  5676. conf->bssid = priv->mac_addr;
  5677. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5678. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5679. print_mac(mac, conf->bssid));
  5680. }
  5681. if (priv->ibss_beacon)
  5682. dev_kfree_skb(priv->ibss_beacon);
  5683. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5684. }
  5685. if (iwl3945_is_rfkill(priv))
  5686. goto done;
  5687. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5688. !is_multicast_ether_addr(conf->bssid)) {
  5689. /* If there is currently a HW scan going on in the background
  5690. * then we need to cancel it else the RXON below will fail. */
  5691. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5692. IWL_WARNING("Aborted scan still in progress "
  5693. "after 100ms\n");
  5694. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5695. mutex_unlock(&priv->mutex);
  5696. return -EAGAIN;
  5697. }
  5698. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5699. /* TODO: Audit driver for usage of these members and see
  5700. * if mac80211 deprecates them (priv->bssid looks like it
  5701. * shouldn't be there, but I haven't scanned the IBSS code
  5702. * to verify) - jpk */
  5703. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5704. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5705. iwl3945_config_ap(priv);
  5706. else {
  5707. rc = iwl3945_commit_rxon(priv);
  5708. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5709. iwl3945_add_station(priv,
  5710. priv->active_rxon.bssid_addr, 1, 0);
  5711. }
  5712. } else {
  5713. iwl3945_scan_cancel_timeout(priv, 100);
  5714. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5715. iwl3945_commit_rxon(priv);
  5716. }
  5717. done:
  5718. spin_lock_irqsave(&priv->lock, flags);
  5719. if (!conf->ssid_len)
  5720. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5721. else
  5722. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5723. priv->essid_len = conf->ssid_len;
  5724. spin_unlock_irqrestore(&priv->lock, flags);
  5725. IWL_DEBUG_MAC80211("leave\n");
  5726. mutex_unlock(&priv->mutex);
  5727. return 0;
  5728. }
  5729. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5730. unsigned int changed_flags,
  5731. unsigned int *total_flags,
  5732. int mc_count, struct dev_addr_list *mc_list)
  5733. {
  5734. struct iwl3945_priv *priv = hw->priv;
  5735. if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
  5736. IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
  5737. NL80211_IFTYPE_MONITOR,
  5738. changed_flags, *total_flags);
  5739. /* queue work 'cuz mac80211 is holding a lock which
  5740. * prevents us from issuing (synchronous) f/w cmds */
  5741. queue_work(priv->workqueue, &priv->set_monitor);
  5742. }
  5743. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
  5744. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5745. }
  5746. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5747. struct ieee80211_if_init_conf *conf)
  5748. {
  5749. struct iwl3945_priv *priv = hw->priv;
  5750. IWL_DEBUG_MAC80211("enter\n");
  5751. mutex_lock(&priv->mutex);
  5752. if (iwl3945_is_ready_rf(priv)) {
  5753. iwl3945_scan_cancel_timeout(priv, 100);
  5754. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5755. iwl3945_commit_rxon(priv);
  5756. }
  5757. if (priv->vif == conf->vif) {
  5758. priv->vif = NULL;
  5759. memset(priv->bssid, 0, ETH_ALEN);
  5760. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5761. priv->essid_len = 0;
  5762. }
  5763. mutex_unlock(&priv->mutex);
  5764. IWL_DEBUG_MAC80211("leave\n");
  5765. }
  5766. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5767. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5768. struct ieee80211_vif *vif,
  5769. struct ieee80211_bss_conf *bss_conf,
  5770. u32 changes)
  5771. {
  5772. struct iwl3945_priv *priv = hw->priv;
  5773. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5774. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5775. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5776. bss_conf->use_short_preamble);
  5777. if (bss_conf->use_short_preamble)
  5778. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5779. else
  5780. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5781. }
  5782. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5783. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5784. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5785. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5786. else
  5787. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5788. }
  5789. if (changes & BSS_CHANGED_ASSOC) {
  5790. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5791. /* This should never happen as this function should
  5792. * never be called from interrupt context. */
  5793. if (WARN_ON_ONCE(in_interrupt()))
  5794. return;
  5795. if (bss_conf->assoc) {
  5796. priv->assoc_id = bss_conf->aid;
  5797. priv->beacon_int = bss_conf->beacon_int;
  5798. priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
  5799. priv->timestamp1 = (bss_conf->timestamp >> 32) &
  5800. 0xFFFFFFFF;
  5801. priv->assoc_capability = bss_conf->assoc_capability;
  5802. priv->next_scan_jiffies = jiffies +
  5803. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5804. mutex_lock(&priv->mutex);
  5805. iwl3945_post_associate(priv);
  5806. mutex_unlock(&priv->mutex);
  5807. } else {
  5808. priv->assoc_id = 0;
  5809. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5810. }
  5811. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5812. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5813. iwl3945_send_rxon_assoc(priv);
  5814. }
  5815. }
  5816. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5817. {
  5818. int rc = 0;
  5819. unsigned long flags;
  5820. struct iwl3945_priv *priv = hw->priv;
  5821. IWL_DEBUG_MAC80211("enter\n");
  5822. mutex_lock(&priv->mutex);
  5823. spin_lock_irqsave(&priv->lock, flags);
  5824. if (!iwl3945_is_ready_rf(priv)) {
  5825. rc = -EIO;
  5826. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5827. goto out_unlock;
  5828. }
  5829. if (priv->iw_mode == NL80211_IFTYPE_AP) { /* APs don't scan */
  5830. rc = -EIO;
  5831. IWL_ERROR("ERROR: APs don't scan\n");
  5832. goto out_unlock;
  5833. }
  5834. /* we don't schedule scan within next_scan_jiffies period */
  5835. if (priv->next_scan_jiffies &&
  5836. time_after(priv->next_scan_jiffies, jiffies)) {
  5837. rc = -EAGAIN;
  5838. goto out_unlock;
  5839. }
  5840. /* if we just finished scan ask for delay for a broadcast scan */
  5841. if ((len == 0) && priv->last_scan_jiffies &&
  5842. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5843. jiffies)) {
  5844. rc = -EAGAIN;
  5845. goto out_unlock;
  5846. }
  5847. if (len) {
  5848. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5849. iwl3945_escape_essid(ssid, len), (int)len);
  5850. priv->one_direct_scan = 1;
  5851. priv->direct_ssid_len = (u8)
  5852. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5853. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5854. } else
  5855. priv->one_direct_scan = 0;
  5856. rc = iwl3945_scan_initiate(priv);
  5857. IWL_DEBUG_MAC80211("leave\n");
  5858. out_unlock:
  5859. spin_unlock_irqrestore(&priv->lock, flags);
  5860. mutex_unlock(&priv->mutex);
  5861. return rc;
  5862. }
  5863. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5864. const u8 *local_addr, const u8 *addr,
  5865. struct ieee80211_key_conf *key)
  5866. {
  5867. struct iwl3945_priv *priv = hw->priv;
  5868. int rc = 0;
  5869. u8 sta_id;
  5870. IWL_DEBUG_MAC80211("enter\n");
  5871. if (!iwl3945_param_hwcrypto) {
  5872. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5873. return -EOPNOTSUPP;
  5874. }
  5875. if (is_zero_ether_addr(addr))
  5876. /* only support pairwise keys */
  5877. return -EOPNOTSUPP;
  5878. sta_id = iwl3945_hw_find_station(priv, addr);
  5879. if (sta_id == IWL_INVALID_STATION) {
  5880. DECLARE_MAC_BUF(mac);
  5881. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  5882. print_mac(mac, addr));
  5883. return -EINVAL;
  5884. }
  5885. mutex_lock(&priv->mutex);
  5886. iwl3945_scan_cancel_timeout(priv, 100);
  5887. switch (cmd) {
  5888. case SET_KEY:
  5889. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5890. if (!rc) {
  5891. iwl3945_set_rxon_hwcrypto(priv, 1);
  5892. iwl3945_commit_rxon(priv);
  5893. key->hw_key_idx = sta_id;
  5894. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5895. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5896. }
  5897. break;
  5898. case DISABLE_KEY:
  5899. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5900. if (!rc) {
  5901. iwl3945_set_rxon_hwcrypto(priv, 0);
  5902. iwl3945_commit_rxon(priv);
  5903. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5904. }
  5905. break;
  5906. default:
  5907. rc = -EINVAL;
  5908. }
  5909. IWL_DEBUG_MAC80211("leave\n");
  5910. mutex_unlock(&priv->mutex);
  5911. return rc;
  5912. }
  5913. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5914. const struct ieee80211_tx_queue_params *params)
  5915. {
  5916. struct iwl3945_priv *priv = hw->priv;
  5917. unsigned long flags;
  5918. int q;
  5919. IWL_DEBUG_MAC80211("enter\n");
  5920. if (!iwl3945_is_ready_rf(priv)) {
  5921. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5922. return -EIO;
  5923. }
  5924. if (queue >= AC_NUM) {
  5925. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5926. return 0;
  5927. }
  5928. if (!priv->qos_data.qos_enable) {
  5929. priv->qos_data.qos_active = 0;
  5930. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  5931. return 0;
  5932. }
  5933. q = AC_NUM - 1 - queue;
  5934. spin_lock_irqsave(&priv->lock, flags);
  5935. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5936. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5937. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5938. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5939. cpu_to_le16((params->txop * 32));
  5940. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5941. priv->qos_data.qos_active = 1;
  5942. spin_unlock_irqrestore(&priv->lock, flags);
  5943. mutex_lock(&priv->mutex);
  5944. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5945. iwl3945_activate_qos(priv, 1);
  5946. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5947. iwl3945_activate_qos(priv, 0);
  5948. mutex_unlock(&priv->mutex);
  5949. IWL_DEBUG_MAC80211("leave\n");
  5950. return 0;
  5951. }
  5952. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5953. struct ieee80211_tx_queue_stats *stats)
  5954. {
  5955. struct iwl3945_priv *priv = hw->priv;
  5956. int i, avail;
  5957. struct iwl3945_tx_queue *txq;
  5958. struct iwl3945_queue *q;
  5959. unsigned long flags;
  5960. IWL_DEBUG_MAC80211("enter\n");
  5961. if (!iwl3945_is_ready_rf(priv)) {
  5962. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5963. return -EIO;
  5964. }
  5965. spin_lock_irqsave(&priv->lock, flags);
  5966. for (i = 0; i < AC_NUM; i++) {
  5967. txq = &priv->txq[i];
  5968. q = &txq->q;
  5969. avail = iwl3945_queue_space(q);
  5970. stats[i].len = q->n_window - avail;
  5971. stats[i].limit = q->n_window - q->high_mark;
  5972. stats[i].count = q->n_window;
  5973. }
  5974. spin_unlock_irqrestore(&priv->lock, flags);
  5975. IWL_DEBUG_MAC80211("leave\n");
  5976. return 0;
  5977. }
  5978. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  5979. struct ieee80211_low_level_stats *stats)
  5980. {
  5981. IWL_DEBUG_MAC80211("enter\n");
  5982. IWL_DEBUG_MAC80211("leave\n");
  5983. return 0;
  5984. }
  5985. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  5986. {
  5987. IWL_DEBUG_MAC80211("enter\n");
  5988. IWL_DEBUG_MAC80211("leave\n");
  5989. return 0;
  5990. }
  5991. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5992. {
  5993. struct iwl3945_priv *priv = hw->priv;
  5994. unsigned long flags;
  5995. mutex_lock(&priv->mutex);
  5996. IWL_DEBUG_MAC80211("enter\n");
  5997. iwl3945_reset_qos(priv);
  5998. spin_lock_irqsave(&priv->lock, flags);
  5999. priv->assoc_id = 0;
  6000. priv->assoc_capability = 0;
  6001. priv->call_post_assoc_from_beacon = 0;
  6002. /* new association get rid of ibss beacon skb */
  6003. if (priv->ibss_beacon)
  6004. dev_kfree_skb(priv->ibss_beacon);
  6005. priv->ibss_beacon = NULL;
  6006. priv->beacon_int = priv->hw->conf.beacon_int;
  6007. priv->timestamp1 = 0;
  6008. priv->timestamp0 = 0;
  6009. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  6010. priv->beacon_int = 0;
  6011. spin_unlock_irqrestore(&priv->lock, flags);
  6012. if (!iwl3945_is_ready_rf(priv)) {
  6013. IWL_DEBUG_MAC80211("leave - not ready\n");
  6014. mutex_unlock(&priv->mutex);
  6015. return;
  6016. }
  6017. /* we are restarting association process
  6018. * clear RXON_FILTER_ASSOC_MSK bit
  6019. */
  6020. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  6021. iwl3945_scan_cancel_timeout(priv, 100);
  6022. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6023. iwl3945_commit_rxon(priv);
  6024. }
  6025. /* Per mac80211.h: This is only used in IBSS mode... */
  6026. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  6027. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6028. mutex_unlock(&priv->mutex);
  6029. return;
  6030. }
  6031. iwl3945_set_rate(priv);
  6032. mutex_unlock(&priv->mutex);
  6033. IWL_DEBUG_MAC80211("leave\n");
  6034. }
  6035. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  6036. {
  6037. struct iwl3945_priv *priv = hw->priv;
  6038. unsigned long flags;
  6039. mutex_lock(&priv->mutex);
  6040. IWL_DEBUG_MAC80211("enter\n");
  6041. if (!iwl3945_is_ready_rf(priv)) {
  6042. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6043. mutex_unlock(&priv->mutex);
  6044. return -EIO;
  6045. }
  6046. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  6047. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6048. mutex_unlock(&priv->mutex);
  6049. return -EIO;
  6050. }
  6051. spin_lock_irqsave(&priv->lock, flags);
  6052. if (priv->ibss_beacon)
  6053. dev_kfree_skb(priv->ibss_beacon);
  6054. priv->ibss_beacon = skb;
  6055. priv->assoc_id = 0;
  6056. IWL_DEBUG_MAC80211("leave\n");
  6057. spin_unlock_irqrestore(&priv->lock, flags);
  6058. iwl3945_reset_qos(priv);
  6059. iwl3945_post_associate(priv);
  6060. mutex_unlock(&priv->mutex);
  6061. return 0;
  6062. }
  6063. /*****************************************************************************
  6064. *
  6065. * sysfs attributes
  6066. *
  6067. *****************************************************************************/
  6068. #ifdef CONFIG_IWL3945_DEBUG
  6069. /*
  6070. * The following adds a new attribute to the sysfs representation
  6071. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6072. * used for controlling the debug level.
  6073. *
  6074. * See the level definitions in iwl for details.
  6075. */
  6076. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6077. {
  6078. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6079. }
  6080. static ssize_t store_debug_level(struct device_driver *d,
  6081. const char *buf, size_t count)
  6082. {
  6083. char *p = (char *)buf;
  6084. u32 val;
  6085. val = simple_strtoul(p, &p, 0);
  6086. if (p == buf)
  6087. printk(KERN_INFO DRV_NAME
  6088. ": %s is not in hex or decimal form.\n", buf);
  6089. else
  6090. iwl3945_debug_level = val;
  6091. return strnlen(buf, count);
  6092. }
  6093. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6094. show_debug_level, store_debug_level);
  6095. #endif /* CONFIG_IWL3945_DEBUG */
  6096. static ssize_t show_temperature(struct device *d,
  6097. struct device_attribute *attr, char *buf)
  6098. {
  6099. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6100. if (!iwl3945_is_alive(priv))
  6101. return -EAGAIN;
  6102. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6103. }
  6104. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6105. static ssize_t show_tx_power(struct device *d,
  6106. struct device_attribute *attr, char *buf)
  6107. {
  6108. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6109. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6110. }
  6111. static ssize_t store_tx_power(struct device *d,
  6112. struct device_attribute *attr,
  6113. const char *buf, size_t count)
  6114. {
  6115. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6116. char *p = (char *)buf;
  6117. u32 val;
  6118. val = simple_strtoul(p, &p, 10);
  6119. if (p == buf)
  6120. printk(KERN_INFO DRV_NAME
  6121. ": %s is not in decimal form.\n", buf);
  6122. else
  6123. iwl3945_hw_reg_set_txpower(priv, val);
  6124. return count;
  6125. }
  6126. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6127. static ssize_t show_flags(struct device *d,
  6128. struct device_attribute *attr, char *buf)
  6129. {
  6130. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6131. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6132. }
  6133. static ssize_t store_flags(struct device *d,
  6134. struct device_attribute *attr,
  6135. const char *buf, size_t count)
  6136. {
  6137. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6138. u32 flags = simple_strtoul(buf, NULL, 0);
  6139. mutex_lock(&priv->mutex);
  6140. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6141. /* Cancel any currently running scans... */
  6142. if (iwl3945_scan_cancel_timeout(priv, 100))
  6143. IWL_WARNING("Could not cancel scan.\n");
  6144. else {
  6145. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6146. flags);
  6147. priv->staging_rxon.flags = cpu_to_le32(flags);
  6148. iwl3945_commit_rxon(priv);
  6149. }
  6150. }
  6151. mutex_unlock(&priv->mutex);
  6152. return count;
  6153. }
  6154. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6155. static ssize_t show_filter_flags(struct device *d,
  6156. struct device_attribute *attr, char *buf)
  6157. {
  6158. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6159. return sprintf(buf, "0x%04X\n",
  6160. le32_to_cpu(priv->active_rxon.filter_flags));
  6161. }
  6162. static ssize_t store_filter_flags(struct device *d,
  6163. struct device_attribute *attr,
  6164. const char *buf, size_t count)
  6165. {
  6166. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6167. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6168. mutex_lock(&priv->mutex);
  6169. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6170. /* Cancel any currently running scans... */
  6171. if (iwl3945_scan_cancel_timeout(priv, 100))
  6172. IWL_WARNING("Could not cancel scan.\n");
  6173. else {
  6174. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6175. "0x%04X\n", filter_flags);
  6176. priv->staging_rxon.filter_flags =
  6177. cpu_to_le32(filter_flags);
  6178. iwl3945_commit_rxon(priv);
  6179. }
  6180. }
  6181. mutex_unlock(&priv->mutex);
  6182. return count;
  6183. }
  6184. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6185. store_filter_flags);
  6186. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6187. static ssize_t show_measurement(struct device *d,
  6188. struct device_attribute *attr, char *buf)
  6189. {
  6190. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6191. struct iwl3945_spectrum_notification measure_report;
  6192. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6193. u8 *data = (u8 *)&measure_report;
  6194. unsigned long flags;
  6195. spin_lock_irqsave(&priv->lock, flags);
  6196. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6197. spin_unlock_irqrestore(&priv->lock, flags);
  6198. return 0;
  6199. }
  6200. memcpy(&measure_report, &priv->measure_report, size);
  6201. priv->measurement_status = 0;
  6202. spin_unlock_irqrestore(&priv->lock, flags);
  6203. while (size && (PAGE_SIZE - len)) {
  6204. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6205. PAGE_SIZE - len, 1);
  6206. len = strlen(buf);
  6207. if (PAGE_SIZE - len)
  6208. buf[len++] = '\n';
  6209. ofs += 16;
  6210. size -= min(size, 16U);
  6211. }
  6212. return len;
  6213. }
  6214. static ssize_t store_measurement(struct device *d,
  6215. struct device_attribute *attr,
  6216. const char *buf, size_t count)
  6217. {
  6218. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6219. struct ieee80211_measurement_params params = {
  6220. .channel = le16_to_cpu(priv->active_rxon.channel),
  6221. .start_time = cpu_to_le64(priv->last_tsf),
  6222. .duration = cpu_to_le16(1),
  6223. };
  6224. u8 type = IWL_MEASURE_BASIC;
  6225. u8 buffer[32];
  6226. u8 channel;
  6227. if (count) {
  6228. char *p = buffer;
  6229. strncpy(buffer, buf, min(sizeof(buffer), count));
  6230. channel = simple_strtoul(p, NULL, 0);
  6231. if (channel)
  6232. params.channel = channel;
  6233. p = buffer;
  6234. while (*p && *p != ' ')
  6235. p++;
  6236. if (*p)
  6237. type = simple_strtoul(p + 1, NULL, 0);
  6238. }
  6239. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6240. "channel %d (for '%s')\n", type, params.channel, buf);
  6241. iwl3945_get_measurement(priv, &params, type);
  6242. return count;
  6243. }
  6244. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6245. show_measurement, store_measurement);
  6246. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6247. static ssize_t store_retry_rate(struct device *d,
  6248. struct device_attribute *attr,
  6249. const char *buf, size_t count)
  6250. {
  6251. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6252. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6253. if (priv->retry_rate <= 0)
  6254. priv->retry_rate = 1;
  6255. return count;
  6256. }
  6257. static ssize_t show_retry_rate(struct device *d,
  6258. struct device_attribute *attr, char *buf)
  6259. {
  6260. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6261. return sprintf(buf, "%d", priv->retry_rate);
  6262. }
  6263. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6264. store_retry_rate);
  6265. static ssize_t store_power_level(struct device *d,
  6266. struct device_attribute *attr,
  6267. const char *buf, size_t count)
  6268. {
  6269. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6270. int rc;
  6271. int mode;
  6272. mode = simple_strtoul(buf, NULL, 0);
  6273. mutex_lock(&priv->mutex);
  6274. if (!iwl3945_is_ready(priv)) {
  6275. rc = -EAGAIN;
  6276. goto out;
  6277. }
  6278. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6279. mode = IWL_POWER_AC;
  6280. else
  6281. mode |= IWL_POWER_ENABLED;
  6282. if (mode != priv->power_mode) {
  6283. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6284. if (rc) {
  6285. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6286. goto out;
  6287. }
  6288. priv->power_mode = mode;
  6289. }
  6290. rc = count;
  6291. out:
  6292. mutex_unlock(&priv->mutex);
  6293. return rc;
  6294. }
  6295. #define MAX_WX_STRING 80
  6296. /* Values are in microsecond */
  6297. static const s32 timeout_duration[] = {
  6298. 350000,
  6299. 250000,
  6300. 75000,
  6301. 37000,
  6302. 25000,
  6303. };
  6304. static const s32 period_duration[] = {
  6305. 400000,
  6306. 700000,
  6307. 1000000,
  6308. 1000000,
  6309. 1000000
  6310. };
  6311. static ssize_t show_power_level(struct device *d,
  6312. struct device_attribute *attr, char *buf)
  6313. {
  6314. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6315. int level = IWL_POWER_LEVEL(priv->power_mode);
  6316. char *p = buf;
  6317. p += sprintf(p, "%d ", level);
  6318. switch (level) {
  6319. case IWL_POWER_MODE_CAM:
  6320. case IWL_POWER_AC:
  6321. p += sprintf(p, "(AC)");
  6322. break;
  6323. case IWL_POWER_BATTERY:
  6324. p += sprintf(p, "(BATTERY)");
  6325. break;
  6326. default:
  6327. p += sprintf(p,
  6328. "(Timeout %dms, Period %dms)",
  6329. timeout_duration[level - 1] / 1000,
  6330. period_duration[level - 1] / 1000);
  6331. }
  6332. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6333. p += sprintf(p, " OFF\n");
  6334. else
  6335. p += sprintf(p, " \n");
  6336. return p - buf + 1;
  6337. }
  6338. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6339. store_power_level);
  6340. static ssize_t show_channels(struct device *d,
  6341. struct device_attribute *attr, char *buf)
  6342. {
  6343. /* all this shit doesn't belong into sysfs anyway */
  6344. return 0;
  6345. }
  6346. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6347. static ssize_t show_statistics(struct device *d,
  6348. struct device_attribute *attr, char *buf)
  6349. {
  6350. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6351. u32 size = sizeof(struct iwl3945_notif_statistics);
  6352. u32 len = 0, ofs = 0;
  6353. u8 *data = (u8 *)&priv->statistics;
  6354. int rc = 0;
  6355. if (!iwl3945_is_alive(priv))
  6356. return -EAGAIN;
  6357. mutex_lock(&priv->mutex);
  6358. rc = iwl3945_send_statistics_request(priv);
  6359. mutex_unlock(&priv->mutex);
  6360. if (rc) {
  6361. len = sprintf(buf,
  6362. "Error sending statistics request: 0x%08X\n", rc);
  6363. return len;
  6364. }
  6365. while (size && (PAGE_SIZE - len)) {
  6366. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6367. PAGE_SIZE - len, 1);
  6368. len = strlen(buf);
  6369. if (PAGE_SIZE - len)
  6370. buf[len++] = '\n';
  6371. ofs += 16;
  6372. size -= min(size, 16U);
  6373. }
  6374. return len;
  6375. }
  6376. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6377. static ssize_t show_antenna(struct device *d,
  6378. struct device_attribute *attr, char *buf)
  6379. {
  6380. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6381. if (!iwl3945_is_alive(priv))
  6382. return -EAGAIN;
  6383. return sprintf(buf, "%d\n", priv->antenna);
  6384. }
  6385. static ssize_t store_antenna(struct device *d,
  6386. struct device_attribute *attr,
  6387. const char *buf, size_t count)
  6388. {
  6389. int ant;
  6390. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6391. if (count == 0)
  6392. return 0;
  6393. if (sscanf(buf, "%1i", &ant) != 1) {
  6394. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6395. return count;
  6396. }
  6397. if ((ant >= 0) && (ant <= 2)) {
  6398. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6399. priv->antenna = (enum iwl3945_antenna)ant;
  6400. } else
  6401. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6402. return count;
  6403. }
  6404. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6405. static ssize_t show_status(struct device *d,
  6406. struct device_attribute *attr, char *buf)
  6407. {
  6408. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6409. if (!iwl3945_is_alive(priv))
  6410. return -EAGAIN;
  6411. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6412. }
  6413. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6414. static ssize_t dump_error_log(struct device *d,
  6415. struct device_attribute *attr,
  6416. const char *buf, size_t count)
  6417. {
  6418. char *p = (char *)buf;
  6419. if (p[0] == '1')
  6420. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6421. return strnlen(buf, count);
  6422. }
  6423. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6424. static ssize_t dump_event_log(struct device *d,
  6425. struct device_attribute *attr,
  6426. const char *buf, size_t count)
  6427. {
  6428. char *p = (char *)buf;
  6429. if (p[0] == '1')
  6430. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6431. return strnlen(buf, count);
  6432. }
  6433. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6434. /*****************************************************************************
  6435. *
  6436. * driver setup and teardown
  6437. *
  6438. *****************************************************************************/
  6439. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6440. {
  6441. priv->workqueue = create_workqueue(DRV_NAME);
  6442. init_waitqueue_head(&priv->wait_command_queue);
  6443. INIT_WORK(&priv->up, iwl3945_bg_up);
  6444. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6445. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6446. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6447. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6448. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6449. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6450. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6451. INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
  6452. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6453. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6454. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6455. iwl3945_hw_setup_deferred_work(priv);
  6456. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6457. iwl3945_irq_tasklet, (unsigned long)priv);
  6458. }
  6459. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6460. {
  6461. iwl3945_hw_cancel_deferred_work(priv);
  6462. cancel_delayed_work_sync(&priv->init_alive_start);
  6463. cancel_delayed_work(&priv->scan_check);
  6464. cancel_delayed_work(&priv->alive_start);
  6465. cancel_work_sync(&priv->beacon_update);
  6466. }
  6467. static struct attribute *iwl3945_sysfs_entries[] = {
  6468. &dev_attr_antenna.attr,
  6469. &dev_attr_channels.attr,
  6470. &dev_attr_dump_errors.attr,
  6471. &dev_attr_dump_events.attr,
  6472. &dev_attr_flags.attr,
  6473. &dev_attr_filter_flags.attr,
  6474. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6475. &dev_attr_measurement.attr,
  6476. #endif
  6477. &dev_attr_power_level.attr,
  6478. &dev_attr_retry_rate.attr,
  6479. &dev_attr_statistics.attr,
  6480. &dev_attr_status.attr,
  6481. &dev_attr_temperature.attr,
  6482. &dev_attr_tx_power.attr,
  6483. NULL
  6484. };
  6485. static struct attribute_group iwl3945_attribute_group = {
  6486. .name = NULL, /* put in device directory */
  6487. .attrs = iwl3945_sysfs_entries,
  6488. };
  6489. static struct ieee80211_ops iwl3945_hw_ops = {
  6490. .tx = iwl3945_mac_tx,
  6491. .start = iwl3945_mac_start,
  6492. .stop = iwl3945_mac_stop,
  6493. .add_interface = iwl3945_mac_add_interface,
  6494. .remove_interface = iwl3945_mac_remove_interface,
  6495. .config = iwl3945_mac_config,
  6496. .config_interface = iwl3945_mac_config_interface,
  6497. .configure_filter = iwl3945_configure_filter,
  6498. .set_key = iwl3945_mac_set_key,
  6499. .get_stats = iwl3945_mac_get_stats,
  6500. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6501. .conf_tx = iwl3945_mac_conf_tx,
  6502. .get_tsf = iwl3945_mac_get_tsf,
  6503. .reset_tsf = iwl3945_mac_reset_tsf,
  6504. .bss_info_changed = iwl3945_bss_info_changed,
  6505. .hw_scan = iwl3945_mac_hw_scan
  6506. };
  6507. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6508. {
  6509. int err = 0;
  6510. struct iwl3945_priv *priv;
  6511. struct ieee80211_hw *hw;
  6512. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6513. unsigned long flags;
  6514. DECLARE_MAC_BUF(mac);
  6515. /* Disabling hardware scan means that mac80211 will perform scans
  6516. * "the hard way", rather than using device's scan. */
  6517. if (iwl3945_param_disable_hw_scan) {
  6518. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6519. iwl3945_hw_ops.hw_scan = NULL;
  6520. }
  6521. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6522. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6523. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6524. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6525. err = -EINVAL;
  6526. goto out;
  6527. }
  6528. /* mac80211 allocates memory for this device instance, including
  6529. * space for this driver's private structure */
  6530. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6531. if (hw == NULL) {
  6532. IWL_ERROR("Can not allocate network device\n");
  6533. err = -ENOMEM;
  6534. goto out;
  6535. }
  6536. SET_IEEE80211_DEV(hw, &pdev->dev);
  6537. hw->rate_control_algorithm = "iwl-3945-rs";
  6538. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6539. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6540. priv = hw->priv;
  6541. priv->hw = hw;
  6542. priv->pci_dev = pdev;
  6543. priv->cfg = cfg;
  6544. /* Select antenna (may be helpful if only one antenna is connected) */
  6545. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6546. #ifdef CONFIG_IWL3945_DEBUG
  6547. iwl3945_debug_level = iwl3945_param_debug;
  6548. atomic_set(&priv->restrict_refcnt, 0);
  6549. #endif
  6550. priv->retry_rate = 1;
  6551. priv->ibss_beacon = NULL;
  6552. /* Tell mac80211 our characteristics */
  6553. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6554. IEEE80211_HW_NOISE_DBM;
  6555. hw->wiphy->interface_modes =
  6556. BIT(NL80211_IFTYPE_AP) |
  6557. BIT(NL80211_IFTYPE_STATION) |
  6558. BIT(NL80211_IFTYPE_ADHOC);
  6559. /* 4 EDCA QOS priorities */
  6560. hw->queues = 4;
  6561. spin_lock_init(&priv->lock);
  6562. spin_lock_init(&priv->power_data.lock);
  6563. spin_lock_init(&priv->sta_lock);
  6564. spin_lock_init(&priv->hcmd_lock);
  6565. INIT_LIST_HEAD(&priv->free_frames);
  6566. mutex_init(&priv->mutex);
  6567. if (pci_enable_device(pdev)) {
  6568. err = -ENODEV;
  6569. goto out_ieee80211_free_hw;
  6570. }
  6571. pci_set_master(pdev);
  6572. /* Clear the driver's (not device's) station table */
  6573. iwl3945_clear_stations_table(priv);
  6574. priv->data_retry_limit = -1;
  6575. priv->ieee_channels = NULL;
  6576. priv->ieee_rates = NULL;
  6577. priv->band = IEEE80211_BAND_2GHZ;
  6578. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6579. if (!err)
  6580. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6581. if (err) {
  6582. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6583. goto out_pci_disable_device;
  6584. }
  6585. pci_set_drvdata(pdev, priv);
  6586. err = pci_request_regions(pdev, DRV_NAME);
  6587. if (err)
  6588. goto out_pci_disable_device;
  6589. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6590. * PCI Tx retries from interfering with C3 CPU state */
  6591. pci_write_config_byte(pdev, 0x41, 0x00);
  6592. priv->hw_base = pci_iomap(pdev, 0, 0);
  6593. if (!priv->hw_base) {
  6594. err = -ENODEV;
  6595. goto out_pci_release_regions;
  6596. }
  6597. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6598. (unsigned long long) pci_resource_len(pdev, 0));
  6599. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6600. /* Initialize module parameter values here */
  6601. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6602. if (iwl3945_param_disable) {
  6603. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6604. IWL_DEBUG_INFO("Radio disabled.\n");
  6605. }
  6606. priv->iw_mode = NL80211_IFTYPE_STATION;
  6607. printk(KERN_INFO DRV_NAME
  6608. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6609. /* Device-specific setup */
  6610. if (iwl3945_hw_set_hw_setting(priv)) {
  6611. IWL_ERROR("failed to set hw settings\n");
  6612. goto out_iounmap;
  6613. }
  6614. if (iwl3945_param_qos_enable)
  6615. priv->qos_data.qos_enable = 1;
  6616. iwl3945_reset_qos(priv);
  6617. priv->qos_data.qos_active = 0;
  6618. priv->qos_data.qos_cap.val = 0;
  6619. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6620. iwl3945_setup_deferred_work(priv);
  6621. iwl3945_setup_rx_handlers(priv);
  6622. priv->rates_mask = IWL_RATES_MASK;
  6623. /* If power management is turned on, default to AC mode */
  6624. priv->power_mode = IWL_POWER_AC;
  6625. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6626. spin_lock_irqsave(&priv->lock, flags);
  6627. iwl3945_disable_interrupts(priv);
  6628. spin_unlock_irqrestore(&priv->lock, flags);
  6629. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6630. if (err) {
  6631. IWL_ERROR("failed to create sysfs device attributes\n");
  6632. goto out_release_irq;
  6633. }
  6634. /* nic init */
  6635. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6636. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6637. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6638. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6639. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6640. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6641. if (err < 0) {
  6642. IWL_DEBUG_INFO("Failed to init the card\n");
  6643. goto out_remove_sysfs;
  6644. }
  6645. /* Read the EEPROM */
  6646. err = iwl3945_eeprom_init(priv);
  6647. if (err) {
  6648. IWL_ERROR("Unable to init EEPROM\n");
  6649. goto out_remove_sysfs;
  6650. }
  6651. /* MAC Address location in EEPROM same for 3945/4965 */
  6652. get_eeprom_mac(priv, priv->mac_addr);
  6653. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6654. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6655. err = iwl3945_init_channel_map(priv);
  6656. if (err) {
  6657. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6658. goto out_remove_sysfs;
  6659. }
  6660. err = iwl3945_init_geos(priv);
  6661. if (err) {
  6662. IWL_ERROR("initializing geos failed: %d\n", err);
  6663. goto out_free_channel_map;
  6664. }
  6665. err = ieee80211_register_hw(priv->hw);
  6666. if (err) {
  6667. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6668. goto out_free_geos;
  6669. }
  6670. priv->hw->conf.beacon_int = 100;
  6671. priv->mac80211_registered = 1;
  6672. pci_save_state(pdev);
  6673. pci_disable_device(pdev);
  6674. err = iwl3945_rfkill_init(priv);
  6675. if (err)
  6676. IWL_ERROR("Unable to initialize RFKILL system. "
  6677. "Ignoring error: %d\n", err);
  6678. return 0;
  6679. out_free_geos:
  6680. iwl3945_free_geos(priv);
  6681. out_free_channel_map:
  6682. iwl3945_free_channel_map(priv);
  6683. out_remove_sysfs:
  6684. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6685. out_release_irq:
  6686. destroy_workqueue(priv->workqueue);
  6687. priv->workqueue = NULL;
  6688. iwl3945_unset_hw_setting(priv);
  6689. out_iounmap:
  6690. pci_iounmap(pdev, priv->hw_base);
  6691. out_pci_release_regions:
  6692. pci_release_regions(pdev);
  6693. out_pci_disable_device:
  6694. pci_disable_device(pdev);
  6695. pci_set_drvdata(pdev, NULL);
  6696. out_ieee80211_free_hw:
  6697. ieee80211_free_hw(priv->hw);
  6698. out:
  6699. return err;
  6700. }
  6701. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6702. {
  6703. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6704. unsigned long flags;
  6705. if (!priv)
  6706. return;
  6707. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6708. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6709. iwl3945_down(priv);
  6710. /* make sure we flush any pending irq or
  6711. * tasklet for the driver
  6712. */
  6713. spin_lock_irqsave(&priv->lock, flags);
  6714. iwl3945_disable_interrupts(priv);
  6715. spin_unlock_irqrestore(&priv->lock, flags);
  6716. iwl_synchronize_irq(priv);
  6717. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6718. iwl3945_rfkill_unregister(priv);
  6719. iwl3945_dealloc_ucode_pci(priv);
  6720. if (priv->rxq.bd)
  6721. iwl3945_rx_queue_free(priv, &priv->rxq);
  6722. iwl3945_hw_txq_ctx_free(priv);
  6723. iwl3945_unset_hw_setting(priv);
  6724. iwl3945_clear_stations_table(priv);
  6725. if (priv->mac80211_registered)
  6726. ieee80211_unregister_hw(priv->hw);
  6727. /*netif_stop_queue(dev); */
  6728. flush_workqueue(priv->workqueue);
  6729. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6730. * priv->workqueue... so we can't take down the workqueue
  6731. * until now... */
  6732. destroy_workqueue(priv->workqueue);
  6733. priv->workqueue = NULL;
  6734. pci_iounmap(pdev, priv->hw_base);
  6735. pci_release_regions(pdev);
  6736. pci_disable_device(pdev);
  6737. pci_set_drvdata(pdev, NULL);
  6738. iwl3945_free_channel_map(priv);
  6739. iwl3945_free_geos(priv);
  6740. kfree(priv->scan);
  6741. if (priv->ibss_beacon)
  6742. dev_kfree_skb(priv->ibss_beacon);
  6743. ieee80211_free_hw(priv->hw);
  6744. }
  6745. #ifdef CONFIG_PM
  6746. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6747. {
  6748. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6749. if (priv->is_open) {
  6750. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6751. iwl3945_mac_stop(priv->hw);
  6752. priv->is_open = 1;
  6753. }
  6754. pci_set_power_state(pdev, PCI_D3hot);
  6755. return 0;
  6756. }
  6757. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6758. {
  6759. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6760. pci_set_power_state(pdev, PCI_D0);
  6761. if (priv->is_open)
  6762. iwl3945_mac_start(priv->hw);
  6763. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6764. return 0;
  6765. }
  6766. #endif /* CONFIG_PM */
  6767. /*************** RFKILL FUNCTIONS **********/
  6768. #ifdef CONFIG_IWL3945_RFKILL
  6769. /* software rf-kill from user */
  6770. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6771. {
  6772. struct iwl3945_priv *priv = data;
  6773. int err = 0;
  6774. if (!priv->rfkill)
  6775. return 0;
  6776. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6777. return 0;
  6778. IWL_DEBUG_RF_KILL("we recieved soft RFKILL set to state %d\n", state);
  6779. mutex_lock(&priv->mutex);
  6780. switch (state) {
  6781. case RFKILL_STATE_UNBLOCKED:
  6782. if (iwl3945_is_rfkill_hw(priv)) {
  6783. err = -EBUSY;
  6784. goto out_unlock;
  6785. }
  6786. iwl3945_radio_kill_sw(priv, 0);
  6787. break;
  6788. case RFKILL_STATE_SOFT_BLOCKED:
  6789. iwl3945_radio_kill_sw(priv, 1);
  6790. break;
  6791. default:
  6792. IWL_WARNING("we recieved unexpected RFKILL state %d\n", state);
  6793. break;
  6794. }
  6795. out_unlock:
  6796. mutex_unlock(&priv->mutex);
  6797. return err;
  6798. }
  6799. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6800. {
  6801. struct device *device = wiphy_dev(priv->hw->wiphy);
  6802. int ret = 0;
  6803. BUG_ON(device == NULL);
  6804. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6805. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6806. if (!priv->rfkill) {
  6807. IWL_ERROR("Unable to allocate rfkill device.\n");
  6808. ret = -ENOMEM;
  6809. goto error;
  6810. }
  6811. priv->rfkill->name = priv->cfg->name;
  6812. priv->rfkill->data = priv;
  6813. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6814. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6815. priv->rfkill->user_claim_unsupported = 1;
  6816. priv->rfkill->dev.class->suspend = NULL;
  6817. priv->rfkill->dev.class->resume = NULL;
  6818. ret = rfkill_register(priv->rfkill);
  6819. if (ret) {
  6820. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6821. goto freed_rfkill;
  6822. }
  6823. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6824. return ret;
  6825. freed_rfkill:
  6826. if (priv->rfkill != NULL)
  6827. rfkill_free(priv->rfkill);
  6828. priv->rfkill = NULL;
  6829. error:
  6830. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6831. return ret;
  6832. }
  6833. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6834. {
  6835. if (priv->rfkill)
  6836. rfkill_unregister(priv->rfkill);
  6837. priv->rfkill = NULL;
  6838. }
  6839. /* set rf-kill to the right state. */
  6840. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6841. {
  6842. if (!priv->rfkill)
  6843. return;
  6844. if (iwl3945_is_rfkill_hw(priv)) {
  6845. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6846. return;
  6847. }
  6848. if (!iwl3945_is_rfkill_sw(priv))
  6849. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6850. else
  6851. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6852. }
  6853. #endif
  6854. /*****************************************************************************
  6855. *
  6856. * driver and module entry point
  6857. *
  6858. *****************************************************************************/
  6859. static struct pci_driver iwl3945_driver = {
  6860. .name = DRV_NAME,
  6861. .id_table = iwl3945_hw_card_ids,
  6862. .probe = iwl3945_pci_probe,
  6863. .remove = __devexit_p(iwl3945_pci_remove),
  6864. #ifdef CONFIG_PM
  6865. .suspend = iwl3945_pci_suspend,
  6866. .resume = iwl3945_pci_resume,
  6867. #endif
  6868. };
  6869. static int __init iwl3945_init(void)
  6870. {
  6871. int ret;
  6872. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6873. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6874. ret = iwl3945_rate_control_register();
  6875. if (ret) {
  6876. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6877. return ret;
  6878. }
  6879. ret = pci_register_driver(&iwl3945_driver);
  6880. if (ret) {
  6881. IWL_ERROR("Unable to initialize PCI module\n");
  6882. goto error_register;
  6883. }
  6884. #ifdef CONFIG_IWL3945_DEBUG
  6885. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6886. if (ret) {
  6887. IWL_ERROR("Unable to create driver sysfs file\n");
  6888. goto error_debug;
  6889. }
  6890. #endif
  6891. return ret;
  6892. #ifdef CONFIG_IWL3945_DEBUG
  6893. error_debug:
  6894. pci_unregister_driver(&iwl3945_driver);
  6895. #endif
  6896. error_register:
  6897. iwl3945_rate_control_unregister();
  6898. return ret;
  6899. }
  6900. static void __exit iwl3945_exit(void)
  6901. {
  6902. #ifdef CONFIG_IWL3945_DEBUG
  6903. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6904. #endif
  6905. pci_unregister_driver(&iwl3945_driver);
  6906. iwl3945_rate_control_unregister();
  6907. }
  6908. MODULE_FIRMWARE("iwlwifi-3945" IWL3945_UCODE_API ".ucode");
  6909. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6910. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6911. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6912. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6913. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6914. MODULE_PARM_DESC(hwcrypto,
  6915. "using hardware crypto engine (default 0 [software])\n");
  6916. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6917. MODULE_PARM_DESC(debug, "debug output mask");
  6918. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6919. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6920. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6921. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6922. /* QoS */
  6923. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6924. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6925. module_exit(iwl3945_exit);
  6926. module_init(iwl3945_init);