iwl-rx.c 37 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. u32 reg = 0;
  126. int ret = 0;
  127. unsigned long flags;
  128. spin_lock_irqsave(&q->lock, flags);
  129. if (q->need_update == 0)
  130. goto exit_unlock;
  131. /* If power-saving is in use, make sure device is awake */
  132. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  133. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  134. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  135. iwl_set_bit(priv, CSR_GP_CNTRL,
  136. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  137. goto exit_unlock;
  138. }
  139. ret = iwl_grab_nic_access(priv);
  140. if (ret)
  141. goto exit_unlock;
  142. /* Device expects a multiple of 8 */
  143. iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  144. q->write & ~0x7);
  145. iwl_release_nic_access(priv);
  146. /* Else device is assumed to be awake */
  147. } else
  148. /* Device expects a multiple of 8 */
  149. iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  150. q->need_update = 0;
  151. exit_unlock:
  152. spin_unlock_irqrestore(&q->lock, flags);
  153. return ret;
  154. }
  155. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  156. /**
  157. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  158. */
  159. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  160. dma_addr_t dma_addr)
  161. {
  162. return cpu_to_le32((u32)(dma_addr >> 8));
  163. }
  164. /**
  165. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  166. *
  167. * If there are slots in the RX queue that need to be restocked,
  168. * and we have free pre-allocated buffers, fill the ranks as much
  169. * as we can, pulling from rx_free.
  170. *
  171. * This moves the 'write' index forward to catch up with 'processed', and
  172. * also updates the memory address in the firmware to reference the new
  173. * target buffer.
  174. */
  175. int iwl_rx_queue_restock(struct iwl_priv *priv)
  176. {
  177. struct iwl_rx_queue *rxq = &priv->rxq;
  178. struct list_head *element;
  179. struct iwl_rx_mem_buffer *rxb;
  180. unsigned long flags;
  181. int write;
  182. int ret = 0;
  183. spin_lock_irqsave(&rxq->lock, flags);
  184. write = rxq->write & ~0x7;
  185. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  186. /* Get next free Rx buffer, remove from free list */
  187. element = rxq->rx_free.next;
  188. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  189. list_del(element);
  190. /* Point to Rx buffer via next RBD in circular buffer */
  191. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  192. rxq->queue[rxq->write] = rxb;
  193. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  194. rxq->free_count--;
  195. }
  196. spin_unlock_irqrestore(&rxq->lock, flags);
  197. /* If the pre-allocated buffer pool is dropping low, schedule to
  198. * refill it */
  199. if (rxq->free_count <= RX_LOW_WATERMARK)
  200. queue_work(priv->workqueue, &priv->rx_replenish);
  201. /* If we've added more space for the firmware to place data, tell it.
  202. * Increment device's write pointer in multiples of 8. */
  203. if ((write != (rxq->write & ~0x7))
  204. || (abs(rxq->write - rxq->read) > 7)) {
  205. spin_lock_irqsave(&rxq->lock, flags);
  206. rxq->need_update = 1;
  207. spin_unlock_irqrestore(&rxq->lock, flags);
  208. ret = iwl_rx_queue_update_write_ptr(priv, rxq);
  209. }
  210. return ret;
  211. }
  212. EXPORT_SYMBOL(iwl_rx_queue_restock);
  213. /**
  214. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  215. *
  216. * When moving to rx_free an SKB is allocated for the slot.
  217. *
  218. * Also restock the Rx queue via iwl_rx_queue_restock.
  219. * This is called as a scheduled work item (except for during initialization)
  220. */
  221. void iwl_rx_allocate(struct iwl_priv *priv)
  222. {
  223. struct iwl_rx_queue *rxq = &priv->rxq;
  224. struct list_head *element;
  225. struct iwl_rx_mem_buffer *rxb;
  226. unsigned long flags;
  227. spin_lock_irqsave(&rxq->lock, flags);
  228. while (!list_empty(&rxq->rx_used)) {
  229. element = rxq->rx_used.next;
  230. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  231. /* Alloc a new receive buffer */
  232. rxb->skb = alloc_skb(priv->hw_params.rx_buf_size,
  233. __GFP_NOWARN | GFP_ATOMIC);
  234. if (!rxb->skb) {
  235. if (net_ratelimit())
  236. printk(KERN_CRIT DRV_NAME
  237. ": Can not allocate SKB buffers\n");
  238. /* We don't reschedule replenish work here -- we will
  239. * call the restock method and if it still needs
  240. * more buffers it will schedule replenish */
  241. break;
  242. }
  243. priv->alloc_rxb_skb++;
  244. list_del(element);
  245. /* Get physical address of RB/SKB */
  246. rxb->dma_addr =
  247. pci_map_single(priv->pci_dev, rxb->skb->data,
  248. priv->hw_params.rx_buf_size, PCI_DMA_FROMDEVICE);
  249. list_add_tail(&rxb->list, &rxq->rx_free);
  250. rxq->free_count++;
  251. }
  252. spin_unlock_irqrestore(&rxq->lock, flags);
  253. }
  254. EXPORT_SYMBOL(iwl_rx_allocate);
  255. void iwl_rx_replenish(struct iwl_priv *priv)
  256. {
  257. unsigned long flags;
  258. iwl_rx_allocate(priv);
  259. spin_lock_irqsave(&priv->lock, flags);
  260. iwl_rx_queue_restock(priv);
  261. spin_unlock_irqrestore(&priv->lock, flags);
  262. }
  263. EXPORT_SYMBOL(iwl_rx_replenish);
  264. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  265. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  266. * This free routine walks the list of POOL entries and if SKB is set to
  267. * non NULL it is unmapped and freed
  268. */
  269. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  270. {
  271. int i;
  272. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  273. if (rxq->pool[i].skb != NULL) {
  274. pci_unmap_single(priv->pci_dev,
  275. rxq->pool[i].dma_addr,
  276. priv->hw_params.rx_buf_size,
  277. PCI_DMA_FROMDEVICE);
  278. dev_kfree_skb(rxq->pool[i].skb);
  279. }
  280. }
  281. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  282. rxq->dma_addr);
  283. rxq->bd = NULL;
  284. }
  285. EXPORT_SYMBOL(iwl_rx_queue_free);
  286. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  287. {
  288. struct iwl_rx_queue *rxq = &priv->rxq;
  289. struct pci_dev *dev = priv->pci_dev;
  290. int i;
  291. spin_lock_init(&rxq->lock);
  292. INIT_LIST_HEAD(&rxq->rx_free);
  293. INIT_LIST_HEAD(&rxq->rx_used);
  294. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  295. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  296. if (!rxq->bd)
  297. return -ENOMEM;
  298. /* Fill the rx_used queue with _all_ of the Rx buffers */
  299. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  300. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  301. /* Set us so that we have processed and used all buffers, but have
  302. * not restocked the Rx queue with fresh buffers */
  303. rxq->read = rxq->write = 0;
  304. rxq->free_count = 0;
  305. rxq->need_update = 0;
  306. return 0;
  307. }
  308. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  309. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  310. {
  311. unsigned long flags;
  312. int i;
  313. spin_lock_irqsave(&rxq->lock, flags);
  314. INIT_LIST_HEAD(&rxq->rx_free);
  315. INIT_LIST_HEAD(&rxq->rx_used);
  316. /* Fill the rx_used queue with _all_ of the Rx buffers */
  317. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  318. /* In the reset function, these buffers may have been allocated
  319. * to an SKB, so we need to unmap and free potential storage */
  320. if (rxq->pool[i].skb != NULL) {
  321. pci_unmap_single(priv->pci_dev,
  322. rxq->pool[i].dma_addr,
  323. priv->hw_params.rx_buf_size,
  324. PCI_DMA_FROMDEVICE);
  325. priv->alloc_rxb_skb--;
  326. dev_kfree_skb(rxq->pool[i].skb);
  327. rxq->pool[i].skb = NULL;
  328. }
  329. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  330. }
  331. /* Set us so that we have processed and used all buffers, but have
  332. * not restocked the Rx queue with fresh buffers */
  333. rxq->read = rxq->write = 0;
  334. rxq->free_count = 0;
  335. spin_unlock_irqrestore(&rxq->lock, flags);
  336. }
  337. EXPORT_SYMBOL(iwl_rx_queue_reset);
  338. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  339. {
  340. int ret;
  341. unsigned long flags;
  342. u32 rb_size;
  343. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  344. const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
  345. spin_lock_irqsave(&priv->lock, flags);
  346. ret = iwl_grab_nic_access(priv);
  347. if (ret) {
  348. spin_unlock_irqrestore(&priv->lock, flags);
  349. return ret;
  350. }
  351. if (priv->cfg->mod_params->amsdu_size_8K)
  352. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  353. else
  354. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  355. /* Stop Rx DMA */
  356. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  357. /* Reset driver's Rx queue write index */
  358. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  359. /* Tell device where to find RBD circular buffer in DRAM */
  360. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  361. (u32)(rxq->dma_addr >> 8));
  362. /* Tell device where in DRAM to update its Rx status */
  363. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  364. (priv->shared_phys + priv->rb_closed_offset) >> 4);
  365. /* Enable Rx DMA
  366. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set becuase of HW bug in
  367. * the credit mechanism in 5000 HW RX FIFO
  368. * Direct rx interrupts to hosts
  369. * Rx buffer size 4 or 8k
  370. * RB timeout 0x10
  371. * 256 RBDs
  372. */
  373. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  374. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  375. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  376. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  377. rb_size|
  378. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  379. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  380. iwl_release_nic_access(priv);
  381. iwl_write32(priv, CSR_INT_COALESCING, 0x40);
  382. spin_unlock_irqrestore(&priv->lock, flags);
  383. return 0;
  384. }
  385. int iwl_rxq_stop(struct iwl_priv *priv)
  386. {
  387. int ret;
  388. unsigned long flags;
  389. spin_lock_irqsave(&priv->lock, flags);
  390. ret = iwl_grab_nic_access(priv);
  391. if (unlikely(ret)) {
  392. spin_unlock_irqrestore(&priv->lock, flags);
  393. return ret;
  394. }
  395. /* stop Rx DMA */
  396. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  397. ret = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  398. (1 << 24), 1000);
  399. if (ret < 0)
  400. IWL_ERROR("Can't stop Rx DMA.\n");
  401. iwl_release_nic_access(priv);
  402. spin_unlock_irqrestore(&priv->lock, flags);
  403. return 0;
  404. }
  405. EXPORT_SYMBOL(iwl_rxq_stop);
  406. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  407. struct iwl_rx_mem_buffer *rxb)
  408. {
  409. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  410. struct iwl4965_missed_beacon_notif *missed_beacon;
  411. missed_beacon = &pkt->u.missed_beacon;
  412. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  413. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  414. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  415. le32_to_cpu(missed_beacon->total_missed_becons),
  416. le32_to_cpu(missed_beacon->num_recvd_beacons),
  417. le32_to_cpu(missed_beacon->num_expected_beacons));
  418. if (!test_bit(STATUS_SCANNING, &priv->status))
  419. iwl_init_sensitivity(priv);
  420. }
  421. }
  422. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  423. int iwl_rx_agg_start(struct iwl_priv *priv, const u8 *addr, int tid, u16 ssn)
  424. {
  425. unsigned long flags;
  426. int sta_id;
  427. sta_id = iwl_find_station(priv, addr);
  428. if (sta_id == IWL_INVALID_STATION)
  429. return -ENXIO;
  430. spin_lock_irqsave(&priv->sta_lock, flags);
  431. priv->stations[sta_id].sta.station_flags_msk = 0;
  432. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  433. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  434. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  435. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  436. spin_unlock_irqrestore(&priv->sta_lock, flags);
  437. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  438. CMD_ASYNC);
  439. }
  440. EXPORT_SYMBOL(iwl_rx_agg_start);
  441. int iwl_rx_agg_stop(struct iwl_priv *priv, const u8 *addr, int tid)
  442. {
  443. unsigned long flags;
  444. int sta_id;
  445. sta_id = iwl_find_station(priv, addr);
  446. if (sta_id == IWL_INVALID_STATION)
  447. return -ENXIO;
  448. spin_lock_irqsave(&priv->sta_lock, flags);
  449. priv->stations[sta_id].sta.station_flags_msk = 0;
  450. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  451. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  452. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  453. spin_unlock_irqrestore(&priv->sta_lock, flags);
  454. return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
  455. CMD_ASYNC);
  456. }
  457. EXPORT_SYMBOL(iwl_rx_agg_stop);
  458. /* Calculate noise level, based on measurements during network silence just
  459. * before arriving beacon. This measurement can be done only if we know
  460. * exactly when to expect beacons, therefore only when we're associated. */
  461. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  462. {
  463. struct statistics_rx_non_phy *rx_info
  464. = &(priv->statistics.rx.general);
  465. int num_active_rx = 0;
  466. int total_silence = 0;
  467. int bcn_silence_a =
  468. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  469. int bcn_silence_b =
  470. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  471. int bcn_silence_c =
  472. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  473. if (bcn_silence_a) {
  474. total_silence += bcn_silence_a;
  475. num_active_rx++;
  476. }
  477. if (bcn_silence_b) {
  478. total_silence += bcn_silence_b;
  479. num_active_rx++;
  480. }
  481. if (bcn_silence_c) {
  482. total_silence += bcn_silence_c;
  483. num_active_rx++;
  484. }
  485. /* Average among active antennas */
  486. if (num_active_rx)
  487. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  488. else
  489. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  490. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  491. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  492. priv->last_rx_noise);
  493. }
  494. #define REG_RECALIB_PERIOD (60)
  495. void iwl_rx_statistics(struct iwl_priv *priv,
  496. struct iwl_rx_mem_buffer *rxb)
  497. {
  498. int change;
  499. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  500. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  501. (int)sizeof(priv->statistics), pkt->len);
  502. change = ((priv->statistics.general.temperature !=
  503. pkt->u.stats.general.temperature) ||
  504. ((priv->statistics.flag &
  505. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  506. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  507. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  508. set_bit(STATUS_STATISTICS, &priv->status);
  509. /* Reschedule the statistics timer to occur in
  510. * REG_RECALIB_PERIOD seconds to ensure we get a
  511. * thermal update even if the uCode doesn't give
  512. * us one */
  513. mod_timer(&priv->statistics_periodic, jiffies +
  514. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  515. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  516. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  517. iwl_rx_calc_noise(priv);
  518. queue_work(priv->workqueue, &priv->run_time_calib_work);
  519. }
  520. iwl_leds_background(priv);
  521. if (priv->cfg->ops->lib->temperature && change)
  522. priv->cfg->ops->lib->temperature(priv);
  523. }
  524. EXPORT_SYMBOL(iwl_rx_statistics);
  525. #define PERFECT_RSSI (-20) /* dBm */
  526. #define WORST_RSSI (-95) /* dBm */
  527. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  528. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  529. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  530. * about formulas used below. */
  531. static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
  532. {
  533. int sig_qual;
  534. int degradation = PERFECT_RSSI - rssi_dbm;
  535. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  536. * as indicator; formula is (signal dbm - noise dbm).
  537. * SNR at or above 40 is a great signal (100%).
  538. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  539. * Weakest usable signal is usually 10 - 15 dB SNR. */
  540. if (noise_dbm) {
  541. if (rssi_dbm - noise_dbm >= 40)
  542. return 100;
  543. else if (rssi_dbm < noise_dbm)
  544. return 0;
  545. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  546. /* Else use just the signal level.
  547. * This formula is a least squares fit of data points collected and
  548. * compared with a reference system that had a percentage (%) display
  549. * for signal quality. */
  550. } else
  551. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  552. (15 * RSSI_RANGE + 62 * degradation)) /
  553. (RSSI_RANGE * RSSI_RANGE);
  554. if (sig_qual > 100)
  555. sig_qual = 100;
  556. else if (sig_qual < 1)
  557. sig_qual = 0;
  558. return sig_qual;
  559. }
  560. #ifdef CONFIG_IWLWIFI_DEBUG
  561. /**
  562. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  563. *
  564. * You may hack this function to show different aspects of received frames,
  565. * including selective frame dumps.
  566. * group100 parameter selects whether to show 1 out of 100 good frames.
  567. *
  568. * TODO: This was originally written for 3945, need to audit for
  569. * proper operation with 4965.
  570. */
  571. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  572. struct iwl_rx_packet *pkt,
  573. struct ieee80211_hdr *header, int group100)
  574. {
  575. u32 to_us;
  576. u32 print_summary = 0;
  577. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  578. u32 hundred = 0;
  579. u32 dataframe = 0;
  580. __le16 fc;
  581. u16 seq_ctl;
  582. u16 channel;
  583. u16 phy_flags;
  584. int rate_sym;
  585. u16 length;
  586. u16 status;
  587. u16 bcn_tmr;
  588. u32 tsf_low;
  589. u64 tsf;
  590. u8 rssi;
  591. u8 agc;
  592. u16 sig_avg;
  593. u16 noise_diff;
  594. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  595. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  596. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  597. u8 *data = IWL_RX_DATA(pkt);
  598. if (likely(!(priv->debug_level & IWL_DL_RX)))
  599. return;
  600. /* MAC header */
  601. fc = header->frame_control;
  602. seq_ctl = le16_to_cpu(header->seq_ctrl);
  603. /* metadata */
  604. channel = le16_to_cpu(rx_hdr->channel);
  605. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  606. rate_sym = rx_hdr->rate;
  607. length = le16_to_cpu(rx_hdr->len);
  608. /* end-of-frame status and timestamp */
  609. status = le32_to_cpu(rx_end->status);
  610. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  611. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  612. tsf = le64_to_cpu(rx_end->timestamp);
  613. /* signal statistics */
  614. rssi = rx_stats->rssi;
  615. agc = rx_stats->agc;
  616. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  617. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  618. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  619. /* if data frame is to us and all is good,
  620. * (optionally) print summary for only 1 out of every 100 */
  621. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  622. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  623. dataframe = 1;
  624. if (!group100)
  625. print_summary = 1; /* print each frame */
  626. else if (priv->framecnt_to_us < 100) {
  627. priv->framecnt_to_us++;
  628. print_summary = 0;
  629. } else {
  630. priv->framecnt_to_us = 0;
  631. print_summary = 1;
  632. hundred = 1;
  633. }
  634. } else {
  635. /* print summary for all other frames */
  636. print_summary = 1;
  637. }
  638. if (print_summary) {
  639. char *title;
  640. int rate_idx;
  641. u32 bitrate;
  642. if (hundred)
  643. title = "100Frames";
  644. else if (ieee80211_has_retry(fc))
  645. title = "Retry";
  646. else if (ieee80211_is_assoc_resp(fc))
  647. title = "AscRsp";
  648. else if (ieee80211_is_reassoc_resp(fc))
  649. title = "RasRsp";
  650. else if (ieee80211_is_probe_resp(fc)) {
  651. title = "PrbRsp";
  652. print_dump = 1; /* dump frame contents */
  653. } else if (ieee80211_is_beacon(fc)) {
  654. title = "Beacon";
  655. print_dump = 1; /* dump frame contents */
  656. } else if (ieee80211_is_atim(fc))
  657. title = "ATIM";
  658. else if (ieee80211_is_auth(fc))
  659. title = "Auth";
  660. else if (ieee80211_is_deauth(fc))
  661. title = "DeAuth";
  662. else if (ieee80211_is_disassoc(fc))
  663. title = "DisAssoc";
  664. else
  665. title = "Frame";
  666. rate_idx = iwl_hwrate_to_plcp_idx(rate_sym);
  667. if (unlikely(rate_idx == -1))
  668. bitrate = 0;
  669. else
  670. bitrate = iwl_rates[rate_idx].ieee / 2;
  671. /* print frame summary.
  672. * MAC addresses show just the last byte (for brevity),
  673. * but you can hack it to show more, if you'd like to. */
  674. if (dataframe)
  675. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  676. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  677. title, le16_to_cpu(fc), header->addr1[5],
  678. length, rssi, channel, bitrate);
  679. else {
  680. /* src/dst addresses assume managed mode */
  681. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  682. "src=0x%02x, rssi=%u, tim=%lu usec, "
  683. "phy=0x%02x, chnl=%d\n",
  684. title, le16_to_cpu(fc), header->addr1[5],
  685. header->addr3[5], rssi,
  686. tsf_low - priv->scan_start_tsf,
  687. phy_flags, channel);
  688. }
  689. }
  690. if (print_dump)
  691. iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
  692. }
  693. #else
  694. static inline void iwl_dbg_report_frame(struct iwl_priv *priv,
  695. struct iwl_rx_packet *pkt,
  696. struct ieee80211_hdr *header,
  697. int group100)
  698. {
  699. }
  700. #endif
  701. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  702. {
  703. /* 0 - mgmt, 1 - cnt, 2 - data */
  704. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  705. priv->rx_stats[idx].cnt++;
  706. priv->rx_stats[idx].bytes += len;
  707. }
  708. /*
  709. * returns non-zero if packet should be dropped
  710. */
  711. static int iwl_set_decrypted_flag(struct iwl_priv *priv,
  712. struct ieee80211_hdr *hdr,
  713. u32 decrypt_res,
  714. struct ieee80211_rx_status *stats)
  715. {
  716. u16 fc = le16_to_cpu(hdr->frame_control);
  717. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  718. return 0;
  719. if (!(fc & IEEE80211_FCTL_PROTECTED))
  720. return 0;
  721. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  722. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  723. case RX_RES_STATUS_SEC_TYPE_TKIP:
  724. /* The uCode has got a bad phase 1 Key, pushes the packet.
  725. * Decryption will be done in SW. */
  726. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  727. RX_RES_STATUS_BAD_KEY_TTAK)
  728. break;
  729. case RX_RES_STATUS_SEC_TYPE_WEP:
  730. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  731. RX_RES_STATUS_BAD_ICV_MIC) {
  732. /* bad ICV, the packet is destroyed since the
  733. * decryption is inplace, drop it */
  734. IWL_DEBUG_RX("Packet destroyed\n");
  735. return -1;
  736. }
  737. case RX_RES_STATUS_SEC_TYPE_CCMP:
  738. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  739. RX_RES_STATUS_DECRYPT_OK) {
  740. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  741. stats->flag |= RX_FLAG_DECRYPTED;
  742. }
  743. break;
  744. default:
  745. break;
  746. }
  747. return 0;
  748. }
  749. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  750. {
  751. u32 decrypt_out = 0;
  752. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  753. RX_RES_STATUS_STATION_FOUND)
  754. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  755. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  756. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  757. /* packet was not encrypted */
  758. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  759. RX_RES_STATUS_SEC_TYPE_NONE)
  760. return decrypt_out;
  761. /* packet was encrypted with unknown alg */
  762. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  763. RX_RES_STATUS_SEC_TYPE_ERR)
  764. return decrypt_out;
  765. /* decryption was not done in HW */
  766. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  767. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  768. return decrypt_out;
  769. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  770. case RX_RES_STATUS_SEC_TYPE_CCMP:
  771. /* alg is CCM: check MIC only */
  772. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  773. /* Bad MIC */
  774. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  775. else
  776. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  777. break;
  778. case RX_RES_STATUS_SEC_TYPE_TKIP:
  779. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  780. /* Bad TTAK */
  781. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  782. break;
  783. }
  784. /* fall through if TTAK OK */
  785. default:
  786. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  787. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  788. else
  789. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  790. break;
  791. };
  792. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  793. decrypt_in, decrypt_out);
  794. return decrypt_out;
  795. }
  796. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  797. int include_phy,
  798. struct iwl_rx_mem_buffer *rxb,
  799. struct ieee80211_rx_status *stats)
  800. {
  801. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  802. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  803. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  804. struct ieee80211_hdr *hdr;
  805. u16 len;
  806. __le32 *rx_end;
  807. unsigned int skblen;
  808. u32 ampdu_status;
  809. u32 ampdu_status_legacy;
  810. if (!include_phy && priv->last_phy_res[0])
  811. rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  812. if (!rx_start) {
  813. IWL_ERROR("MPDU frame without a PHY data\n");
  814. return;
  815. }
  816. if (include_phy) {
  817. hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] +
  818. rx_start->cfg_phy_cnt);
  819. len = le16_to_cpu(rx_start->byte_count);
  820. rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] +
  821. sizeof(struct iwl_rx_phy_res) +
  822. rx_start->cfg_phy_cnt + len);
  823. } else {
  824. struct iwl4965_rx_mpdu_res_start *amsdu =
  825. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  826. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  827. sizeof(struct iwl4965_rx_mpdu_res_start));
  828. len = le16_to_cpu(amsdu->byte_count);
  829. rx_start->byte_count = amsdu->byte_count;
  830. rx_end = (__le32 *) (((u8 *) hdr) + len);
  831. }
  832. ampdu_status = le32_to_cpu(*rx_end);
  833. skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32);
  834. if (!include_phy) {
  835. /* New status scheme, need to translate */
  836. ampdu_status_legacy = ampdu_status;
  837. ampdu_status = iwl_translate_rx_status(priv, ampdu_status);
  838. }
  839. /* start from MAC */
  840. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  841. skb_put(rxb->skb, len); /* end where data ends */
  842. /* We only process data packets if the interface is open */
  843. if (unlikely(!priv->is_open)) {
  844. IWL_DEBUG_DROP_LIMIT
  845. ("Dropping packet while interface is not open.\n");
  846. return;
  847. }
  848. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  849. /* in case of HW accelerated crypto and bad decryption, drop */
  850. if (!priv->hw_params.sw_crypto &&
  851. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  852. return;
  853. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  854. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  855. priv->alloc_rxb_skb--;
  856. rxb->skb = NULL;
  857. }
  858. /* Calc max signal level (dBm) among 3 possible receivers */
  859. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  860. struct iwl_rx_phy_res *rx_resp)
  861. {
  862. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  863. }
  864. static void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  865. {
  866. unsigned long flags;
  867. spin_lock_irqsave(&priv->sta_lock, flags);
  868. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  869. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  870. priv->stations[sta_id].sta.sta.modify_mask = 0;
  871. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  872. spin_unlock_irqrestore(&priv->sta_lock, flags);
  873. iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  874. }
  875. static void iwl_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  876. {
  877. /* FIXME: need locking over ps_status ??? */
  878. u8 sta_id = iwl_find_station(priv, addr);
  879. if (sta_id != IWL_INVALID_STATION) {
  880. u8 sta_awake = priv->stations[sta_id].
  881. ps_status == STA_PS_STATUS_WAKE;
  882. if (sta_awake && ps_bit)
  883. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  884. else if (!sta_awake && !ps_bit) {
  885. iwl_sta_modify_ps_wake(priv, sta_id);
  886. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  887. }
  888. }
  889. }
  890. /* This is necessary only for a number of statistics, see the caller. */
  891. static int iwl_is_network_packet(struct iwl_priv *priv,
  892. struct ieee80211_hdr *header)
  893. {
  894. /* Filter incoming packets to determine if they are targeted toward
  895. * this network, discarding packets coming from ourselves */
  896. switch (priv->iw_mode) {
  897. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  898. /* packets to our IBSS update information */
  899. return !compare_ether_addr(header->addr3, priv->bssid);
  900. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  901. /* packets to our IBSS update information */
  902. return !compare_ether_addr(header->addr2, priv->bssid);
  903. default:
  904. return 1;
  905. }
  906. }
  907. /* Called for REPLY_RX (legacy ABG frames), or
  908. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  909. void iwl_rx_reply_rx(struct iwl_priv *priv,
  910. struct iwl_rx_mem_buffer *rxb)
  911. {
  912. struct ieee80211_hdr *header;
  913. struct ieee80211_rx_status rx_status;
  914. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  915. /* Use phy data (Rx signal strength, etc.) contained within
  916. * this rx packet for legacy frames,
  917. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  918. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  919. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  920. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) :
  921. (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  922. __le32 *rx_end;
  923. unsigned int len = 0;
  924. u16 fc;
  925. u8 network_packet;
  926. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  927. rx_status.freq =
  928. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  929. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  930. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  931. rx_status.rate_idx =
  932. iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  933. if (rx_status.band == IEEE80211_BAND_5GHZ)
  934. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  935. rx_status.flag = 0;
  936. /* TSF isn't reliable. In order to allow smooth user experience,
  937. * this W/A doesn't propagate it to the mac80211 */
  938. /*rx_status.flag |= RX_FLAG_TSFT;*/
  939. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  940. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  941. rx_start->cfg_phy_cnt);
  942. return;
  943. }
  944. if (!include_phy) {
  945. if (priv->last_phy_res[0])
  946. rx_start = (struct iwl_rx_phy_res *)
  947. &priv->last_phy_res[1];
  948. else
  949. rx_start = NULL;
  950. }
  951. if (!rx_start) {
  952. IWL_ERROR("MPDU frame without a PHY data\n");
  953. return;
  954. }
  955. if (include_phy) {
  956. header = (struct ieee80211_hdr *)((u8 *) &rx_start[1]
  957. + rx_start->cfg_phy_cnt);
  958. len = le16_to_cpu(rx_start->byte_count);
  959. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  960. sizeof(struct iwl_rx_phy_res) + len);
  961. } else {
  962. struct iwl4965_rx_mpdu_res_start *amsdu =
  963. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  964. header = (void *)(pkt->u.raw +
  965. sizeof(struct iwl4965_rx_mpdu_res_start));
  966. len = le16_to_cpu(amsdu->byte_count);
  967. rx_end = (__le32 *) (pkt->u.raw +
  968. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  969. }
  970. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  971. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  972. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  973. le32_to_cpu(*rx_end));
  974. return;
  975. }
  976. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  977. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  978. rx_status.signal = iwl_calc_rssi(priv, rx_start);
  979. /* Meaningful noise values are available only from beacon statistics,
  980. * which are gathered only when associated, and indicate noise
  981. * only for the associated network channel ...
  982. * Ignore these noise values while scanning (other channels) */
  983. if (iwl_is_associated(priv) &&
  984. !test_bit(STATUS_SCANNING, &priv->status)) {
  985. rx_status.noise = priv->last_rx_noise;
  986. rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
  987. rx_status.noise);
  988. } else {
  989. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  990. rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
  991. }
  992. /* Reset beacon noise level if not associated. */
  993. if (!iwl_is_associated(priv))
  994. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  995. /* Set "1" to report good data frames in groups of 100 */
  996. /* FIXME: need to optimze the call: */
  997. iwl_dbg_report_frame(priv, pkt, header, 1);
  998. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  999. rx_status.signal, rx_status.noise, rx_status.signal,
  1000. (unsigned long long)rx_status.mactime);
  1001. /*
  1002. * "antenna number"
  1003. *
  1004. * It seems that the antenna field in the phy flags value
  1005. * is actually a bitfield. This is undefined by radiotap,
  1006. * it wants an actual antenna number but I always get "7"
  1007. * for most legacy frames I receive indicating that the
  1008. * same frame was received on all three RX chains.
  1009. *
  1010. * I think this field should be removed in favour of a
  1011. * new 802.11n radiotap field "RX chains" that is defined
  1012. * as a bitmask.
  1013. */
  1014. rx_status.antenna = le16_to_cpu(rx_start->phy_flags &
  1015. RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  1016. /* set the preamble flag if appropriate */
  1017. if (rx_start->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1018. rx_status.flag |= RX_FLAG_SHORTPRE;
  1019. /* Take shortcut when only in monitor mode */
  1020. if (priv->iw_mode == NL80211_IFTYPE_MONITOR) {
  1021. iwl_pass_packet_to_mac80211(priv, include_phy,
  1022. rxb, &rx_status);
  1023. return;
  1024. }
  1025. network_packet = iwl_is_network_packet(priv, header);
  1026. if (network_packet) {
  1027. priv->last_rx_rssi = rx_status.signal;
  1028. priv->last_beacon_time = priv->ucode_beacon_time;
  1029. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  1030. }
  1031. fc = le16_to_cpu(header->frame_control);
  1032. switch (fc & IEEE80211_FCTL_FTYPE) {
  1033. case IEEE80211_FTYPE_MGMT:
  1034. case IEEE80211_FTYPE_DATA:
  1035. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1036. iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  1037. header->addr2);
  1038. /* fall through */
  1039. default:
  1040. iwl_pass_packet_to_mac80211(priv, include_phy, rxb,
  1041. &rx_status);
  1042. break;
  1043. }
  1044. }
  1045. EXPORT_SYMBOL(iwl_rx_reply_rx);
  1046. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  1047. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  1048. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  1049. struct iwl_rx_mem_buffer *rxb)
  1050. {
  1051. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1052. priv->last_phy_res[0] = 1;
  1053. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  1054. sizeof(struct iwl_rx_phy_res));
  1055. }
  1056. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);