3c359.c 58 KB

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  1. /*
  2. * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
  3. *
  4. * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
  5. *
  6. * Base Driver Olympic:
  7. * Written 1999 Peter De Schrijver & Mike Phillips
  8. *
  9. * This software may be used and distributed according to the terms
  10. * of the GNU General Public License, incorporated herein by reference.
  11. *
  12. * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
  13. *
  14. * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
  15. * 3/05/01 - Last clean up stuff before submission.
  16. * 2/15/01 - Finally, update to new pci api.
  17. *
  18. * To Do:
  19. */
  20. /*
  21. * Technical Card Details
  22. *
  23. * All access to data is done with 16/8 bit transfers. The transfer
  24. * method really sucks. You can only read or write one location at a time.
  25. *
  26. * Also, the microcode for the card must be uploaded if the card does not have
  27. * the flashrom on board. This is a 28K bloat in the driver when compiled
  28. * as a module.
  29. *
  30. * Rx is very simple, status into a ring of descriptors, dma data transfer,
  31. * interrupts to tell us when a packet is received.
  32. *
  33. * Tx is a little more interesting. Similar scenario, descriptor and dma data
  34. * transfers, but we don't have to interrupt the card to tell it another packet
  35. * is ready for transmission, we are just doing simple memory writes, not io or mmio
  36. * writes. The card can be set up to simply poll on the next
  37. * descriptor pointer and when this value is non-zero will automatically download
  38. * the next packet. The card then interrupts us when the packet is done.
  39. *
  40. */
  41. #define XL_DEBUG 0
  42. #include <linux/jiffies.h>
  43. #include <linux/module.h>
  44. #include <linux/kernel.h>
  45. #include <linux/errno.h>
  46. #include <linux/timer.h>
  47. #include <linux/in.h>
  48. #include <linux/ioport.h>
  49. #include <linux/string.h>
  50. #include <linux/proc_fs.h>
  51. #include <linux/ptrace.h>
  52. #include <linux/skbuff.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/delay.h>
  55. #include <linux/netdevice.h>
  56. #include <linux/trdevice.h>
  57. #include <linux/stddef.h>
  58. #include <linux/init.h>
  59. #include <linux/pci.h>
  60. #include <linux/spinlock.h>
  61. #include <linux/bitops.h>
  62. #include <net/checksum.h>
  63. #include <asm/io.h>
  64. #include <asm/system.h>
  65. #include "3c359.h"
  66. static char version[] __devinitdata =
  67. "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
  68. MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
  69. MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
  70. /* Module paramters */
  71. /* Ring Speed 0,4,16
  72. * 0 = Autosense
  73. * 4,16 = Selected speed only, no autosense
  74. * This allows the card to be the first on the ring
  75. * and become the active monitor.
  76. *
  77. * WARNING: Some hubs will allow you to insert
  78. * at the wrong speed.
  79. *
  80. * The adapter will _not_ fail to open if there are no
  81. * active monitors on the ring, it will simply open up in
  82. * its last known ringspeed if no ringspeed is specified.
  83. */
  84. static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
  85. module_param_array(ringspeed, int, NULL, 0);
  86. MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
  87. /* Packet buffer size */
  88. static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
  89. module_param_array(pkt_buf_sz, int, NULL, 0) ;
  90. MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
  91. /* Message Level */
  92. static int message_level[XL_MAX_ADAPTERS] = {0,} ;
  93. module_param_array(message_level, int, NULL, 0) ;
  94. MODULE_PARM_DESC(message_level, "3c359: Level of reported messages") ;
  95. /*
  96. * This is a real nasty way of doing this, but otherwise you
  97. * will be stuck with 1555 lines of hex #'s in the code.
  98. */
  99. #include "3c359_microcode.h"
  100. static struct pci_device_id xl_pci_tbl[] =
  101. {
  102. {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
  103. { } /* terminate list */
  104. };
  105. MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
  106. static int xl_init(struct net_device *dev);
  107. static int xl_open(struct net_device *dev);
  108. static int xl_open_hw(struct net_device *dev) ;
  109. static int xl_hw_reset(struct net_device *dev);
  110. static int xl_xmit(struct sk_buff *skb, struct net_device *dev);
  111. static void xl_dn_comp(struct net_device *dev);
  112. static int xl_close(struct net_device *dev);
  113. static void xl_set_rx_mode(struct net_device *dev);
  114. static irqreturn_t xl_interrupt(int irq, void *dev_id);
  115. static int xl_set_mac_address(struct net_device *dev, void *addr) ;
  116. static void xl_arb_cmd(struct net_device *dev);
  117. static void xl_asb_cmd(struct net_device *dev) ;
  118. static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
  119. static void xl_wait_misr_flags(struct net_device *dev) ;
  120. static int xl_change_mtu(struct net_device *dev, int mtu);
  121. static void xl_srb_bh(struct net_device *dev) ;
  122. static void xl_asb_bh(struct net_device *dev) ;
  123. static void xl_reset(struct net_device *dev) ;
  124. static void xl_freemem(struct net_device *dev) ;
  125. /* EEProm Access Functions */
  126. static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
  127. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
  128. /* Debugging functions */
  129. #if XL_DEBUG
  130. static void print_tx_state(struct net_device *dev) ;
  131. static void print_rx_state(struct net_device *dev) ;
  132. static void print_tx_state(struct net_device *dev)
  133. {
  134. struct xl_private *xl_priv = netdev_priv(dev);
  135. struct xl_tx_desc *txd ;
  136. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  137. int i ;
  138. printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
  139. xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
  140. printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
  141. for (i = 0; i < 16; i++) {
  142. txd = &(xl_priv->xl_tx_ring[i]) ;
  143. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
  144. txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
  145. }
  146. printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
  147. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  148. printk("Queue status = %0x \n",netif_running(dev) ) ;
  149. }
  150. static void print_rx_state(struct net_device *dev)
  151. {
  152. struct xl_private *xl_priv = netdev_priv(dev);
  153. struct xl_rx_desc *rxd ;
  154. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  155. int i ;
  156. printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
  157. printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
  158. for (i = 0; i < 16; i++) {
  159. /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
  160. rxd = &(xl_priv->xl_rx_ring[i]) ;
  161. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
  162. rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
  163. }
  164. printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
  165. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  166. printk("Queue status = %0x \n",netif_running(dev) ) ;
  167. }
  168. #endif
  169. /*
  170. * Read values from the on-board EEProm. This looks very strange
  171. * but you have to wait for the EEProm to get/set the value before
  172. * passing/getting the next value from the nic. As with all requests
  173. * on this nic it has to be done in two stages, a) tell the nic which
  174. * memory address you want to access and b) pass/get the value from the nic.
  175. * With the EEProm, you have to wait before and inbetween access a) and b).
  176. * As this is only read at initialization time and the wait period is very
  177. * small we shouldn't have to worry about scheduling issues.
  178. */
  179. static u16 xl_ee_read(struct net_device *dev, int ee_addr)
  180. {
  181. struct xl_private *xl_priv = netdev_priv(dev);
  182. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  183. /* Wait for EEProm to not be busy */
  184. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  185. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  186. /* Tell EEProm what we want to do and where */
  187. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  188. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  189. /* Wait for EEProm to not be busy */
  190. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  191. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  192. /* Tell EEProm what we want to do and where */
  193. writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  194. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  195. /* Finally read the value from the EEProm */
  196. writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  197. return readw(xl_mmio + MMIO_MACDATA) ;
  198. }
  199. /*
  200. * Write values to the onboard eeprom. As with eeprom read you need to
  201. * set which location to write, wait, value to write, wait, with the
  202. * added twist of having to enable eeprom writes as well.
  203. */
  204. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
  205. {
  206. struct xl_private *xl_priv = netdev_priv(dev);
  207. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  208. /* Wait for EEProm to not be busy */
  209. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  210. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  211. /* Enable write/erase */
  212. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  213. writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
  214. /* Wait for EEProm to not be busy */
  215. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  216. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  217. /* Put the value we want to write into EEDATA */
  218. writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  219. writew(ee_value, xl_mmio + MMIO_MACDATA) ;
  220. /* Tell EEProm to write eevalue into ee_addr */
  221. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  222. writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
  223. /* Wait for EEProm to not be busy, to ensure write gets done */
  224. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  225. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  226. return ;
  227. }
  228. static int __devinit xl_probe(struct pci_dev *pdev,
  229. const struct pci_device_id *ent)
  230. {
  231. struct net_device *dev ;
  232. struct xl_private *xl_priv ;
  233. static int card_no = -1 ;
  234. int i ;
  235. card_no++ ;
  236. if (pci_enable_device(pdev)) {
  237. return -ENODEV ;
  238. }
  239. pci_set_master(pdev);
  240. if ((i = pci_request_regions(pdev,"3c359"))) {
  241. return i ;
  242. } ;
  243. /*
  244. * Allowing init_trdev to allocate the dev->priv structure will align xl_private
  245. * on a 32 bytes boundary which we need for the rx/tx descriptors
  246. */
  247. dev = alloc_trdev(sizeof(struct xl_private)) ;
  248. if (!dev) {
  249. pci_release_regions(pdev) ;
  250. return -ENOMEM ;
  251. }
  252. xl_priv = netdev_priv(dev);
  253. #if XL_DEBUG
  254. printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
  255. pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start);
  256. #endif
  257. dev->irq=pdev->irq;
  258. dev->base_addr=pci_resource_start(pdev,0) ;
  259. xl_priv->xl_card_name = pci_name(pdev);
  260. xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
  261. xl_priv->pdev = pdev ;
  262. if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
  263. xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
  264. else
  265. xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
  266. dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
  267. xl_priv->xl_ring_speed = ringspeed[card_no] ;
  268. xl_priv->xl_message_level = message_level[card_no] ;
  269. xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
  270. xl_priv->xl_copy_all_options = 0 ;
  271. if((i = xl_init(dev))) {
  272. iounmap(xl_priv->xl_mmio) ;
  273. free_netdev(dev) ;
  274. pci_release_regions(pdev) ;
  275. return i ;
  276. }
  277. dev->open=&xl_open;
  278. dev->hard_start_xmit=&xl_xmit;
  279. dev->change_mtu=&xl_change_mtu;
  280. dev->stop=&xl_close;
  281. dev->do_ioctl=NULL;
  282. dev->set_multicast_list=&xl_set_rx_mode;
  283. dev->set_mac_address=&xl_set_mac_address ;
  284. SET_NETDEV_DEV(dev, &pdev->dev);
  285. pci_set_drvdata(pdev,dev) ;
  286. if ((i = register_netdev(dev))) {
  287. printk(KERN_ERR "3C359, register netdev failed\n") ;
  288. pci_set_drvdata(pdev,NULL) ;
  289. iounmap(xl_priv->xl_mmio) ;
  290. free_netdev(dev) ;
  291. pci_release_regions(pdev) ;
  292. return i ;
  293. }
  294. printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
  295. return 0;
  296. }
  297. static int __devinit xl_init(struct net_device *dev)
  298. {
  299. struct xl_private *xl_priv = netdev_priv(dev);
  300. printk(KERN_INFO "%s \n", version);
  301. printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
  302. xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
  303. spin_lock_init(&xl_priv->xl_lock) ;
  304. return xl_hw_reset(dev) ;
  305. }
  306. /*
  307. * Hardware reset. This needs to be a separate entity as we need to reset the card
  308. * when we change the EEProm settings.
  309. */
  310. static int xl_hw_reset(struct net_device *dev)
  311. {
  312. struct xl_private *xl_priv = netdev_priv(dev);
  313. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  314. unsigned long t ;
  315. u16 i ;
  316. u16 result_16 ;
  317. u8 result_8 ;
  318. u16 start ;
  319. int j ;
  320. /*
  321. * Reset the card. If the card has got the microcode on board, we have
  322. * missed the initialization interrupt, so we must always do this.
  323. */
  324. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  325. /*
  326. * Must wait for cmdInProgress bit (12) to clear before continuing with
  327. * card configuration.
  328. */
  329. t=jiffies;
  330. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  331. schedule();
  332. if (time_after(jiffies, t + 40 * HZ)) {
  333. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
  334. return -ENODEV;
  335. }
  336. }
  337. /*
  338. * Enable pmbar by setting bit in CPAttention
  339. */
  340. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  341. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  342. result_8 = result_8 | CPA_PMBARVIS ;
  343. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  344. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  345. /*
  346. * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
  347. * If not, we need to upload the microcode to the card
  348. */
  349. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  350. #if XL_DEBUG
  351. printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
  352. #endif
  353. if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
  354. /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
  355. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  356. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  357. result_16 = result_16 & ~((0x7F) << 2) ;
  358. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  359. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  360. /* Set CPAttention, memWrEn bit */
  361. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  362. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  363. result_8 = result_8 | CPA_MEMWREN ;
  364. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  365. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  366. /*
  367. * Now to write the microcode into the shared ram
  368. * The microcode must finish at position 0xFFFF, so we must subtract
  369. * to get the start position for the code
  370. */
  371. start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */
  372. printk(KERN_INFO "3C359: Uploading Microcode: ");
  373. for (i = start, j = 0; j < mc_size; i++, j++) {
  374. writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  375. writeb(microcode[j],xl_mmio + MMIO_MACDATA) ;
  376. if (j % 1024 == 0)
  377. printk(".");
  378. }
  379. printk("\n") ;
  380. for (i=0;i < 16; i++) {
  381. writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  382. writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ;
  383. }
  384. /*
  385. * Have to write the start address of the upload to FFF4, but
  386. * the address must be >> 4. You do not want to know how long
  387. * it took me to discover this.
  388. */
  389. writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  390. writew(start >> 4, xl_mmio + MMIO_MACDATA);
  391. /* Clear the CPAttention, memWrEn Bit */
  392. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  393. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  394. result_8 = result_8 & ~CPA_MEMWREN ;
  395. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  396. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  397. /* Clear the cpHold bit in pmbar */
  398. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  399. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  400. result_16 = result_16 & ~PMB_CPHOLD ;
  401. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  402. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  403. } /* If microcode upload required */
  404. /*
  405. * The card should now go though a self test procedure and get itself ready
  406. * to be opened, we must wait for an srb response with the initialization
  407. * information.
  408. */
  409. #if XL_DEBUG
  410. printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
  411. #endif
  412. writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
  413. t=jiffies;
  414. while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
  415. schedule();
  416. if (time_after(jiffies, t + 15 * HZ)) {
  417. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  418. return -ENODEV;
  419. }
  420. }
  421. /*
  422. * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
  423. * DnPriReqThresh, read the tech docs if you want to know what
  424. * values they need to be.
  425. */
  426. writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  427. writew(0xD000, xl_mmio + MMIO_MACDATA) ;
  428. writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  429. writew(0X0020, xl_mmio + MMIO_MACDATA) ;
  430. writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
  431. writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
  432. writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
  433. /*
  434. * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
  435. * Tech docs have this wrong !!!!
  436. */
  437. writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  438. xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  439. writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  440. xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
  441. #if XL_DEBUG
  442. writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  443. if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
  444. printk(KERN_INFO "Default ring speed 4 mbps \n") ;
  445. } else {
  446. printk(KERN_INFO "Default ring speed 16 mbps \n") ;
  447. }
  448. printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
  449. #endif
  450. return 0;
  451. }
  452. static int xl_open(struct net_device *dev)
  453. {
  454. struct xl_private *xl_priv=netdev_priv(dev);
  455. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  456. u8 i ;
  457. __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
  458. int open_err ;
  459. u16 switchsettings, switchsettings_eeprom ;
  460. if(request_irq(dev->irq, &xl_interrupt, IRQF_SHARED , "3c359", dev)) {
  461. return -EAGAIN;
  462. }
  463. /*
  464. * Read the information from the EEPROM that we need.
  465. */
  466. hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10));
  467. hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11));
  468. hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12));
  469. /* Ring speed */
  470. switchsettings_eeprom = xl_ee_read(dev,0x08) ;
  471. switchsettings = switchsettings_eeprom ;
  472. if (xl_priv->xl_ring_speed != 0) {
  473. if (xl_priv->xl_ring_speed == 4)
  474. switchsettings = switchsettings | 0x02 ;
  475. else
  476. switchsettings = switchsettings & ~0x02 ;
  477. }
  478. /* Only write EEProm if there has been a change */
  479. if (switchsettings != switchsettings_eeprom) {
  480. xl_ee_write(dev,0x08,switchsettings) ;
  481. /* Hardware reset after changing EEProm */
  482. xl_hw_reset(dev) ;
  483. }
  484. memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
  485. open_err = xl_open_hw(dev) ;
  486. /*
  487. * This really needs to be cleaned up with better error reporting.
  488. */
  489. if (open_err != 0) { /* Something went wrong with the open command */
  490. if (open_err & 0x07) { /* Wrong speed, retry at different speed */
  491. printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
  492. switchsettings = switchsettings ^ 2 ;
  493. xl_ee_write(dev,0x08,switchsettings) ;
  494. xl_hw_reset(dev) ;
  495. open_err = xl_open_hw(dev) ;
  496. if (open_err != 0) {
  497. printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
  498. free_irq(dev->irq,dev) ;
  499. return -ENODEV ;
  500. }
  501. } else {
  502. printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
  503. free_irq(dev->irq,dev) ;
  504. return -ENODEV ;
  505. }
  506. }
  507. /*
  508. * Now to set up the Rx and Tx buffer structures
  509. */
  510. /* These MUST be on 8 byte boundaries */
  511. xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL);
  512. if (xl_priv->xl_tx_ring == NULL) {
  513. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
  514. dev->name);
  515. free_irq(dev->irq,dev);
  516. return -ENOMEM;
  517. }
  518. xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL);
  519. if (xl_priv->xl_tx_ring == NULL) {
  520. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
  521. dev->name);
  522. free_irq(dev->irq,dev);
  523. kfree(xl_priv->xl_tx_ring);
  524. return -ENOMEM;
  525. }
  526. /* Setup Rx Ring */
  527. for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
  528. struct sk_buff *skb ;
  529. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  530. if (skb==NULL)
  531. break ;
  532. skb->dev = dev ;
  533. xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
  534. xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
  535. xl_priv->rx_ring_skb[i] = skb ;
  536. }
  537. if (i==0) {
  538. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
  539. free_irq(dev->irq,dev) ;
  540. return -EIO ;
  541. }
  542. xl_priv->rx_ring_no = i ;
  543. xl_priv->rx_ring_tail = 0 ;
  544. xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
  545. for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
  546. xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)));
  547. }
  548. xl_priv->xl_rx_ring[i].upnextptr = 0 ;
  549. writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
  550. /* Setup Tx Ring */
  551. xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
  552. xl_priv->tx_ring_head = 1 ;
  553. xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
  554. xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
  555. /*
  556. * Setup the first dummy DPD entry for polling to start working.
  557. */
  558. xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY;
  559. xl_priv->xl_tx_ring[0].buffer = 0 ;
  560. xl_priv->xl_tx_ring[0].buffer_length = 0 ;
  561. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  562. writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
  563. writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
  564. writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
  565. writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
  566. writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
  567. /*
  568. * Enable interrupts on the card
  569. */
  570. writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  571. writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  572. netif_start_queue(dev) ;
  573. return 0;
  574. }
  575. static int xl_open_hw(struct net_device *dev)
  576. {
  577. struct xl_private *xl_priv=netdev_priv(dev);
  578. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  579. u16 vsoff ;
  580. char ver_str[33];
  581. int open_err ;
  582. int i ;
  583. unsigned long t ;
  584. /*
  585. * Okay, let's build up the Open.NIC srb command
  586. *
  587. */
  588. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  589. writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
  590. /*
  591. * Use this as a test byte, if it comes back with the same value, the command didn't work
  592. */
  593. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  594. writeb(0xff,xl_mmio + MMIO_MACDATA) ;
  595. /* Open options */
  596. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  597. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  598. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  599. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  600. /*
  601. * Node address, be careful here, the docs say you can just put zeros here and it will use
  602. * the hardware address, it doesn't, you must include the node address in the open command.
  603. */
  604. if (xl_priv->xl_laa[0]) { /* If using a LAA address */
  605. for (i=10;i<16;i++) {
  606. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  607. writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
  608. }
  609. memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
  610. } else { /* Regular hardware address */
  611. for (i=10;i<16;i++) {
  612. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  613. writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
  614. }
  615. }
  616. /* Default everything else to 0 */
  617. for (i = 16; i < 34; i++) {
  618. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  619. writeb(0x00,xl_mmio + MMIO_MACDATA) ;
  620. }
  621. /*
  622. * Set the csrb bit in the MISR register
  623. */
  624. xl_wait_misr_flags(dev) ;
  625. writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  626. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  627. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  628. writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
  629. /*
  630. * Now wait for the command to run
  631. */
  632. t=jiffies;
  633. while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  634. schedule();
  635. if (time_after(jiffies, t + 40 * HZ)) {
  636. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  637. break ;
  638. }
  639. }
  640. /*
  641. * Let's interpret the open response
  642. */
  643. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  644. if (readb(xl_mmio + MMIO_MACDATA)!=0) {
  645. open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  646. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  647. open_err |= readb(xl_mmio + MMIO_MACDATA) ;
  648. return open_err ;
  649. } else {
  650. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  651. xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  652. printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
  653. printk("ASB: %04x",xl_priv->asb ) ;
  654. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  655. printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ;
  656. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  657. xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  658. printk(", ARB: %04x \n",xl_priv->arb ) ;
  659. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  660. vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  661. /*
  662. * Interesting, sending the individual characters directly to printk was causing klogd to use
  663. * use 100% of processor time, so we build up the string and print that instead.
  664. */
  665. for (i=0;i<0x20;i++) {
  666. writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  667. ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
  668. }
  669. ver_str[i] = '\0' ;
  670. printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
  671. }
  672. /*
  673. * Issue the AckInterrupt
  674. */
  675. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  676. return 0 ;
  677. }
  678. /*
  679. * There are two ways of implementing rx on the 359 NIC, either
  680. * interrupt driven or polling. We are going to uses interrupts,
  681. * it is the easier way of doing things.
  682. *
  683. * The Rx works with a ring of Rx descriptors. At initialise time the ring
  684. * entries point to the next entry except for the last entry in the ring
  685. * which points to 0. The card is programmed with the location of the first
  686. * available descriptor and keeps reading the next_ptr until next_ptr is set
  687. * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
  688. * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
  689. * and then point the end of the ring to our current position and point our current
  690. * position to 0, therefore making the current position the last position on the ring.
  691. * The last position on the ring therefore loops continually loops around the rx ring.
  692. *
  693. * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
  694. * expands as the card adds new packets and we go around eating the tail processing the
  695. * packets.)
  696. *
  697. * Undoubtably it could be streamlined and improved upon, but at the moment it works
  698. * and the fast path through the routine is fine.
  699. *
  700. * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
  701. * in xl_rx so would increase the size of the function significantly.
  702. */
  703. static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
  704. {
  705. struct xl_private *xl_priv=netdev_priv(dev);
  706. int n = xl_priv->rx_ring_tail;
  707. int prev_ring_loc;
  708. prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
  709. xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n));
  710. xl_priv->xl_rx_ring[n].framestatus = 0;
  711. xl_priv->xl_rx_ring[n].upnextptr = 0;
  712. xl_priv->rx_ring_tail++;
  713. xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1);
  714. }
  715. static void xl_rx(struct net_device *dev)
  716. {
  717. struct xl_private *xl_priv=netdev_priv(dev);
  718. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  719. struct sk_buff *skb, *skb2 ;
  720. int frame_length = 0, copy_len = 0 ;
  721. int temp_ring_loc ;
  722. /*
  723. * Receive the next frame, loop around the ring until all frames
  724. * have been received.
  725. */
  726. while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
  727. if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
  728. /*
  729. * This is a pain, you need to go through all the descriptors until the last one
  730. * for this frame to find the framelength
  731. */
  732. temp_ring_loc = xl_priv->rx_ring_tail ;
  733. while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
  734. temp_ring_loc++ ;
  735. temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
  736. }
  737. frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF;
  738. skb = dev_alloc_skb(frame_length) ;
  739. if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
  740. printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
  741. while (xl_priv->rx_ring_tail != temp_ring_loc)
  742. adv_rx_ring(dev) ;
  743. adv_rx_ring(dev) ; /* One more time just for luck :) */
  744. dev->stats.rx_dropped++ ;
  745. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  746. return ;
  747. }
  748. while (xl_priv->rx_ring_tail != temp_ring_loc) {
  749. copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF;
  750. frame_length -= copy_len ;
  751. pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  752. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  753. skb_put(skb, copy_len),
  754. copy_len);
  755. pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  756. adv_rx_ring(dev) ;
  757. }
  758. /* Now we have found the last fragment */
  759. pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  760. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  761. skb_put(skb,copy_len), frame_length);
  762. /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
  763. pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  764. adv_rx_ring(dev) ;
  765. skb->protocol = tr_type_trans(skb,dev) ;
  766. netif_rx(skb) ;
  767. } else { /* Single Descriptor Used, simply swap buffers over, fast path */
  768. frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF;
  769. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  770. if (skb==NULL) { /* Still need to fix the rx ring */
  771. printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
  772. adv_rx_ring(dev) ;
  773. dev->stats.rx_dropped++ ;
  774. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  775. return ;
  776. }
  777. skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
  778. pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  779. skb_put(skb2, frame_length) ;
  780. skb2->protocol = tr_type_trans(skb2,dev) ;
  781. xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
  782. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
  783. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
  784. adv_rx_ring(dev) ;
  785. dev->stats.rx_packets++ ;
  786. dev->stats.rx_bytes += frame_length ;
  787. netif_rx(skb2) ;
  788. } /* if multiple buffers */
  789. dev->last_rx = jiffies ;
  790. } /* while packet to do */
  791. /* Clear the updComplete interrupt */
  792. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  793. return ;
  794. }
  795. /*
  796. * This is ruthless, it doesn't care what state the card is in it will
  797. * completely reset the adapter.
  798. */
  799. static void xl_reset(struct net_device *dev)
  800. {
  801. struct xl_private *xl_priv=netdev_priv(dev);
  802. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  803. unsigned long t;
  804. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  805. /*
  806. * Must wait for cmdInProgress bit (12) to clear before continuing with
  807. * card configuration.
  808. */
  809. t=jiffies;
  810. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  811. if (time_after(jiffies, t + 40 * HZ)) {
  812. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  813. break ;
  814. }
  815. }
  816. }
  817. static void xl_freemem(struct net_device *dev)
  818. {
  819. struct xl_private *xl_priv=netdev_priv(dev);
  820. int i ;
  821. for (i=0;i<XL_RX_RING_SIZE;i++) {
  822. dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
  823. pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
  824. xl_priv->rx_ring_tail++ ;
  825. xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
  826. }
  827. /* unmap ring */
  828. pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
  829. pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
  830. kfree(xl_priv->xl_rx_ring) ;
  831. kfree(xl_priv->xl_tx_ring) ;
  832. return ;
  833. }
  834. static irqreturn_t xl_interrupt(int irq, void *dev_id)
  835. {
  836. struct net_device *dev = (struct net_device *)dev_id;
  837. struct xl_private *xl_priv =netdev_priv(dev);
  838. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  839. u16 intstatus, macstatus ;
  840. intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
  841. if (!(intstatus & 1)) /* We didn't generate the interrupt */
  842. return IRQ_NONE;
  843. spin_lock(&xl_priv->xl_lock) ;
  844. /*
  845. * Process the interrupt
  846. */
  847. /*
  848. * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
  849. */
  850. if (intstatus == 0x0001) {
  851. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  852. printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
  853. } else {
  854. if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
  855. /*
  856. * Host Error.
  857. * It may be possible to recover from this, but usually it means something
  858. * is seriously fubar, so we just close the adapter.
  859. */
  860. if (intstatus & HOSTERRINT) {
  861. printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
  862. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  863. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  864. netif_stop_queue(dev) ;
  865. xl_freemem(dev) ;
  866. free_irq(dev->irq,dev);
  867. xl_reset(dev) ;
  868. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  869. spin_unlock(&xl_priv->xl_lock) ;
  870. return IRQ_HANDLED;
  871. } /* Host Error */
  872. if (intstatus & SRBRINT ) { /* Srbc interrupt */
  873. writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  874. if (xl_priv->srb_queued)
  875. xl_srb_bh(dev) ;
  876. } /* SRBR Interrupt */
  877. if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
  878. writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  879. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
  880. /* !!! FIX-ME !!!!
  881. Must put a timeout check here ! */
  882. /* Empty Loop */
  883. }
  884. printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
  885. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  886. } /* TxUnderRun */
  887. if (intstatus & ARBCINT ) { /* Arbc interrupt */
  888. xl_arb_cmd(dev) ;
  889. } /* Arbc */
  890. if (intstatus & ASBFINT) {
  891. if (xl_priv->asb_queued == 1) {
  892. xl_asb_cmd(dev) ;
  893. } else if (xl_priv->asb_queued == 2) {
  894. xl_asb_bh(dev) ;
  895. } else {
  896. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  897. }
  898. } /* Asbf */
  899. if (intstatus & UPCOMPINT ) /* UpComplete */
  900. xl_rx(dev) ;
  901. if (intstatus & DNCOMPINT ) /* DnComplete */
  902. xl_dn_comp(dev) ;
  903. if (intstatus & HARDERRINT ) { /* Hardware error */
  904. writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  905. macstatus = readw(xl_mmio + MMIO_MACDATA) ;
  906. printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
  907. if (macstatus & (1<<14))
  908. printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
  909. if (macstatus & (1<<3))
  910. printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
  911. if (macstatus & (1<<2))
  912. printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ;
  913. printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
  914. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  915. netif_stop_queue(dev) ;
  916. xl_freemem(dev) ;
  917. free_irq(dev->irq,dev);
  918. unregister_netdev(dev) ;
  919. free_netdev(dev) ;
  920. xl_reset(dev) ;
  921. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  922. spin_unlock(&xl_priv->xl_lock) ;
  923. return IRQ_HANDLED;
  924. }
  925. } else {
  926. printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
  927. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  928. }
  929. }
  930. /* Turn interrupts back on */
  931. writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  932. writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  933. spin_unlock(&xl_priv->xl_lock) ;
  934. return IRQ_HANDLED;
  935. }
  936. /*
  937. * Tx - Polling configuration
  938. */
  939. static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
  940. {
  941. struct xl_private *xl_priv=netdev_priv(dev);
  942. struct xl_tx_desc *txd ;
  943. int tx_head, tx_tail, tx_prev ;
  944. unsigned long flags ;
  945. spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
  946. netif_stop_queue(dev) ;
  947. if (xl_priv->free_ring_entries > 1 ) {
  948. /*
  949. * Set up the descriptor for the packet
  950. */
  951. tx_head = xl_priv->tx_ring_head ;
  952. tx_tail = xl_priv->tx_ring_tail ;
  953. txd = &(xl_priv->xl_tx_ring[tx_head]) ;
  954. txd->dnnextptr = 0 ;
  955. txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE;
  956. txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
  957. txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST;
  958. xl_priv->tx_ring_skb[tx_head] = skb ;
  959. dev->stats.tx_packets++ ;
  960. dev->stats.tx_bytes += skb->len ;
  961. /*
  962. * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
  963. * to ensure no negative numbers in unsigned locations.
  964. */
  965. tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
  966. xl_priv->tx_ring_head++ ;
  967. xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
  968. xl_priv->free_ring_entries-- ;
  969. xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head));
  970. /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
  971. /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
  972. netif_wake_queue(dev) ;
  973. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  974. return 0;
  975. } else {
  976. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  977. return 1;
  978. }
  979. }
  980. /*
  981. * The NIC has told us that a packet has been downloaded onto the card, we must
  982. * find out which packet it has done, clear the skb and information for the packet
  983. * then advance around the ring for all tranmitted packets
  984. */
  985. static void xl_dn_comp(struct net_device *dev)
  986. {
  987. struct xl_private *xl_priv=netdev_priv(dev);
  988. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  989. struct xl_tx_desc *txd ;
  990. if (xl_priv->tx_ring_tail == 255) {/* First time */
  991. xl_priv->xl_tx_ring[0].framestartheader = 0 ;
  992. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  993. xl_priv->tx_ring_tail = 1 ;
  994. }
  995. while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
  996. txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
  997. pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE);
  998. txd->framestartheader = 0 ;
  999. txd->buffer = cpu_to_le32(0xdeadbeef);
  1000. txd->buffer_length = 0 ;
  1001. dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
  1002. xl_priv->tx_ring_tail++ ;
  1003. xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
  1004. xl_priv->free_ring_entries++ ;
  1005. }
  1006. netif_wake_queue(dev) ;
  1007. writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1008. }
  1009. /*
  1010. * Close the adapter properly.
  1011. * This srb reply cannot be handled from interrupt context as we have
  1012. * to free the interrupt from the driver.
  1013. */
  1014. static int xl_close(struct net_device *dev)
  1015. {
  1016. struct xl_private *xl_priv = netdev_priv(dev);
  1017. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1018. unsigned long t ;
  1019. netif_stop_queue(dev) ;
  1020. /*
  1021. * Close the adapter, need to stall the rx and tx queues.
  1022. */
  1023. writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
  1024. t=jiffies;
  1025. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1026. schedule();
  1027. if (time_after(jiffies, t + 10 * HZ)) {
  1028. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
  1029. break ;
  1030. }
  1031. }
  1032. writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
  1033. t=jiffies;
  1034. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1035. schedule();
  1036. if (time_after(jiffies, t + 10 * HZ)) {
  1037. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
  1038. break ;
  1039. }
  1040. }
  1041. writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
  1042. t=jiffies;
  1043. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1044. schedule();
  1045. if (time_after(jiffies, t + 10 * HZ)) {
  1046. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
  1047. break ;
  1048. }
  1049. }
  1050. /* Turn off interrupts, we will still get the indication though
  1051. * so we can trap it
  1052. */
  1053. writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
  1054. xl_srb_cmd(dev,CLOSE_NIC) ;
  1055. t=jiffies;
  1056. while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  1057. schedule();
  1058. if (time_after(jiffies, t + 10 * HZ)) {
  1059. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
  1060. break ;
  1061. }
  1062. }
  1063. /* Read the srb response from the adapter */
  1064. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1065. if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
  1066. printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
  1067. } else {
  1068. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1069. if (readb(xl_mmio + MMIO_MACDATA)==0) {
  1070. printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
  1071. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1072. xl_freemem(dev) ;
  1073. free_irq(dev->irq,dev) ;
  1074. } else {
  1075. printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
  1076. }
  1077. }
  1078. /* Reset the upload and download logic */
  1079. writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
  1080. t=jiffies;
  1081. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1082. schedule();
  1083. if (time_after(jiffies, t + 10 * HZ)) {
  1084. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
  1085. break ;
  1086. }
  1087. }
  1088. writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
  1089. t=jiffies;
  1090. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1091. schedule();
  1092. if (time_after(jiffies, t + 10 * HZ)) {
  1093. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
  1094. break ;
  1095. }
  1096. }
  1097. xl_hw_reset(dev) ;
  1098. return 0 ;
  1099. }
  1100. static void xl_set_rx_mode(struct net_device *dev)
  1101. {
  1102. struct xl_private *xl_priv = netdev_priv(dev);
  1103. struct dev_mc_list *dmi ;
  1104. unsigned char dev_mc_address[4] ;
  1105. u16 options ;
  1106. int i ;
  1107. if (dev->flags & IFF_PROMISC)
  1108. options = 0x0004 ;
  1109. else
  1110. options = 0x0000 ;
  1111. if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
  1112. xl_priv->xl_copy_all_options = options ;
  1113. xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
  1114. return ;
  1115. }
  1116. dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
  1117. for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
  1118. dev_mc_address[0] |= dmi->dmi_addr[2] ;
  1119. dev_mc_address[1] |= dmi->dmi_addr[3] ;
  1120. dev_mc_address[2] |= dmi->dmi_addr[4] ;
  1121. dev_mc_address[3] |= dmi->dmi_addr[5] ;
  1122. }
  1123. if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
  1124. memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
  1125. xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
  1126. }
  1127. return ;
  1128. }
  1129. /*
  1130. * We issued an srb command and now we must read
  1131. * the response from the completed command.
  1132. */
  1133. static void xl_srb_bh(struct net_device *dev)
  1134. {
  1135. struct xl_private *xl_priv = netdev_priv(dev);
  1136. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1137. u8 srb_cmd, ret_code ;
  1138. int i ;
  1139. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1140. srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1141. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1142. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1143. /* Ret_code is standard across all commands */
  1144. switch (ret_code) {
  1145. case 1:
  1146. printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
  1147. break ;
  1148. case 4:
  1149. printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
  1150. break ;
  1151. case 6:
  1152. printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
  1153. break ;
  1154. case 0: /* Successful command execution */
  1155. switch (srb_cmd) {
  1156. case READ_LOG: /* Returns 14 bytes of data from the NIC */
  1157. if(xl_priv->xl_message_level)
  1158. printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
  1159. /*
  1160. * We still have to read the log even if message_level = 0 and we don't want
  1161. * to see it
  1162. */
  1163. for (i=0;i<14;i++) {
  1164. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1165. if(xl_priv->xl_message_level)
  1166. printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
  1167. }
  1168. printk("\n") ;
  1169. break ;
  1170. case SET_FUNC_ADDRESS:
  1171. if(xl_priv->xl_message_level)
  1172. printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
  1173. break ;
  1174. case CLOSE_NIC:
  1175. if(xl_priv->xl_message_level)
  1176. printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
  1177. break ;
  1178. case SET_MULTICAST_MODE:
  1179. if(xl_priv->xl_message_level)
  1180. printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
  1181. break ;
  1182. case SET_RECEIVE_MODE:
  1183. if(xl_priv->xl_message_level) {
  1184. if (xl_priv->xl_copy_all_options == 0x0004)
  1185. printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
  1186. else
  1187. printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
  1188. }
  1189. break ;
  1190. } /* switch */
  1191. break ;
  1192. } /* switch */
  1193. return ;
  1194. }
  1195. static int xl_set_mac_address (struct net_device *dev, void *addr)
  1196. {
  1197. struct sockaddr *saddr = addr ;
  1198. struct xl_private *xl_priv = netdev_priv(dev);
  1199. if (netif_running(dev)) {
  1200. printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
  1201. return -EIO ;
  1202. }
  1203. memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
  1204. if (xl_priv->xl_message_level) {
  1205. printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
  1206. xl_priv->xl_laa[1], xl_priv->xl_laa[2],
  1207. xl_priv->xl_laa[3], xl_priv->xl_laa[4],
  1208. xl_priv->xl_laa[5]);
  1209. }
  1210. return 0 ;
  1211. }
  1212. static void xl_arb_cmd(struct net_device *dev)
  1213. {
  1214. struct xl_private *xl_priv = netdev_priv(dev);
  1215. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1216. u8 arb_cmd ;
  1217. u16 lan_status, lan_status_diff ;
  1218. writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1219. arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1220. if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
  1221. writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1222. printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ;
  1223. lan_status = swab16(readw(xl_mmio + MMIO_MACDATA));
  1224. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1225. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1226. lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
  1227. if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
  1228. if (lan_status_diff & LSC_LWF)
  1229. printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
  1230. if (lan_status_diff & LSC_ARW)
  1231. printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
  1232. if (lan_status_diff & LSC_FPE)
  1233. printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
  1234. if (lan_status_diff & LSC_RR)
  1235. printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
  1236. /* Adapter has been closed by the hardware */
  1237. netif_stop_queue(dev);
  1238. xl_freemem(dev) ;
  1239. free_irq(dev->irq,dev);
  1240. printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
  1241. } /* If serious error */
  1242. if (xl_priv->xl_message_level) {
  1243. if (lan_status_diff & LSC_SIG_LOSS)
  1244. printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
  1245. if (lan_status_diff & LSC_HARD_ERR)
  1246. printk(KERN_INFO "%s: Beaconing \n",dev->name);
  1247. if (lan_status_diff & LSC_SOFT_ERR)
  1248. printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
  1249. if (lan_status_diff & LSC_TRAN_BCN)
  1250. printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
  1251. if (lan_status_diff & LSC_SS)
  1252. printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
  1253. if (lan_status_diff & LSC_RING_REC)
  1254. printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
  1255. if (lan_status_diff & LSC_FDX_MODE)
  1256. printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
  1257. }
  1258. if (lan_status_diff & LSC_CO) {
  1259. if (xl_priv->xl_message_level)
  1260. printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
  1261. /* Issue READ.LOG command */
  1262. xl_srb_cmd(dev, READ_LOG) ;
  1263. }
  1264. /* There is no command in the tech docs to issue the read_sr_counters */
  1265. if (lan_status_diff & LSC_SR_CO) {
  1266. if (xl_priv->xl_message_level)
  1267. printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
  1268. }
  1269. xl_priv->xl_lan_status = lan_status ;
  1270. } /* Lan.change.status */
  1271. else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
  1272. #if XL_DEBUG
  1273. printk(KERN_INFO "Received.Data \n") ;
  1274. #endif
  1275. writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1276. xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  1277. /* Now we are going to be really basic here and not do anything
  1278. * with the data at all. The tech docs do not give me enough
  1279. * information to calculate the buffers properly so we're
  1280. * just going to tell the nic that we've dealt with the frame
  1281. * anyway.
  1282. */
  1283. dev->last_rx = jiffies ;
  1284. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1285. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1286. /* Is the ASB free ? */
  1287. xl_priv->asb_queued = 0 ;
  1288. writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1289. if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
  1290. xl_priv->asb_queued = 1 ;
  1291. xl_wait_misr_flags(dev) ;
  1292. writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1293. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1294. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1295. writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
  1296. return ;
  1297. /* Drop out and wait for the bottom half to be run */
  1298. }
  1299. xl_asb_cmd(dev) ;
  1300. } else {
  1301. printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
  1302. }
  1303. /* Acknowledge the arb interrupt */
  1304. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1305. return ;
  1306. }
  1307. /*
  1308. * There is only one asb command, but we can get called from different
  1309. * places.
  1310. */
  1311. static void xl_asb_cmd(struct net_device *dev)
  1312. {
  1313. struct xl_private *xl_priv = netdev_priv(dev);
  1314. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1315. if (xl_priv->asb_queued == 1)
  1316. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1317. writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1318. writeb(0x81, xl_mmio + MMIO_MACDATA) ;
  1319. writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1320. writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
  1321. xl_wait_misr_flags(dev) ;
  1322. writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1323. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1324. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1325. writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
  1326. xl_priv->asb_queued = 2 ;
  1327. return ;
  1328. }
  1329. /*
  1330. * This will only get called if there was an error
  1331. * from the asb cmd.
  1332. */
  1333. static void xl_asb_bh(struct net_device *dev)
  1334. {
  1335. struct xl_private *xl_priv = netdev_priv(dev);
  1336. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1337. u8 ret_code ;
  1338. writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1339. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1340. switch (ret_code) {
  1341. case 0x01:
  1342. printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
  1343. break ;
  1344. case 0x26:
  1345. printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
  1346. break ;
  1347. case 0x40:
  1348. printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
  1349. break ;
  1350. }
  1351. xl_priv->asb_queued = 0 ;
  1352. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1353. return ;
  1354. }
  1355. /*
  1356. * Issue srb commands to the nic
  1357. */
  1358. static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
  1359. {
  1360. struct xl_private *xl_priv = netdev_priv(dev);
  1361. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1362. switch (srb_cmd) {
  1363. case READ_LOG:
  1364. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1365. writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
  1366. break;
  1367. case CLOSE_NIC:
  1368. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1369. writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
  1370. break ;
  1371. case SET_RECEIVE_MODE:
  1372. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1373. writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
  1374. writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1375. writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
  1376. break ;
  1377. case SET_FUNC_ADDRESS:
  1378. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1379. writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
  1380. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1381. writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
  1382. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1383. writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
  1384. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1385. writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
  1386. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1387. writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
  1388. break ;
  1389. } /* switch */
  1390. xl_wait_misr_flags(dev) ;
  1391. /* Write 0xff to the CSRB flag */
  1392. writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1393. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  1394. /* Set csrb bit in MISR register to process command */
  1395. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1396. writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
  1397. xl_priv->srb_queued = 1 ;
  1398. return ;
  1399. }
  1400. /*
  1401. * This is nasty, to use the MISR command you have to wait for 6 memory locations
  1402. * to be zero. This is the way the driver does on other OS'es so we should be ok with
  1403. * the empty loop.
  1404. */
  1405. static void xl_wait_misr_flags(struct net_device *dev)
  1406. {
  1407. struct xl_private *xl_priv = netdev_priv(dev);
  1408. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1409. int i ;
  1410. writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1411. if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
  1412. for (i=0; i<6; i++) {
  1413. writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1414. while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
  1415. }
  1416. }
  1417. writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1418. writeb(0x80, xl_mmio + MMIO_MACDATA) ;
  1419. return ;
  1420. }
  1421. /*
  1422. * Change mtu size, this should work the same as olympic
  1423. */
  1424. static int xl_change_mtu(struct net_device *dev, int mtu)
  1425. {
  1426. struct xl_private *xl_priv = netdev_priv(dev);
  1427. u16 max_mtu ;
  1428. if (xl_priv->xl_ring_speed == 4)
  1429. max_mtu = 4500 ;
  1430. else
  1431. max_mtu = 18000 ;
  1432. if (mtu > max_mtu)
  1433. return -EINVAL ;
  1434. if (mtu < 100)
  1435. return -EINVAL ;
  1436. dev->mtu = mtu ;
  1437. xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
  1438. return 0 ;
  1439. }
  1440. static void __devexit xl_remove_one (struct pci_dev *pdev)
  1441. {
  1442. struct net_device *dev = pci_get_drvdata(pdev);
  1443. struct xl_private *xl_priv=netdev_priv(dev);
  1444. unregister_netdev(dev);
  1445. iounmap(xl_priv->xl_mmio) ;
  1446. pci_release_regions(pdev) ;
  1447. pci_set_drvdata(pdev,NULL) ;
  1448. free_netdev(dev);
  1449. return ;
  1450. }
  1451. static struct pci_driver xl_3c359_driver = {
  1452. .name = "3c359",
  1453. .id_table = xl_pci_tbl,
  1454. .probe = xl_probe,
  1455. .remove = __devexit_p(xl_remove_one),
  1456. };
  1457. static int __init xl_pci_init (void)
  1458. {
  1459. return pci_register_driver(&xl_3c359_driver);
  1460. }
  1461. static void __exit xl_pci_cleanup (void)
  1462. {
  1463. pci_unregister_driver (&xl_3c359_driver);
  1464. }
  1465. module_init(xl_pci_init);
  1466. module_exit(xl_pci_cleanup);
  1467. MODULE_LICENSE("GPL") ;