mdio_10g.c 10 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2006-2008 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. /*
  10. * Useful functions for working with MDIO clause 45 PHYs
  11. */
  12. #include <linux/types.h>
  13. #include <linux/ethtool.h>
  14. #include <linux/delay.h>
  15. #include "net_driver.h"
  16. #include "mdio_10g.h"
  17. #include "boards.h"
  18. int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd,
  19. int spins, int spintime)
  20. {
  21. u32 ctrl;
  22. int phy_id = port->mii.phy_id;
  23. /* Catch callers passing values in the wrong units (or just silly) */
  24. EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
  25. mdio_clause45_write(port, phy_id, mmd, MDIO_MMDREG_CTRL1,
  26. (1 << MDIO_MMDREG_CTRL1_RESET_LBN));
  27. /* Wait for the reset bit to clear. */
  28. do {
  29. msleep(spintime);
  30. ctrl = mdio_clause45_read(port, phy_id, mmd, MDIO_MMDREG_CTRL1);
  31. spins--;
  32. } while (spins && (ctrl & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)));
  33. return spins ? spins : -ETIMEDOUT;
  34. }
  35. static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
  36. int fault_fatal)
  37. {
  38. int status;
  39. int phy_id = efx->mii.phy_id;
  40. if (LOOPBACK_INTERNAL(efx))
  41. return 0;
  42. /* Read MMD STATUS2 to check it is responding. */
  43. status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT2);
  44. if (((status >> MDIO_MMDREG_STAT2_PRESENT_LBN) &
  45. ((1 << MDIO_MMDREG_STAT2_PRESENT_WIDTH) - 1)) !=
  46. MDIO_MMDREG_STAT2_PRESENT_VAL) {
  47. EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
  48. return -EIO;
  49. }
  50. /* Read MMD STATUS 1 to check for fault. */
  51. status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT1);
  52. if ((status & (1 << MDIO_MMDREG_STAT1_FAULT_LBN)) != 0) {
  53. if (fault_fatal) {
  54. EFX_ERR(efx, "PHY MMD %d reporting fatal"
  55. " fault: status %x\n", mmd, status);
  56. return -EIO;
  57. } else {
  58. EFX_LOG(efx, "PHY MMD %d reporting status"
  59. " %x (expected)\n", mmd, status);
  60. }
  61. }
  62. return 0;
  63. }
  64. /* This ought to be ridiculous overkill. We expect it to fail rarely */
  65. #define MDIO45_RESET_TIME 1000 /* ms */
  66. #define MDIO45_RESET_ITERS 100
  67. int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
  68. unsigned int mmd_mask)
  69. {
  70. const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
  71. int tries = MDIO45_RESET_ITERS;
  72. int rc = 0;
  73. int in_reset;
  74. while (tries) {
  75. int mask = mmd_mask;
  76. int mmd = 0;
  77. int stat;
  78. in_reset = 0;
  79. while (mask) {
  80. if (mask & 1) {
  81. stat = mdio_clause45_read(efx,
  82. efx->mii.phy_id,
  83. mmd,
  84. MDIO_MMDREG_CTRL1);
  85. if (stat < 0) {
  86. EFX_ERR(efx, "failed to read status of"
  87. " MMD %d\n", mmd);
  88. return -EIO;
  89. }
  90. if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
  91. in_reset |= (1 << mmd);
  92. }
  93. mask = mask >> 1;
  94. mmd++;
  95. }
  96. if (!in_reset)
  97. break;
  98. tries--;
  99. msleep(spintime);
  100. }
  101. if (in_reset != 0) {
  102. EFX_ERR(efx, "not all MMDs came out of reset in time."
  103. " MMDs still in reset: %x\n", in_reset);
  104. rc = -ETIMEDOUT;
  105. }
  106. return rc;
  107. }
  108. int mdio_clause45_check_mmds(struct efx_nic *efx,
  109. unsigned int mmd_mask, unsigned int fatal_mask)
  110. {
  111. int devices, mmd = 0;
  112. int probe_mmd;
  113. /* Historically we have probed the PHYXS to find out what devices are
  114. * present,but that doesn't work so well if the PHYXS isn't expected
  115. * to exist, if so just find the first item in the list supplied. */
  116. probe_mmd = (mmd_mask & MDIO_MMDREG_DEVS0_PHYXS) ? MDIO_MMD_PHYXS :
  117. __ffs(mmd_mask);
  118. devices = mdio_clause45_read(efx, efx->mii.phy_id,
  119. probe_mmd, MDIO_MMDREG_DEVS0);
  120. /* Check all the expected MMDs are present */
  121. if (devices < 0) {
  122. EFX_ERR(efx, "failed to read devices present\n");
  123. return -EIO;
  124. }
  125. if ((devices & mmd_mask) != mmd_mask) {
  126. EFX_ERR(efx, "required MMDs not present: got %x, "
  127. "wanted %x\n", devices, mmd_mask);
  128. return -ENODEV;
  129. }
  130. EFX_TRACE(efx, "Devices present: %x\n", devices);
  131. /* Check all required MMDs are responding and happy. */
  132. while (mmd_mask) {
  133. if (mmd_mask & 1) {
  134. int fault_fatal = fatal_mask & 1;
  135. if (mdio_clause45_check_mmd(efx, mmd, fault_fatal))
  136. return -EIO;
  137. }
  138. mmd_mask = mmd_mask >> 1;
  139. fatal_mask = fatal_mask >> 1;
  140. mmd++;
  141. }
  142. return 0;
  143. }
  144. bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
  145. {
  146. int phy_id = efx->mii.phy_id;
  147. int status;
  148. bool ok = true;
  149. int mmd = 0;
  150. /* If the port is in loopback, then we should only consider a subset
  151. * of mmd's */
  152. if (LOOPBACK_INTERNAL(efx))
  153. return true;
  154. else if (efx->loopback_mode == LOOPBACK_NETWORK)
  155. return false;
  156. else if (efx_phy_mode_disabled(efx->phy_mode))
  157. return false;
  158. else if (efx->loopback_mode == LOOPBACK_PHYXS)
  159. mmd_mask &= ~(MDIO_MMDREG_DEVS0_PHYXS |
  160. MDIO_MMDREG_DEVS0_PCS |
  161. MDIO_MMDREG_DEVS0_PMAPMD);
  162. else if (efx->loopback_mode == LOOPBACK_PCS)
  163. mmd_mask &= ~(MDIO_MMDREG_DEVS0_PCS |
  164. MDIO_MMDREG_DEVS0_PMAPMD);
  165. else if (efx->loopback_mode == LOOPBACK_PMAPMD)
  166. mmd_mask &= ~MDIO_MMDREG_DEVS0_PMAPMD;
  167. while (mmd_mask) {
  168. if (mmd_mask & 1) {
  169. /* Double reads because link state is latched, and a
  170. * read moves the current state into the register */
  171. status = mdio_clause45_read(efx, phy_id,
  172. mmd, MDIO_MMDREG_STAT1);
  173. status = mdio_clause45_read(efx, phy_id,
  174. mmd, MDIO_MMDREG_STAT1);
  175. ok = ok && (status & (1 << MDIO_MMDREG_STAT1_LINK_LBN));
  176. }
  177. mmd_mask = (mmd_mask >> 1);
  178. mmd++;
  179. }
  180. return ok;
  181. }
  182. void mdio_clause45_transmit_disable(struct efx_nic *efx)
  183. {
  184. int phy_id = efx->mii.phy_id;
  185. int ctrl1, ctrl2;
  186. ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
  187. MDIO_MMDREG_TXDIS);
  188. if (efx->phy_mode & PHY_MODE_TX_DISABLED)
  189. ctrl2 |= (1 << MDIO_MMDREG_TXDIS_GLOBAL_LBN);
  190. else
  191. ctrl1 &= ~(1 << MDIO_MMDREG_TXDIS_GLOBAL_LBN);
  192. if (ctrl1 != ctrl2)
  193. mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
  194. MDIO_MMDREG_TXDIS, ctrl2);
  195. }
  196. void mdio_clause45_phy_reconfigure(struct efx_nic *efx)
  197. {
  198. int phy_id = efx->mii.phy_id;
  199. int ctrl1, ctrl2;
  200. /* Handle (with debouncing) PMA/PMD loopback */
  201. ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
  202. MDIO_MMDREG_CTRL1);
  203. if (efx->loopback_mode == LOOPBACK_PMAPMD)
  204. ctrl2 |= (1 << MDIO_PMAPMD_CTRL1_LBACK_LBN);
  205. else
  206. ctrl2 &= ~(1 << MDIO_PMAPMD_CTRL1_LBACK_LBN);
  207. if (ctrl1 != ctrl2)
  208. mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
  209. MDIO_MMDREG_CTRL1, ctrl2);
  210. /* Handle (with debouncing) PCS loopback */
  211. ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
  212. MDIO_MMDREG_CTRL1);
  213. if (efx->loopback_mode == LOOPBACK_PCS)
  214. ctrl2 |= (1 << MDIO_MMDREG_CTRL1_LBACK_LBN);
  215. else
  216. ctrl2 &= ~(1 << MDIO_MMDREG_CTRL1_LBACK_LBN);
  217. if (ctrl1 != ctrl2)
  218. mdio_clause45_write(efx, phy_id, MDIO_MMD_PCS,
  219. MDIO_MMDREG_CTRL1, ctrl2);
  220. /* Handle (with debouncing) PHYXS network loopback */
  221. ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
  222. MDIO_MMDREG_CTRL1);
  223. if (efx->loopback_mode == LOOPBACK_NETWORK)
  224. ctrl2 |= (1 << MDIO_MMDREG_CTRL1_LBACK_LBN);
  225. else
  226. ctrl2 &= ~(1 << MDIO_MMDREG_CTRL1_LBACK_LBN);
  227. if (ctrl1 != ctrl2)
  228. mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
  229. MDIO_MMDREG_CTRL1, ctrl2);
  230. }
  231. /**
  232. * mdio_clause45_get_settings - Read (some of) the PHY settings over MDIO.
  233. * @efx: Efx NIC
  234. * @ecmd: Buffer for settings
  235. *
  236. * On return the 'port', 'speed', 'supported' and 'advertising' fields of
  237. * ecmd have been filled out based on the PMA type.
  238. */
  239. void mdio_clause45_get_settings(struct efx_nic *efx,
  240. struct ethtool_cmd *ecmd)
  241. {
  242. int pma_type;
  243. /* If no PMA is present we are presumably talking something XAUI-ish
  244. * like CX4. Which we report as FIBRE (see below) */
  245. if ((efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)) == 0) {
  246. ecmd->speed = SPEED_10000;
  247. ecmd->port = PORT_FIBRE;
  248. ecmd->supported = SUPPORTED_FIBRE;
  249. ecmd->advertising = ADVERTISED_FIBRE;
  250. return;
  251. }
  252. pma_type = mdio_clause45_read(efx, efx->mii.phy_id,
  253. MDIO_MMD_PMAPMD, MDIO_MMDREG_CTRL2);
  254. pma_type &= MDIO_PMAPMD_CTRL2_TYPE_MASK;
  255. switch (pma_type) {
  256. /* We represent CX4 as fibre in the absence of anything
  257. better. */
  258. case MDIO_PMAPMD_CTRL2_10G_CX4:
  259. ecmd->speed = SPEED_10000;
  260. ecmd->port = PORT_FIBRE;
  261. ecmd->supported = SUPPORTED_FIBRE;
  262. ecmd->advertising = ADVERTISED_FIBRE;
  263. break;
  264. /* 10G Base-T */
  265. case MDIO_PMAPMD_CTRL2_10G_BT:
  266. ecmd->speed = SPEED_10000;
  267. ecmd->port = PORT_TP;
  268. ecmd->supported = SUPPORTED_TP | SUPPORTED_10000baseT_Full;
  269. ecmd->advertising = (ADVERTISED_FIBRE
  270. | ADVERTISED_10000baseT_Full);
  271. break;
  272. case MDIO_PMAPMD_CTRL2_1G_BT:
  273. ecmd->speed = SPEED_1000;
  274. ecmd->port = PORT_TP;
  275. ecmd->supported = SUPPORTED_TP | SUPPORTED_1000baseT_Full;
  276. ecmd->advertising = (ADVERTISED_FIBRE
  277. | ADVERTISED_1000baseT_Full);
  278. break;
  279. case MDIO_PMAPMD_CTRL2_100_BT:
  280. ecmd->speed = SPEED_100;
  281. ecmd->port = PORT_TP;
  282. ecmd->supported = SUPPORTED_TP | SUPPORTED_100baseT_Full;
  283. ecmd->advertising = (ADVERTISED_FIBRE
  284. | ADVERTISED_100baseT_Full);
  285. break;
  286. case MDIO_PMAPMD_CTRL2_10_BT:
  287. ecmd->speed = SPEED_10;
  288. ecmd->port = PORT_TP;
  289. ecmd->supported = SUPPORTED_TP | SUPPORTED_10baseT_Full;
  290. ecmd->advertising = ADVERTISED_FIBRE | ADVERTISED_10baseT_Full;
  291. break;
  292. /* All the other defined modes are flavours of
  293. * 10G optical */
  294. default:
  295. ecmd->speed = SPEED_10000;
  296. ecmd->port = PORT_FIBRE;
  297. ecmd->supported = SUPPORTED_FIBRE;
  298. ecmd->advertising = ADVERTISED_FIBRE;
  299. break;
  300. }
  301. }
  302. /**
  303. * mdio_clause45_set_settings - Set (some of) the PHY settings over MDIO.
  304. * @efx: Efx NIC
  305. * @ecmd: New settings
  306. *
  307. * Currently this just enforces that we are _not_ changing the
  308. * 'port', 'speed', 'supported' or 'advertising' settings as these
  309. * cannot be changed on any currently supported PHY.
  310. */
  311. int mdio_clause45_set_settings(struct efx_nic *efx,
  312. struct ethtool_cmd *ecmd)
  313. {
  314. struct ethtool_cmd tmpcmd;
  315. mdio_clause45_get_settings(efx, &tmpcmd);
  316. /* None of the current PHYs support more than one mode
  317. * of operation (and only 10GBT ever will), so keep things
  318. * simple for now */
  319. if ((ecmd->speed == tmpcmd.speed) && (ecmd->port == tmpcmd.port) &&
  320. (ecmd->supported == tmpcmd.supported) &&
  321. (ecmd->advertising == tmpcmd.advertising))
  322. return 0;
  323. return -EOPNOTSUPP;
  324. }