netxen_nic_ctx.c 18 KB

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  1. /*
  2. * Copyright (C) 2003 - 2008 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. */
  30. #include "netxen_nic_hw.h"
  31. #include "netxen_nic.h"
  32. #include "netxen_nic_phan_reg.h"
  33. #define NXHAL_VERSION 1
  34. static int
  35. netxen_api_lock(struct netxen_adapter *adapter)
  36. {
  37. u32 done = 0, timeout = 0;
  38. for (;;) {
  39. /* Acquire PCIE HW semaphore5 */
  40. netxen_nic_read_w0(adapter,
  41. NETXEN_PCIE_REG(PCIE_SEM5_LOCK), &done);
  42. if (done == 1)
  43. break;
  44. if (++timeout >= NX_OS_CRB_RETRY_COUNT) {
  45. printk(KERN_ERR "%s: lock timeout.\n", __func__);
  46. return -1;
  47. }
  48. msleep(1);
  49. }
  50. #if 0
  51. netxen_nic_write_w1(adapter,
  52. NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER);
  53. #endif
  54. return 0;
  55. }
  56. static int
  57. netxen_api_unlock(struct netxen_adapter *adapter)
  58. {
  59. u32 val;
  60. /* Release PCIE HW semaphore5 */
  61. netxen_nic_read_w0(adapter,
  62. NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK), &val);
  63. return 0;
  64. }
  65. static u32
  66. netxen_poll_rsp(struct netxen_adapter *adapter)
  67. {
  68. u32 raw_rsp, rsp = NX_CDRP_RSP_OK;
  69. int timeout = 0;
  70. do {
  71. /* give atleast 1ms for firmware to respond */
  72. msleep(1);
  73. if (++timeout > NX_OS_CRB_RETRY_COUNT)
  74. return NX_CDRP_RSP_TIMEOUT;
  75. netxen_nic_read_w1(adapter, NX_CDRP_CRB_OFFSET,
  76. &raw_rsp);
  77. rsp = le32_to_cpu(raw_rsp);
  78. } while (!NX_CDRP_IS_RSP(rsp));
  79. return rsp;
  80. }
  81. static u32
  82. netxen_issue_cmd(struct netxen_adapter *adapter,
  83. u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
  84. {
  85. u32 rsp;
  86. u32 signature = 0;
  87. u32 rcode = NX_RCODE_SUCCESS;
  88. signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version);
  89. /* Acquire semaphore before accessing CRB */
  90. if (netxen_api_lock(adapter))
  91. return NX_RCODE_TIMEOUT;
  92. netxen_nic_write_w1(adapter, NX_SIGN_CRB_OFFSET,
  93. cpu_to_le32(signature));
  94. netxen_nic_write_w1(adapter, NX_ARG1_CRB_OFFSET,
  95. cpu_to_le32(arg1));
  96. netxen_nic_write_w1(adapter, NX_ARG2_CRB_OFFSET,
  97. cpu_to_le32(arg2));
  98. netxen_nic_write_w1(adapter, NX_ARG3_CRB_OFFSET,
  99. cpu_to_le32(arg3));
  100. netxen_nic_write_w1(adapter, NX_CDRP_CRB_OFFSET,
  101. cpu_to_le32(NX_CDRP_FORM_CMD(cmd)));
  102. rsp = netxen_poll_rsp(adapter);
  103. if (rsp == NX_CDRP_RSP_TIMEOUT) {
  104. printk(KERN_ERR "%s: card response timeout.\n",
  105. netxen_nic_driver_name);
  106. rcode = NX_RCODE_TIMEOUT;
  107. } else if (rsp == NX_CDRP_RSP_FAIL) {
  108. netxen_nic_read_w1(adapter, NX_ARG1_CRB_OFFSET, &rcode);
  109. rcode = le32_to_cpu(rcode);
  110. printk(KERN_ERR "%s: failed card response code:0x%x\n",
  111. netxen_nic_driver_name, rcode);
  112. }
  113. /* Release semaphore */
  114. netxen_api_unlock(adapter);
  115. return rcode;
  116. }
  117. int
  118. nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu)
  119. {
  120. u32 rcode = NX_RCODE_SUCCESS;
  121. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0];
  122. if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE)
  123. rcode = netxen_issue_cmd(adapter,
  124. adapter->ahw.pci_func,
  125. NXHAL_VERSION,
  126. recv_ctx->context_id,
  127. mtu,
  128. 0,
  129. NX_CDRP_CMD_SET_MTU);
  130. if (rcode != NX_RCODE_SUCCESS)
  131. return -EIO;
  132. return 0;
  133. }
  134. static int
  135. nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
  136. {
  137. void *addr;
  138. nx_hostrq_rx_ctx_t *prq;
  139. nx_cardrsp_rx_ctx_t *prsp;
  140. nx_hostrq_rds_ring_t *prq_rds;
  141. nx_hostrq_sds_ring_t *prq_sds;
  142. nx_cardrsp_rds_ring_t *prsp_rds;
  143. nx_cardrsp_sds_ring_t *prsp_sds;
  144. struct nx_host_rds_ring *rds_ring;
  145. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  146. u64 phys_addr;
  147. int i, nrds_rings, nsds_rings;
  148. size_t rq_size, rsp_size;
  149. u32 cap, reg;
  150. int err;
  151. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0];
  152. /* only one sds ring for now */
  153. nrds_rings = adapter->max_rds_rings;
  154. nsds_rings = 1;
  155. rq_size =
  156. SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings);
  157. rsp_size =
  158. SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings);
  159. addr = pci_alloc_consistent(adapter->pdev,
  160. rq_size, &hostrq_phys_addr);
  161. if (addr == NULL)
  162. return -ENOMEM;
  163. prq = (nx_hostrq_rx_ctx_t *)addr;
  164. addr = pci_alloc_consistent(adapter->pdev,
  165. rsp_size, &cardrsp_phys_addr);
  166. if (addr == NULL) {
  167. err = -ENOMEM;
  168. goto out_free_rq;
  169. }
  170. prsp = (nx_cardrsp_rx_ctx_t *)addr;
  171. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  172. cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN);
  173. cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS);
  174. prq->capabilities[0] = cpu_to_le32(cap);
  175. prq->host_int_crb_mode =
  176. cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
  177. prq->host_rds_crb_mode =
  178. cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE);
  179. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  180. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  181. prq->rds_ring_offset = 0;
  182. prq->sds_ring_offset = prq->rds_ring_offset +
  183. (sizeof(nx_hostrq_rds_ring_t) * nrds_rings);
  184. prq_rds = (nx_hostrq_rds_ring_t *)(prq->data + prq->rds_ring_offset);
  185. for (i = 0; i < nrds_rings; i++) {
  186. rds_ring = &recv_ctx->rds_rings[i];
  187. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  188. prq_rds[i].ring_size = cpu_to_le32(rds_ring->max_rx_desc_count);
  189. prq_rds[i].ring_kind = cpu_to_le32(i);
  190. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  191. }
  192. prq_sds = (nx_hostrq_sds_ring_t *)(prq->data + prq->sds_ring_offset);
  193. prq_sds[0].host_phys_addr =
  194. cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
  195. prq_sds[0].ring_size = cpu_to_le32(adapter->max_rx_desc_count);
  196. /* only one msix vector for now */
  197. prq_sds[0].msi_index = cpu_to_le32(0);
  198. /* now byteswap offsets */
  199. prq->rds_ring_offset = cpu_to_le32(prq->rds_ring_offset);
  200. prq->sds_ring_offset = cpu_to_le32(prq->sds_ring_offset);
  201. phys_addr = hostrq_phys_addr;
  202. err = netxen_issue_cmd(adapter,
  203. adapter->ahw.pci_func,
  204. NXHAL_VERSION,
  205. (u32)(phys_addr >> 32),
  206. (u32)(phys_addr & 0xffffffff),
  207. rq_size,
  208. NX_CDRP_CMD_CREATE_RX_CTX);
  209. if (err) {
  210. printk(KERN_WARNING
  211. "Failed to create rx ctx in firmware%d\n", err);
  212. goto out_free_rsp;
  213. }
  214. prsp_rds = ((nx_cardrsp_rds_ring_t *)
  215. &prsp->data[prsp->rds_ring_offset]);
  216. for (i = 0; i < le32_to_cpu(prsp->num_rds_rings); i++) {
  217. rds_ring = &recv_ctx->rds_rings[i];
  218. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  219. rds_ring->crb_rcv_producer = NETXEN_NIC_REG(reg - 0x200);
  220. }
  221. prsp_sds = ((nx_cardrsp_sds_ring_t *)
  222. &prsp->data[prsp->sds_ring_offset]);
  223. reg = le32_to_cpu(prsp_sds[0].host_consumer_crb);
  224. recv_ctx->crb_sts_consumer = NETXEN_NIC_REG(reg - 0x200);
  225. reg = le32_to_cpu(prsp_sds[0].interrupt_crb);
  226. adapter->crb_intr_mask = NETXEN_NIC_REG(reg - 0x200);
  227. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  228. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  229. recv_ctx->virt_port = le16_to_cpu(prsp->virt_port);
  230. out_free_rsp:
  231. pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
  232. out_free_rq:
  233. pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
  234. return err;
  235. }
  236. static void
  237. nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
  238. {
  239. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx[0];
  240. if (netxen_issue_cmd(adapter,
  241. adapter->ahw.pci_func,
  242. NXHAL_VERSION,
  243. recv_ctx->context_id,
  244. NX_DESTROY_CTX_RESET,
  245. 0,
  246. NX_CDRP_CMD_DESTROY_RX_CTX)) {
  247. printk(KERN_WARNING
  248. "%s: Failed to destroy rx ctx in firmware\n",
  249. netxen_nic_driver_name);
  250. }
  251. }
  252. static int
  253. nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
  254. {
  255. nx_hostrq_tx_ctx_t *prq;
  256. nx_hostrq_cds_ring_t *prq_cds;
  257. nx_cardrsp_tx_ctx_t *prsp;
  258. void *rq_addr, *rsp_addr;
  259. size_t rq_size, rsp_size;
  260. u32 temp;
  261. int err = 0;
  262. u64 offset, phys_addr;
  263. dma_addr_t rq_phys_addr, rsp_phys_addr;
  264. rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
  265. rq_addr = pci_alloc_consistent(adapter->pdev,
  266. rq_size, &rq_phys_addr);
  267. if (!rq_addr)
  268. return -ENOMEM;
  269. rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t);
  270. rsp_addr = pci_alloc_consistent(adapter->pdev,
  271. rsp_size, &rsp_phys_addr);
  272. if (!rsp_addr) {
  273. err = -ENOMEM;
  274. goto out_free_rq;
  275. }
  276. memset(rq_addr, 0, rq_size);
  277. prq = (nx_hostrq_tx_ctx_t *)rq_addr;
  278. memset(rsp_addr, 0, rsp_size);
  279. prsp = (nx_cardrsp_tx_ctx_t *)rsp_addr;
  280. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  281. temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO);
  282. prq->capabilities[0] = cpu_to_le32(temp);
  283. prq->host_int_crb_mode =
  284. cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
  285. prq->interrupt_ctl = 0;
  286. prq->msi_index = 0;
  287. prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr);
  288. offset = adapter->ctx_desc_phys_addr+sizeof(struct netxen_ring_ctx);
  289. prq->cmd_cons_dma_addr = cpu_to_le64(offset);
  290. prq_cds = &prq->cds_ring;
  291. prq_cds->host_phys_addr =
  292. cpu_to_le64(adapter->ahw.cmd_desc_phys_addr);
  293. prq_cds->ring_size = cpu_to_le32(adapter->max_tx_desc_count);
  294. phys_addr = rq_phys_addr;
  295. err = netxen_issue_cmd(adapter,
  296. adapter->ahw.pci_func,
  297. NXHAL_VERSION,
  298. (u32)(phys_addr >> 32),
  299. ((u32)phys_addr & 0xffffffff),
  300. rq_size,
  301. NX_CDRP_CMD_CREATE_TX_CTX);
  302. if (err == NX_RCODE_SUCCESS) {
  303. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  304. adapter->crb_addr_cmd_producer =
  305. NETXEN_NIC_REG(temp - 0x200);
  306. #if 0
  307. adapter->tx_state =
  308. le32_to_cpu(prsp->host_ctx_state);
  309. #endif
  310. adapter->tx_context_id =
  311. le16_to_cpu(prsp->context_id);
  312. } else {
  313. printk(KERN_WARNING
  314. "Failed to create tx ctx in firmware%d\n", err);
  315. err = -EIO;
  316. }
  317. pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
  318. out_free_rq:
  319. pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
  320. return err;
  321. }
  322. static void
  323. nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
  324. {
  325. if (netxen_issue_cmd(adapter,
  326. adapter->ahw.pci_func,
  327. NXHAL_VERSION,
  328. adapter->tx_context_id,
  329. NX_DESTROY_CTX_RESET,
  330. 0,
  331. NX_CDRP_CMD_DESTROY_TX_CTX)) {
  332. printk(KERN_WARNING
  333. "%s: Failed to destroy tx ctx in firmware\n",
  334. netxen_nic_driver_name);
  335. }
  336. }
  337. static u64 ctx_addr_sig_regs[][3] = {
  338. {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
  339. {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
  340. {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
  341. {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
  342. };
  343. #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
  344. #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
  345. #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
  346. #define lower32(x) ((u32)((x) & 0xffffffff))
  347. #define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff))
  348. static struct netxen_recv_crb recv_crb_registers[] = {
  349. /* Instance 0 */
  350. {
  351. /* crb_rcv_producer: */
  352. {
  353. NETXEN_NIC_REG(0x100),
  354. /* Jumbo frames */
  355. NETXEN_NIC_REG(0x110),
  356. /* LRO */
  357. NETXEN_NIC_REG(0x120)
  358. },
  359. /* crb_sts_consumer: */
  360. NETXEN_NIC_REG(0x138),
  361. },
  362. /* Instance 1 */
  363. {
  364. /* crb_rcv_producer: */
  365. {
  366. NETXEN_NIC_REG(0x144),
  367. /* Jumbo frames */
  368. NETXEN_NIC_REG(0x154),
  369. /* LRO */
  370. NETXEN_NIC_REG(0x164)
  371. },
  372. /* crb_sts_consumer: */
  373. NETXEN_NIC_REG(0x17c),
  374. },
  375. /* Instance 2 */
  376. {
  377. /* crb_rcv_producer: */
  378. {
  379. NETXEN_NIC_REG(0x1d8),
  380. /* Jumbo frames */
  381. NETXEN_NIC_REG(0x1f8),
  382. /* LRO */
  383. NETXEN_NIC_REG(0x208)
  384. },
  385. /* crb_sts_consumer: */
  386. NETXEN_NIC_REG(0x220),
  387. },
  388. /* Instance 3 */
  389. {
  390. /* crb_rcv_producer: */
  391. {
  392. NETXEN_NIC_REG(0x22c),
  393. /* Jumbo frames */
  394. NETXEN_NIC_REG(0x23c),
  395. /* LRO */
  396. NETXEN_NIC_REG(0x24c)
  397. },
  398. /* crb_sts_consumer: */
  399. NETXEN_NIC_REG(0x264),
  400. },
  401. };
  402. static int
  403. netxen_init_old_ctx(struct netxen_adapter *adapter)
  404. {
  405. struct netxen_recv_context *recv_ctx;
  406. struct nx_host_rds_ring *rds_ring;
  407. int ctx, ring;
  408. int func_id = adapter->portnum;
  409. adapter->ctx_desc->cmd_ring_addr =
  410. cpu_to_le64(adapter->ahw.cmd_desc_phys_addr);
  411. adapter->ctx_desc->cmd_ring_size =
  412. cpu_to_le32(adapter->max_tx_desc_count);
  413. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  414. recv_ctx = &adapter->recv_ctx[ctx];
  415. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  416. rds_ring = &recv_ctx->rds_rings[ring];
  417. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
  418. cpu_to_le64(rds_ring->phys_addr);
  419. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
  420. cpu_to_le32(rds_ring->max_rx_desc_count);
  421. }
  422. adapter->ctx_desc->sts_ring_addr =
  423. cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
  424. adapter->ctx_desc->sts_ring_size =
  425. cpu_to_le32(adapter->max_rx_desc_count);
  426. }
  427. adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id),
  428. lower32(adapter->ctx_desc_phys_addr));
  429. adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id),
  430. upper32(adapter->ctx_desc_phys_addr));
  431. adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id),
  432. NETXEN_CTX_SIGNATURE | func_id);
  433. return 0;
  434. }
  435. static uint32_t sw_int_mask[4] = {
  436. CRB_SW_INT_MASK_0, CRB_SW_INT_MASK_1,
  437. CRB_SW_INT_MASK_2, CRB_SW_INT_MASK_3
  438. };
  439. int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
  440. {
  441. struct netxen_hardware_context *hw = &adapter->ahw;
  442. u32 state = 0;
  443. void *addr;
  444. int err = 0;
  445. int ctx, ring;
  446. struct netxen_recv_context *recv_ctx;
  447. struct nx_host_rds_ring *rds_ring;
  448. err = netxen_receive_peg_ready(adapter);
  449. if (err) {
  450. printk(KERN_ERR "Rcv Peg initialization not complete:%x.\n",
  451. state);
  452. return err;
  453. }
  454. addr = pci_alloc_consistent(adapter->pdev,
  455. sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
  456. &adapter->ctx_desc_phys_addr);
  457. if (addr == NULL) {
  458. DPRINTK(ERR, "failed to allocate hw context\n");
  459. return -ENOMEM;
  460. }
  461. memset(addr, 0, sizeof(struct netxen_ring_ctx));
  462. adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
  463. adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
  464. adapter->ctx_desc->cmd_consumer_offset =
  465. cpu_to_le64(adapter->ctx_desc_phys_addr +
  466. sizeof(struct netxen_ring_ctx));
  467. adapter->cmd_consumer =
  468. (__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
  469. /* cmd desc ring */
  470. addr = pci_alloc_consistent(adapter->pdev,
  471. sizeof(struct cmd_desc_type0) *
  472. adapter->max_tx_desc_count,
  473. &hw->cmd_desc_phys_addr);
  474. if (addr == NULL) {
  475. printk(KERN_ERR "%s failed to allocate tx desc ring\n",
  476. netxen_nic_driver_name);
  477. return -ENOMEM;
  478. }
  479. hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
  480. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  481. recv_ctx = &adapter->recv_ctx[ctx];
  482. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  483. /* rx desc ring */
  484. rds_ring = &recv_ctx->rds_rings[ring];
  485. addr = pci_alloc_consistent(adapter->pdev,
  486. RCV_DESC_RINGSIZE,
  487. &rds_ring->phys_addr);
  488. if (addr == NULL) {
  489. printk(KERN_ERR "%s failed to allocate rx "
  490. "desc ring[%d]\n",
  491. netxen_nic_driver_name, ring);
  492. err = -ENOMEM;
  493. goto err_out_free;
  494. }
  495. rds_ring->desc_head = (struct rcv_desc *)addr;
  496. if (adapter->fw_major < 4)
  497. rds_ring->crb_rcv_producer =
  498. recv_crb_registers[adapter->portnum].
  499. crb_rcv_producer[ring];
  500. }
  501. /* status desc ring */
  502. addr = pci_alloc_consistent(adapter->pdev,
  503. STATUS_DESC_RINGSIZE,
  504. &recv_ctx->rcv_status_desc_phys_addr);
  505. if (addr == NULL) {
  506. printk(KERN_ERR "%s failed to allocate sts desc ring\n",
  507. netxen_nic_driver_name);
  508. err = -ENOMEM;
  509. goto err_out_free;
  510. }
  511. recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
  512. if (adapter->fw_major < 4)
  513. recv_ctx->crb_sts_consumer =
  514. recv_crb_registers[adapter->portnum].
  515. crb_sts_consumer;
  516. }
  517. if (adapter->fw_major >= 4) {
  518. adapter->intr_scheme = INTR_SCHEME_PERPORT;
  519. adapter->msi_mode = MSI_MODE_MULTIFUNC;
  520. err = nx_fw_cmd_create_rx_ctx(adapter);
  521. if (err)
  522. goto err_out_free;
  523. err = nx_fw_cmd_create_tx_ctx(adapter);
  524. if (err)
  525. goto err_out_free;
  526. } else {
  527. adapter->intr_scheme = adapter->pci_read_normalize(adapter,
  528. CRB_NIC_CAPABILITIES_FW);
  529. adapter->msi_mode = adapter->pci_read_normalize(adapter,
  530. CRB_NIC_MSI_MODE_FW);
  531. adapter->crb_intr_mask = sw_int_mask[adapter->portnum];
  532. err = netxen_init_old_ctx(adapter);
  533. if (err) {
  534. netxen_free_hw_resources(adapter);
  535. return err;
  536. }
  537. }
  538. return 0;
  539. err_out_free:
  540. netxen_free_hw_resources(adapter);
  541. return err;
  542. }
  543. void netxen_free_hw_resources(struct netxen_adapter *adapter)
  544. {
  545. struct netxen_recv_context *recv_ctx;
  546. struct nx_host_rds_ring *rds_ring;
  547. int ctx, ring;
  548. if (adapter->fw_major >= 4) {
  549. nx_fw_cmd_destroy_tx_ctx(adapter);
  550. nx_fw_cmd_destroy_rx_ctx(adapter);
  551. }
  552. if (adapter->ctx_desc != NULL) {
  553. pci_free_consistent(adapter->pdev,
  554. sizeof(struct netxen_ring_ctx) +
  555. sizeof(uint32_t),
  556. adapter->ctx_desc,
  557. adapter->ctx_desc_phys_addr);
  558. adapter->ctx_desc = NULL;
  559. }
  560. if (adapter->ahw.cmd_desc_head != NULL) {
  561. pci_free_consistent(adapter->pdev,
  562. sizeof(struct cmd_desc_type0) *
  563. adapter->max_tx_desc_count,
  564. adapter->ahw.cmd_desc_head,
  565. adapter->ahw.cmd_desc_phys_addr);
  566. adapter->ahw.cmd_desc_head = NULL;
  567. }
  568. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  569. recv_ctx = &adapter->recv_ctx[ctx];
  570. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  571. rds_ring = &recv_ctx->rds_rings[ring];
  572. if (rds_ring->desc_head != NULL) {
  573. pci_free_consistent(adapter->pdev,
  574. RCV_DESC_RINGSIZE,
  575. rds_ring->desc_head,
  576. rds_ring->phys_addr);
  577. rds_ring->desc_head = NULL;
  578. }
  579. }
  580. if (recv_ctx->rcv_status_desc_head != NULL) {
  581. pci_free_consistent(adapter->pdev,
  582. STATUS_DESC_RINGSIZE,
  583. recv_ctx->rcv_status_desc_head,
  584. recv_ctx->rcv_status_desc_phys_addr);
  585. recv_ctx->rcv_status_desc_head = NULL;
  586. }
  587. }
  588. }