en_rx.c 30 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/mlx4/qp.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/if_ether.h>
  37. #include <linux/if_vlan.h>
  38. #include <linux/vmalloc.h>
  39. #include "mlx4_en.h"
  40. static void *get_wqe(struct mlx4_en_rx_ring *ring, int n)
  41. {
  42. int offset = n << ring->srq.wqe_shift;
  43. return ring->buf + offset;
  44. }
  45. static void mlx4_en_srq_event(struct mlx4_srq *srq, enum mlx4_event type)
  46. {
  47. return;
  48. }
  49. static int mlx4_en_get_frag_header(struct skb_frag_struct *frags, void **mac_hdr,
  50. void **ip_hdr, void **tcpudp_hdr,
  51. u64 *hdr_flags, void *priv)
  52. {
  53. *mac_hdr = page_address(frags->page) + frags->page_offset;
  54. *ip_hdr = *mac_hdr + ETH_HLEN;
  55. *tcpudp_hdr = (struct tcphdr *)(*ip_hdr + sizeof(struct iphdr));
  56. *hdr_flags = LRO_IPV4 | LRO_TCP;
  57. return 0;
  58. }
  59. static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
  60. struct mlx4_en_rx_desc *rx_desc,
  61. struct skb_frag_struct *skb_frags,
  62. struct mlx4_en_rx_alloc *ring_alloc,
  63. int i)
  64. {
  65. struct mlx4_en_dev *mdev = priv->mdev;
  66. struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  67. struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
  68. struct page *page;
  69. dma_addr_t dma;
  70. if (page_alloc->offset == frag_info->last_offset) {
  71. /* Allocate new page */
  72. page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
  73. if (!page)
  74. return -ENOMEM;
  75. skb_frags[i].page = page_alloc->page;
  76. skb_frags[i].page_offset = page_alloc->offset;
  77. page_alloc->page = page;
  78. page_alloc->offset = frag_info->frag_align;
  79. } else {
  80. page = page_alloc->page;
  81. get_page(page);
  82. skb_frags[i].page = page;
  83. skb_frags[i].page_offset = page_alloc->offset;
  84. page_alloc->offset += frag_info->frag_stride;
  85. }
  86. dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
  87. skb_frags[i].page_offset, frag_info->frag_size,
  88. PCI_DMA_FROMDEVICE);
  89. rx_desc->data[i].addr = cpu_to_be64(dma);
  90. return 0;
  91. }
  92. static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
  93. struct mlx4_en_rx_ring *ring)
  94. {
  95. struct mlx4_en_rx_alloc *page_alloc;
  96. int i;
  97. for (i = 0; i < priv->num_frags; i++) {
  98. page_alloc = &ring->page_alloc[i];
  99. page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
  100. MLX4_EN_ALLOC_ORDER);
  101. if (!page_alloc->page)
  102. goto out;
  103. page_alloc->offset = priv->frag_info[i].frag_align;
  104. mlx4_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
  105. i, page_alloc->page);
  106. }
  107. return 0;
  108. out:
  109. while (i--) {
  110. page_alloc = &ring->page_alloc[i];
  111. put_page(page_alloc->page);
  112. page_alloc->page = NULL;
  113. }
  114. return -ENOMEM;
  115. }
  116. static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
  117. struct mlx4_en_rx_ring *ring)
  118. {
  119. struct mlx4_en_rx_alloc *page_alloc;
  120. int i;
  121. for (i = 0; i < priv->num_frags; i++) {
  122. page_alloc = &ring->page_alloc[i];
  123. mlx4_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
  124. i, page_count(page_alloc->page));
  125. put_page(page_alloc->page);
  126. page_alloc->page = NULL;
  127. }
  128. }
  129. static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  130. struct mlx4_en_rx_ring *ring, int index)
  131. {
  132. struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  133. struct skb_frag_struct *skb_frags = ring->rx_info +
  134. (index << priv->log_rx_info);
  135. int possible_frags;
  136. int i;
  137. /* Pre-link descriptor */
  138. rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask);
  139. /* Set size and memtype fields */
  140. for (i = 0; i < priv->num_frags; i++) {
  141. skb_frags[i].size = priv->frag_info[i].frag_size;
  142. rx_desc->data[i].byte_count =
  143. cpu_to_be32(priv->frag_info[i].frag_size);
  144. rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  145. }
  146. /* If the number of used fragments does not fill up the ring stride,
  147. * remaining (unused) fragments must be padded with null address/size
  148. * and a special memory key */
  149. possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  150. for (i = priv->num_frags; i < possible_frags; i++) {
  151. rx_desc->data[i].byte_count = 0;
  152. rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  153. rx_desc->data[i].addr = 0;
  154. }
  155. }
  156. static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
  157. struct mlx4_en_rx_ring *ring, int index)
  158. {
  159. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
  160. struct skb_frag_struct *skb_frags = ring->rx_info +
  161. (index << priv->log_rx_info);
  162. int i;
  163. for (i = 0; i < priv->num_frags; i++)
  164. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
  165. goto err;
  166. return 0;
  167. err:
  168. while (i--)
  169. put_page(skb_frags[i].page);
  170. return -ENOMEM;
  171. }
  172. static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
  173. {
  174. *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
  175. }
  176. static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
  177. {
  178. struct mlx4_en_dev *mdev = priv->mdev;
  179. struct mlx4_en_rx_ring *ring;
  180. int ring_ind;
  181. int buf_ind;
  182. for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
  183. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  184. ring = &priv->rx_ring[ring_ind];
  185. if (mlx4_en_prepare_rx_desc(priv, ring,
  186. ring->actual_size)) {
  187. if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
  188. mlx4_err(mdev, "Failed to allocate "
  189. "enough rx buffers\n");
  190. return -ENOMEM;
  191. } else {
  192. if (netif_msg_rx_err(priv))
  193. mlx4_warn(mdev,
  194. "Only %d buffers allocated\n",
  195. ring->actual_size);
  196. goto out;
  197. }
  198. }
  199. ring->actual_size++;
  200. ring->prod++;
  201. }
  202. }
  203. out:
  204. return 0;
  205. }
  206. static int mlx4_en_fill_rx_buf(struct net_device *dev,
  207. struct mlx4_en_rx_ring *ring)
  208. {
  209. struct mlx4_en_priv *priv = netdev_priv(dev);
  210. int num = 0;
  211. int err;
  212. while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
  213. err = mlx4_en_prepare_rx_desc(priv, ring, ring->prod &
  214. ring->size_mask);
  215. if (err) {
  216. if (netif_msg_rx_err(priv))
  217. mlx4_warn(priv->mdev,
  218. "Failed preparing rx descriptor\n");
  219. priv->port_stats.rx_alloc_failed++;
  220. break;
  221. }
  222. ++num;
  223. ++ring->prod;
  224. }
  225. if ((u32) (ring->prod - ring->cons) == ring->size)
  226. ring->full = 1;
  227. return num;
  228. }
  229. static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
  230. struct mlx4_en_rx_ring *ring)
  231. {
  232. struct mlx4_en_dev *mdev = priv->mdev;
  233. struct skb_frag_struct *skb_frags;
  234. struct mlx4_en_rx_desc *rx_desc;
  235. dma_addr_t dma;
  236. int index;
  237. int nr;
  238. mlx4_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
  239. ring->cons, ring->prod);
  240. /* Unmap and free Rx buffers */
  241. BUG_ON((u32) (ring->prod - ring->cons) > ring->size);
  242. while (ring->cons != ring->prod) {
  243. index = ring->cons & ring->size_mask;
  244. rx_desc = ring->buf + (index << ring->log_stride);
  245. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  246. mlx4_dbg(DRV, priv, "Processing descriptor:%d\n", index);
  247. for (nr = 0; nr < priv->num_frags; nr++) {
  248. mlx4_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
  249. dma = be64_to_cpu(rx_desc->data[nr].addr);
  250. mlx4_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma);
  251. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  252. PCI_DMA_FROMDEVICE);
  253. put_page(skb_frags[nr].page);
  254. }
  255. ++ring->cons;
  256. }
  257. }
  258. void mlx4_en_rx_refill(struct work_struct *work)
  259. {
  260. struct delayed_work *delay = container_of(work, struct delayed_work, work);
  261. struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
  262. refill_task);
  263. struct mlx4_en_dev *mdev = priv->mdev;
  264. struct net_device *dev = priv->dev;
  265. struct mlx4_en_rx_ring *ring;
  266. int need_refill = 0;
  267. int i;
  268. mutex_lock(&mdev->state_lock);
  269. if (!mdev->device_up || !priv->port_up)
  270. goto out;
  271. /* We only get here if there are no receive buffers, so we can't race
  272. * with Rx interrupts while filling buffers */
  273. for (i = 0; i < priv->rx_ring_num; i++) {
  274. ring = &priv->rx_ring[i];
  275. if (ring->need_refill) {
  276. if (mlx4_en_fill_rx_buf(dev, ring)) {
  277. ring->need_refill = 0;
  278. mlx4_en_update_rx_prod_db(ring);
  279. } else
  280. need_refill = 1;
  281. }
  282. }
  283. if (need_refill)
  284. queue_delayed_work(mdev->workqueue, &priv->refill_task, HZ);
  285. out:
  286. mutex_unlock(&mdev->state_lock);
  287. }
  288. int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
  289. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  290. {
  291. struct mlx4_en_dev *mdev = priv->mdev;
  292. int err;
  293. int tmp;
  294. /* Sanity check SRQ size before proceeding */
  295. if (size >= mdev->dev->caps.max_srq_wqes)
  296. return -EINVAL;
  297. ring->prod = 0;
  298. ring->cons = 0;
  299. ring->size = size;
  300. ring->size_mask = size - 1;
  301. ring->stride = stride;
  302. ring->log_stride = ffs(ring->stride) - 1;
  303. ring->buf_size = ring->size * ring->stride;
  304. tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
  305. sizeof(struct skb_frag_struct));
  306. ring->rx_info = vmalloc(tmp);
  307. if (!ring->rx_info) {
  308. mlx4_err(mdev, "Failed allocating rx_info ring\n");
  309. return -ENOMEM;
  310. }
  311. mlx4_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
  312. ring->rx_info, tmp);
  313. err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
  314. ring->buf_size, 2 * PAGE_SIZE);
  315. if (err)
  316. goto err_ring;
  317. err = mlx4_en_map_buffer(&ring->wqres.buf);
  318. if (err) {
  319. mlx4_err(mdev, "Failed to map RX buffer\n");
  320. goto err_hwq;
  321. }
  322. ring->buf = ring->wqres.buf.direct.buf;
  323. /* Configure lro mngr */
  324. memset(&ring->lro, 0, sizeof(struct net_lro_mgr));
  325. ring->lro.dev = priv->dev;
  326. ring->lro.features = LRO_F_NAPI;
  327. ring->lro.frag_align_pad = NET_IP_ALIGN;
  328. ring->lro.ip_summed = CHECKSUM_UNNECESSARY;
  329. ring->lro.ip_summed_aggr = CHECKSUM_UNNECESSARY;
  330. ring->lro.max_desc = mdev->profile.num_lro;
  331. ring->lro.max_aggr = MAX_SKB_FRAGS;
  332. ring->lro.lro_arr = kzalloc(mdev->profile.num_lro *
  333. sizeof(struct net_lro_desc),
  334. GFP_KERNEL);
  335. if (!ring->lro.lro_arr) {
  336. mlx4_err(mdev, "Failed to allocate lro array\n");
  337. goto err_map;
  338. }
  339. ring->lro.get_frag_header = mlx4_en_get_frag_header;
  340. return 0;
  341. err_map:
  342. mlx4_en_unmap_buffer(&ring->wqres.buf);
  343. err_hwq:
  344. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  345. err_ring:
  346. vfree(ring->rx_info);
  347. ring->rx_info = NULL;
  348. return err;
  349. }
  350. int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
  351. {
  352. struct mlx4_en_dev *mdev = priv->mdev;
  353. struct mlx4_wqe_srq_next_seg *next;
  354. struct mlx4_en_rx_ring *ring;
  355. int i;
  356. int ring_ind;
  357. int err;
  358. int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
  359. DS_SIZE * priv->num_frags);
  360. int max_gs = (stride - sizeof(struct mlx4_wqe_srq_next_seg)) / DS_SIZE;
  361. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  362. ring = &priv->rx_ring[ring_ind];
  363. ring->prod = 0;
  364. ring->cons = 0;
  365. ring->actual_size = 0;
  366. ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
  367. ring->stride = stride;
  368. ring->log_stride = ffs(ring->stride) - 1;
  369. ring->buf_size = ring->size * ring->stride;
  370. memset(ring->buf, 0, ring->buf_size);
  371. mlx4_en_update_rx_prod_db(ring);
  372. /* Initailize all descriptors */
  373. for (i = 0; i < ring->size; i++)
  374. mlx4_en_init_rx_desc(priv, ring, i);
  375. /* Initialize page allocators */
  376. err = mlx4_en_init_allocator(priv, ring);
  377. if (err) {
  378. mlx4_err(mdev, "Failed initializing ring allocator\n");
  379. goto err_allocator;
  380. }
  381. /* Fill Rx buffers */
  382. ring->full = 0;
  383. }
  384. if (mlx4_en_fill_rx_buffers(priv))
  385. goto err_buffers;
  386. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  387. ring = &priv->rx_ring[ring_ind];
  388. mlx4_en_update_rx_prod_db(ring);
  389. /* Configure SRQ representing the ring */
  390. ring->srq.max = ring->size;
  391. ring->srq.max_gs = max_gs;
  392. ring->srq.wqe_shift = ilog2(ring->stride);
  393. for (i = 0; i < ring->srq.max; ++i) {
  394. next = get_wqe(ring, i);
  395. next->next_wqe_index =
  396. cpu_to_be16((i + 1) & (ring->srq.max - 1));
  397. }
  398. err = mlx4_srq_alloc(mdev->dev, mdev->priv_pdn, &ring->wqres.mtt,
  399. ring->wqres.db.dma, &ring->srq);
  400. if (err){
  401. mlx4_err(mdev, "Failed to allocate srq\n");
  402. goto err_srq;
  403. }
  404. ring->srq.event = mlx4_en_srq_event;
  405. }
  406. return 0;
  407. err_srq:
  408. while (ring_ind >= 0) {
  409. ring = &priv->rx_ring[ring_ind];
  410. mlx4_srq_free(mdev->dev, &ring->srq);
  411. ring_ind--;
  412. }
  413. err_buffers:
  414. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
  415. mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
  416. ring_ind = priv->rx_ring_num - 1;
  417. err_allocator:
  418. while (ring_ind >= 0) {
  419. mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
  420. ring_ind--;
  421. }
  422. return err;
  423. }
  424. void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
  425. struct mlx4_en_rx_ring *ring)
  426. {
  427. struct mlx4_en_dev *mdev = priv->mdev;
  428. kfree(ring->lro.lro_arr);
  429. mlx4_en_unmap_buffer(&ring->wqres.buf);
  430. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  431. vfree(ring->rx_info);
  432. ring->rx_info = NULL;
  433. }
  434. void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
  435. struct mlx4_en_rx_ring *ring)
  436. {
  437. struct mlx4_en_dev *mdev = priv->mdev;
  438. mlx4_srq_free(mdev->dev, &ring->srq);
  439. mlx4_en_free_rx_buf(priv, ring);
  440. mlx4_en_destroy_allocator(priv, ring);
  441. }
  442. /* Unmap a completed descriptor and free unused pages */
  443. static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
  444. struct mlx4_en_rx_desc *rx_desc,
  445. struct skb_frag_struct *skb_frags,
  446. struct skb_frag_struct *skb_frags_rx,
  447. struct mlx4_en_rx_alloc *page_alloc,
  448. int length)
  449. {
  450. struct mlx4_en_dev *mdev = priv->mdev;
  451. struct mlx4_en_frag_info *frag_info;
  452. int nr;
  453. dma_addr_t dma;
  454. /* Collect used fragments while replacing them in the HW descirptors */
  455. for (nr = 0; nr < priv->num_frags; nr++) {
  456. frag_info = &priv->frag_info[nr];
  457. if (length <= frag_info->frag_prefix_size)
  458. break;
  459. /* Save page reference in skb */
  460. skb_frags_rx[nr].page = skb_frags[nr].page;
  461. skb_frags_rx[nr].size = skb_frags[nr].size;
  462. skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset;
  463. dma = be64_to_cpu(rx_desc->data[nr].addr);
  464. /* Allocate a replacement page */
  465. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
  466. goto fail;
  467. /* Unmap buffer */
  468. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  469. PCI_DMA_FROMDEVICE);
  470. }
  471. /* Adjust size of last fragment to match actual length */
  472. skb_frags_rx[nr - 1].size = length -
  473. priv->frag_info[nr - 1].frag_prefix_size;
  474. return nr;
  475. fail:
  476. /* Drop all accumulated fragments (which have already been replaced in
  477. * the descriptor) of this packet; remaining fragments are reused... */
  478. while (nr > 0) {
  479. nr--;
  480. put_page(skb_frags_rx[nr].page);
  481. }
  482. return 0;
  483. }
  484. static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
  485. struct mlx4_en_rx_desc *rx_desc,
  486. struct skb_frag_struct *skb_frags,
  487. struct mlx4_en_rx_alloc *page_alloc,
  488. unsigned int length)
  489. {
  490. struct mlx4_en_dev *mdev = priv->mdev;
  491. struct sk_buff *skb;
  492. void *va;
  493. int used_frags;
  494. dma_addr_t dma;
  495. skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
  496. if (!skb) {
  497. mlx4_dbg(RX_ERR, priv, "Failed allocating skb\n");
  498. return NULL;
  499. }
  500. skb->dev = priv->dev;
  501. skb_reserve(skb, NET_IP_ALIGN);
  502. skb->len = length;
  503. skb->truesize = length + sizeof(struct sk_buff);
  504. /* Get pointer to first fragment so we could copy the headers into the
  505. * (linear part of the) skb */
  506. va = page_address(skb_frags[0].page) + skb_frags[0].page_offset;
  507. if (length <= SMALL_PACKET_SIZE) {
  508. /* We are copying all relevant data to the skb - temporarily
  509. * synch buffers for the copy */
  510. dma = be64_to_cpu(rx_desc->data[0].addr);
  511. dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0,
  512. length, DMA_FROM_DEVICE);
  513. skb_copy_to_linear_data(skb, va, length);
  514. dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0,
  515. length, DMA_FROM_DEVICE);
  516. skb->tail += length;
  517. } else {
  518. /* Move relevant fragments to skb */
  519. used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
  520. skb_shinfo(skb)->frags,
  521. page_alloc, length);
  522. skb_shinfo(skb)->nr_frags = used_frags;
  523. /* Copy headers into the skb linear buffer */
  524. memcpy(skb->data, va, HEADER_COPY_SIZE);
  525. skb->tail += HEADER_COPY_SIZE;
  526. /* Skip headers in first fragment */
  527. skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
  528. /* Adjust size of first fragment */
  529. skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE;
  530. skb->data_len = length - HEADER_COPY_SIZE;
  531. }
  532. return skb;
  533. }
  534. static void mlx4_en_copy_desc(struct mlx4_en_priv *priv,
  535. struct mlx4_en_rx_ring *ring,
  536. int from, int to, int num)
  537. {
  538. struct skb_frag_struct *skb_frags_from;
  539. struct skb_frag_struct *skb_frags_to;
  540. struct mlx4_en_rx_desc *rx_desc_from;
  541. struct mlx4_en_rx_desc *rx_desc_to;
  542. int from_index, to_index;
  543. int nr, i;
  544. for (i = 0; i < num; i++) {
  545. from_index = (from + i) & ring->size_mask;
  546. to_index = (to + i) & ring->size_mask;
  547. skb_frags_from = ring->rx_info + (from_index << priv->log_rx_info);
  548. skb_frags_to = ring->rx_info + (to_index << priv->log_rx_info);
  549. rx_desc_from = ring->buf + (from_index << ring->log_stride);
  550. rx_desc_to = ring->buf + (to_index << ring->log_stride);
  551. for (nr = 0; nr < priv->num_frags; nr++) {
  552. skb_frags_to[nr].page = skb_frags_from[nr].page;
  553. skb_frags_to[nr].page_offset = skb_frags_from[nr].page_offset;
  554. rx_desc_to->data[nr].addr = rx_desc_from->data[nr].addr;
  555. }
  556. }
  557. }
  558. int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
  559. {
  560. struct mlx4_en_priv *priv = netdev_priv(dev);
  561. struct mlx4_en_dev *mdev = priv->mdev;
  562. struct mlx4_cqe *cqe;
  563. struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
  564. struct skb_frag_struct *skb_frags;
  565. struct skb_frag_struct lro_frags[MLX4_EN_MAX_RX_FRAGS];
  566. struct mlx4_en_rx_desc *rx_desc;
  567. struct sk_buff *skb;
  568. int index;
  569. int nr;
  570. unsigned int length;
  571. int polled = 0;
  572. int ip_summed;
  573. if (!priv->port_up)
  574. return 0;
  575. /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
  576. * descriptor offset can be deduced from the CQE index instead of
  577. * reading 'cqe->index' */
  578. index = cq->mcq.cons_index & ring->size_mask;
  579. cqe = &cq->buf[index];
  580. /* Process all completed CQEs */
  581. while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
  582. cq->mcq.cons_index & cq->size)) {
  583. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  584. rx_desc = ring->buf + (index << ring->log_stride);
  585. /*
  586. * make sure we read the CQE after we read the ownership bit
  587. */
  588. rmb();
  589. /* Drop packet on bad receive or bad checksum */
  590. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  591. MLX4_CQE_OPCODE_ERROR)) {
  592. mlx4_err(mdev, "CQE completed in error - vendor "
  593. "syndrom:%d syndrom:%d\n",
  594. ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
  595. ((struct mlx4_err_cqe *) cqe)->syndrome);
  596. goto next;
  597. }
  598. if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
  599. mlx4_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
  600. goto next;
  601. }
  602. /*
  603. * Packet is OK - process it.
  604. */
  605. length = be32_to_cpu(cqe->byte_cnt);
  606. ring->bytes += length;
  607. ring->packets++;
  608. if (likely(priv->rx_csum)) {
  609. if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
  610. (cqe->checksum == cpu_to_be16(0xffff))) {
  611. priv->port_stats.rx_chksum_good++;
  612. /* This packet is eligible for LRO if it is:
  613. * - DIX Ethernet (type interpretation)
  614. * - TCP/IP (v4)
  615. * - without IP options
  616. * - not an IP fragment */
  617. if (mlx4_en_can_lro(cqe->status) &&
  618. dev->features & NETIF_F_LRO) {
  619. nr = mlx4_en_complete_rx_desc(
  620. priv, rx_desc,
  621. skb_frags, lro_frags,
  622. ring->page_alloc, length);
  623. if (!nr)
  624. goto next;
  625. if (priv->vlgrp && (cqe->vlan_my_qpn &
  626. cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK))) {
  627. lro_vlan_hwaccel_receive_frags(
  628. &ring->lro, lro_frags,
  629. length, length,
  630. priv->vlgrp,
  631. be16_to_cpu(cqe->sl_vid),
  632. NULL, 0);
  633. } else
  634. lro_receive_frags(&ring->lro,
  635. lro_frags,
  636. length,
  637. length,
  638. NULL, 0);
  639. goto next;
  640. }
  641. /* LRO not possible, complete processing here */
  642. ip_summed = CHECKSUM_UNNECESSARY;
  643. INC_PERF_COUNTER(priv->pstats.lro_misses);
  644. } else {
  645. ip_summed = CHECKSUM_NONE;
  646. priv->port_stats.rx_chksum_none++;
  647. }
  648. } else {
  649. ip_summed = CHECKSUM_NONE;
  650. priv->port_stats.rx_chksum_none++;
  651. }
  652. skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
  653. ring->page_alloc, length);
  654. if (!skb) {
  655. priv->stats.rx_dropped++;
  656. goto next;
  657. }
  658. skb->ip_summed = ip_summed;
  659. skb->protocol = eth_type_trans(skb, dev);
  660. /* Push it up the stack */
  661. if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) &
  662. MLX4_CQE_VLAN_PRESENT_MASK)) {
  663. vlan_hwaccel_receive_skb(skb, priv->vlgrp,
  664. be16_to_cpu(cqe->sl_vid));
  665. } else
  666. netif_receive_skb(skb);
  667. dev->last_rx = jiffies;
  668. next:
  669. ++cq->mcq.cons_index;
  670. index = (cq->mcq.cons_index) & ring->size_mask;
  671. cqe = &cq->buf[index];
  672. if (++polled == budget) {
  673. /* We are here because we reached the NAPI budget -
  674. * flush only pending LRO sessions */
  675. lro_flush_all(&ring->lro);
  676. goto out;
  677. }
  678. }
  679. /* If CQ is empty flush all LRO sessions unconditionally */
  680. lro_flush_all(&ring->lro);
  681. out:
  682. AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
  683. mlx4_cq_set_ci(&cq->mcq);
  684. wmb(); /* ensure HW sees CQ consumer before we post new buffers */
  685. ring->cons = cq->mcq.cons_index;
  686. ring->prod += polled; /* Polled descriptors were realocated in place */
  687. if (unlikely(!ring->full)) {
  688. mlx4_en_copy_desc(priv, ring, ring->cons - polled,
  689. ring->prod - polled, polled);
  690. mlx4_en_fill_rx_buf(dev, ring);
  691. }
  692. mlx4_en_update_rx_prod_db(ring);
  693. return polled;
  694. }
  695. void mlx4_en_rx_irq(struct mlx4_cq *mcq)
  696. {
  697. struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
  698. struct mlx4_en_priv *priv = netdev_priv(cq->dev);
  699. if (priv->port_up)
  700. netif_rx_schedule(cq->dev, &cq->napi);
  701. else
  702. mlx4_en_arm_cq(priv, cq);
  703. }
  704. /* Rx CQ polling - called by NAPI */
  705. int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
  706. {
  707. struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
  708. struct net_device *dev = cq->dev;
  709. struct mlx4_en_priv *priv = netdev_priv(dev);
  710. int done;
  711. done = mlx4_en_process_rx_cq(dev, cq, budget);
  712. /* If we used up all the quota - we're probably not done yet... */
  713. if (done == budget)
  714. INC_PERF_COUNTER(priv->pstats.napi_quota);
  715. else {
  716. /* Done for now */
  717. netif_rx_complete(dev, napi);
  718. mlx4_en_arm_cq(priv, cq);
  719. }
  720. return done;
  721. }
  722. /* Calculate the last offset position that accomodates a full fragment
  723. * (assuming fagment size = stride-align) */
  724. static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
  725. {
  726. u16 res = MLX4_EN_ALLOC_SIZE % stride;
  727. u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
  728. mlx4_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
  729. "res:%d offset:%d\n", stride, align, res, offset);
  730. return offset;
  731. }
  732. static int frag_sizes[] = {
  733. FRAG_SZ0,
  734. FRAG_SZ1,
  735. FRAG_SZ2,
  736. FRAG_SZ3
  737. };
  738. void mlx4_en_calc_rx_buf(struct net_device *dev)
  739. {
  740. struct mlx4_en_priv *priv = netdev_priv(dev);
  741. int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
  742. int buf_size = 0;
  743. int i = 0;
  744. while (buf_size < eff_mtu) {
  745. priv->frag_info[i].frag_size =
  746. (eff_mtu > buf_size + frag_sizes[i]) ?
  747. frag_sizes[i] : eff_mtu - buf_size;
  748. priv->frag_info[i].frag_prefix_size = buf_size;
  749. if (!i) {
  750. priv->frag_info[i].frag_align = NET_IP_ALIGN;
  751. priv->frag_info[i].frag_stride =
  752. ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
  753. } else {
  754. priv->frag_info[i].frag_align = 0;
  755. priv->frag_info[i].frag_stride =
  756. ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
  757. }
  758. priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
  759. priv, priv->frag_info[i].frag_stride,
  760. priv->frag_info[i].frag_align);
  761. buf_size += priv->frag_info[i].frag_size;
  762. i++;
  763. }
  764. priv->num_frags = i;
  765. priv->rx_skb_size = eff_mtu;
  766. priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
  767. mlx4_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
  768. "num_frags:%d):\n", eff_mtu, priv->num_frags);
  769. for (i = 0; i < priv->num_frags; i++) {
  770. mlx4_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
  771. "stride:%d last_offset:%d\n", i,
  772. priv->frag_info[i].frag_size,
  773. priv->frag_info[i].frag_prefix_size,
  774. priv->frag_info[i].frag_align,
  775. priv->frag_info[i].frag_stride,
  776. priv->frag_info[i].last_offset);
  777. }
  778. }
  779. /* RSS related functions */
  780. /* Calculate rss size and map each entry in rss table to rx ring */
  781. void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
  782. struct mlx4_en_rss_map *rss_map,
  783. int num_entries, int num_rings)
  784. {
  785. int i;
  786. rss_map->size = roundup_pow_of_two(num_entries);
  787. mlx4_dbg(DRV, priv, "Setting default RSS map of %d entires\n",
  788. rss_map->size);
  789. for (i = 0; i < rss_map->size; i++) {
  790. rss_map->map[i] = i % num_rings;
  791. mlx4_dbg(DRV, priv, "Entry %d ---> ring %d\n", i, rss_map->map[i]);
  792. }
  793. }
  794. static void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event)
  795. {
  796. return;
  797. }
  798. static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv,
  799. int qpn, int srqn, int cqn,
  800. enum mlx4_qp_state *state,
  801. struct mlx4_qp *qp)
  802. {
  803. struct mlx4_en_dev *mdev = priv->mdev;
  804. struct mlx4_qp_context *context;
  805. int err = 0;
  806. context = kmalloc(sizeof *context , GFP_KERNEL);
  807. if (!context) {
  808. mlx4_err(mdev, "Failed to allocate qp context\n");
  809. return -ENOMEM;
  810. }
  811. err = mlx4_qp_alloc(mdev->dev, qpn, qp);
  812. if (err) {
  813. mlx4_err(mdev, "Failed to allocate qp #%d\n", qpn);
  814. goto out;
  815. return err;
  816. }
  817. qp->event = mlx4_en_sqp_event;
  818. memset(context, 0, sizeof *context);
  819. mlx4_en_fill_qp_context(priv, 0, 0, 0, 0, qpn, cqn, srqn, context);
  820. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, context, qp, state);
  821. if (err) {
  822. mlx4_qp_remove(mdev->dev, qp);
  823. mlx4_qp_free(mdev->dev, qp);
  824. }
  825. out:
  826. kfree(context);
  827. return err;
  828. }
  829. /* Allocate rx qp's and configure them according to rss map */
  830. int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
  831. {
  832. struct mlx4_en_dev *mdev = priv->mdev;
  833. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  834. struct mlx4_qp_context context;
  835. struct mlx4_en_rss_context *rss_context;
  836. void *ptr;
  837. int rss_xor = mdev->profile.rss_xor;
  838. u8 rss_mask = mdev->profile.rss_mask;
  839. int i, srqn, qpn, cqn;
  840. int err = 0;
  841. int good_qps = 0;
  842. mlx4_dbg(DRV, priv, "Configuring rss steering for port %u\n", priv->port);
  843. err = mlx4_qp_reserve_range(mdev->dev, rss_map->size,
  844. rss_map->size, &rss_map->base_qpn);
  845. if (err) {
  846. mlx4_err(mdev, "Failed reserving %d qps for port %u\n",
  847. rss_map->size, priv->port);
  848. return err;
  849. }
  850. for (i = 0; i < rss_map->size; i++) {
  851. cqn = priv->rx_ring[rss_map->map[i]].cqn;
  852. srqn = priv->rx_ring[rss_map->map[i]].srq.srqn;
  853. qpn = rss_map->base_qpn + i;
  854. err = mlx4_en_config_rss_qp(priv, qpn, srqn, cqn,
  855. &rss_map->state[i],
  856. &rss_map->qps[i]);
  857. if (err)
  858. goto rss_err;
  859. ++good_qps;
  860. }
  861. /* Configure RSS indirection qp */
  862. err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn);
  863. if (err) {
  864. mlx4_err(mdev, "Failed to reserve range for RSS "
  865. "indirection qp\n");
  866. goto rss_err;
  867. }
  868. err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
  869. if (err) {
  870. mlx4_err(mdev, "Failed to allocate RSS indirection QP\n");
  871. goto reserve_err;
  872. }
  873. rss_map->indir_qp.event = mlx4_en_sqp_event;
  874. mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
  875. priv->rx_ring[0].cqn, 0, &context);
  876. ptr = ((void *) &context) + 0x3c;
  877. rss_context = (struct mlx4_en_rss_context *) ptr;
  878. rss_context->base_qpn = cpu_to_be32(ilog2(rss_map->size) << 24 |
  879. (rss_map->base_qpn));
  880. rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
  881. rss_context->hash_fn = rss_xor & 0x3;
  882. rss_context->flags = rss_mask << 2;
  883. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
  884. &rss_map->indir_qp, &rss_map->indir_state);
  885. if (err)
  886. goto indir_err;
  887. return 0;
  888. indir_err:
  889. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  890. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  891. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  892. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  893. reserve_err:
  894. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  895. rss_err:
  896. for (i = 0; i < good_qps; i++) {
  897. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  898. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  899. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  900. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  901. }
  902. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  903. return err;
  904. }
  905. void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
  906. {
  907. struct mlx4_en_dev *mdev = priv->mdev;
  908. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  909. int i;
  910. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  911. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  912. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  913. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  914. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  915. for (i = 0; i < rss_map->size; i++) {
  916. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  917. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  918. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  919. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  920. }
  921. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  922. }