setup-sh7722.c 9.8 KB

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  1. /*
  2. * SH7722 Setup
  3. *
  4. * Copyright (C) 2006 - 2008 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/serial.h>
  13. #include <linux/serial_sci.h>
  14. #include <linux/mm.h>
  15. #include <linux/uio_driver.h>
  16. #include <asm/clock.h>
  17. #include <asm/mmzone.h>
  18. static struct resource rtc_resources[] = {
  19. [0] = {
  20. .start = 0xa465fec0,
  21. .end = 0xa465fec0 + 0x58 - 1,
  22. .flags = IORESOURCE_IO,
  23. },
  24. [1] = {
  25. /* Period IRQ */
  26. .start = 45,
  27. .flags = IORESOURCE_IRQ,
  28. },
  29. [2] = {
  30. /* Carry IRQ */
  31. .start = 46,
  32. .flags = IORESOURCE_IRQ,
  33. },
  34. [3] = {
  35. /* Alarm IRQ */
  36. .start = 44,
  37. .flags = IORESOURCE_IRQ,
  38. },
  39. };
  40. static struct platform_device rtc_device = {
  41. .name = "sh-rtc",
  42. .id = -1,
  43. .num_resources = ARRAY_SIZE(rtc_resources),
  44. .resource = rtc_resources,
  45. };
  46. static struct resource usbf_resources[] = {
  47. [0] = {
  48. .name = "m66592_udc",
  49. .start = 0x04480000,
  50. .end = 0x044800FF,
  51. .flags = IORESOURCE_MEM,
  52. },
  53. [1] = {
  54. .start = 65,
  55. .end = 65,
  56. .flags = IORESOURCE_IRQ,
  57. },
  58. };
  59. static struct platform_device usbf_device = {
  60. .name = "m66592_udc",
  61. .id = -1,
  62. .dev = {
  63. .dma_mask = NULL,
  64. .coherent_dma_mask = 0xffffffff,
  65. },
  66. .num_resources = ARRAY_SIZE(usbf_resources),
  67. .resource = usbf_resources,
  68. };
  69. static struct resource iic_resources[] = {
  70. [0] = {
  71. .name = "IIC",
  72. .start = 0x04470000,
  73. .end = 0x04470017,
  74. .flags = IORESOURCE_MEM,
  75. },
  76. [1] = {
  77. .start = 96,
  78. .end = 99,
  79. .flags = IORESOURCE_IRQ,
  80. },
  81. };
  82. static struct platform_device iic_device = {
  83. .name = "i2c-sh_mobile",
  84. .num_resources = ARRAY_SIZE(iic_resources),
  85. .resource = iic_resources,
  86. };
  87. static struct uio_info vpu_platform_data = {
  88. .name = "VPU4",
  89. .version = "0",
  90. .irq = 60,
  91. };
  92. static struct resource vpu_resources[] = {
  93. [0] = {
  94. .name = "VPU",
  95. .start = 0xfe900000,
  96. .end = 0xfe9022eb,
  97. .flags = IORESOURCE_MEM,
  98. },
  99. [1] = {
  100. /* place holder for contiguous memory */
  101. },
  102. };
  103. static struct platform_device vpu_device = {
  104. .name = "uio_pdrv_genirq",
  105. .id = 0,
  106. .dev = {
  107. .platform_data = &vpu_platform_data,
  108. },
  109. .resource = vpu_resources,
  110. .num_resources = ARRAY_SIZE(vpu_resources),
  111. };
  112. static struct uio_info veu_platform_data = {
  113. .name = "VEU",
  114. .version = "0",
  115. .irq = 54,
  116. };
  117. static struct resource veu_resources[] = {
  118. [0] = {
  119. .name = "VEU",
  120. .start = 0xfe920000,
  121. .end = 0xfe9200b7,
  122. .flags = IORESOURCE_MEM,
  123. },
  124. [1] = {
  125. /* place holder for contiguous memory */
  126. },
  127. };
  128. static struct platform_device veu_device = {
  129. .name = "uio_pdrv_genirq",
  130. .id = 1,
  131. .dev = {
  132. .platform_data = &veu_platform_data,
  133. },
  134. .resource = veu_resources,
  135. .num_resources = ARRAY_SIZE(veu_resources),
  136. };
  137. static struct plat_sci_port sci_platform_data[] = {
  138. {
  139. .mapbase = 0xffe00000,
  140. .flags = UPF_BOOT_AUTOCONF,
  141. .type = PORT_SCIF,
  142. .irqs = { 80, 80, 80, 80 },
  143. },
  144. {
  145. .mapbase = 0xffe10000,
  146. .flags = UPF_BOOT_AUTOCONF,
  147. .type = PORT_SCIF,
  148. .irqs = { 81, 81, 81, 81 },
  149. },
  150. {
  151. .mapbase = 0xffe20000,
  152. .flags = UPF_BOOT_AUTOCONF,
  153. .type = PORT_SCIF,
  154. .irqs = { 82, 82, 82, 82 },
  155. },
  156. {
  157. .flags = 0,
  158. }
  159. };
  160. static struct platform_device sci_device = {
  161. .name = "sh-sci",
  162. .id = -1,
  163. .dev = {
  164. .platform_data = sci_platform_data,
  165. },
  166. };
  167. static struct platform_device *sh7722_devices[] __initdata = {
  168. &rtc_device,
  169. &usbf_device,
  170. &iic_device,
  171. &sci_device,
  172. &vpu_device,
  173. &veu_device,
  174. };
  175. static int __init sh7722_devices_setup(void)
  176. {
  177. clk_always_enable("mstp031"); /* TLB */
  178. clk_always_enable("mstp030"); /* IC */
  179. clk_always_enable("mstp029"); /* OC */
  180. clk_always_enable("mstp028"); /* URAM */
  181. clk_always_enable("mstp026"); /* XYMEM */
  182. clk_always_enable("mstp022"); /* INTC */
  183. clk_always_enable("mstp020"); /* SuperHyway */
  184. clk_always_enable("mstp109"); /* I2C */
  185. clk_always_enable("mstp211"); /* USB */
  186. clk_always_enable("mstp202"); /* VEU */
  187. clk_always_enable("mstp201"); /* VPU */
  188. platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
  189. platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
  190. return platform_add_devices(sh7722_devices,
  191. ARRAY_SIZE(sh7722_devices));
  192. }
  193. __initcall(sh7722_devices_setup);
  194. enum {
  195. UNUSED=0,
  196. /* interrupt sources */
  197. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  198. HUDI,
  199. SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
  200. RTC_ATI, RTC_PRI, RTC_CUI,
  201. DMAC0, DMAC1, DMAC2, DMAC3,
  202. VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
  203. VPU, TPU,
  204. USB_USBI0, USB_USBI1,
  205. DMAC4, DMAC5, DMAC_DADERR,
  206. KEYSC,
  207. SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
  208. FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
  209. I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
  210. SDHI0, SDHI1, SDHI2, SDHI3,
  211. CMT, TSIF, SIU, TWODG,
  212. TMU0, TMU1, TMU2,
  213. IRDA, JPU, LCDC,
  214. /* interrupt groups */
  215. SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
  216. };
  217. static struct intc_vect vectors[] __initdata = {
  218. INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
  219. INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
  220. INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
  221. INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
  222. INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
  223. INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
  224. INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
  225. INTC_VECT(RTC_CUI, 0x7c0),
  226. INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
  227. INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
  228. INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
  229. INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
  230. INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
  231. INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
  232. INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
  233. INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
  234. INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
  235. INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
  236. INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
  237. INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
  238. INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
  239. INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
  240. INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
  241. INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
  242. INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
  243. INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
  244. INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
  245. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  246. INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
  247. INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
  248. };
  249. static struct intc_group groups[] __initdata = {
  250. INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
  251. INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
  252. INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
  253. INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
  254. INTC_GROUP(USB, USB_USBI0, USB_USBI1),
  255. INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
  256. INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
  257. FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
  258. INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
  259. INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
  260. };
  261. static struct intc_mask_reg mask_registers[] __initdata = {
  262. { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
  263. { } },
  264. { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
  265. { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
  266. { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
  267. { 0, 0, 0, VPU, } },
  268. { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
  269. { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
  270. { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
  271. { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
  272. { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
  273. { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
  274. { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
  275. { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
  276. { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
  277. { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
  278. FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
  279. { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
  280. { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
  281. { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
  282. { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
  283. { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
  284. { } },
  285. { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
  286. { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
  287. { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
  288. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  289. };
  290. static struct intc_prio_reg prio_registers[] __initdata = {
  291. { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
  292. { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
  293. { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
  294. { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
  295. { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
  296. { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
  297. { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
  298. { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
  299. { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
  300. { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
  301. { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
  302. { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
  303. { 0xa4140010, 0, 32, 4, /* INTPRI00 */
  304. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  305. };
  306. static struct intc_sense_reg sense_registers[] __initdata = {
  307. { 0xa414001c, 16, 2, /* ICR1 */
  308. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  309. };
  310. static struct intc_mask_reg ack_registers[] __initdata = {
  311. { 0xa4140024, 0, 8, /* INTREQ00 */
  312. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  313. };
  314. static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
  315. mask_registers, prio_registers, sense_registers,
  316. ack_registers);
  317. void __init plat_irq_setup(void)
  318. {
  319. register_intc_controller(&intc_desc);
  320. }
  321. void __init plat_mem_setup(void)
  322. {
  323. /* Register the URAM space as Node 1 */
  324. setup_bootmem_node(1, 0x055f0000, 0x05610000);
  325. }