setup-sh7710.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166
  1. /*
  2. * SH3 Setup code for SH7710, SH7712
  3. *
  4. * Copyright (C) 2006, 2007 Paul Mundt
  5. * Copyright (C) 2007 Nobuhiro Iwamatsu
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/platform_device.h>
  12. #include <linux/init.h>
  13. #include <linux/irq.h>
  14. #include <linux/serial.h>
  15. #include <linux/serial_sci.h>
  16. #include <asm/rtc.h>
  17. enum {
  18. UNUSED = 0,
  19. /* interrupt sources */
  20. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  21. DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
  22. SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  23. SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
  24. DMAC_DEI4, DMAC_DEI5,
  25. IPSEC,
  26. EDMAC0, EDMAC1, EDMAC2,
  27. SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
  28. SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
  29. TMU0, TMU1, TMU2,
  30. RTC_ATI, RTC_PRI, RTC_CUI,
  31. WDT,
  32. REF,
  33. /* interrupt groups */
  34. RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
  35. };
  36. static struct intc_vect vectors[] __initdata = {
  37. /* IRQ0->5 are handled in setup-sh3.c */
  38. INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
  39. INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
  40. INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
  41. INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
  42. INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
  43. INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
  44. INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
  45. #ifdef CONFIG_CPU_SUBTYPE_SH7710
  46. INTC_VECT(IPSEC, 0xbe0),
  47. #endif
  48. INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
  49. INTC_VECT(EDMAC2, 0xc40),
  50. INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
  51. INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
  52. INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
  53. INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
  54. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  55. INTC_VECT(TMU2, 0x440),
  56. INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
  57. INTC_VECT(RTC_CUI, 0x4c0),
  58. INTC_VECT(WDT, 0x560),
  59. INTC_VECT(REF, 0x580),
  60. };
  61. static struct intc_group groups[] __initdata = {
  62. INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
  63. INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
  64. INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
  65. INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
  66. INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
  67. INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
  68. INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
  69. };
  70. static struct intc_prio_reg prio_registers[] __initdata = {
  71. { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  72. { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
  73. { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  74. { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
  75. { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
  76. { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } },
  77. { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
  78. { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
  79. { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
  80. };
  81. static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
  82. NULL, prio_registers, NULL);
  83. static struct resource rtc_resources[] = {
  84. [0] = {
  85. .start = 0xa413fec0,
  86. .end = 0xa413fec0 + 0x1e,
  87. .flags = IORESOURCE_IO,
  88. },
  89. [1] = {
  90. .start = 20,
  91. .flags = IORESOURCE_IRQ,
  92. },
  93. [2] = {
  94. .start = 21,
  95. .flags = IORESOURCE_IRQ,
  96. },
  97. [3] = {
  98. .start = 22,
  99. .flags = IORESOURCE_IRQ,
  100. },
  101. };
  102. static struct sh_rtc_platform_info rtc_info = {
  103. .capabilities = RTC_CAP_4_DIGIT_YEAR,
  104. };
  105. static struct platform_device rtc_device = {
  106. .name = "sh-rtc",
  107. .id = -1,
  108. .num_resources = ARRAY_SIZE(rtc_resources),
  109. .resource = rtc_resources,
  110. .dev = {
  111. .platform_data = &rtc_info,
  112. },
  113. };
  114. static struct plat_sci_port sci_platform_data[] = {
  115. {
  116. .mapbase = 0xa4400000,
  117. .flags = UPF_BOOT_AUTOCONF,
  118. .type = PORT_SCIF,
  119. .irqs = { 52, 53, 55, 54 },
  120. }, {
  121. .mapbase = 0xa4410000,
  122. .flags = UPF_BOOT_AUTOCONF,
  123. .type = PORT_SCIF,
  124. .irqs = { 56, 57, 59, 58 },
  125. }, {
  126. .flags = 0,
  127. }
  128. };
  129. static struct platform_device sci_device = {
  130. .name = "sh-sci",
  131. .id = -1,
  132. .dev = {
  133. .platform_data = sci_platform_data,
  134. },
  135. };
  136. static struct platform_device *sh7710_devices[] __initdata = {
  137. &sci_device,
  138. &rtc_device,
  139. };
  140. static int __init sh7710_devices_setup(void)
  141. {
  142. return platform_add_devices(sh7710_devices,
  143. ARRAY_SIZE(sh7710_devices));
  144. }
  145. __initcall(sh7710_devices_setup);
  146. void __init plat_irq_setup(void)
  147. {
  148. register_intc_controller(&intc_desc);
  149. plat_irq_setup_sh3();
  150. }