mpc8536ds.dts 9.7 KB

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  1. /*
  2. * MPC8536 DS Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "fsl,mpc8536ds";
  14. compatible = "fsl,mpc8536ds";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. pci2 = &pci2;
  25. pci3 = &pci3;
  26. };
  27. cpus {
  28. #cpus = <1>;
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. PowerPC,8536@0 {
  32. device_type = "cpu";
  33. reg = <0>;
  34. next-level-cache = <&L2>;
  35. };
  36. };
  37. memory {
  38. device_type = "memory";
  39. reg = <00000000 00000000>; // Filled by U-Boot
  40. };
  41. soc@ffe00000 {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. device_type = "soc";
  45. compatible = "simple-bus";
  46. ranges = <0x0 0xffe00000 0x100000>;
  47. reg = <0xffe00000 0x1000>;
  48. bus-frequency = <0>; // Filled out by uboot.
  49. memory-controller@2000 {
  50. compatible = "fsl,mpc8536-memory-controller";
  51. reg = <0x2000 0x1000>;
  52. interrupt-parent = <&mpic>;
  53. interrupts = <18 0x2>;
  54. };
  55. L2: l2-cache-controller@20000 {
  56. compatible = "fsl,mpc8536-l2-cache-controller";
  57. reg = <0x20000 0x1000>;
  58. interrupt-parent = <&mpic>;
  59. interrupts = <16 0x2>;
  60. };
  61. i2c@3000 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. cell-index = <0>;
  65. compatible = "fsl-i2c";
  66. reg = <0x3000 0x100>;
  67. interrupts = <43 0x2>;
  68. interrupt-parent = <&mpic>;
  69. dfsrr;
  70. };
  71. i2c@3100 {
  72. #address-cells = <1>;
  73. #size-cells = <0>;
  74. cell-index = <1>;
  75. compatible = "fsl-i2c";
  76. reg = <0x3100 0x100>;
  77. interrupts = <43 0x2>;
  78. interrupt-parent = <&mpic>;
  79. dfsrr;
  80. rtc@68 {
  81. compatible = "dallas,ds3232";
  82. reg = <0x68>;
  83. interrupts = <0 0x1>;
  84. interrupt-parent = <&mpic>;
  85. };
  86. };
  87. dma@21300 {
  88. #address-cells = <1>;
  89. #size-cells = <1>;
  90. compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
  91. reg = <0x21300 4>;
  92. ranges = <0 0x21100 0x200>;
  93. cell-index = <0>;
  94. dma-channel@0 {
  95. compatible = "fsl,mpc8536-dma-channel",
  96. "fsl,eloplus-dma-channel";
  97. reg = <0x0 0x80>;
  98. cell-index = <0>;
  99. interrupt-parent = <&mpic>;
  100. interrupts = <20 2>;
  101. };
  102. dma-channel@80 {
  103. compatible = "fsl,mpc8536-dma-channel",
  104. "fsl,eloplus-dma-channel";
  105. reg = <0x80 0x80>;
  106. cell-index = <1>;
  107. interrupt-parent = <&mpic>;
  108. interrupts = <21 2>;
  109. };
  110. dma-channel@100 {
  111. compatible = "fsl,mpc8536-dma-channel",
  112. "fsl,eloplus-dma-channel";
  113. reg = <0x100 0x80>;
  114. cell-index = <2>;
  115. interrupt-parent = <&mpic>;
  116. interrupts = <22 2>;
  117. };
  118. dma-channel@180 {
  119. compatible = "fsl,mpc8536-dma-channel",
  120. "fsl,eloplus-dma-channel";
  121. reg = <0x180 0x80>;
  122. cell-index = <3>;
  123. interrupt-parent = <&mpic>;
  124. interrupts = <23 2>;
  125. };
  126. };
  127. mdio@24520 {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. compatible = "fsl,gianfar-mdio";
  131. reg = <0x24520 0x20>;
  132. phy0: ethernet-phy@0 {
  133. interrupt-parent = <&mpic>;
  134. interrupts = <10 0x1>;
  135. reg = <0>;
  136. device_type = "ethernet-phy";
  137. };
  138. phy1: ethernet-phy@1 {
  139. interrupt-parent = <&mpic>;
  140. interrupts = <10 0x1>;
  141. reg = <1>;
  142. device_type = "ethernet-phy";
  143. };
  144. };
  145. usb@22000 {
  146. compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  147. reg = <0x22000 0x1000>;
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. interrupt-parent = <&mpic>;
  151. interrupts = <28 0x2>;
  152. phy_type = "ulpi";
  153. };
  154. usb@23000 {
  155. compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  156. reg = <0x23000 0x1000>;
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. interrupt-parent = <&mpic>;
  160. interrupts = <46 0x2>;
  161. phy_type = "ulpi";
  162. };
  163. enet0: ethernet@24000 {
  164. cell-index = <0>;
  165. device_type = "network";
  166. model = "eTSEC";
  167. compatible = "gianfar";
  168. reg = <0x24000 0x1000>;
  169. local-mac-address = [ 00 00 00 00 00 00 ];
  170. interrupts = <29 2 30 2 34 2>;
  171. interrupt-parent = <&mpic>;
  172. phy-handle = <&phy1>;
  173. phy-connection-type = "rgmii-id";
  174. };
  175. enet1: ethernet@26000 {
  176. cell-index = <1>;
  177. device_type = "network";
  178. model = "eTSEC";
  179. compatible = "gianfar";
  180. reg = <0x26000 0x1000>;
  181. local-mac-address = [ 00 00 00 00 00 00 ];
  182. interrupts = <31 2 32 2 33 2>;
  183. interrupt-parent = <&mpic>;
  184. phy-handle = <&phy0>;
  185. phy-connection-type = "rgmii-id";
  186. };
  187. usb@2b000 {
  188. compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
  189. reg = <0x2b000 0x1000>;
  190. #address-cells = <1>;
  191. #size-cells = <0>;
  192. interrupt-parent = <&mpic>;
  193. interrupts = <60 0x2>;
  194. dr_mode = "peripheral";
  195. phy_type = "ulpi";
  196. };
  197. serial0: serial@4500 {
  198. cell-index = <0>;
  199. device_type = "serial";
  200. compatible = "ns16550";
  201. reg = <0x4500 0x100>;
  202. clock-frequency = <0>;
  203. interrupts = <42 0x2>;
  204. interrupt-parent = <&mpic>;
  205. };
  206. serial1: serial@4600 {
  207. cell-index = <1>;
  208. device_type = "serial";
  209. compatible = "ns16550";
  210. reg = <0x4600 0x100>;
  211. clock-frequency = <0>;
  212. interrupts = <42 0x2>;
  213. interrupt-parent = <&mpic>;
  214. };
  215. crypto@30000 {
  216. compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
  217. "fsl,sec2.1", "fsl,sec2.0";
  218. reg = <0x30000 0x10000>;
  219. interrupts = <45 2 58 2>;
  220. interrupt-parent = <&mpic>;
  221. fsl,num-channels = <4>;
  222. fsl,channel-fifo-len = <24>;
  223. fsl,exec-units-mask = <0x9fe>;
  224. fsl,descriptor-types-mask = <0x3ab0ebf>;
  225. };
  226. sata@18000 {
  227. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  228. reg = <0x18000 0x1000>;
  229. cell-index = <1>;
  230. interrupts = <74 0x2>;
  231. interrupt-parent = <&mpic>;
  232. };
  233. sata@19000 {
  234. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  235. reg = <0x19000 0x1000>;
  236. cell-index = <2>;
  237. interrupts = <41 0x2>;
  238. interrupt-parent = <&mpic>;
  239. };
  240. global-utilities@e0000 { //global utilities block
  241. compatible = "fsl,mpc8548-guts";
  242. reg = <0xe0000 0x1000>;
  243. fsl,has-rstcr;
  244. };
  245. mpic: pic@40000 {
  246. clock-frequency = <0>;
  247. interrupt-controller;
  248. #address-cells = <0>;
  249. #interrupt-cells = <2>;
  250. reg = <0x40000 0x40000>;
  251. compatible = "chrp,open-pic";
  252. device_type = "open-pic";
  253. big-endian;
  254. };
  255. msi@41600 {
  256. compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
  257. reg = <0x41600 0x80>;
  258. msi-available-ranges = <0 0x100>;
  259. interrupts = <
  260. 0xe0 0
  261. 0xe1 0
  262. 0xe2 0
  263. 0xe3 0
  264. 0xe4 0
  265. 0xe5 0
  266. 0xe6 0
  267. 0xe7 0>;
  268. interrupt-parent = <&mpic>;
  269. };
  270. };
  271. pci0: pci@ffe08000 {
  272. cell-index = <0>;
  273. compatible = "fsl,mpc8540-pci";
  274. device_type = "pci";
  275. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  276. interrupt-map = <
  277. /* IDSEL 0x11 J17 Slot 1 */
  278. 0x8800 0 0 1 &mpic 1 1
  279. 0x8800 0 0 2 &mpic 2 1
  280. 0x8800 0 0 3 &mpic 3 1
  281. 0x8800 0 0 4 &mpic 4 1>;
  282. interrupt-parent = <&mpic>;
  283. interrupts = <24 0x2>;
  284. bus-range = <0 0xff>;
  285. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
  286. 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
  287. clock-frequency = <66666666>;
  288. #interrupt-cells = <1>;
  289. #size-cells = <2>;
  290. #address-cells = <3>;
  291. reg = <0xffe08000 0x1000>;
  292. };
  293. pci1: pcie@ffe09000 {
  294. cell-index = <1>;
  295. compatible = "fsl,mpc8548-pcie";
  296. device_type = "pci";
  297. #interrupt-cells = <1>;
  298. #size-cells = <2>;
  299. #address-cells = <3>;
  300. reg = <0xffe09000 0x1000>;
  301. bus-range = <0 0xff>;
  302. ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
  303. 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
  304. clock-frequency = <33333333>;
  305. interrupt-parent = <&mpic>;
  306. interrupts = <25 0x2>;
  307. interrupt-map-mask = <0xf800 0 0 7>;
  308. interrupt-map = <
  309. /* IDSEL 0x0 */
  310. 0000 0 0 1 &mpic 4 1
  311. 0000 0 0 2 &mpic 5 1
  312. 0000 0 0 3 &mpic 6 1
  313. 0000 0 0 4 &mpic 7 1
  314. >;
  315. pcie@0 {
  316. reg = <0 0 0 0 0>;
  317. #size-cells = <2>;
  318. #address-cells = <3>;
  319. device_type = "pci";
  320. ranges = <0x02000000 0 0x98000000
  321. 0x02000000 0 0x98000000
  322. 0 0x08000000
  323. 0x01000000 0 0x00000000
  324. 0x01000000 0 0x00000000
  325. 0 0x00010000>;
  326. };
  327. };
  328. pci2: pcie@ffe0a000 {
  329. cell-index = <2>;
  330. compatible = "fsl,mpc8548-pcie";
  331. device_type = "pci";
  332. #interrupt-cells = <1>;
  333. #size-cells = <2>;
  334. #address-cells = <3>;
  335. reg = <0xffe0a000 0x1000>;
  336. bus-range = <0 0xff>;
  337. ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
  338. 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
  339. clock-frequency = <33333333>;
  340. interrupt-parent = <&mpic>;
  341. interrupts = <26 0x2>;
  342. interrupt-map-mask = <0xf800 0 0 7>;
  343. interrupt-map = <
  344. /* IDSEL 0x0 */
  345. 0000 0 0 1 &mpic 0 1
  346. 0000 0 0 2 &mpic 1 1
  347. 0000 0 0 3 &mpic 2 1
  348. 0000 0 0 4 &mpic 3 1
  349. >;
  350. pcie@0 {
  351. reg = <0 0 0 0 0>;
  352. #size-cells = <2>;
  353. #address-cells = <3>;
  354. device_type = "pci";
  355. ranges = <0x02000000 0 0x90000000
  356. 0x02000000 0 0x90000000
  357. 0 0x08000000
  358. 0x01000000 0 0x00000000
  359. 0x01000000 0 0x00000000
  360. 0 0x00010000>;
  361. };
  362. };
  363. pci3: pcie@ffe0b000 {
  364. cell-index = <3>;
  365. compatible = "fsl,mpc8548-pcie";
  366. device_type = "pci";
  367. #interrupt-cells = <1>;
  368. #size-cells = <2>;
  369. #address-cells = <3>;
  370. reg = <0xffe0b000 0x1000>;
  371. bus-range = <0 0xff>;
  372. ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
  373. 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
  374. clock-frequency = <33333333>;
  375. interrupt-parent = <&mpic>;
  376. interrupts = <27 0x2>;
  377. interrupt-map-mask = <0xf800 0 0 7>;
  378. interrupt-map = <
  379. /* IDSEL 0x0 */
  380. 0000 0 0 1 &mpic 8 1
  381. 0000 0 0 2 &mpic 9 1
  382. 0000 0 0 3 &mpic 10 1
  383. 0000 0 0 4 &mpic 11 1
  384. >;
  385. pcie@0 {
  386. reg = <0 0 0 0 0>;
  387. #size-cells = <2>;
  388. #address-cells = <3>;
  389. device_type = "pci";
  390. ranges = <0x02000000 0 0xa0000000
  391. 0x02000000 0 0xa0000000
  392. 0 0x20000000
  393. 0x01000000 0 0x00000000
  394. 0x01000000 0 0x00000000
  395. 0 0x00100000>;
  396. };
  397. };
  398. };