mpc8349emitxgp.dts 5.6 KB

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  1. /*
  2. * MPC8349E-mITX-GP Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITXGP";
  14. compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8349@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>; // from bootloader
  34. bus-frequency = <0>; // from bootloader
  35. clock-frequency = <0>; // from bootloader
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>;
  41. };
  42. soc8349@e0000000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. device_type = "soc";
  46. compatible = "simple-bus";
  47. ranges = <0x0 0xe0000000 0x00100000>;
  48. reg = <0xe0000000 0x00000200>;
  49. bus-frequency = <0>; // from bootloader
  50. wdt@200 {
  51. device_type = "watchdog";
  52. compatible = "mpc83xx_wdt";
  53. reg = <0x200 0x100>;
  54. };
  55. i2c@3000 {
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. cell-index = <0>;
  59. compatible = "fsl-i2c";
  60. reg = <0x3000 0x100>;
  61. interrupts = <14 0x8>;
  62. interrupt-parent = <&ipic>;
  63. dfsrr;
  64. };
  65. i2c@3100 {
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. cell-index = <1>;
  69. compatible = "fsl-i2c";
  70. reg = <0x3100 0x100>;
  71. interrupts = <15 0x8>;
  72. interrupt-parent = <&ipic>;
  73. dfsrr;
  74. rtc@68 {
  75. device_type = "rtc";
  76. compatible = "dallas,ds1339";
  77. reg = <0x68>;
  78. interrupts = <18 0x8>;
  79. interrupt-parent = <&ipic>;
  80. };
  81. };
  82. spi@7000 {
  83. cell-index = <0>;
  84. compatible = "fsl,spi";
  85. reg = <0x7000 0x1000>;
  86. interrupts = <16 0x8>;
  87. interrupt-parent = <&ipic>;
  88. mode = "cpu";
  89. };
  90. dma@82a8 {
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  94. reg = <0x82a8 4>;
  95. ranges = <0 0x8100 0x1a8>;
  96. interrupt-parent = <&ipic>;
  97. interrupts = <71 8>;
  98. cell-index = <0>;
  99. dma-channel@0 {
  100. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  101. reg = <0 0x80>;
  102. cell-index = <0>;
  103. interrupt-parent = <&ipic>;
  104. interrupts = <71 8>;
  105. };
  106. dma-channel@80 {
  107. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  108. reg = <0x80 0x80>;
  109. cell-index = <1>;
  110. interrupt-parent = <&ipic>;
  111. interrupts = <71 8>;
  112. };
  113. dma-channel@100 {
  114. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  115. reg = <0x100 0x80>;
  116. cell-index = <2>;
  117. interrupt-parent = <&ipic>;
  118. interrupts = <71 8>;
  119. };
  120. dma-channel@180 {
  121. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  122. reg = <0x180 0x28>;
  123. cell-index = <3>;
  124. interrupt-parent = <&ipic>;
  125. interrupts = <71 8>;
  126. };
  127. };
  128. usb@23000 {
  129. compatible = "fsl-usb2-dr";
  130. reg = <0x23000 0x1000>;
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. interrupt-parent = <&ipic>;
  134. interrupts = <38 0x8>;
  135. dr_mode = "otg";
  136. phy_type = "ulpi";
  137. };
  138. mdio@24520 {
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. compatible = "fsl,gianfar-mdio";
  142. reg = <0x24520 0x20>;
  143. /* Vitesse 8201 */
  144. phy1c: ethernet-phy@1c {
  145. interrupt-parent = <&ipic>;
  146. interrupts = <18 0x8>;
  147. reg = <0x1c>;
  148. device_type = "ethernet-phy";
  149. };
  150. };
  151. enet0: ethernet@24000 {
  152. cell-index = <0>;
  153. device_type = "network";
  154. model = "TSEC";
  155. compatible = "gianfar";
  156. reg = <0x24000 0x1000>;
  157. local-mac-address = [ 00 00 00 00 00 00 ];
  158. interrupts = <32 0x8 33 0x8 34 0x8>;
  159. interrupt-parent = <&ipic>;
  160. phy-handle = <&phy1c>;
  161. linux,network-index = <0>;
  162. };
  163. serial0: serial@4500 {
  164. cell-index = <0>;
  165. device_type = "serial";
  166. compatible = "ns16550";
  167. reg = <0x4500 0x100>;
  168. clock-frequency = <0>; // from bootloader
  169. interrupts = <9 0x8>;
  170. interrupt-parent = <&ipic>;
  171. };
  172. serial1: serial@4600 {
  173. cell-index = <1>;
  174. device_type = "serial";
  175. compatible = "ns16550";
  176. reg = <0x4600 0x100>;
  177. clock-frequency = <0>; // from bootloader
  178. interrupts = <10 0x8>;
  179. interrupt-parent = <&ipic>;
  180. };
  181. crypto@30000 {
  182. compatible = "fsl,sec2.0";
  183. reg = <0x30000 0x10000>;
  184. interrupts = <11 0x8>;
  185. interrupt-parent = <&ipic>;
  186. fsl,num-channels = <4>;
  187. fsl,channel-fifo-len = <24>;
  188. fsl,exec-units-mask = <0x7e>;
  189. fsl,descriptor-types-mask = <0x01010ebf>;
  190. };
  191. ipic: pic@700 {
  192. interrupt-controller;
  193. #address-cells = <0>;
  194. #interrupt-cells = <2>;
  195. reg = <0x700 0x100>;
  196. device_type = "ipic";
  197. };
  198. };
  199. pci0: pci@e0008600 {
  200. cell-index = <2>;
  201. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  202. interrupt-map = <
  203. /* IDSEL 0x0F - PCI Slot */
  204. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  205. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  206. >;
  207. interrupt-parent = <&ipic>;
  208. interrupts = <67 0x8>;
  209. bus-range = <0x1 0x1>;
  210. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  211. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  212. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  213. clock-frequency = <66666666>;
  214. #interrupt-cells = <1>;
  215. #size-cells = <2>;
  216. #address-cells = <3>;
  217. reg = <0xe0008600 0x100 /* internal registers */
  218. 0xe0008380 0x8>; /* config space access registers */
  219. compatible = "fsl,mpc8349-pci";
  220. device_type = "pci";
  221. };
  222. };