mfp-pxa3xx.c 6.0 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/mfp.c
  3. *
  4. * PXA3xx Multi-Function Pin Support
  5. *
  6. * Copyright (C) 2007 Marvell Internation Ltd.
  7. *
  8. * 2007-08-21: eric miao <eric.miao@marvell.com>
  9. * initial version
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <linux/sysdev.h>
  20. #include <mach/hardware.h>
  21. #include <mach/mfp.h>
  22. #include <mach/mfp-pxa3xx.h>
  23. #include <mach/pxa3xx-regs.h>
  24. /* mfp_spin_lock is used to ensure that MFP register configuration
  25. * (most likely a read-modify-write operation) is atomic, and that
  26. * mfp_table[] is consistent
  27. */
  28. static DEFINE_SPINLOCK(mfp_spin_lock);
  29. static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
  30. struct pxa3xx_mfp_pin {
  31. unsigned long config; /* -1 for not configured */
  32. unsigned long mfpr_off; /* MFPRxx Register offset */
  33. unsigned long mfpr_run; /* Run-Mode Register Value */
  34. unsigned long mfpr_lpm; /* Low Power Mode Register Value */
  35. };
  36. static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
  37. /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
  38. static const unsigned long mfpr_lpm[] = {
  39. MFPR_LPM_INPUT,
  40. MFPR_LPM_DRIVE_LOW,
  41. MFPR_LPM_DRIVE_HIGH,
  42. MFPR_LPM_PULL_LOW,
  43. MFPR_LPM_PULL_HIGH,
  44. MFPR_LPM_FLOAT,
  45. };
  46. /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
  47. static const unsigned long mfpr_pull[] = {
  48. MFPR_PULL_NONE,
  49. MFPR_PULL_LOW,
  50. MFPR_PULL_HIGH,
  51. MFPR_PULL_BOTH,
  52. };
  53. /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
  54. static const unsigned long mfpr_edge[] = {
  55. MFPR_EDGE_NONE,
  56. MFPR_EDGE_RISE,
  57. MFPR_EDGE_FALL,
  58. MFPR_EDGE_BOTH,
  59. };
  60. #define mfpr_readl(off) \
  61. __raw_readl(mfpr_mmio_base + (off))
  62. #define mfpr_writel(off, val) \
  63. __raw_writel(val, mfpr_mmio_base + (off))
  64. #define mfp_configured(p) ((p)->config != -1)
  65. /*
  66. * perform a read-back of any MFPR register to make sure the
  67. * previous writings are finished
  68. */
  69. #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0)
  70. static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p)
  71. {
  72. if (mfp_configured(p))
  73. mfpr_writel(p->mfpr_off, p->mfpr_run);
  74. }
  75. static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p)
  76. {
  77. if (mfp_configured(p)) {
  78. unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
  79. if (mfpr_clr != p->mfpr_run)
  80. mfpr_writel(p->mfpr_off, mfpr_clr);
  81. if (p->mfpr_lpm != mfpr_clr)
  82. mfpr_writel(p->mfpr_off, p->mfpr_lpm);
  83. }
  84. }
  85. void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num)
  86. {
  87. unsigned long flags;
  88. int i;
  89. spin_lock_irqsave(&mfp_spin_lock, flags);
  90. for (i = 0; i < num; i++, mfp_cfgs++) {
  91. unsigned long tmp, c = *mfp_cfgs;
  92. struct pxa3xx_mfp_pin *p;
  93. int pin, af, drv, lpm, edge, pull;
  94. pin = MFP_PIN(c);
  95. BUG_ON(pin >= MFP_PIN_MAX);
  96. p = &mfp_table[pin];
  97. af = MFP_AF(c);
  98. drv = MFP_DS(c);
  99. lpm = MFP_LPM_STATE(c);
  100. edge = MFP_LPM_EDGE(c);
  101. pull = MFP_PULL(c);
  102. /* run-mode pull settings will conflict with MFPR bits of
  103. * low power mode state, calculate mfpr_run and mfpr_lpm
  104. * individually if pull != MFP_PULL_NONE
  105. */
  106. tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
  107. if (likely(pull == MFP_PULL_NONE)) {
  108. p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
  109. p->mfpr_lpm = p->mfpr_run;
  110. } else {
  111. p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
  112. p->mfpr_run = tmp | mfpr_pull[pull];
  113. }
  114. p->config = c; __mfp_config_run(p);
  115. }
  116. mfpr_sync();
  117. spin_unlock_irqrestore(&mfp_spin_lock, flags);
  118. }
  119. unsigned long pxa3xx_mfp_read(int mfp)
  120. {
  121. unsigned long val, flags;
  122. BUG_ON(mfp >= MFP_PIN_MAX);
  123. spin_lock_irqsave(&mfp_spin_lock, flags);
  124. val = mfpr_readl(mfp_table[mfp].mfpr_off);
  125. spin_unlock_irqrestore(&mfp_spin_lock, flags);
  126. return val;
  127. }
  128. void pxa3xx_mfp_write(int mfp, unsigned long val)
  129. {
  130. unsigned long flags;
  131. BUG_ON(mfp >= MFP_PIN_MAX);
  132. spin_lock_irqsave(&mfp_spin_lock, flags);
  133. mfpr_writel(mfp_table[mfp].mfpr_off, val);
  134. mfpr_sync();
  135. spin_unlock_irqrestore(&mfp_spin_lock, flags);
  136. }
  137. void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
  138. {
  139. struct pxa3xx_mfp_addr_map *p;
  140. unsigned long offset, flags;
  141. int i;
  142. spin_lock_irqsave(&mfp_spin_lock, flags);
  143. for (p = map; p->start != MFP_PIN_INVALID; p++) {
  144. offset = p->offset;
  145. i = p->start;
  146. do {
  147. mfp_table[i].mfpr_off = offset;
  148. mfp_table[i].mfpr_run = 0;
  149. mfp_table[i].mfpr_lpm = 0;
  150. offset += 4; i++;
  151. } while ((i <= p->end) && (p->end != -1));
  152. }
  153. spin_unlock_irqrestore(&mfp_spin_lock, flags);
  154. }
  155. void __init pxa3xx_init_mfp(void)
  156. {
  157. int i;
  158. for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
  159. mfp_table[i].config = -1;
  160. }
  161. #ifdef CONFIG_PM
  162. /*
  163. * Configure the MFPs appropriately for suspend/resume.
  164. * FIXME: this should probably depend on which system state we're
  165. * entering - for instance, we might not want to place MFP pins in
  166. * a pull-down mode if they're an active low chip select, and we're
  167. * just entering standby.
  168. */
  169. static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state)
  170. {
  171. int pin;
  172. for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
  173. struct pxa3xx_mfp_pin *p = &mfp_table[pin];
  174. __mfp_config_lpm(p);
  175. }
  176. return 0;
  177. }
  178. static int pxa3xx_mfp_resume(struct sys_device *d)
  179. {
  180. int pin;
  181. for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) {
  182. struct pxa3xx_mfp_pin *p = &mfp_table[pin];
  183. __mfp_config_run(p);
  184. }
  185. /* clear RDH bit when MFP settings are restored
  186. *
  187. * NOTE: the last 3 bits DxS are write-1-to-clear so carefully
  188. * preserve them here in case they will be referenced later
  189. */
  190. ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
  191. return 0;
  192. }
  193. #else
  194. #define pxa3xx_mfp_suspend NULL
  195. #define pxa3xx_mfp_resume NULL
  196. #endif
  197. struct sysdev_class pxa3xx_mfp_sysclass = {
  198. .name = "mfp",
  199. .suspend = pxa3xx_mfp_suspend,
  200. .resume = pxa3xx_mfp_resume,
  201. };
  202. static int __init mfp_init_devicefs(void)
  203. {
  204. if (cpu_is_pxa3xx())
  205. return sysdev_class_register(&pxa3xx_mfp_sysclass);
  206. return 0;
  207. }
  208. postcore_initcall(mfp_init_devicefs);