lpd270.c 12 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/lpd270.c
  3. *
  4. * Support for the LogicPD PXA270 Card Engine.
  5. * Derived from the mainstone code, which carries these notices:
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <linux/bitops.h>
  21. #include <linux/fb.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/pwm_backlight.h>
  26. #include <asm/types.h>
  27. #include <asm/setup.h>
  28. #include <asm/memory.h>
  29. #include <asm/mach-types.h>
  30. #include <mach/hardware.h>
  31. #include <asm/irq.h>
  32. #include <asm/sizes.h>
  33. #include <asm/mach/arch.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/mach/irq.h>
  36. #include <asm/mach/flash.h>
  37. #include <mach/pxa-regs.h>
  38. #include <mach/pxa2xx-regs.h>
  39. #include <mach/mfp-pxa27x.h>
  40. #include <mach/lpd270.h>
  41. #include <mach/audio.h>
  42. #include <mach/pxafb.h>
  43. #include <mach/mmc.h>
  44. #include <mach/irda.h>
  45. #include <mach/ohci.h>
  46. #include "generic.h"
  47. #include "devices.h"
  48. static unsigned long lpd270_pin_config[] __initdata = {
  49. /* Chip Selects */
  50. GPIO15_nCS_1, /* Mainboard Flash */
  51. GPIO78_nCS_2, /* CPLD + Ethernet */
  52. /* LCD - 16bpp Active TFT */
  53. GPIO58_LCD_LDD_0,
  54. GPIO59_LCD_LDD_1,
  55. GPIO60_LCD_LDD_2,
  56. GPIO61_LCD_LDD_3,
  57. GPIO62_LCD_LDD_4,
  58. GPIO63_LCD_LDD_5,
  59. GPIO64_LCD_LDD_6,
  60. GPIO65_LCD_LDD_7,
  61. GPIO66_LCD_LDD_8,
  62. GPIO67_LCD_LDD_9,
  63. GPIO68_LCD_LDD_10,
  64. GPIO69_LCD_LDD_11,
  65. GPIO70_LCD_LDD_12,
  66. GPIO71_LCD_LDD_13,
  67. GPIO72_LCD_LDD_14,
  68. GPIO73_LCD_LDD_15,
  69. GPIO74_LCD_FCLK,
  70. GPIO75_LCD_LCLK,
  71. GPIO76_LCD_PCLK,
  72. GPIO77_LCD_BIAS,
  73. GPIO16_PWM0_OUT, /* Backlight */
  74. /* USB Host */
  75. GPIO88_USBH1_PWR,
  76. GPIO89_USBH1_PEN,
  77. /* AC97 */
  78. GPIO45_AC97_SYSCLK,
  79. GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  80. };
  81. static unsigned int lpd270_irq_enabled;
  82. static void lpd270_mask_irq(unsigned int irq)
  83. {
  84. int lpd270_irq = irq - LPD270_IRQ(0);
  85. __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  86. lpd270_irq_enabled &= ~(1 << lpd270_irq);
  87. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  88. }
  89. static void lpd270_unmask_irq(unsigned int irq)
  90. {
  91. int lpd270_irq = irq - LPD270_IRQ(0);
  92. lpd270_irq_enabled |= 1 << lpd270_irq;
  93. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  94. }
  95. static struct irq_chip lpd270_irq_chip = {
  96. .name = "CPLD",
  97. .ack = lpd270_mask_irq,
  98. .mask = lpd270_mask_irq,
  99. .unmask = lpd270_unmask_irq,
  100. };
  101. static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
  102. {
  103. unsigned long pending;
  104. pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  105. do {
  106. GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
  107. if (likely(pending)) {
  108. irq = LPD270_IRQ(0) + __ffs(pending);
  109. generic_handle_irq(irq);
  110. pending = __raw_readw(LPD270_INT_STATUS) &
  111. lpd270_irq_enabled;
  112. }
  113. } while (pending);
  114. }
  115. static void __init lpd270_init_irq(void)
  116. {
  117. int irq;
  118. pxa27x_init_irq();
  119. __raw_writew(0, LPD270_INT_MASK);
  120. __raw_writew(0, LPD270_INT_STATUS);
  121. /* setup extra LogicPD PXA270 irqs */
  122. for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
  123. set_irq_chip(irq, &lpd270_irq_chip);
  124. set_irq_handler(irq, handle_level_irq);
  125. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  126. }
  127. set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
  128. set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
  129. }
  130. #ifdef CONFIG_PM
  131. static int lpd270_irq_resume(struct sys_device *dev)
  132. {
  133. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  134. return 0;
  135. }
  136. static struct sysdev_class lpd270_irq_sysclass = {
  137. .name = "cpld_irq",
  138. .resume = lpd270_irq_resume,
  139. };
  140. static struct sys_device lpd270_irq_device = {
  141. .cls = &lpd270_irq_sysclass,
  142. };
  143. static int __init lpd270_irq_device_init(void)
  144. {
  145. int ret = -ENODEV;
  146. if (machine_is_logicpd_pxa270()) {
  147. ret = sysdev_class_register(&lpd270_irq_sysclass);
  148. if (ret == 0)
  149. ret = sysdev_register(&lpd270_irq_device);
  150. }
  151. return ret;
  152. }
  153. device_initcall(lpd270_irq_device_init);
  154. #endif
  155. static struct resource smc91x_resources[] = {
  156. [0] = {
  157. .start = LPD270_ETH_PHYS,
  158. .end = (LPD270_ETH_PHYS + 0xfffff),
  159. .flags = IORESOURCE_MEM,
  160. },
  161. [1] = {
  162. .start = LPD270_ETHERNET_IRQ,
  163. .end = LPD270_ETHERNET_IRQ,
  164. .flags = IORESOURCE_IRQ,
  165. },
  166. };
  167. static struct platform_device smc91x_device = {
  168. .name = "smc91x",
  169. .id = 0,
  170. .num_resources = ARRAY_SIZE(smc91x_resources),
  171. .resource = smc91x_resources,
  172. };
  173. static struct resource lpd270_flash_resources[] = {
  174. [0] = {
  175. .start = PXA_CS0_PHYS,
  176. .end = PXA_CS0_PHYS + SZ_64M - 1,
  177. .flags = IORESOURCE_MEM,
  178. },
  179. [1] = {
  180. .start = PXA_CS1_PHYS,
  181. .end = PXA_CS1_PHYS + SZ_64M - 1,
  182. .flags = IORESOURCE_MEM,
  183. },
  184. };
  185. static struct mtd_partition lpd270_flash0_partitions[] = {
  186. {
  187. .name = "Bootloader",
  188. .size = 0x00040000,
  189. .offset = 0,
  190. .mask_flags = MTD_WRITEABLE /* force read-only */
  191. }, {
  192. .name = "Kernel",
  193. .size = 0x00400000,
  194. .offset = 0x00040000,
  195. }, {
  196. .name = "Filesystem",
  197. .size = MTDPART_SIZ_FULL,
  198. .offset = 0x00440000
  199. },
  200. };
  201. static struct flash_platform_data lpd270_flash_data[2] = {
  202. {
  203. .name = "processor-flash",
  204. .map_name = "cfi_probe",
  205. .parts = lpd270_flash0_partitions,
  206. .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
  207. }, {
  208. .name = "mainboard-flash",
  209. .map_name = "cfi_probe",
  210. .parts = NULL,
  211. .nr_parts = 0,
  212. }
  213. };
  214. static struct platform_device lpd270_flash_device[2] = {
  215. {
  216. .name = "pxa2xx-flash",
  217. .id = 0,
  218. .dev = {
  219. .platform_data = &lpd270_flash_data[0],
  220. },
  221. .resource = &lpd270_flash_resources[0],
  222. .num_resources = 1,
  223. }, {
  224. .name = "pxa2xx-flash",
  225. .id = 1,
  226. .dev = {
  227. .platform_data = &lpd270_flash_data[1],
  228. },
  229. .resource = &lpd270_flash_resources[1],
  230. .num_resources = 1,
  231. },
  232. };
  233. static struct platform_pwm_backlight_data lpd270_backlight_data = {
  234. .pwm_id = 0,
  235. .max_brightness = 1,
  236. .dft_brightness = 1,
  237. .pwm_period_ns = 78770,
  238. };
  239. static struct platform_device lpd270_backlight_device = {
  240. .name = "pwm-backlight",
  241. .dev = {
  242. .parent = &pxa27x_device_pwm0.dev,
  243. .platform_data = &lpd270_backlight_data,
  244. },
  245. };
  246. /* 5.7" TFT QVGA (LoLo display number 1) */
  247. static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
  248. .pixclock = 150000,
  249. .xres = 320,
  250. .yres = 240,
  251. .bpp = 16,
  252. .hsync_len = 0x14,
  253. .left_margin = 0x28,
  254. .right_margin = 0x0a,
  255. .vsync_len = 0x02,
  256. .upper_margin = 0x08,
  257. .lower_margin = 0x14,
  258. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  259. };
  260. static struct pxafb_mach_info sharp_lq057q3dc02 = {
  261. .modes = &sharp_lq057q3dc02_mode,
  262. .num_modes = 1,
  263. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  264. LCD_ALTERNATE_MAPPING,
  265. };
  266. /* 12.1" TFT SVGA (LoLo display number 2) */
  267. static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
  268. .pixclock = 50000,
  269. .xres = 800,
  270. .yres = 600,
  271. .bpp = 16,
  272. .hsync_len = 0x05,
  273. .left_margin = 0x52,
  274. .right_margin = 0x05,
  275. .vsync_len = 0x04,
  276. .upper_margin = 0x14,
  277. .lower_margin = 0x0a,
  278. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  279. };
  280. static struct pxafb_mach_info sharp_lq121s1dg31 = {
  281. .modes = &sharp_lq121s1dg31_mode,
  282. .num_modes = 1,
  283. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  284. LCD_ALTERNATE_MAPPING,
  285. };
  286. /* 3.6" TFT QVGA (LoLo display number 3) */
  287. static struct pxafb_mode_info sharp_lq036q1da01_mode = {
  288. .pixclock = 150000,
  289. .xres = 320,
  290. .yres = 240,
  291. .bpp = 16,
  292. .hsync_len = 0x0e,
  293. .left_margin = 0x04,
  294. .right_margin = 0x0a,
  295. .vsync_len = 0x03,
  296. .upper_margin = 0x03,
  297. .lower_margin = 0x03,
  298. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  299. };
  300. static struct pxafb_mach_info sharp_lq036q1da01 = {
  301. .modes = &sharp_lq036q1da01_mode,
  302. .num_modes = 1,
  303. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  304. LCD_ALTERNATE_MAPPING,
  305. };
  306. /* 6.4" TFT VGA (LoLo display number 5) */
  307. static struct pxafb_mode_info sharp_lq64d343_mode = {
  308. .pixclock = 25000,
  309. .xres = 640,
  310. .yres = 480,
  311. .bpp = 16,
  312. .hsync_len = 0x31,
  313. .left_margin = 0x89,
  314. .right_margin = 0x19,
  315. .vsync_len = 0x12,
  316. .upper_margin = 0x22,
  317. .lower_margin = 0x00,
  318. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  319. };
  320. static struct pxafb_mach_info sharp_lq64d343 = {
  321. .modes = &sharp_lq64d343_mode,
  322. .num_modes = 1,
  323. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  324. LCD_ALTERNATE_MAPPING,
  325. };
  326. /* 10.4" TFT VGA (LoLo display number 7) */
  327. static struct pxafb_mode_info sharp_lq10d368_mode = {
  328. .pixclock = 25000,
  329. .xres = 640,
  330. .yres = 480,
  331. .bpp = 16,
  332. .hsync_len = 0x31,
  333. .left_margin = 0x89,
  334. .right_margin = 0x19,
  335. .vsync_len = 0x12,
  336. .upper_margin = 0x22,
  337. .lower_margin = 0x00,
  338. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  339. };
  340. static struct pxafb_mach_info sharp_lq10d368 = {
  341. .modes = &sharp_lq10d368_mode,
  342. .num_modes = 1,
  343. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  344. LCD_ALTERNATE_MAPPING,
  345. };
  346. /* 3.5" TFT QVGA (LoLo display number 8) */
  347. static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
  348. .pixclock = 150000,
  349. .xres = 240,
  350. .yres = 320,
  351. .bpp = 16,
  352. .hsync_len = 0x0e,
  353. .left_margin = 0x0a,
  354. .right_margin = 0x0a,
  355. .vsync_len = 0x03,
  356. .upper_margin = 0x05,
  357. .lower_margin = 0x14,
  358. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  359. };
  360. static struct pxafb_mach_info sharp_lq035q7db02_20 = {
  361. .modes = &sharp_lq035q7db02_20_mode,
  362. .num_modes = 1,
  363. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  364. LCD_ALTERNATE_MAPPING,
  365. };
  366. static struct pxafb_mach_info *lpd270_lcd_to_use;
  367. static int __init lpd270_set_lcd(char *str)
  368. {
  369. if (!strnicmp(str, "lq057q3dc02", 11)) {
  370. lpd270_lcd_to_use = &sharp_lq057q3dc02;
  371. } else if (!strnicmp(str, "lq121s1dg31", 11)) {
  372. lpd270_lcd_to_use = &sharp_lq121s1dg31;
  373. } else if (!strnicmp(str, "lq036q1da01", 11)) {
  374. lpd270_lcd_to_use = &sharp_lq036q1da01;
  375. } else if (!strnicmp(str, "lq64d343", 8)) {
  376. lpd270_lcd_to_use = &sharp_lq64d343;
  377. } else if (!strnicmp(str, "lq10d368", 8)) {
  378. lpd270_lcd_to_use = &sharp_lq10d368;
  379. } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
  380. lpd270_lcd_to_use = &sharp_lq035q7db02_20;
  381. } else {
  382. printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
  383. }
  384. return 1;
  385. }
  386. __setup("lcd=", lpd270_set_lcd);
  387. static struct platform_device *platform_devices[] __initdata = {
  388. &smc91x_device,
  389. &lpd270_backlight_device,
  390. &lpd270_flash_device[0],
  391. &lpd270_flash_device[1],
  392. };
  393. static struct pxaohci_platform_data lpd270_ohci_platform_data = {
  394. .port_mode = PMM_PERPORT_MODE,
  395. .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
  396. };
  397. static void __init lpd270_init(void)
  398. {
  399. pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
  400. lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  401. lpd270_flash_data[1].width = 4;
  402. /*
  403. * System bus arbiter setting:
  404. * - Core_Park
  405. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  406. */
  407. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  408. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  409. pxa_set_ac97_info(NULL);
  410. if (lpd270_lcd_to_use != NULL)
  411. set_pxa_fb_info(lpd270_lcd_to_use);
  412. pxa_set_ohci_info(&lpd270_ohci_platform_data);
  413. }
  414. static struct map_desc lpd270_io_desc[] __initdata = {
  415. {
  416. .virtual = LPD270_CPLD_VIRT,
  417. .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
  418. .length = LPD270_CPLD_SIZE,
  419. .type = MT_DEVICE,
  420. },
  421. };
  422. static void __init lpd270_map_io(void)
  423. {
  424. pxa_map_io();
  425. iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
  426. /* for use I SRAM as framebuffer. */
  427. PSLR |= 0x00000F04;
  428. PCFR = 0x00000066;
  429. }
  430. MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
  431. /* Maintainer: Peter Barada */
  432. .phys_io = 0x40000000,
  433. .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  434. .boot_params = 0xa0000100,
  435. .map_io = lpd270_map_io,
  436. .init_irq = lpd270_init_irq,
  437. .timer = &pxa_timer,
  438. .init_machine = lpd270_init,
  439. MACHINE_END