devices.c 18 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <mach/gpio.h>
  7. #include <mach/udc.h>
  8. #include <mach/pxafb.h>
  9. #include <mach/mmc.h>
  10. #include <mach/irda.h>
  11. #include <mach/i2c.h>
  12. #include <mach/mfp-pxa27x.h>
  13. #include <mach/ohci.h>
  14. #include <mach/pxa27x_keypad.h>
  15. #include <mach/pxa2xx_spi.h>
  16. #include <mach/camera.h>
  17. #include <mach/audio.h>
  18. #include <mach/pxa3xx_nand.h>
  19. #include "devices.h"
  20. #include "generic.h"
  21. void __init pxa_register_device(struct platform_device *dev, void *data)
  22. {
  23. int ret;
  24. dev->dev.platform_data = data;
  25. ret = platform_device_register(dev);
  26. if (ret)
  27. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  28. }
  29. static struct resource pxamci_resources[] = {
  30. [0] = {
  31. .start = 0x41100000,
  32. .end = 0x41100fff,
  33. .flags = IORESOURCE_MEM,
  34. },
  35. [1] = {
  36. .start = IRQ_MMC,
  37. .end = IRQ_MMC,
  38. .flags = IORESOURCE_IRQ,
  39. },
  40. [2] = {
  41. .start = 21,
  42. .end = 21,
  43. .flags = IORESOURCE_DMA,
  44. },
  45. [3] = {
  46. .start = 22,
  47. .end = 22,
  48. .flags = IORESOURCE_DMA,
  49. },
  50. };
  51. static u64 pxamci_dmamask = 0xffffffffUL;
  52. struct platform_device pxa_device_mci = {
  53. .name = "pxa2xx-mci",
  54. .id = 0,
  55. .dev = {
  56. .dma_mask = &pxamci_dmamask,
  57. .coherent_dma_mask = 0xffffffff,
  58. },
  59. .num_resources = ARRAY_SIZE(pxamci_resources),
  60. .resource = pxamci_resources,
  61. };
  62. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  63. {
  64. pxa_register_device(&pxa_device_mci, info);
  65. }
  66. static struct pxa2xx_udc_mach_info pxa_udc_info;
  67. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  68. {
  69. memcpy(&pxa_udc_info, info, sizeof *info);
  70. }
  71. static struct resource pxa2xx_udc_resources[] = {
  72. [0] = {
  73. .start = 0x40600000,
  74. .end = 0x4060ffff,
  75. .flags = IORESOURCE_MEM,
  76. },
  77. [1] = {
  78. .start = IRQ_USB,
  79. .end = IRQ_USB,
  80. .flags = IORESOURCE_IRQ,
  81. },
  82. };
  83. static u64 udc_dma_mask = ~(u32)0;
  84. struct platform_device pxa25x_device_udc = {
  85. .name = "pxa25x-udc",
  86. .id = -1,
  87. .resource = pxa2xx_udc_resources,
  88. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  89. .dev = {
  90. .platform_data = &pxa_udc_info,
  91. .dma_mask = &udc_dma_mask,
  92. }
  93. };
  94. struct platform_device pxa27x_device_udc = {
  95. .name = "pxa27x-udc",
  96. .id = -1,
  97. .resource = pxa2xx_udc_resources,
  98. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  99. .dev = {
  100. .platform_data = &pxa_udc_info,
  101. .dma_mask = &udc_dma_mask,
  102. }
  103. };
  104. static struct resource pxafb_resources[] = {
  105. [0] = {
  106. .start = 0x44000000,
  107. .end = 0x4400ffff,
  108. .flags = IORESOURCE_MEM,
  109. },
  110. [1] = {
  111. .start = IRQ_LCD,
  112. .end = IRQ_LCD,
  113. .flags = IORESOURCE_IRQ,
  114. },
  115. };
  116. static u64 fb_dma_mask = ~(u64)0;
  117. struct platform_device pxa_device_fb = {
  118. .name = "pxa2xx-fb",
  119. .id = -1,
  120. .dev = {
  121. .dma_mask = &fb_dma_mask,
  122. .coherent_dma_mask = 0xffffffff,
  123. },
  124. .num_resources = ARRAY_SIZE(pxafb_resources),
  125. .resource = pxafb_resources,
  126. };
  127. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  128. {
  129. pxa_register_device(&pxa_device_fb, info);
  130. }
  131. void __init set_pxa_fb_parent(struct device *parent_dev)
  132. {
  133. pxa_device_fb.dev.parent = parent_dev;
  134. }
  135. static struct resource pxa_resource_ffuart[] = {
  136. {
  137. .start = __PREG(FFUART),
  138. .end = __PREG(FFUART) + 35,
  139. .flags = IORESOURCE_MEM,
  140. }, {
  141. .start = IRQ_FFUART,
  142. .end = IRQ_FFUART,
  143. .flags = IORESOURCE_IRQ,
  144. }
  145. };
  146. struct platform_device pxa_device_ffuart= {
  147. .name = "pxa2xx-uart",
  148. .id = 0,
  149. .resource = pxa_resource_ffuart,
  150. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  151. };
  152. static struct resource pxa_resource_btuart[] = {
  153. {
  154. .start = __PREG(BTUART),
  155. .end = __PREG(BTUART) + 35,
  156. .flags = IORESOURCE_MEM,
  157. }, {
  158. .start = IRQ_BTUART,
  159. .end = IRQ_BTUART,
  160. .flags = IORESOURCE_IRQ,
  161. }
  162. };
  163. struct platform_device pxa_device_btuart = {
  164. .name = "pxa2xx-uart",
  165. .id = 1,
  166. .resource = pxa_resource_btuart,
  167. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  168. };
  169. static struct resource pxa_resource_stuart[] = {
  170. {
  171. .start = __PREG(STUART),
  172. .end = __PREG(STUART) + 35,
  173. .flags = IORESOURCE_MEM,
  174. }, {
  175. .start = IRQ_STUART,
  176. .end = IRQ_STUART,
  177. .flags = IORESOURCE_IRQ,
  178. }
  179. };
  180. struct platform_device pxa_device_stuart = {
  181. .name = "pxa2xx-uart",
  182. .id = 2,
  183. .resource = pxa_resource_stuart,
  184. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  185. };
  186. static struct resource pxa_resource_hwuart[] = {
  187. {
  188. .start = __PREG(HWUART),
  189. .end = __PREG(HWUART) + 47,
  190. .flags = IORESOURCE_MEM,
  191. }, {
  192. .start = IRQ_HWUART,
  193. .end = IRQ_HWUART,
  194. .flags = IORESOURCE_IRQ,
  195. }
  196. };
  197. struct platform_device pxa_device_hwuart = {
  198. .name = "pxa2xx-uart",
  199. .id = 3,
  200. .resource = pxa_resource_hwuart,
  201. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  202. };
  203. static struct resource pxai2c_resources[] = {
  204. {
  205. .start = 0x40301680,
  206. .end = 0x403016a3,
  207. .flags = IORESOURCE_MEM,
  208. }, {
  209. .start = IRQ_I2C,
  210. .end = IRQ_I2C,
  211. .flags = IORESOURCE_IRQ,
  212. },
  213. };
  214. struct platform_device pxa_device_i2c = {
  215. .name = "pxa2xx-i2c",
  216. .id = 0,
  217. .resource = pxai2c_resources,
  218. .num_resources = ARRAY_SIZE(pxai2c_resources),
  219. };
  220. static unsigned long pxa27x_i2c_mfp_cfg[] = {
  221. GPIO117_I2C_SCL,
  222. GPIO118_I2C_SDA,
  223. };
  224. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  225. {
  226. if (cpu_is_pxa27x())
  227. pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
  228. pxa_register_device(&pxa_device_i2c, info);
  229. }
  230. static struct resource pxai2s_resources[] = {
  231. {
  232. .start = 0x40400000,
  233. .end = 0x40400083,
  234. .flags = IORESOURCE_MEM,
  235. }, {
  236. .start = IRQ_I2S,
  237. .end = IRQ_I2S,
  238. .flags = IORESOURCE_IRQ,
  239. },
  240. };
  241. struct platform_device pxa_device_i2s = {
  242. .name = "pxa2xx-i2s",
  243. .id = -1,
  244. .resource = pxai2s_resources,
  245. .num_resources = ARRAY_SIZE(pxai2s_resources),
  246. };
  247. static u64 pxaficp_dmamask = ~(u32)0;
  248. struct platform_device pxa_device_ficp = {
  249. .name = "pxa2xx-ir",
  250. .id = -1,
  251. .dev = {
  252. .dma_mask = &pxaficp_dmamask,
  253. .coherent_dma_mask = 0xffffffff,
  254. },
  255. };
  256. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  257. {
  258. pxa_register_device(&pxa_device_ficp, info);
  259. }
  260. struct platform_device pxa_device_rtc = {
  261. .name = "sa1100-rtc",
  262. .id = -1,
  263. };
  264. static struct resource pxa_ac97_resources[] = {
  265. [0] = {
  266. .start = 0x40500000,
  267. .end = 0x40500000 + 0xfff,
  268. .flags = IORESOURCE_MEM,
  269. },
  270. [1] = {
  271. .start = IRQ_AC97,
  272. .end = IRQ_AC97,
  273. .flags = IORESOURCE_IRQ,
  274. },
  275. };
  276. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  277. struct platform_device pxa_device_ac97 = {
  278. .name = "pxa2xx-ac97",
  279. .id = -1,
  280. .dev = {
  281. .dma_mask = &pxa_ac97_dmamask,
  282. .coherent_dma_mask = 0xffffffff,
  283. },
  284. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  285. .resource = pxa_ac97_resources,
  286. };
  287. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  288. {
  289. pxa_register_device(&pxa_device_ac97, ops);
  290. }
  291. #ifdef CONFIG_PXA25x
  292. static struct resource pxa25x_resource_pwm0[] = {
  293. [0] = {
  294. .start = 0x40b00000,
  295. .end = 0x40b0000f,
  296. .flags = IORESOURCE_MEM,
  297. },
  298. };
  299. struct platform_device pxa25x_device_pwm0 = {
  300. .name = "pxa25x-pwm",
  301. .id = 0,
  302. .resource = pxa25x_resource_pwm0,
  303. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  304. };
  305. static struct resource pxa25x_resource_pwm1[] = {
  306. [0] = {
  307. .start = 0x40c00000,
  308. .end = 0x40c0000f,
  309. .flags = IORESOURCE_MEM,
  310. },
  311. };
  312. struct platform_device pxa25x_device_pwm1 = {
  313. .name = "pxa25x-pwm",
  314. .id = 1,
  315. .resource = pxa25x_resource_pwm1,
  316. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  317. };
  318. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  319. static struct resource pxa25x_resource_ssp[] = {
  320. [0] = {
  321. .start = 0x41000000,
  322. .end = 0x4100001f,
  323. .flags = IORESOURCE_MEM,
  324. },
  325. [1] = {
  326. .start = IRQ_SSP,
  327. .end = IRQ_SSP,
  328. .flags = IORESOURCE_IRQ,
  329. },
  330. [2] = {
  331. /* DRCMR for RX */
  332. .start = 13,
  333. .end = 13,
  334. .flags = IORESOURCE_DMA,
  335. },
  336. [3] = {
  337. /* DRCMR for TX */
  338. .start = 14,
  339. .end = 14,
  340. .flags = IORESOURCE_DMA,
  341. },
  342. };
  343. struct platform_device pxa25x_device_ssp = {
  344. .name = "pxa25x-ssp",
  345. .id = 0,
  346. .dev = {
  347. .dma_mask = &pxa25x_ssp_dma_mask,
  348. .coherent_dma_mask = DMA_BIT_MASK(32),
  349. },
  350. .resource = pxa25x_resource_ssp,
  351. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  352. };
  353. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  354. static struct resource pxa25x_resource_nssp[] = {
  355. [0] = {
  356. .start = 0x41400000,
  357. .end = 0x4140002f,
  358. .flags = IORESOURCE_MEM,
  359. },
  360. [1] = {
  361. .start = IRQ_NSSP,
  362. .end = IRQ_NSSP,
  363. .flags = IORESOURCE_IRQ,
  364. },
  365. [2] = {
  366. /* DRCMR for RX */
  367. .start = 15,
  368. .end = 15,
  369. .flags = IORESOURCE_DMA,
  370. },
  371. [3] = {
  372. /* DRCMR for TX */
  373. .start = 16,
  374. .end = 16,
  375. .flags = IORESOURCE_DMA,
  376. },
  377. };
  378. struct platform_device pxa25x_device_nssp = {
  379. .name = "pxa25x-nssp",
  380. .id = 1,
  381. .dev = {
  382. .dma_mask = &pxa25x_nssp_dma_mask,
  383. .coherent_dma_mask = DMA_BIT_MASK(32),
  384. },
  385. .resource = pxa25x_resource_nssp,
  386. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  387. };
  388. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  389. static struct resource pxa25x_resource_assp[] = {
  390. [0] = {
  391. .start = 0x41500000,
  392. .end = 0x4150002f,
  393. .flags = IORESOURCE_MEM,
  394. },
  395. [1] = {
  396. .start = IRQ_ASSP,
  397. .end = IRQ_ASSP,
  398. .flags = IORESOURCE_IRQ,
  399. },
  400. [2] = {
  401. /* DRCMR for RX */
  402. .start = 23,
  403. .end = 23,
  404. .flags = IORESOURCE_DMA,
  405. },
  406. [3] = {
  407. /* DRCMR for TX */
  408. .start = 24,
  409. .end = 24,
  410. .flags = IORESOURCE_DMA,
  411. },
  412. };
  413. struct platform_device pxa25x_device_assp = {
  414. /* ASSP is basically equivalent to NSSP */
  415. .name = "pxa25x-nssp",
  416. .id = 2,
  417. .dev = {
  418. .dma_mask = &pxa25x_assp_dma_mask,
  419. .coherent_dma_mask = DMA_BIT_MASK(32),
  420. },
  421. .resource = pxa25x_resource_assp,
  422. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  423. };
  424. #endif /* CONFIG_PXA25x */
  425. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  426. static struct resource pxa27x_resource_keypad[] = {
  427. [0] = {
  428. .start = 0x41500000,
  429. .end = 0x4150004c,
  430. .flags = IORESOURCE_MEM,
  431. },
  432. [1] = {
  433. .start = IRQ_KEYPAD,
  434. .end = IRQ_KEYPAD,
  435. .flags = IORESOURCE_IRQ,
  436. },
  437. };
  438. struct platform_device pxa27x_device_keypad = {
  439. .name = "pxa27x-keypad",
  440. .id = -1,
  441. .resource = pxa27x_resource_keypad,
  442. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  443. };
  444. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  445. {
  446. pxa_register_device(&pxa27x_device_keypad, info);
  447. }
  448. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  449. static struct resource pxa27x_resource_ohci[] = {
  450. [0] = {
  451. .start = 0x4C000000,
  452. .end = 0x4C00ff6f,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. [1] = {
  456. .start = IRQ_USBH1,
  457. .end = IRQ_USBH1,
  458. .flags = IORESOURCE_IRQ,
  459. },
  460. };
  461. struct platform_device pxa27x_device_ohci = {
  462. .name = "pxa27x-ohci",
  463. .id = -1,
  464. .dev = {
  465. .dma_mask = &pxa27x_ohci_dma_mask,
  466. .coherent_dma_mask = DMA_BIT_MASK(32),
  467. },
  468. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  469. .resource = pxa27x_resource_ohci,
  470. };
  471. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  472. {
  473. pxa_register_device(&pxa27x_device_ohci, info);
  474. }
  475. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  476. static struct resource pxa27x_resource_ssp1[] = {
  477. [0] = {
  478. .start = 0x41000000,
  479. .end = 0x4100003f,
  480. .flags = IORESOURCE_MEM,
  481. },
  482. [1] = {
  483. .start = IRQ_SSP,
  484. .end = IRQ_SSP,
  485. .flags = IORESOURCE_IRQ,
  486. },
  487. [2] = {
  488. /* DRCMR for RX */
  489. .start = 13,
  490. .end = 13,
  491. .flags = IORESOURCE_DMA,
  492. },
  493. [3] = {
  494. /* DRCMR for TX */
  495. .start = 14,
  496. .end = 14,
  497. .flags = IORESOURCE_DMA,
  498. },
  499. };
  500. struct platform_device pxa27x_device_ssp1 = {
  501. .name = "pxa27x-ssp",
  502. .id = 0,
  503. .dev = {
  504. .dma_mask = &pxa27x_ssp1_dma_mask,
  505. .coherent_dma_mask = DMA_BIT_MASK(32),
  506. },
  507. .resource = pxa27x_resource_ssp1,
  508. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  509. };
  510. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  511. static struct resource pxa27x_resource_ssp2[] = {
  512. [0] = {
  513. .start = 0x41700000,
  514. .end = 0x4170003f,
  515. .flags = IORESOURCE_MEM,
  516. },
  517. [1] = {
  518. .start = IRQ_SSP2,
  519. .end = IRQ_SSP2,
  520. .flags = IORESOURCE_IRQ,
  521. },
  522. [2] = {
  523. /* DRCMR for RX */
  524. .start = 15,
  525. .end = 15,
  526. .flags = IORESOURCE_DMA,
  527. },
  528. [3] = {
  529. /* DRCMR for TX */
  530. .start = 16,
  531. .end = 16,
  532. .flags = IORESOURCE_DMA,
  533. },
  534. };
  535. struct platform_device pxa27x_device_ssp2 = {
  536. .name = "pxa27x-ssp",
  537. .id = 1,
  538. .dev = {
  539. .dma_mask = &pxa27x_ssp2_dma_mask,
  540. .coherent_dma_mask = DMA_BIT_MASK(32),
  541. },
  542. .resource = pxa27x_resource_ssp2,
  543. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  544. };
  545. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  546. static struct resource pxa27x_resource_ssp3[] = {
  547. [0] = {
  548. .start = 0x41900000,
  549. .end = 0x4190003f,
  550. .flags = IORESOURCE_MEM,
  551. },
  552. [1] = {
  553. .start = IRQ_SSP3,
  554. .end = IRQ_SSP3,
  555. .flags = IORESOURCE_IRQ,
  556. },
  557. [2] = {
  558. /* DRCMR for RX */
  559. .start = 66,
  560. .end = 66,
  561. .flags = IORESOURCE_DMA,
  562. },
  563. [3] = {
  564. /* DRCMR for TX */
  565. .start = 67,
  566. .end = 67,
  567. .flags = IORESOURCE_DMA,
  568. },
  569. };
  570. struct platform_device pxa27x_device_ssp3 = {
  571. .name = "pxa27x-ssp",
  572. .id = 2,
  573. .dev = {
  574. .dma_mask = &pxa27x_ssp3_dma_mask,
  575. .coherent_dma_mask = DMA_BIT_MASK(32),
  576. },
  577. .resource = pxa27x_resource_ssp3,
  578. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  579. };
  580. static struct resource pxa27x_resource_pwm0[] = {
  581. [0] = {
  582. .start = 0x40b00000,
  583. .end = 0x40b0001f,
  584. .flags = IORESOURCE_MEM,
  585. },
  586. };
  587. struct platform_device pxa27x_device_pwm0 = {
  588. .name = "pxa27x-pwm",
  589. .id = 0,
  590. .resource = pxa27x_resource_pwm0,
  591. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  592. };
  593. static struct resource pxa27x_resource_pwm1[] = {
  594. [0] = {
  595. .start = 0x40c00000,
  596. .end = 0x40c0001f,
  597. .flags = IORESOURCE_MEM,
  598. },
  599. };
  600. struct platform_device pxa27x_device_pwm1 = {
  601. .name = "pxa27x-pwm",
  602. .id = 1,
  603. .resource = pxa27x_resource_pwm1,
  604. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  605. };
  606. static struct resource pxa27x_resource_camera[] = {
  607. [0] = {
  608. .start = 0x50000000,
  609. .end = 0x50000fff,
  610. .flags = IORESOURCE_MEM,
  611. },
  612. [1] = {
  613. .start = IRQ_CAMERA,
  614. .end = IRQ_CAMERA,
  615. .flags = IORESOURCE_IRQ,
  616. },
  617. };
  618. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  619. static struct platform_device pxa27x_device_camera = {
  620. .name = "pxa27x-camera",
  621. .id = 0, /* This is used to put cameras on this interface */
  622. .dev = {
  623. .dma_mask = &pxa27x_dma_mask_camera,
  624. .coherent_dma_mask = 0xffffffff,
  625. },
  626. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  627. .resource = pxa27x_resource_camera,
  628. };
  629. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  630. {
  631. pxa_register_device(&pxa27x_device_camera, info);
  632. }
  633. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  634. #ifdef CONFIG_PXA3xx
  635. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  636. static struct resource pxa3xx_resource_ssp4[] = {
  637. [0] = {
  638. .start = 0x41a00000,
  639. .end = 0x41a0003f,
  640. .flags = IORESOURCE_MEM,
  641. },
  642. [1] = {
  643. .start = IRQ_SSP4,
  644. .end = IRQ_SSP4,
  645. .flags = IORESOURCE_IRQ,
  646. },
  647. [2] = {
  648. /* DRCMR for RX */
  649. .start = 2,
  650. .end = 2,
  651. .flags = IORESOURCE_DMA,
  652. },
  653. [3] = {
  654. /* DRCMR for TX */
  655. .start = 3,
  656. .end = 3,
  657. .flags = IORESOURCE_DMA,
  658. },
  659. };
  660. struct platform_device pxa3xx_device_ssp4 = {
  661. /* PXA3xx SSP is basically equivalent to PXA27x */
  662. .name = "pxa27x-ssp",
  663. .id = 3,
  664. .dev = {
  665. .dma_mask = &pxa3xx_ssp4_dma_mask,
  666. .coherent_dma_mask = DMA_BIT_MASK(32),
  667. },
  668. .resource = pxa3xx_resource_ssp4,
  669. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  670. };
  671. static struct resource pxa3xx_resources_mci2[] = {
  672. [0] = {
  673. .start = 0x42000000,
  674. .end = 0x42000fff,
  675. .flags = IORESOURCE_MEM,
  676. },
  677. [1] = {
  678. .start = IRQ_MMC2,
  679. .end = IRQ_MMC2,
  680. .flags = IORESOURCE_IRQ,
  681. },
  682. [2] = {
  683. .start = 93,
  684. .end = 93,
  685. .flags = IORESOURCE_DMA,
  686. },
  687. [3] = {
  688. .start = 94,
  689. .end = 94,
  690. .flags = IORESOURCE_DMA,
  691. },
  692. };
  693. struct platform_device pxa3xx_device_mci2 = {
  694. .name = "pxa2xx-mci",
  695. .id = 1,
  696. .dev = {
  697. .dma_mask = &pxamci_dmamask,
  698. .coherent_dma_mask = 0xffffffff,
  699. },
  700. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  701. .resource = pxa3xx_resources_mci2,
  702. };
  703. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  704. {
  705. pxa_register_device(&pxa3xx_device_mci2, info);
  706. }
  707. static struct resource pxa3xx_resources_mci3[] = {
  708. [0] = {
  709. .start = 0x42500000,
  710. .end = 0x42500fff,
  711. .flags = IORESOURCE_MEM,
  712. },
  713. [1] = {
  714. .start = IRQ_MMC3,
  715. .end = IRQ_MMC3,
  716. .flags = IORESOURCE_IRQ,
  717. },
  718. [2] = {
  719. .start = 100,
  720. .end = 100,
  721. .flags = IORESOURCE_DMA,
  722. },
  723. [3] = {
  724. .start = 101,
  725. .end = 101,
  726. .flags = IORESOURCE_DMA,
  727. },
  728. };
  729. struct platform_device pxa3xx_device_mci3 = {
  730. .name = "pxa2xx-mci",
  731. .id = 2,
  732. .dev = {
  733. .dma_mask = &pxamci_dmamask,
  734. .coherent_dma_mask = 0xffffffff,
  735. },
  736. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  737. .resource = pxa3xx_resources_mci3,
  738. };
  739. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  740. {
  741. pxa_register_device(&pxa3xx_device_mci3, info);
  742. }
  743. static struct resource pxa3xx_resources_nand[] = {
  744. [0] = {
  745. .start = 0x43100000,
  746. .end = 0x43100053,
  747. .flags = IORESOURCE_MEM,
  748. },
  749. [1] = {
  750. .start = IRQ_NAND,
  751. .end = IRQ_NAND,
  752. .flags = IORESOURCE_IRQ,
  753. },
  754. [2] = {
  755. /* DRCMR for Data DMA */
  756. .start = 97,
  757. .end = 97,
  758. .flags = IORESOURCE_DMA,
  759. },
  760. [3] = {
  761. /* DRCMR for Command DMA */
  762. .start = 99,
  763. .end = 99,
  764. .flags = IORESOURCE_DMA,
  765. },
  766. };
  767. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  768. struct platform_device pxa3xx_device_nand = {
  769. .name = "pxa3xx-nand",
  770. .id = -1,
  771. .dev = {
  772. .dma_mask = &pxa3xx_nand_dma_mask,
  773. .coherent_dma_mask = DMA_BIT_MASK(32),
  774. },
  775. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  776. .resource = pxa3xx_resources_nand,
  777. };
  778. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  779. {
  780. pxa_register_device(&pxa3xx_device_nand, info);
  781. }
  782. #endif /* CONFIG_PXA3xx */
  783. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  784. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  785. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  786. {
  787. struct platform_device *pd;
  788. pd = platform_device_alloc("pxa2xx-spi", id);
  789. if (pd == NULL) {
  790. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  791. id);
  792. return;
  793. }
  794. pd->dev.platform_data = info;
  795. platform_device_add(pd);
  796. }