clock.h 2.6 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576
  1. /*
  2. * linux/arch/arm/mach-omap2/clock.h
  3. *
  4. * Copyright (C) 2005-2008 Texas Instruments, Inc.
  5. * Copyright (C) 2004-2008 Nokia Corporation
  6. *
  7. * Contacts:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Paul Walmsley
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  16. #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  17. #include <mach/clock.h>
  18. /* The maximum error between a target DPLL rate and the rounded rate in Hz */
  19. #define DEFAULT_DPLL_RATE_TOLERANCE 50000
  20. int omap2_clk_init(void);
  21. int omap2_clk_enable(struct clk *clk);
  22. void omap2_clk_disable(struct clk *clk);
  23. long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
  24. int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
  25. int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
  26. int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
  27. long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
  28. #ifdef CONFIG_OMAP_RESET_CLOCKS
  29. void omap2_clk_disable_unused(struct clk *clk);
  30. #else
  31. #define omap2_clk_disable_unused NULL
  32. #endif
  33. void omap2_clksel_recalc(struct clk *clk);
  34. void omap2_init_clk_clkdm(struct clk *clk);
  35. void omap2_init_clksel_parent(struct clk *clk);
  36. u32 omap2_clksel_get_divisor(struct clk *clk);
  37. u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
  38. u32 *new_div);
  39. u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
  40. u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
  41. void omap2_fixed_divisor_recalc(struct clk *clk);
  42. long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
  43. int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
  44. u32 omap2_get_dpll_rate(struct clk *clk);
  45. int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
  46. void omap2_clk_prepare_for_reboot(void);
  47. extern u8 cpu_mask;
  48. /* clksel_rate data common to 24xx/343x */
  49. static const struct clksel_rate gpt_32k_rates[] = {
  50. { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
  51. { .div = 0 }
  52. };
  53. static const struct clksel_rate gpt_sys_rates[] = {
  54. { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
  55. { .div = 0 }
  56. };
  57. static const struct clksel_rate gfx_l3_rates[] = {
  58. { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
  59. { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
  60. { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
  61. { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
  62. { .div = 0 }
  63. };
  64. #endif