qeth_core_main.c 135 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include <asm/sysinfo.h>
  25. #include "qeth_core.h"
  26. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  27. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  28. /* N P A M L V H */
  29. [QETH_DBF_SETUP] = {"qeth_setup",
  30. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_MSG] = {"qeth_msg",
  32. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  33. [QETH_DBF_CTRL] = {"qeth_control",
  34. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  35. };
  36. EXPORT_SYMBOL_GPL(qeth_dbf);
  37. struct qeth_card_list_struct qeth_core_card_list;
  38. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  39. struct kmem_cache *qeth_core_header_cache;
  40. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  41. static struct device *qeth_core_root_dev;
  42. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  43. static struct lock_class_key qdio_out_skb_queue_key;
  44. static void qeth_send_control_data_cb(struct qeth_channel *,
  45. struct qeth_cmd_buffer *);
  46. static int qeth_issue_next_read(struct qeth_card *);
  47. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  48. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  49. static void qeth_free_buffer_pool(struct qeth_card *);
  50. static int qeth_qdio_establish(struct qeth_card *);
  51. static inline const char *qeth_get_cardname(struct qeth_card *card)
  52. {
  53. if (card->info.guestlan) {
  54. switch (card->info.type) {
  55. case QETH_CARD_TYPE_OSD:
  56. return " Guest LAN QDIO";
  57. case QETH_CARD_TYPE_IQD:
  58. return " Guest LAN Hiper";
  59. case QETH_CARD_TYPE_OSM:
  60. return " Guest LAN QDIO - OSM";
  61. case QETH_CARD_TYPE_OSX:
  62. return " Guest LAN QDIO - OSX";
  63. default:
  64. return " unknown";
  65. }
  66. } else {
  67. switch (card->info.type) {
  68. case QETH_CARD_TYPE_OSD:
  69. return " OSD Express";
  70. case QETH_CARD_TYPE_IQD:
  71. return " HiperSockets";
  72. case QETH_CARD_TYPE_OSN:
  73. return " OSN QDIO";
  74. case QETH_CARD_TYPE_OSM:
  75. return " OSM QDIO";
  76. case QETH_CARD_TYPE_OSX:
  77. return " OSX QDIO";
  78. default:
  79. return " unknown";
  80. }
  81. }
  82. return " n/a";
  83. }
  84. /* max length to be returned: 14 */
  85. const char *qeth_get_cardname_short(struct qeth_card *card)
  86. {
  87. if (card->info.guestlan) {
  88. switch (card->info.type) {
  89. case QETH_CARD_TYPE_OSD:
  90. return "GuestLAN QDIO";
  91. case QETH_CARD_TYPE_IQD:
  92. return "GuestLAN Hiper";
  93. case QETH_CARD_TYPE_OSM:
  94. return "GuestLAN OSM";
  95. case QETH_CARD_TYPE_OSX:
  96. return "GuestLAN OSX";
  97. default:
  98. return "unknown";
  99. }
  100. } else {
  101. switch (card->info.type) {
  102. case QETH_CARD_TYPE_OSD:
  103. switch (card->info.link_type) {
  104. case QETH_LINK_TYPE_FAST_ETH:
  105. return "OSD_100";
  106. case QETH_LINK_TYPE_HSTR:
  107. return "HSTR";
  108. case QETH_LINK_TYPE_GBIT_ETH:
  109. return "OSD_1000";
  110. case QETH_LINK_TYPE_10GBIT_ETH:
  111. return "OSD_10GIG";
  112. case QETH_LINK_TYPE_LANE_ETH100:
  113. return "OSD_FE_LANE";
  114. case QETH_LINK_TYPE_LANE_TR:
  115. return "OSD_TR_LANE";
  116. case QETH_LINK_TYPE_LANE_ETH1000:
  117. return "OSD_GbE_LANE";
  118. case QETH_LINK_TYPE_LANE:
  119. return "OSD_ATM_LANE";
  120. default:
  121. return "OSD_Express";
  122. }
  123. case QETH_CARD_TYPE_IQD:
  124. return "HiperSockets";
  125. case QETH_CARD_TYPE_OSN:
  126. return "OSN";
  127. case QETH_CARD_TYPE_OSM:
  128. return "OSM_1000";
  129. case QETH_CARD_TYPE_OSX:
  130. return "OSX_10GIG";
  131. default:
  132. return "unknown";
  133. }
  134. }
  135. return "n/a";
  136. }
  137. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  138. int clear_start_mask)
  139. {
  140. unsigned long flags;
  141. spin_lock_irqsave(&card->thread_mask_lock, flags);
  142. card->thread_allowed_mask = threads;
  143. if (clear_start_mask)
  144. card->thread_start_mask &= threads;
  145. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  146. wake_up(&card->wait_q);
  147. }
  148. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  149. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  150. {
  151. unsigned long flags;
  152. int rc = 0;
  153. spin_lock_irqsave(&card->thread_mask_lock, flags);
  154. rc = (card->thread_running_mask & threads);
  155. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  156. return rc;
  157. }
  158. EXPORT_SYMBOL_GPL(qeth_threads_running);
  159. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  160. {
  161. return wait_event_interruptible(card->wait_q,
  162. qeth_threads_running(card, threads) == 0);
  163. }
  164. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  165. void qeth_clear_working_pool_list(struct qeth_card *card)
  166. {
  167. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  168. QETH_CARD_TEXT(card, 5, "clwrklst");
  169. list_for_each_entry_safe(pool_entry, tmp,
  170. &card->qdio.in_buf_pool.entry_list, list){
  171. list_del(&pool_entry->list);
  172. }
  173. }
  174. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  175. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  176. {
  177. struct qeth_buffer_pool_entry *pool_entry;
  178. void *ptr;
  179. int i, j;
  180. QETH_CARD_TEXT(card, 5, "alocpool");
  181. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  182. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  183. if (!pool_entry) {
  184. qeth_free_buffer_pool(card);
  185. return -ENOMEM;
  186. }
  187. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  188. ptr = (void *) __get_free_page(GFP_KERNEL);
  189. if (!ptr) {
  190. while (j > 0)
  191. free_page((unsigned long)
  192. pool_entry->elements[--j]);
  193. kfree(pool_entry);
  194. qeth_free_buffer_pool(card);
  195. return -ENOMEM;
  196. }
  197. pool_entry->elements[j] = ptr;
  198. }
  199. list_add(&pool_entry->init_list,
  200. &card->qdio.init_pool.entry_list);
  201. }
  202. return 0;
  203. }
  204. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  205. {
  206. QETH_CARD_TEXT(card, 2, "realcbp");
  207. if ((card->state != CARD_STATE_DOWN) &&
  208. (card->state != CARD_STATE_RECOVER))
  209. return -EPERM;
  210. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  211. qeth_clear_working_pool_list(card);
  212. qeth_free_buffer_pool(card);
  213. card->qdio.in_buf_pool.buf_count = bufcnt;
  214. card->qdio.init_pool.buf_count = bufcnt;
  215. return qeth_alloc_buffer_pool(card);
  216. }
  217. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  218. static int qeth_issue_next_read(struct qeth_card *card)
  219. {
  220. int rc;
  221. struct qeth_cmd_buffer *iob;
  222. QETH_CARD_TEXT(card, 5, "issnxrd");
  223. if (card->read.state != CH_STATE_UP)
  224. return -EIO;
  225. iob = qeth_get_buffer(&card->read);
  226. if (!iob) {
  227. dev_warn(&card->gdev->dev, "The qeth device driver "
  228. "failed to recover an error on the device\n");
  229. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  230. "available\n", dev_name(&card->gdev->dev));
  231. return -ENOMEM;
  232. }
  233. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  234. QETH_CARD_TEXT(card, 6, "noirqpnd");
  235. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  236. (addr_t) iob, 0, 0);
  237. if (rc) {
  238. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  239. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  240. atomic_set(&card->read.irq_pending, 0);
  241. card->read_or_write_problem = 1;
  242. qeth_schedule_recovery(card);
  243. wake_up(&card->wait_q);
  244. }
  245. return rc;
  246. }
  247. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  248. {
  249. struct qeth_reply *reply;
  250. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  251. if (reply) {
  252. atomic_set(&reply->refcnt, 1);
  253. atomic_set(&reply->received, 0);
  254. reply->card = card;
  255. };
  256. return reply;
  257. }
  258. static void qeth_get_reply(struct qeth_reply *reply)
  259. {
  260. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  261. atomic_inc(&reply->refcnt);
  262. }
  263. static void qeth_put_reply(struct qeth_reply *reply)
  264. {
  265. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  266. if (atomic_dec_and_test(&reply->refcnt))
  267. kfree(reply);
  268. }
  269. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  270. struct qeth_card *card)
  271. {
  272. char *ipa_name;
  273. int com = cmd->hdr.command;
  274. ipa_name = qeth_get_ipa_cmd_name(com);
  275. if (rc)
  276. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  277. "x%X \"%s\"\n",
  278. ipa_name, com, dev_name(&card->gdev->dev),
  279. QETH_CARD_IFNAME(card), rc,
  280. qeth_get_ipa_msg(rc));
  281. else
  282. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  283. ipa_name, com, dev_name(&card->gdev->dev),
  284. QETH_CARD_IFNAME(card));
  285. }
  286. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  287. struct qeth_cmd_buffer *iob)
  288. {
  289. struct qeth_ipa_cmd *cmd = NULL;
  290. QETH_CARD_TEXT(card, 5, "chkipad");
  291. if (IS_IPA(iob->data)) {
  292. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  293. if (IS_IPA_REPLY(cmd)) {
  294. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  295. cmd->hdr.command != IPA_CMD_DELCCID &&
  296. cmd->hdr.command != IPA_CMD_MODCCID &&
  297. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  298. qeth_issue_ipa_msg(cmd,
  299. cmd->hdr.return_code, card);
  300. return cmd;
  301. } else {
  302. switch (cmd->hdr.command) {
  303. case IPA_CMD_STOPLAN:
  304. dev_warn(&card->gdev->dev,
  305. "The link for interface %s on CHPID"
  306. " 0x%X failed\n",
  307. QETH_CARD_IFNAME(card),
  308. card->info.chpid);
  309. card->lan_online = 0;
  310. if (card->dev && netif_carrier_ok(card->dev))
  311. netif_carrier_off(card->dev);
  312. return NULL;
  313. case IPA_CMD_STARTLAN:
  314. dev_info(&card->gdev->dev,
  315. "The link for %s on CHPID 0x%X has"
  316. " been restored\n",
  317. QETH_CARD_IFNAME(card),
  318. card->info.chpid);
  319. netif_carrier_on(card->dev);
  320. card->lan_online = 1;
  321. if (card->info.hwtrap)
  322. card->info.hwtrap = 2;
  323. qeth_schedule_recovery(card);
  324. return NULL;
  325. case IPA_CMD_MODCCID:
  326. return cmd;
  327. case IPA_CMD_REGISTER_LOCAL_ADDR:
  328. QETH_CARD_TEXT(card, 3, "irla");
  329. break;
  330. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  331. QETH_CARD_TEXT(card, 3, "urla");
  332. break;
  333. default:
  334. QETH_DBF_MESSAGE(2, "Received data is IPA "
  335. "but not a reply!\n");
  336. break;
  337. }
  338. }
  339. }
  340. return cmd;
  341. }
  342. void qeth_clear_ipacmd_list(struct qeth_card *card)
  343. {
  344. struct qeth_reply *reply, *r;
  345. unsigned long flags;
  346. QETH_CARD_TEXT(card, 4, "clipalst");
  347. spin_lock_irqsave(&card->lock, flags);
  348. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  349. qeth_get_reply(reply);
  350. reply->rc = -EIO;
  351. atomic_inc(&reply->received);
  352. list_del_init(&reply->list);
  353. wake_up(&reply->wait_q);
  354. qeth_put_reply(reply);
  355. }
  356. spin_unlock_irqrestore(&card->lock, flags);
  357. atomic_set(&card->write.irq_pending, 0);
  358. }
  359. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  360. static int qeth_check_idx_response(struct qeth_card *card,
  361. unsigned char *buffer)
  362. {
  363. if (!buffer)
  364. return 0;
  365. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  366. if ((buffer[2] & 0xc0) == 0xc0) {
  367. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  368. "with cause code 0x%02x%s\n",
  369. buffer[4],
  370. ((buffer[4] == 0x22) ?
  371. " -- try another portname" : ""));
  372. QETH_CARD_TEXT(card, 2, "ckidxres");
  373. QETH_CARD_TEXT(card, 2, " idxterm");
  374. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  375. if (buffer[4] == 0xf6) {
  376. dev_err(&card->gdev->dev,
  377. "The qeth device is not configured "
  378. "for the OSI layer required by z/VM\n");
  379. return -EPERM;
  380. }
  381. return -EIO;
  382. }
  383. return 0;
  384. }
  385. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  386. __u32 len)
  387. {
  388. struct qeth_card *card;
  389. card = CARD_FROM_CDEV(channel->ccwdev);
  390. QETH_CARD_TEXT(card, 4, "setupccw");
  391. if (channel == &card->read)
  392. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  393. else
  394. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  395. channel->ccw.count = len;
  396. channel->ccw.cda = (__u32) __pa(iob);
  397. }
  398. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  399. {
  400. __u8 index;
  401. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  402. index = channel->io_buf_no;
  403. do {
  404. if (channel->iob[index].state == BUF_STATE_FREE) {
  405. channel->iob[index].state = BUF_STATE_LOCKED;
  406. channel->io_buf_no = (channel->io_buf_no + 1) %
  407. QETH_CMD_BUFFER_NO;
  408. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  409. return channel->iob + index;
  410. }
  411. index = (index + 1) % QETH_CMD_BUFFER_NO;
  412. } while (index != channel->io_buf_no);
  413. return NULL;
  414. }
  415. void qeth_release_buffer(struct qeth_channel *channel,
  416. struct qeth_cmd_buffer *iob)
  417. {
  418. unsigned long flags;
  419. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  420. spin_lock_irqsave(&channel->iob_lock, flags);
  421. memset(iob->data, 0, QETH_BUFSIZE);
  422. iob->state = BUF_STATE_FREE;
  423. iob->callback = qeth_send_control_data_cb;
  424. iob->rc = 0;
  425. spin_unlock_irqrestore(&channel->iob_lock, flags);
  426. }
  427. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  428. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  429. {
  430. struct qeth_cmd_buffer *buffer = NULL;
  431. unsigned long flags;
  432. spin_lock_irqsave(&channel->iob_lock, flags);
  433. buffer = __qeth_get_buffer(channel);
  434. spin_unlock_irqrestore(&channel->iob_lock, flags);
  435. return buffer;
  436. }
  437. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  438. {
  439. struct qeth_cmd_buffer *buffer;
  440. wait_event(channel->wait_q,
  441. ((buffer = qeth_get_buffer(channel)) != NULL));
  442. return buffer;
  443. }
  444. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  445. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  446. {
  447. int cnt;
  448. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  449. qeth_release_buffer(channel, &channel->iob[cnt]);
  450. channel->buf_no = 0;
  451. channel->io_buf_no = 0;
  452. }
  453. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  454. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  455. struct qeth_cmd_buffer *iob)
  456. {
  457. struct qeth_card *card;
  458. struct qeth_reply *reply, *r;
  459. struct qeth_ipa_cmd *cmd;
  460. unsigned long flags;
  461. int keep_reply;
  462. int rc = 0;
  463. card = CARD_FROM_CDEV(channel->ccwdev);
  464. QETH_CARD_TEXT(card, 4, "sndctlcb");
  465. rc = qeth_check_idx_response(card, iob->data);
  466. switch (rc) {
  467. case 0:
  468. break;
  469. case -EIO:
  470. qeth_clear_ipacmd_list(card);
  471. qeth_schedule_recovery(card);
  472. /* fall through */
  473. default:
  474. goto out;
  475. }
  476. cmd = qeth_check_ipa_data(card, iob);
  477. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  478. goto out;
  479. /*in case of OSN : check if cmd is set */
  480. if (card->info.type == QETH_CARD_TYPE_OSN &&
  481. cmd &&
  482. cmd->hdr.command != IPA_CMD_STARTLAN &&
  483. card->osn_info.assist_cb != NULL) {
  484. card->osn_info.assist_cb(card->dev, cmd);
  485. goto out;
  486. }
  487. spin_lock_irqsave(&card->lock, flags);
  488. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  489. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  490. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  491. qeth_get_reply(reply);
  492. list_del_init(&reply->list);
  493. spin_unlock_irqrestore(&card->lock, flags);
  494. keep_reply = 0;
  495. if (reply->callback != NULL) {
  496. if (cmd) {
  497. reply->offset = (__u16)((char *)cmd -
  498. (char *)iob->data);
  499. keep_reply = reply->callback(card,
  500. reply,
  501. (unsigned long)cmd);
  502. } else
  503. keep_reply = reply->callback(card,
  504. reply,
  505. (unsigned long)iob);
  506. }
  507. if (cmd)
  508. reply->rc = (u16) cmd->hdr.return_code;
  509. else if (iob->rc)
  510. reply->rc = iob->rc;
  511. if (keep_reply) {
  512. spin_lock_irqsave(&card->lock, flags);
  513. list_add_tail(&reply->list,
  514. &card->cmd_waiter_list);
  515. spin_unlock_irqrestore(&card->lock, flags);
  516. } else {
  517. atomic_inc(&reply->received);
  518. wake_up(&reply->wait_q);
  519. }
  520. qeth_put_reply(reply);
  521. goto out;
  522. }
  523. }
  524. spin_unlock_irqrestore(&card->lock, flags);
  525. out:
  526. memcpy(&card->seqno.pdu_hdr_ack,
  527. QETH_PDU_HEADER_SEQ_NO(iob->data),
  528. QETH_SEQ_NO_LENGTH);
  529. qeth_release_buffer(channel, iob);
  530. }
  531. static int qeth_setup_channel(struct qeth_channel *channel)
  532. {
  533. int cnt;
  534. QETH_DBF_TEXT(SETUP, 2, "setupch");
  535. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  536. channel->iob[cnt].data =
  537. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  538. if (channel->iob[cnt].data == NULL)
  539. break;
  540. channel->iob[cnt].state = BUF_STATE_FREE;
  541. channel->iob[cnt].channel = channel;
  542. channel->iob[cnt].callback = qeth_send_control_data_cb;
  543. channel->iob[cnt].rc = 0;
  544. }
  545. if (cnt < QETH_CMD_BUFFER_NO) {
  546. while (cnt-- > 0)
  547. kfree(channel->iob[cnt].data);
  548. return -ENOMEM;
  549. }
  550. channel->buf_no = 0;
  551. channel->io_buf_no = 0;
  552. atomic_set(&channel->irq_pending, 0);
  553. spin_lock_init(&channel->iob_lock);
  554. init_waitqueue_head(&channel->wait_q);
  555. return 0;
  556. }
  557. static int qeth_set_thread_start_bit(struct qeth_card *card,
  558. unsigned long thread)
  559. {
  560. unsigned long flags;
  561. spin_lock_irqsave(&card->thread_mask_lock, flags);
  562. if (!(card->thread_allowed_mask & thread) ||
  563. (card->thread_start_mask & thread)) {
  564. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  565. return -EPERM;
  566. }
  567. card->thread_start_mask |= thread;
  568. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  569. return 0;
  570. }
  571. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  572. {
  573. unsigned long flags;
  574. spin_lock_irqsave(&card->thread_mask_lock, flags);
  575. card->thread_start_mask &= ~thread;
  576. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  577. wake_up(&card->wait_q);
  578. }
  579. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  580. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  581. {
  582. unsigned long flags;
  583. spin_lock_irqsave(&card->thread_mask_lock, flags);
  584. card->thread_running_mask &= ~thread;
  585. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  586. wake_up(&card->wait_q);
  587. }
  588. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  589. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  590. {
  591. unsigned long flags;
  592. int rc = 0;
  593. spin_lock_irqsave(&card->thread_mask_lock, flags);
  594. if (card->thread_start_mask & thread) {
  595. if ((card->thread_allowed_mask & thread) &&
  596. !(card->thread_running_mask & thread)) {
  597. rc = 1;
  598. card->thread_start_mask &= ~thread;
  599. card->thread_running_mask |= thread;
  600. } else
  601. rc = -EPERM;
  602. }
  603. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  604. return rc;
  605. }
  606. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  607. {
  608. int rc = 0;
  609. wait_event(card->wait_q,
  610. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  611. return rc;
  612. }
  613. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  614. void qeth_schedule_recovery(struct qeth_card *card)
  615. {
  616. QETH_CARD_TEXT(card, 2, "startrec");
  617. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  618. schedule_work(&card->kernel_thread_starter);
  619. }
  620. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  621. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  622. {
  623. int dstat, cstat;
  624. char *sense;
  625. struct qeth_card *card;
  626. sense = (char *) irb->ecw;
  627. cstat = irb->scsw.cmd.cstat;
  628. dstat = irb->scsw.cmd.dstat;
  629. card = CARD_FROM_CDEV(cdev);
  630. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  631. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  632. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  633. QETH_CARD_TEXT(card, 2, "CGENCHK");
  634. dev_warn(&cdev->dev, "The qeth device driver "
  635. "failed to recover an error on the device\n");
  636. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  637. dev_name(&cdev->dev), dstat, cstat);
  638. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  639. 16, 1, irb, 64, 1);
  640. return 1;
  641. }
  642. if (dstat & DEV_STAT_UNIT_CHECK) {
  643. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  644. SENSE_RESETTING_EVENT_FLAG) {
  645. QETH_CARD_TEXT(card, 2, "REVIND");
  646. return 1;
  647. }
  648. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  649. SENSE_COMMAND_REJECT_FLAG) {
  650. QETH_CARD_TEXT(card, 2, "CMDREJi");
  651. return 1;
  652. }
  653. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  654. QETH_CARD_TEXT(card, 2, "AFFE");
  655. return 1;
  656. }
  657. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  658. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  659. return 0;
  660. }
  661. QETH_CARD_TEXT(card, 2, "DGENCHK");
  662. return 1;
  663. }
  664. return 0;
  665. }
  666. static long __qeth_check_irb_error(struct ccw_device *cdev,
  667. unsigned long intparm, struct irb *irb)
  668. {
  669. struct qeth_card *card;
  670. card = CARD_FROM_CDEV(cdev);
  671. if (!IS_ERR(irb))
  672. return 0;
  673. switch (PTR_ERR(irb)) {
  674. case -EIO:
  675. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  676. dev_name(&cdev->dev));
  677. QETH_CARD_TEXT(card, 2, "ckirberr");
  678. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  679. break;
  680. case -ETIMEDOUT:
  681. dev_warn(&cdev->dev, "A hardware operation timed out"
  682. " on the device\n");
  683. QETH_CARD_TEXT(card, 2, "ckirberr");
  684. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  685. if (intparm == QETH_RCD_PARM) {
  686. if (card && (card->data.ccwdev == cdev)) {
  687. card->data.state = CH_STATE_DOWN;
  688. wake_up(&card->wait_q);
  689. }
  690. }
  691. break;
  692. default:
  693. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  694. dev_name(&cdev->dev), PTR_ERR(irb));
  695. QETH_CARD_TEXT(card, 2, "ckirberr");
  696. QETH_CARD_TEXT(card, 2, " rc???");
  697. }
  698. return PTR_ERR(irb);
  699. }
  700. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  701. struct irb *irb)
  702. {
  703. int rc;
  704. int cstat, dstat;
  705. struct qeth_cmd_buffer *buffer;
  706. struct qeth_channel *channel;
  707. struct qeth_card *card;
  708. struct qeth_cmd_buffer *iob;
  709. __u8 index;
  710. if (__qeth_check_irb_error(cdev, intparm, irb))
  711. return;
  712. cstat = irb->scsw.cmd.cstat;
  713. dstat = irb->scsw.cmd.dstat;
  714. card = CARD_FROM_CDEV(cdev);
  715. if (!card)
  716. return;
  717. QETH_CARD_TEXT(card, 5, "irq");
  718. if (card->read.ccwdev == cdev) {
  719. channel = &card->read;
  720. QETH_CARD_TEXT(card, 5, "read");
  721. } else if (card->write.ccwdev == cdev) {
  722. channel = &card->write;
  723. QETH_CARD_TEXT(card, 5, "write");
  724. } else {
  725. channel = &card->data;
  726. QETH_CARD_TEXT(card, 5, "data");
  727. }
  728. atomic_set(&channel->irq_pending, 0);
  729. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  730. channel->state = CH_STATE_STOPPED;
  731. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  732. channel->state = CH_STATE_HALTED;
  733. /*let's wake up immediately on data channel*/
  734. if ((channel == &card->data) && (intparm != 0) &&
  735. (intparm != QETH_RCD_PARM))
  736. goto out;
  737. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  738. QETH_CARD_TEXT(card, 6, "clrchpar");
  739. /* we don't have to handle this further */
  740. intparm = 0;
  741. }
  742. if (intparm == QETH_HALT_CHANNEL_PARM) {
  743. QETH_CARD_TEXT(card, 6, "hltchpar");
  744. /* we don't have to handle this further */
  745. intparm = 0;
  746. }
  747. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  748. (dstat & DEV_STAT_UNIT_CHECK) ||
  749. (cstat)) {
  750. if (irb->esw.esw0.erw.cons) {
  751. dev_warn(&channel->ccwdev->dev,
  752. "The qeth device driver failed to recover "
  753. "an error on the device\n");
  754. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  755. "0x%X dstat 0x%X\n",
  756. dev_name(&channel->ccwdev->dev), cstat, dstat);
  757. print_hex_dump(KERN_WARNING, "qeth: irb ",
  758. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  759. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  760. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  761. }
  762. if (intparm == QETH_RCD_PARM) {
  763. channel->state = CH_STATE_DOWN;
  764. goto out;
  765. }
  766. rc = qeth_get_problem(cdev, irb);
  767. if (rc) {
  768. qeth_clear_ipacmd_list(card);
  769. qeth_schedule_recovery(card);
  770. goto out;
  771. }
  772. }
  773. if (intparm == QETH_RCD_PARM) {
  774. channel->state = CH_STATE_RCD_DONE;
  775. goto out;
  776. }
  777. if (intparm) {
  778. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  779. buffer->state = BUF_STATE_PROCESSED;
  780. }
  781. if (channel == &card->data)
  782. return;
  783. if (channel == &card->read &&
  784. channel->state == CH_STATE_UP)
  785. qeth_issue_next_read(card);
  786. iob = channel->iob;
  787. index = channel->buf_no;
  788. while (iob[index].state == BUF_STATE_PROCESSED) {
  789. if (iob[index].callback != NULL)
  790. iob[index].callback(channel, iob + index);
  791. index = (index + 1) % QETH_CMD_BUFFER_NO;
  792. }
  793. channel->buf_no = index;
  794. out:
  795. wake_up(&card->wait_q);
  796. return;
  797. }
  798. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  799. struct qeth_qdio_out_buffer *buf)
  800. {
  801. int i;
  802. struct sk_buff *skb;
  803. /* is PCI flag set on buffer? */
  804. if (buf->buffer->element[0].flags & 0x40)
  805. atomic_dec(&queue->set_pci_flags_count);
  806. skb = skb_dequeue(&buf->skb_list);
  807. while (skb) {
  808. atomic_dec(&skb->users);
  809. dev_kfree_skb_any(skb);
  810. skb = skb_dequeue(&buf->skb_list);
  811. }
  812. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  813. if (buf->buffer->element[i].addr && buf->is_header[i])
  814. kmem_cache_free(qeth_core_header_cache,
  815. buf->buffer->element[i].addr);
  816. buf->is_header[i] = 0;
  817. buf->buffer->element[i].length = 0;
  818. buf->buffer->element[i].addr = NULL;
  819. buf->buffer->element[i].flags = 0;
  820. }
  821. buf->buffer->element[15].flags = 0;
  822. buf->next_element_to_fill = 0;
  823. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  824. }
  825. void qeth_clear_qdio_buffers(struct qeth_card *card)
  826. {
  827. int i, j;
  828. QETH_CARD_TEXT(card, 2, "clearqdbf");
  829. /* clear outbound buffers to free skbs */
  830. for (i = 0; i < card->qdio.no_out_queues; ++i)
  831. if (card->qdio.out_qs[i]) {
  832. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  833. qeth_clear_output_buffer(card->qdio.out_qs[i],
  834. &card->qdio.out_qs[i]->bufs[j]);
  835. }
  836. }
  837. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  838. static void qeth_free_buffer_pool(struct qeth_card *card)
  839. {
  840. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  841. int i = 0;
  842. list_for_each_entry_safe(pool_entry, tmp,
  843. &card->qdio.init_pool.entry_list, init_list){
  844. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  845. free_page((unsigned long)pool_entry->elements[i]);
  846. list_del(&pool_entry->init_list);
  847. kfree(pool_entry);
  848. }
  849. }
  850. static void qeth_free_qdio_buffers(struct qeth_card *card)
  851. {
  852. int i, j;
  853. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  854. QETH_QDIO_UNINITIALIZED)
  855. return;
  856. kfree(card->qdio.in_q);
  857. card->qdio.in_q = NULL;
  858. /* inbound buffer pool */
  859. qeth_free_buffer_pool(card);
  860. /* free outbound qdio_qs */
  861. if (card->qdio.out_qs) {
  862. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  863. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  864. qeth_clear_output_buffer(card->qdio.out_qs[i],
  865. &card->qdio.out_qs[i]->bufs[j]);
  866. kfree(card->qdio.out_qs[i]);
  867. }
  868. kfree(card->qdio.out_qs);
  869. card->qdio.out_qs = NULL;
  870. }
  871. }
  872. static void qeth_clean_channel(struct qeth_channel *channel)
  873. {
  874. int cnt;
  875. QETH_DBF_TEXT(SETUP, 2, "freech");
  876. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  877. kfree(channel->iob[cnt].data);
  878. }
  879. static void qeth_get_channel_path_desc(struct qeth_card *card)
  880. {
  881. struct ccw_device *ccwdev;
  882. struct channelPath_dsc {
  883. u8 flags;
  884. u8 lsn;
  885. u8 desc;
  886. u8 chpid;
  887. u8 swla;
  888. u8 zeroes;
  889. u8 chla;
  890. u8 chpp;
  891. } *chp_dsc;
  892. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  893. ccwdev = card->data.ccwdev;
  894. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  895. if (chp_dsc != NULL) {
  896. /* CHPP field bit 6 == 1 -> single queue */
  897. if ((chp_dsc->chpp & 0x02) == 0x02) {
  898. if ((atomic_read(&card->qdio.state) !=
  899. QETH_QDIO_UNINITIALIZED) &&
  900. (card->qdio.no_out_queues == 4))
  901. /* change from 4 to 1 outbound queues */
  902. qeth_free_qdio_buffers(card);
  903. card->qdio.no_out_queues = 1;
  904. if (card->qdio.default_out_queue != 0)
  905. dev_info(&card->gdev->dev,
  906. "Priority Queueing not supported\n");
  907. card->qdio.default_out_queue = 0;
  908. } else {
  909. if ((atomic_read(&card->qdio.state) !=
  910. QETH_QDIO_UNINITIALIZED) &&
  911. (card->qdio.no_out_queues == 1)) {
  912. /* change from 1 to 4 outbound queues */
  913. qeth_free_qdio_buffers(card);
  914. card->qdio.default_out_queue = 2;
  915. }
  916. card->qdio.no_out_queues = 4;
  917. }
  918. card->info.func_level = 0x4100 + chp_dsc->desc;
  919. kfree(chp_dsc);
  920. }
  921. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  922. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  923. return;
  924. }
  925. static void qeth_init_qdio_info(struct qeth_card *card)
  926. {
  927. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  928. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  929. /* inbound */
  930. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  931. if (card->info.type == QETH_CARD_TYPE_IQD)
  932. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  933. else
  934. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  935. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  936. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  937. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  938. }
  939. static void qeth_set_intial_options(struct qeth_card *card)
  940. {
  941. card->options.route4.type = NO_ROUTER;
  942. card->options.route6.type = NO_ROUTER;
  943. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  944. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  945. card->options.fake_broadcast = 0;
  946. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  947. card->options.performance_stats = 0;
  948. card->options.rx_sg_cb = QETH_RX_SG_CB;
  949. card->options.isolation = ISOLATION_MODE_NONE;
  950. }
  951. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  952. {
  953. unsigned long flags;
  954. int rc = 0;
  955. spin_lock_irqsave(&card->thread_mask_lock, flags);
  956. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  957. (u8) card->thread_start_mask,
  958. (u8) card->thread_allowed_mask,
  959. (u8) card->thread_running_mask);
  960. rc = (card->thread_start_mask & thread);
  961. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  962. return rc;
  963. }
  964. static void qeth_start_kernel_thread(struct work_struct *work)
  965. {
  966. struct qeth_card *card = container_of(work, struct qeth_card,
  967. kernel_thread_starter);
  968. QETH_CARD_TEXT(card , 2, "strthrd");
  969. if (card->read.state != CH_STATE_UP &&
  970. card->write.state != CH_STATE_UP)
  971. return;
  972. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  973. kthread_run(card->discipline.recover, (void *) card,
  974. "qeth_recover");
  975. }
  976. static int qeth_setup_card(struct qeth_card *card)
  977. {
  978. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  979. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  980. card->read.state = CH_STATE_DOWN;
  981. card->write.state = CH_STATE_DOWN;
  982. card->data.state = CH_STATE_DOWN;
  983. card->state = CARD_STATE_DOWN;
  984. card->lan_online = 0;
  985. card->read_or_write_problem = 0;
  986. card->dev = NULL;
  987. spin_lock_init(&card->vlanlock);
  988. spin_lock_init(&card->mclock);
  989. card->vlangrp = NULL;
  990. spin_lock_init(&card->lock);
  991. spin_lock_init(&card->ip_lock);
  992. spin_lock_init(&card->thread_mask_lock);
  993. mutex_init(&card->conf_mutex);
  994. mutex_init(&card->discipline_mutex);
  995. card->thread_start_mask = 0;
  996. card->thread_allowed_mask = 0;
  997. card->thread_running_mask = 0;
  998. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  999. INIT_LIST_HEAD(&card->ip_list);
  1000. INIT_LIST_HEAD(card->ip_tbd_list);
  1001. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1002. init_waitqueue_head(&card->wait_q);
  1003. /* initial options */
  1004. qeth_set_intial_options(card);
  1005. /* IP address takeover */
  1006. INIT_LIST_HEAD(&card->ipato.entries);
  1007. card->ipato.enabled = 0;
  1008. card->ipato.invert4 = 0;
  1009. card->ipato.invert6 = 0;
  1010. /* init QDIO stuff */
  1011. qeth_init_qdio_info(card);
  1012. return 0;
  1013. }
  1014. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1015. {
  1016. struct qeth_card *card = container_of(slr, struct qeth_card,
  1017. qeth_service_level);
  1018. if (card->info.mcl_level[0])
  1019. seq_printf(m, "qeth: %s firmware level %s\n",
  1020. CARD_BUS_ID(card), card->info.mcl_level);
  1021. }
  1022. static struct qeth_card *qeth_alloc_card(void)
  1023. {
  1024. struct qeth_card *card;
  1025. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1026. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1027. if (!card)
  1028. goto out;
  1029. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1030. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1031. if (!card->ip_tbd_list) {
  1032. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1033. goto out_card;
  1034. }
  1035. if (qeth_setup_channel(&card->read))
  1036. goto out_ip;
  1037. if (qeth_setup_channel(&card->write))
  1038. goto out_channel;
  1039. card->options.layer2 = -1;
  1040. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1041. register_service_level(&card->qeth_service_level);
  1042. return card;
  1043. out_channel:
  1044. qeth_clean_channel(&card->read);
  1045. out_ip:
  1046. kfree(card->ip_tbd_list);
  1047. out_card:
  1048. kfree(card);
  1049. out:
  1050. return NULL;
  1051. }
  1052. static int qeth_determine_card_type(struct qeth_card *card)
  1053. {
  1054. int i = 0;
  1055. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1056. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1057. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1058. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1059. if ((CARD_RDEV(card)->id.dev_type ==
  1060. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1061. (CARD_RDEV(card)->id.dev_model ==
  1062. known_devices[i][QETH_DEV_MODEL_IND])) {
  1063. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1064. card->qdio.no_out_queues =
  1065. known_devices[i][QETH_QUEUE_NO_IND];
  1066. card->info.is_multicast_different =
  1067. known_devices[i][QETH_MULTICAST_IND];
  1068. qeth_get_channel_path_desc(card);
  1069. return 0;
  1070. }
  1071. i++;
  1072. }
  1073. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1074. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1075. "unknown type\n");
  1076. return -ENOENT;
  1077. }
  1078. static int qeth_clear_channel(struct qeth_channel *channel)
  1079. {
  1080. unsigned long flags;
  1081. struct qeth_card *card;
  1082. int rc;
  1083. card = CARD_FROM_CDEV(channel->ccwdev);
  1084. QETH_CARD_TEXT(card, 3, "clearch");
  1085. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1086. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1087. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1088. if (rc)
  1089. return rc;
  1090. rc = wait_event_interruptible_timeout(card->wait_q,
  1091. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1092. if (rc == -ERESTARTSYS)
  1093. return rc;
  1094. if (channel->state != CH_STATE_STOPPED)
  1095. return -ETIME;
  1096. channel->state = CH_STATE_DOWN;
  1097. return 0;
  1098. }
  1099. static int qeth_halt_channel(struct qeth_channel *channel)
  1100. {
  1101. unsigned long flags;
  1102. struct qeth_card *card;
  1103. int rc;
  1104. card = CARD_FROM_CDEV(channel->ccwdev);
  1105. QETH_CARD_TEXT(card, 3, "haltch");
  1106. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1107. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1108. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1109. if (rc)
  1110. return rc;
  1111. rc = wait_event_interruptible_timeout(card->wait_q,
  1112. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1113. if (rc == -ERESTARTSYS)
  1114. return rc;
  1115. if (channel->state != CH_STATE_HALTED)
  1116. return -ETIME;
  1117. return 0;
  1118. }
  1119. static int qeth_halt_channels(struct qeth_card *card)
  1120. {
  1121. int rc1 = 0, rc2 = 0, rc3 = 0;
  1122. QETH_CARD_TEXT(card, 3, "haltchs");
  1123. rc1 = qeth_halt_channel(&card->read);
  1124. rc2 = qeth_halt_channel(&card->write);
  1125. rc3 = qeth_halt_channel(&card->data);
  1126. if (rc1)
  1127. return rc1;
  1128. if (rc2)
  1129. return rc2;
  1130. return rc3;
  1131. }
  1132. static int qeth_clear_channels(struct qeth_card *card)
  1133. {
  1134. int rc1 = 0, rc2 = 0, rc3 = 0;
  1135. QETH_CARD_TEXT(card, 3, "clearchs");
  1136. rc1 = qeth_clear_channel(&card->read);
  1137. rc2 = qeth_clear_channel(&card->write);
  1138. rc3 = qeth_clear_channel(&card->data);
  1139. if (rc1)
  1140. return rc1;
  1141. if (rc2)
  1142. return rc2;
  1143. return rc3;
  1144. }
  1145. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1146. {
  1147. int rc = 0;
  1148. QETH_CARD_TEXT(card, 3, "clhacrd");
  1149. if (halt)
  1150. rc = qeth_halt_channels(card);
  1151. if (rc)
  1152. return rc;
  1153. return qeth_clear_channels(card);
  1154. }
  1155. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1156. {
  1157. int rc = 0;
  1158. QETH_CARD_TEXT(card, 3, "qdioclr");
  1159. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1160. QETH_QDIO_CLEANING)) {
  1161. case QETH_QDIO_ESTABLISHED:
  1162. if (card->info.type == QETH_CARD_TYPE_IQD)
  1163. rc = qdio_shutdown(CARD_DDEV(card),
  1164. QDIO_FLAG_CLEANUP_USING_HALT);
  1165. else
  1166. rc = qdio_shutdown(CARD_DDEV(card),
  1167. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1168. if (rc)
  1169. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1170. qdio_free(CARD_DDEV(card));
  1171. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1172. break;
  1173. case QETH_QDIO_CLEANING:
  1174. return rc;
  1175. default:
  1176. break;
  1177. }
  1178. rc = qeth_clear_halt_card(card, use_halt);
  1179. if (rc)
  1180. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1181. card->state = CARD_STATE_DOWN;
  1182. return rc;
  1183. }
  1184. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1185. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1186. int *length)
  1187. {
  1188. struct ciw *ciw;
  1189. char *rcd_buf;
  1190. int ret;
  1191. struct qeth_channel *channel = &card->data;
  1192. unsigned long flags;
  1193. /*
  1194. * scan for RCD command in extended SenseID data
  1195. */
  1196. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1197. if (!ciw || ciw->cmd == 0)
  1198. return -EOPNOTSUPP;
  1199. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1200. if (!rcd_buf)
  1201. return -ENOMEM;
  1202. channel->ccw.cmd_code = ciw->cmd;
  1203. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1204. channel->ccw.count = ciw->count;
  1205. channel->ccw.flags = CCW_FLAG_SLI;
  1206. channel->state = CH_STATE_RCD;
  1207. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1208. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1209. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1210. QETH_RCD_TIMEOUT);
  1211. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1212. if (!ret)
  1213. wait_event(card->wait_q,
  1214. (channel->state == CH_STATE_RCD_DONE ||
  1215. channel->state == CH_STATE_DOWN));
  1216. if (channel->state == CH_STATE_DOWN)
  1217. ret = -EIO;
  1218. else
  1219. channel->state = CH_STATE_DOWN;
  1220. if (ret) {
  1221. kfree(rcd_buf);
  1222. *buffer = NULL;
  1223. *length = 0;
  1224. } else {
  1225. *length = ciw->count;
  1226. *buffer = rcd_buf;
  1227. }
  1228. return ret;
  1229. }
  1230. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1231. {
  1232. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1233. card->info.chpid = prcd[30];
  1234. card->info.unit_addr2 = prcd[31];
  1235. card->info.cula = prcd[63];
  1236. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1237. (prcd[0x11] == _ascebc['M']));
  1238. }
  1239. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1240. {
  1241. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1242. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1243. card->info.blkt.time_total = 250;
  1244. card->info.blkt.inter_packet = 5;
  1245. card->info.blkt.inter_packet_jumbo = 15;
  1246. } else {
  1247. card->info.blkt.time_total = 0;
  1248. card->info.blkt.inter_packet = 0;
  1249. card->info.blkt.inter_packet_jumbo = 0;
  1250. }
  1251. }
  1252. static void qeth_init_tokens(struct qeth_card *card)
  1253. {
  1254. card->token.issuer_rm_w = 0x00010103UL;
  1255. card->token.cm_filter_w = 0x00010108UL;
  1256. card->token.cm_connection_w = 0x0001010aUL;
  1257. card->token.ulp_filter_w = 0x0001010bUL;
  1258. card->token.ulp_connection_w = 0x0001010dUL;
  1259. }
  1260. static void qeth_init_func_level(struct qeth_card *card)
  1261. {
  1262. switch (card->info.type) {
  1263. case QETH_CARD_TYPE_IQD:
  1264. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1265. break;
  1266. case QETH_CARD_TYPE_OSD:
  1267. case QETH_CARD_TYPE_OSN:
  1268. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1269. break;
  1270. default:
  1271. break;
  1272. }
  1273. }
  1274. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1275. void (*idx_reply_cb)(struct qeth_channel *,
  1276. struct qeth_cmd_buffer *))
  1277. {
  1278. struct qeth_cmd_buffer *iob;
  1279. unsigned long flags;
  1280. int rc;
  1281. struct qeth_card *card;
  1282. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1283. card = CARD_FROM_CDEV(channel->ccwdev);
  1284. iob = qeth_get_buffer(channel);
  1285. iob->callback = idx_reply_cb;
  1286. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1287. channel->ccw.count = QETH_BUFSIZE;
  1288. channel->ccw.cda = (__u32) __pa(iob->data);
  1289. wait_event(card->wait_q,
  1290. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1291. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1292. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1293. rc = ccw_device_start(channel->ccwdev,
  1294. &channel->ccw, (addr_t) iob, 0, 0);
  1295. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1296. if (rc) {
  1297. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1298. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1299. atomic_set(&channel->irq_pending, 0);
  1300. wake_up(&card->wait_q);
  1301. return rc;
  1302. }
  1303. rc = wait_event_interruptible_timeout(card->wait_q,
  1304. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1305. if (rc == -ERESTARTSYS)
  1306. return rc;
  1307. if (channel->state != CH_STATE_UP) {
  1308. rc = -ETIME;
  1309. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1310. qeth_clear_cmd_buffers(channel);
  1311. } else
  1312. rc = 0;
  1313. return rc;
  1314. }
  1315. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1316. void (*idx_reply_cb)(struct qeth_channel *,
  1317. struct qeth_cmd_buffer *))
  1318. {
  1319. struct qeth_card *card;
  1320. struct qeth_cmd_buffer *iob;
  1321. unsigned long flags;
  1322. __u16 temp;
  1323. __u8 tmp;
  1324. int rc;
  1325. struct ccw_dev_id temp_devid;
  1326. card = CARD_FROM_CDEV(channel->ccwdev);
  1327. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1328. iob = qeth_get_buffer(channel);
  1329. iob->callback = idx_reply_cb;
  1330. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1331. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1332. channel->ccw.cda = (__u32) __pa(iob->data);
  1333. if (channel == &card->write) {
  1334. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1335. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1336. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1337. card->seqno.trans_hdr++;
  1338. } else {
  1339. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1340. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1341. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1342. }
  1343. tmp = ((__u8)card->info.portno) | 0x80;
  1344. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1345. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1346. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1347. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1348. &card->info.func_level, sizeof(__u16));
  1349. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1350. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1351. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1352. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1353. wait_event(card->wait_q,
  1354. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1355. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1356. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1357. rc = ccw_device_start(channel->ccwdev,
  1358. &channel->ccw, (addr_t) iob, 0, 0);
  1359. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1360. if (rc) {
  1361. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1362. rc);
  1363. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1364. atomic_set(&channel->irq_pending, 0);
  1365. wake_up(&card->wait_q);
  1366. return rc;
  1367. }
  1368. rc = wait_event_interruptible_timeout(card->wait_q,
  1369. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1370. if (rc == -ERESTARTSYS)
  1371. return rc;
  1372. if (channel->state != CH_STATE_ACTIVATING) {
  1373. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1374. " failed to recover an error on the device\n");
  1375. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1376. dev_name(&channel->ccwdev->dev));
  1377. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1378. qeth_clear_cmd_buffers(channel);
  1379. return -ETIME;
  1380. }
  1381. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1382. }
  1383. static int qeth_peer_func_level(int level)
  1384. {
  1385. if ((level & 0xff) == 8)
  1386. return (level & 0xff) + 0x400;
  1387. if (((level >> 8) & 3) == 1)
  1388. return (level & 0xff) + 0x200;
  1389. return level;
  1390. }
  1391. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1392. struct qeth_cmd_buffer *iob)
  1393. {
  1394. struct qeth_card *card;
  1395. __u16 temp;
  1396. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1397. if (channel->state == CH_STATE_DOWN) {
  1398. channel->state = CH_STATE_ACTIVATING;
  1399. goto out;
  1400. }
  1401. card = CARD_FROM_CDEV(channel->ccwdev);
  1402. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1403. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1404. dev_err(&card->write.ccwdev->dev,
  1405. "The adapter is used exclusively by another "
  1406. "host\n");
  1407. else
  1408. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1409. " negative reply\n",
  1410. dev_name(&card->write.ccwdev->dev));
  1411. goto out;
  1412. }
  1413. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1414. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1415. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1416. "function level mismatch (sent: 0x%x, received: "
  1417. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1418. card->info.func_level, temp);
  1419. goto out;
  1420. }
  1421. channel->state = CH_STATE_UP;
  1422. out:
  1423. qeth_release_buffer(channel, iob);
  1424. }
  1425. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1426. struct qeth_cmd_buffer *iob)
  1427. {
  1428. struct qeth_card *card;
  1429. __u16 temp;
  1430. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1431. if (channel->state == CH_STATE_DOWN) {
  1432. channel->state = CH_STATE_ACTIVATING;
  1433. goto out;
  1434. }
  1435. card = CARD_FROM_CDEV(channel->ccwdev);
  1436. if (qeth_check_idx_response(card, iob->data))
  1437. goto out;
  1438. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1439. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1440. case QETH_IDX_ACT_ERR_EXCL:
  1441. dev_err(&card->write.ccwdev->dev,
  1442. "The adapter is used exclusively by another "
  1443. "host\n");
  1444. break;
  1445. case QETH_IDX_ACT_ERR_AUTH:
  1446. case QETH_IDX_ACT_ERR_AUTH_USER:
  1447. dev_err(&card->read.ccwdev->dev,
  1448. "Setting the device online failed because of "
  1449. "insufficient authorization\n");
  1450. break;
  1451. default:
  1452. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1453. " negative reply\n",
  1454. dev_name(&card->read.ccwdev->dev));
  1455. }
  1456. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1457. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1458. goto out;
  1459. }
  1460. /**
  1461. * * temporary fix for microcode bug
  1462. * * to revert it,replace OR by AND
  1463. * */
  1464. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1465. (card->info.type == QETH_CARD_TYPE_OSD))
  1466. card->info.portname_required = 1;
  1467. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1468. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1469. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1470. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1471. dev_name(&card->read.ccwdev->dev),
  1472. card->info.func_level, temp);
  1473. goto out;
  1474. }
  1475. memcpy(&card->token.issuer_rm_r,
  1476. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1477. QETH_MPC_TOKEN_LENGTH);
  1478. memcpy(&card->info.mcl_level[0],
  1479. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1480. channel->state = CH_STATE_UP;
  1481. out:
  1482. qeth_release_buffer(channel, iob);
  1483. }
  1484. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1485. struct qeth_cmd_buffer *iob)
  1486. {
  1487. qeth_setup_ccw(&card->write, iob->data, len);
  1488. iob->callback = qeth_release_buffer;
  1489. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1490. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1491. card->seqno.trans_hdr++;
  1492. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1493. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1494. card->seqno.pdu_hdr++;
  1495. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1496. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1497. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1498. }
  1499. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1500. int qeth_send_control_data(struct qeth_card *card, int len,
  1501. struct qeth_cmd_buffer *iob,
  1502. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1503. unsigned long),
  1504. void *reply_param)
  1505. {
  1506. int rc;
  1507. unsigned long flags;
  1508. struct qeth_reply *reply = NULL;
  1509. unsigned long timeout, event_timeout;
  1510. struct qeth_ipa_cmd *cmd;
  1511. QETH_CARD_TEXT(card, 2, "sendctl");
  1512. if (card->read_or_write_problem) {
  1513. qeth_release_buffer(iob->channel, iob);
  1514. return -EIO;
  1515. }
  1516. reply = qeth_alloc_reply(card);
  1517. if (!reply) {
  1518. return -ENOMEM;
  1519. }
  1520. reply->callback = reply_cb;
  1521. reply->param = reply_param;
  1522. if (card->state == CARD_STATE_DOWN)
  1523. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1524. else
  1525. reply->seqno = card->seqno.ipa++;
  1526. init_waitqueue_head(&reply->wait_q);
  1527. spin_lock_irqsave(&card->lock, flags);
  1528. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1529. spin_unlock_irqrestore(&card->lock, flags);
  1530. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1531. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1532. qeth_prepare_control_data(card, len, iob);
  1533. if (IS_IPA(iob->data))
  1534. event_timeout = QETH_IPA_TIMEOUT;
  1535. else
  1536. event_timeout = QETH_TIMEOUT;
  1537. timeout = jiffies + event_timeout;
  1538. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1539. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1540. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1541. (addr_t) iob, 0, 0);
  1542. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1543. if (rc) {
  1544. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1545. "ccw_device_start rc = %i\n",
  1546. dev_name(&card->write.ccwdev->dev), rc);
  1547. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1548. spin_lock_irqsave(&card->lock, flags);
  1549. list_del_init(&reply->list);
  1550. qeth_put_reply(reply);
  1551. spin_unlock_irqrestore(&card->lock, flags);
  1552. qeth_release_buffer(iob->channel, iob);
  1553. atomic_set(&card->write.irq_pending, 0);
  1554. wake_up(&card->wait_q);
  1555. return rc;
  1556. }
  1557. /* we have only one long running ipassist, since we can ensure
  1558. process context of this command we can sleep */
  1559. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1560. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1561. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1562. if (!wait_event_timeout(reply->wait_q,
  1563. atomic_read(&reply->received), event_timeout))
  1564. goto time_err;
  1565. } else {
  1566. while (!atomic_read(&reply->received)) {
  1567. if (time_after(jiffies, timeout))
  1568. goto time_err;
  1569. cpu_relax();
  1570. };
  1571. }
  1572. if (reply->rc == -EIO)
  1573. goto error;
  1574. rc = reply->rc;
  1575. qeth_put_reply(reply);
  1576. return rc;
  1577. time_err:
  1578. reply->rc = -ETIME;
  1579. spin_lock_irqsave(&reply->card->lock, flags);
  1580. list_del_init(&reply->list);
  1581. spin_unlock_irqrestore(&reply->card->lock, flags);
  1582. atomic_inc(&reply->received);
  1583. error:
  1584. atomic_set(&card->write.irq_pending, 0);
  1585. qeth_release_buffer(iob->channel, iob);
  1586. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1587. rc = reply->rc;
  1588. qeth_put_reply(reply);
  1589. return rc;
  1590. }
  1591. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1592. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1593. unsigned long data)
  1594. {
  1595. struct qeth_cmd_buffer *iob;
  1596. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1597. iob = (struct qeth_cmd_buffer *) data;
  1598. memcpy(&card->token.cm_filter_r,
  1599. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1600. QETH_MPC_TOKEN_LENGTH);
  1601. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1602. return 0;
  1603. }
  1604. static int qeth_cm_enable(struct qeth_card *card)
  1605. {
  1606. int rc;
  1607. struct qeth_cmd_buffer *iob;
  1608. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1609. iob = qeth_wait_for_buffer(&card->write);
  1610. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1611. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1612. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1613. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1614. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1615. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1616. qeth_cm_enable_cb, NULL);
  1617. return rc;
  1618. }
  1619. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1620. unsigned long data)
  1621. {
  1622. struct qeth_cmd_buffer *iob;
  1623. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1624. iob = (struct qeth_cmd_buffer *) data;
  1625. memcpy(&card->token.cm_connection_r,
  1626. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1627. QETH_MPC_TOKEN_LENGTH);
  1628. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1629. return 0;
  1630. }
  1631. static int qeth_cm_setup(struct qeth_card *card)
  1632. {
  1633. int rc;
  1634. struct qeth_cmd_buffer *iob;
  1635. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1636. iob = qeth_wait_for_buffer(&card->write);
  1637. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1638. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1639. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1640. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1641. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1642. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1643. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1644. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1645. qeth_cm_setup_cb, NULL);
  1646. return rc;
  1647. }
  1648. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1649. {
  1650. switch (card->info.type) {
  1651. case QETH_CARD_TYPE_UNKNOWN:
  1652. return 1500;
  1653. case QETH_CARD_TYPE_IQD:
  1654. return card->info.max_mtu;
  1655. case QETH_CARD_TYPE_OSD:
  1656. switch (card->info.link_type) {
  1657. case QETH_LINK_TYPE_HSTR:
  1658. case QETH_LINK_TYPE_LANE_TR:
  1659. return 2000;
  1660. default:
  1661. return 1492;
  1662. }
  1663. case QETH_CARD_TYPE_OSM:
  1664. case QETH_CARD_TYPE_OSX:
  1665. return 1492;
  1666. default:
  1667. return 1500;
  1668. }
  1669. }
  1670. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1671. {
  1672. switch (framesize) {
  1673. case 0x4000:
  1674. return 8192;
  1675. case 0x6000:
  1676. return 16384;
  1677. case 0xa000:
  1678. return 32768;
  1679. case 0xffff:
  1680. return 57344;
  1681. default:
  1682. return 0;
  1683. }
  1684. }
  1685. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1686. {
  1687. switch (card->info.type) {
  1688. case QETH_CARD_TYPE_OSD:
  1689. case QETH_CARD_TYPE_OSM:
  1690. case QETH_CARD_TYPE_OSX:
  1691. case QETH_CARD_TYPE_IQD:
  1692. return ((mtu >= 576) &&
  1693. (mtu <= card->info.max_mtu));
  1694. case QETH_CARD_TYPE_OSN:
  1695. case QETH_CARD_TYPE_UNKNOWN:
  1696. default:
  1697. return 1;
  1698. }
  1699. }
  1700. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1701. unsigned long data)
  1702. {
  1703. __u16 mtu, framesize;
  1704. __u16 len;
  1705. __u8 link_type;
  1706. struct qeth_cmd_buffer *iob;
  1707. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1708. iob = (struct qeth_cmd_buffer *) data;
  1709. memcpy(&card->token.ulp_filter_r,
  1710. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1711. QETH_MPC_TOKEN_LENGTH);
  1712. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1713. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1714. mtu = qeth_get_mtu_outof_framesize(framesize);
  1715. if (!mtu) {
  1716. iob->rc = -EINVAL;
  1717. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1718. return 0;
  1719. }
  1720. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1721. /* frame size has changed */
  1722. if (card->dev &&
  1723. ((card->dev->mtu == card->info.initial_mtu) ||
  1724. (card->dev->mtu > mtu)))
  1725. card->dev->mtu = mtu;
  1726. qeth_free_qdio_buffers(card);
  1727. }
  1728. card->info.initial_mtu = mtu;
  1729. card->info.max_mtu = mtu;
  1730. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1731. } else {
  1732. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1733. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1734. iob->data);
  1735. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1736. }
  1737. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1738. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1739. memcpy(&link_type,
  1740. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1741. card->info.link_type = link_type;
  1742. } else
  1743. card->info.link_type = 0;
  1744. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1745. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1746. return 0;
  1747. }
  1748. static int qeth_ulp_enable(struct qeth_card *card)
  1749. {
  1750. int rc;
  1751. char prot_type;
  1752. struct qeth_cmd_buffer *iob;
  1753. /*FIXME: trace view callbacks*/
  1754. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1755. iob = qeth_wait_for_buffer(&card->write);
  1756. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1757. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1758. (__u8) card->info.portno;
  1759. if (card->options.layer2)
  1760. if (card->info.type == QETH_CARD_TYPE_OSN)
  1761. prot_type = QETH_PROT_OSN2;
  1762. else
  1763. prot_type = QETH_PROT_LAYER2;
  1764. else
  1765. prot_type = QETH_PROT_TCPIP;
  1766. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1767. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1768. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1769. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1770. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1771. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1772. card->info.portname, 9);
  1773. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1774. qeth_ulp_enable_cb, NULL);
  1775. return rc;
  1776. }
  1777. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1778. unsigned long data)
  1779. {
  1780. struct qeth_cmd_buffer *iob;
  1781. int rc = 0;
  1782. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1783. iob = (struct qeth_cmd_buffer *) data;
  1784. memcpy(&card->token.ulp_connection_r,
  1785. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1786. QETH_MPC_TOKEN_LENGTH);
  1787. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1788. 3)) {
  1789. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1790. dev_err(&card->gdev->dev, "A connection could not be "
  1791. "established because of an OLM limit\n");
  1792. iob->rc = -EMLINK;
  1793. }
  1794. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1795. return rc;
  1796. }
  1797. static int qeth_ulp_setup(struct qeth_card *card)
  1798. {
  1799. int rc;
  1800. __u16 temp;
  1801. struct qeth_cmd_buffer *iob;
  1802. struct ccw_dev_id dev_id;
  1803. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1804. iob = qeth_wait_for_buffer(&card->write);
  1805. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1806. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1807. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1808. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1809. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1810. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1811. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1812. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1813. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1814. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1815. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1816. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1817. qeth_ulp_setup_cb, NULL);
  1818. return rc;
  1819. }
  1820. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1821. {
  1822. int i, j;
  1823. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1824. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1825. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1826. return 0;
  1827. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1828. GFP_KERNEL);
  1829. if (!card->qdio.in_q)
  1830. goto out_nomem;
  1831. QETH_DBF_TEXT(SETUP, 2, "inq");
  1832. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1833. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1834. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1835. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1836. card->qdio.in_q->bufs[i].buffer =
  1837. &card->qdio.in_q->qdio_bufs[i];
  1838. /* inbound buffer pool */
  1839. if (qeth_alloc_buffer_pool(card))
  1840. goto out_freeinq;
  1841. /* outbound */
  1842. card->qdio.out_qs =
  1843. kmalloc(card->qdio.no_out_queues *
  1844. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1845. if (!card->qdio.out_qs)
  1846. goto out_freepool;
  1847. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1848. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1849. GFP_KERNEL);
  1850. if (!card->qdio.out_qs[i])
  1851. goto out_freeoutq;
  1852. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1853. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1854. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1855. card->qdio.out_qs[i]->queue_no = i;
  1856. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1857. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1858. card->qdio.out_qs[i]->bufs[j].buffer =
  1859. &card->qdio.out_qs[i]->qdio_bufs[j];
  1860. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1861. skb_list);
  1862. lockdep_set_class(
  1863. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1864. &qdio_out_skb_queue_key);
  1865. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1866. }
  1867. }
  1868. return 0;
  1869. out_freeoutq:
  1870. while (i > 0)
  1871. kfree(card->qdio.out_qs[--i]);
  1872. kfree(card->qdio.out_qs);
  1873. card->qdio.out_qs = NULL;
  1874. out_freepool:
  1875. qeth_free_buffer_pool(card);
  1876. out_freeinq:
  1877. kfree(card->qdio.in_q);
  1878. card->qdio.in_q = NULL;
  1879. out_nomem:
  1880. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1881. return -ENOMEM;
  1882. }
  1883. static void qeth_create_qib_param_field(struct qeth_card *card,
  1884. char *param_field)
  1885. {
  1886. param_field[0] = _ascebc['P'];
  1887. param_field[1] = _ascebc['C'];
  1888. param_field[2] = _ascebc['I'];
  1889. param_field[3] = _ascebc['T'];
  1890. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1891. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1892. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1893. }
  1894. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1895. char *param_field)
  1896. {
  1897. param_field[16] = _ascebc['B'];
  1898. param_field[17] = _ascebc['L'];
  1899. param_field[18] = _ascebc['K'];
  1900. param_field[19] = _ascebc['T'];
  1901. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1902. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1903. *((unsigned int *) (&param_field[28])) =
  1904. card->info.blkt.inter_packet_jumbo;
  1905. }
  1906. static int qeth_qdio_activate(struct qeth_card *card)
  1907. {
  1908. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1909. return qdio_activate(CARD_DDEV(card));
  1910. }
  1911. static int qeth_dm_act(struct qeth_card *card)
  1912. {
  1913. int rc;
  1914. struct qeth_cmd_buffer *iob;
  1915. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1916. iob = qeth_wait_for_buffer(&card->write);
  1917. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1918. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1919. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1920. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1921. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1922. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1923. return rc;
  1924. }
  1925. static int qeth_mpc_initialize(struct qeth_card *card)
  1926. {
  1927. int rc;
  1928. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1929. rc = qeth_issue_next_read(card);
  1930. if (rc) {
  1931. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1932. return rc;
  1933. }
  1934. rc = qeth_cm_enable(card);
  1935. if (rc) {
  1936. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1937. goto out_qdio;
  1938. }
  1939. rc = qeth_cm_setup(card);
  1940. if (rc) {
  1941. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1942. goto out_qdio;
  1943. }
  1944. rc = qeth_ulp_enable(card);
  1945. if (rc) {
  1946. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1947. goto out_qdio;
  1948. }
  1949. rc = qeth_ulp_setup(card);
  1950. if (rc) {
  1951. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1952. goto out_qdio;
  1953. }
  1954. rc = qeth_alloc_qdio_buffers(card);
  1955. if (rc) {
  1956. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1957. goto out_qdio;
  1958. }
  1959. rc = qeth_qdio_establish(card);
  1960. if (rc) {
  1961. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1962. qeth_free_qdio_buffers(card);
  1963. goto out_qdio;
  1964. }
  1965. rc = qeth_qdio_activate(card);
  1966. if (rc) {
  1967. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1968. goto out_qdio;
  1969. }
  1970. rc = qeth_dm_act(card);
  1971. if (rc) {
  1972. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1973. goto out_qdio;
  1974. }
  1975. return 0;
  1976. out_qdio:
  1977. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1978. return rc;
  1979. }
  1980. static void qeth_print_status_with_portname(struct qeth_card *card)
  1981. {
  1982. char dbf_text[15];
  1983. int i;
  1984. sprintf(dbf_text, "%s", card->info.portname + 1);
  1985. for (i = 0; i < 8; i++)
  1986. dbf_text[i] =
  1987. (char) _ebcasc[(__u8) dbf_text[i]];
  1988. dbf_text[8] = 0;
  1989. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1990. "with link type %s (portname: %s)\n",
  1991. qeth_get_cardname(card),
  1992. (card->info.mcl_level[0]) ? " (level: " : "",
  1993. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1994. (card->info.mcl_level[0]) ? ")" : "",
  1995. qeth_get_cardname_short(card),
  1996. dbf_text);
  1997. }
  1998. static void qeth_print_status_no_portname(struct qeth_card *card)
  1999. {
  2000. if (card->info.portname[0])
  2001. dev_info(&card->gdev->dev, "Device is a%s "
  2002. "card%s%s%s\nwith link type %s "
  2003. "(no portname needed by interface).\n",
  2004. qeth_get_cardname(card),
  2005. (card->info.mcl_level[0]) ? " (level: " : "",
  2006. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2007. (card->info.mcl_level[0]) ? ")" : "",
  2008. qeth_get_cardname_short(card));
  2009. else
  2010. dev_info(&card->gdev->dev, "Device is a%s "
  2011. "card%s%s%s\nwith link type %s.\n",
  2012. qeth_get_cardname(card),
  2013. (card->info.mcl_level[0]) ? " (level: " : "",
  2014. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2015. (card->info.mcl_level[0]) ? ")" : "",
  2016. qeth_get_cardname_short(card));
  2017. }
  2018. void qeth_print_status_message(struct qeth_card *card)
  2019. {
  2020. switch (card->info.type) {
  2021. case QETH_CARD_TYPE_OSD:
  2022. case QETH_CARD_TYPE_OSM:
  2023. case QETH_CARD_TYPE_OSX:
  2024. /* VM will use a non-zero first character
  2025. * to indicate a HiperSockets like reporting
  2026. * of the level OSA sets the first character to zero
  2027. * */
  2028. if (!card->info.mcl_level[0]) {
  2029. sprintf(card->info.mcl_level, "%02x%02x",
  2030. card->info.mcl_level[2],
  2031. card->info.mcl_level[3]);
  2032. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2033. break;
  2034. }
  2035. /* fallthrough */
  2036. case QETH_CARD_TYPE_IQD:
  2037. if ((card->info.guestlan) ||
  2038. (card->info.mcl_level[0] & 0x80)) {
  2039. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2040. card->info.mcl_level[0]];
  2041. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2042. card->info.mcl_level[1]];
  2043. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2044. card->info.mcl_level[2]];
  2045. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2046. card->info.mcl_level[3]];
  2047. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2048. }
  2049. break;
  2050. default:
  2051. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2052. }
  2053. if (card->info.portname_required)
  2054. qeth_print_status_with_portname(card);
  2055. else
  2056. qeth_print_status_no_portname(card);
  2057. }
  2058. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2059. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2060. {
  2061. struct qeth_buffer_pool_entry *entry;
  2062. QETH_CARD_TEXT(card, 5, "inwrklst");
  2063. list_for_each_entry(entry,
  2064. &card->qdio.init_pool.entry_list, init_list) {
  2065. qeth_put_buffer_pool_entry(card, entry);
  2066. }
  2067. }
  2068. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2069. struct qeth_card *card)
  2070. {
  2071. struct list_head *plh;
  2072. struct qeth_buffer_pool_entry *entry;
  2073. int i, free;
  2074. struct page *page;
  2075. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2076. return NULL;
  2077. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2078. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2079. free = 1;
  2080. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2081. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2082. free = 0;
  2083. break;
  2084. }
  2085. }
  2086. if (free) {
  2087. list_del_init(&entry->list);
  2088. return entry;
  2089. }
  2090. }
  2091. /* no free buffer in pool so take first one and swap pages */
  2092. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2093. struct qeth_buffer_pool_entry, list);
  2094. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2095. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2096. page = alloc_page(GFP_ATOMIC);
  2097. if (!page) {
  2098. return NULL;
  2099. } else {
  2100. free_page((unsigned long)entry->elements[i]);
  2101. entry->elements[i] = page_address(page);
  2102. if (card->options.performance_stats)
  2103. card->perf_stats.sg_alloc_page_rx++;
  2104. }
  2105. }
  2106. }
  2107. list_del_init(&entry->list);
  2108. return entry;
  2109. }
  2110. static int qeth_init_input_buffer(struct qeth_card *card,
  2111. struct qeth_qdio_buffer *buf)
  2112. {
  2113. struct qeth_buffer_pool_entry *pool_entry;
  2114. int i;
  2115. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2116. if (!pool_entry)
  2117. return 1;
  2118. /*
  2119. * since the buffer is accessed only from the input_tasklet
  2120. * there shouldn't be a need to synchronize; also, since we use
  2121. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2122. * buffers
  2123. */
  2124. buf->pool_entry = pool_entry;
  2125. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2126. buf->buffer->element[i].length = PAGE_SIZE;
  2127. buf->buffer->element[i].addr = pool_entry->elements[i];
  2128. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2129. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2130. else
  2131. buf->buffer->element[i].flags = 0;
  2132. }
  2133. return 0;
  2134. }
  2135. int qeth_init_qdio_queues(struct qeth_card *card)
  2136. {
  2137. int i, j;
  2138. int rc;
  2139. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2140. /* inbound queue */
  2141. memset(card->qdio.in_q->qdio_bufs, 0,
  2142. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2143. qeth_initialize_working_pool_list(card);
  2144. /*give only as many buffers to hardware as we have buffer pool entries*/
  2145. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2146. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2147. card->qdio.in_q->next_buf_to_init =
  2148. card->qdio.in_buf_pool.buf_count - 1;
  2149. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2150. card->qdio.in_buf_pool.buf_count - 1);
  2151. if (rc) {
  2152. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2153. return rc;
  2154. }
  2155. /* outbound queue */
  2156. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2157. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2158. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2159. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2160. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2161. &card->qdio.out_qs[i]->bufs[j]);
  2162. }
  2163. card->qdio.out_qs[i]->card = card;
  2164. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2165. card->qdio.out_qs[i]->do_pack = 0;
  2166. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2167. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2168. atomic_set(&card->qdio.out_qs[i]->state,
  2169. QETH_OUT_Q_UNLOCKED);
  2170. }
  2171. return 0;
  2172. }
  2173. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2174. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2175. {
  2176. switch (link_type) {
  2177. case QETH_LINK_TYPE_HSTR:
  2178. return 2;
  2179. default:
  2180. return 1;
  2181. }
  2182. }
  2183. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2184. struct qeth_ipa_cmd *cmd, __u8 command,
  2185. enum qeth_prot_versions prot)
  2186. {
  2187. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2188. cmd->hdr.command = command;
  2189. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2190. cmd->hdr.seqno = card->seqno.ipa;
  2191. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2192. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2193. if (card->options.layer2)
  2194. cmd->hdr.prim_version_no = 2;
  2195. else
  2196. cmd->hdr.prim_version_no = 1;
  2197. cmd->hdr.param_count = 1;
  2198. cmd->hdr.prot_version = prot;
  2199. cmd->hdr.ipa_supported = 0;
  2200. cmd->hdr.ipa_enabled = 0;
  2201. }
  2202. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2203. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2204. {
  2205. struct qeth_cmd_buffer *iob;
  2206. struct qeth_ipa_cmd *cmd;
  2207. iob = qeth_wait_for_buffer(&card->write);
  2208. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2209. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2210. return iob;
  2211. }
  2212. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2213. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2214. char prot_type)
  2215. {
  2216. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2217. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2218. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2219. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2220. }
  2221. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2222. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2223. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2224. unsigned long),
  2225. void *reply_param)
  2226. {
  2227. int rc;
  2228. char prot_type;
  2229. QETH_CARD_TEXT(card, 4, "sendipa");
  2230. if (card->options.layer2)
  2231. if (card->info.type == QETH_CARD_TYPE_OSN)
  2232. prot_type = QETH_PROT_OSN2;
  2233. else
  2234. prot_type = QETH_PROT_LAYER2;
  2235. else
  2236. prot_type = QETH_PROT_TCPIP;
  2237. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2238. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2239. iob, reply_cb, reply_param);
  2240. if (rc == -ETIME) {
  2241. qeth_clear_ipacmd_list(card);
  2242. qeth_schedule_recovery(card);
  2243. }
  2244. return rc;
  2245. }
  2246. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2247. int qeth_send_startlan(struct qeth_card *card)
  2248. {
  2249. int rc;
  2250. struct qeth_cmd_buffer *iob;
  2251. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2252. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2253. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2254. return rc;
  2255. }
  2256. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2257. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2258. struct qeth_reply *reply, unsigned long data)
  2259. {
  2260. struct qeth_ipa_cmd *cmd;
  2261. QETH_CARD_TEXT(card, 4, "defadpcb");
  2262. cmd = (struct qeth_ipa_cmd *) data;
  2263. if (cmd->hdr.return_code == 0)
  2264. cmd->hdr.return_code =
  2265. cmd->data.setadapterparms.hdr.return_code;
  2266. return 0;
  2267. }
  2268. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2269. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2270. struct qeth_reply *reply, unsigned long data)
  2271. {
  2272. struct qeth_ipa_cmd *cmd;
  2273. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2274. cmd = (struct qeth_ipa_cmd *) data;
  2275. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2276. card->info.link_type =
  2277. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2278. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2279. }
  2280. card->options.adp.supported_funcs =
  2281. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2282. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2283. }
  2284. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2285. __u32 command, __u32 cmdlen)
  2286. {
  2287. struct qeth_cmd_buffer *iob;
  2288. struct qeth_ipa_cmd *cmd;
  2289. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2290. QETH_PROT_IPV4);
  2291. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2292. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2293. cmd->data.setadapterparms.hdr.command_code = command;
  2294. cmd->data.setadapterparms.hdr.used_total = 1;
  2295. cmd->data.setadapterparms.hdr.seq_no = 1;
  2296. return iob;
  2297. }
  2298. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2299. int qeth_query_setadapterparms(struct qeth_card *card)
  2300. {
  2301. int rc;
  2302. struct qeth_cmd_buffer *iob;
  2303. QETH_CARD_TEXT(card, 3, "queryadp");
  2304. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2305. sizeof(struct qeth_ipacmd_setadpparms));
  2306. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2307. return rc;
  2308. }
  2309. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2310. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2311. struct qeth_reply *reply, unsigned long data)
  2312. {
  2313. struct qeth_ipa_cmd *cmd;
  2314. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2315. cmd = (struct qeth_ipa_cmd *) data;
  2316. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2317. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2318. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2319. } else {
  2320. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2321. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2322. }
  2323. QETH_DBF_TEXT(SETUP, 2, "suppenbl");
  2324. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_supported);
  2325. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_enabled);
  2326. return 0;
  2327. }
  2328. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2329. {
  2330. int rc;
  2331. struct qeth_cmd_buffer *iob;
  2332. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2333. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2334. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2335. return rc;
  2336. }
  2337. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2338. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2339. struct qeth_reply *reply, unsigned long data)
  2340. {
  2341. struct qeth_ipa_cmd *cmd;
  2342. __u16 rc;
  2343. cmd = (struct qeth_ipa_cmd *)data;
  2344. rc = cmd->hdr.return_code;
  2345. if (rc)
  2346. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2347. else
  2348. card->info.diagass_support = cmd->data.diagass.ext;
  2349. return 0;
  2350. }
  2351. static int qeth_query_setdiagass(struct qeth_card *card)
  2352. {
  2353. struct qeth_cmd_buffer *iob;
  2354. struct qeth_ipa_cmd *cmd;
  2355. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2356. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2357. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2358. cmd->data.diagass.subcmd_len = 16;
  2359. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2360. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2361. }
  2362. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2363. {
  2364. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2365. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2366. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2367. struct ccw_dev_id ccwid;
  2368. int level, rc;
  2369. tid->chpid = card->info.chpid;
  2370. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2371. tid->ssid = ccwid.ssid;
  2372. tid->devno = ccwid.devno;
  2373. if (!info)
  2374. return;
  2375. rc = stsi(NULL, 0, 0, 0);
  2376. if (rc == -ENOSYS)
  2377. level = rc;
  2378. else
  2379. level = (((unsigned int) rc) >> 28);
  2380. if ((level >= 2) && (stsi(info222, 2, 2, 2) != -ENOSYS))
  2381. tid->lparnr = info222->lpar_number;
  2382. if ((level >= 3) && (stsi(info322, 3, 2, 2) != -ENOSYS)) {
  2383. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2384. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2385. }
  2386. free_page(info);
  2387. return;
  2388. }
  2389. static int qeth_hw_trap_cb(struct qeth_card *card,
  2390. struct qeth_reply *reply, unsigned long data)
  2391. {
  2392. struct qeth_ipa_cmd *cmd;
  2393. __u16 rc;
  2394. cmd = (struct qeth_ipa_cmd *)data;
  2395. rc = cmd->hdr.return_code;
  2396. if (rc)
  2397. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2398. return 0;
  2399. }
  2400. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2401. {
  2402. struct qeth_cmd_buffer *iob;
  2403. struct qeth_ipa_cmd *cmd;
  2404. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2405. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2406. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2407. cmd->data.diagass.subcmd_len = 80;
  2408. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2409. cmd->data.diagass.type = 1;
  2410. cmd->data.diagass.action = action;
  2411. switch (action) {
  2412. case QETH_DIAGS_TRAP_ARM:
  2413. cmd->data.diagass.options = 0x0003;
  2414. cmd->data.diagass.ext = 0x00010000 +
  2415. sizeof(struct qeth_trap_id);
  2416. qeth_get_trap_id(card,
  2417. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2418. break;
  2419. case QETH_DIAGS_TRAP_DISARM:
  2420. cmd->data.diagass.options = 0x0001;
  2421. break;
  2422. case QETH_DIAGS_TRAP_CAPTURE:
  2423. break;
  2424. }
  2425. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2426. }
  2427. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2428. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2429. unsigned int qdio_error, const char *dbftext)
  2430. {
  2431. if (qdio_error) {
  2432. QETH_CARD_TEXT(card, 2, dbftext);
  2433. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2434. buf->element[15].flags & 0xff);
  2435. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2436. buf->element[14].flags & 0xff);
  2437. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2438. if ((buf->element[15].flags & 0xff) == 0x12) {
  2439. card->stats.rx_dropped++;
  2440. return 0;
  2441. } else
  2442. return 1;
  2443. }
  2444. return 0;
  2445. }
  2446. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2447. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2448. {
  2449. struct qeth_qdio_q *queue = card->qdio.in_q;
  2450. int count;
  2451. int i;
  2452. int rc;
  2453. int newcount = 0;
  2454. count = (index < queue->next_buf_to_init)?
  2455. card->qdio.in_buf_pool.buf_count -
  2456. (queue->next_buf_to_init - index) :
  2457. card->qdio.in_buf_pool.buf_count -
  2458. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2459. /* only requeue at a certain threshold to avoid SIGAs */
  2460. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2461. for (i = queue->next_buf_to_init;
  2462. i < queue->next_buf_to_init + count; ++i) {
  2463. if (qeth_init_input_buffer(card,
  2464. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2465. break;
  2466. } else {
  2467. newcount++;
  2468. }
  2469. }
  2470. if (newcount < count) {
  2471. /* we are in memory shortage so we switch back to
  2472. traditional skb allocation and drop packages */
  2473. atomic_set(&card->force_alloc_skb, 3);
  2474. count = newcount;
  2475. } else {
  2476. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2477. }
  2478. /*
  2479. * according to old code it should be avoided to requeue all
  2480. * 128 buffers in order to benefit from PCI avoidance.
  2481. * this function keeps at least one buffer (the buffer at
  2482. * 'index') un-requeued -> this buffer is the first buffer that
  2483. * will be requeued the next time
  2484. */
  2485. if (card->options.performance_stats) {
  2486. card->perf_stats.inbound_do_qdio_cnt++;
  2487. card->perf_stats.inbound_do_qdio_start_time =
  2488. qeth_get_micros();
  2489. }
  2490. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2491. queue->next_buf_to_init, count);
  2492. if (card->options.performance_stats)
  2493. card->perf_stats.inbound_do_qdio_time +=
  2494. qeth_get_micros() -
  2495. card->perf_stats.inbound_do_qdio_start_time;
  2496. if (rc) {
  2497. dev_warn(&card->gdev->dev,
  2498. "QDIO reported an error, rc=%i\n", rc);
  2499. QETH_CARD_TEXT(card, 2, "qinberr");
  2500. }
  2501. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2502. QDIO_MAX_BUFFERS_PER_Q;
  2503. }
  2504. }
  2505. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2506. static int qeth_handle_send_error(struct qeth_card *card,
  2507. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2508. {
  2509. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2510. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2511. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2512. if (sbalf15 == 0) {
  2513. qdio_err = 0;
  2514. } else {
  2515. qdio_err = 1;
  2516. }
  2517. }
  2518. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2519. if (!qdio_err)
  2520. return QETH_SEND_ERROR_NONE;
  2521. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2522. return QETH_SEND_ERROR_RETRY;
  2523. QETH_CARD_TEXT(card, 1, "lnkfail");
  2524. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2525. (u16)qdio_err, (u8)sbalf15);
  2526. return QETH_SEND_ERROR_LINK_FAILURE;
  2527. }
  2528. /*
  2529. * Switched to packing state if the number of used buffers on a queue
  2530. * reaches a certain limit.
  2531. */
  2532. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2533. {
  2534. if (!queue->do_pack) {
  2535. if (atomic_read(&queue->used_buffers)
  2536. >= QETH_HIGH_WATERMARK_PACK){
  2537. /* switch non-PACKING -> PACKING */
  2538. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2539. if (queue->card->options.performance_stats)
  2540. queue->card->perf_stats.sc_dp_p++;
  2541. queue->do_pack = 1;
  2542. }
  2543. }
  2544. }
  2545. /*
  2546. * Switches from packing to non-packing mode. If there is a packing
  2547. * buffer on the queue this buffer will be prepared to be flushed.
  2548. * In that case 1 is returned to inform the caller. If no buffer
  2549. * has to be flushed, zero is returned.
  2550. */
  2551. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2552. {
  2553. struct qeth_qdio_out_buffer *buffer;
  2554. int flush_count = 0;
  2555. if (queue->do_pack) {
  2556. if (atomic_read(&queue->used_buffers)
  2557. <= QETH_LOW_WATERMARK_PACK) {
  2558. /* switch PACKING -> non-PACKING */
  2559. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2560. if (queue->card->options.performance_stats)
  2561. queue->card->perf_stats.sc_p_dp++;
  2562. queue->do_pack = 0;
  2563. /* flush packing buffers */
  2564. buffer = &queue->bufs[queue->next_buf_to_fill];
  2565. if ((atomic_read(&buffer->state) ==
  2566. QETH_QDIO_BUF_EMPTY) &&
  2567. (buffer->next_element_to_fill > 0)) {
  2568. atomic_set(&buffer->state,
  2569. QETH_QDIO_BUF_PRIMED);
  2570. flush_count++;
  2571. queue->next_buf_to_fill =
  2572. (queue->next_buf_to_fill + 1) %
  2573. QDIO_MAX_BUFFERS_PER_Q;
  2574. }
  2575. }
  2576. }
  2577. return flush_count;
  2578. }
  2579. /*
  2580. * Called to flush a packing buffer if no more pci flags are on the queue.
  2581. * Checks if there is a packing buffer and prepares it to be flushed.
  2582. * In that case returns 1, otherwise zero.
  2583. */
  2584. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2585. {
  2586. struct qeth_qdio_out_buffer *buffer;
  2587. buffer = &queue->bufs[queue->next_buf_to_fill];
  2588. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2589. (buffer->next_element_to_fill > 0)) {
  2590. /* it's a packing buffer */
  2591. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2592. queue->next_buf_to_fill =
  2593. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2594. return 1;
  2595. }
  2596. return 0;
  2597. }
  2598. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2599. int count)
  2600. {
  2601. struct qeth_qdio_out_buffer *buf;
  2602. int rc;
  2603. int i;
  2604. unsigned int qdio_flags;
  2605. for (i = index; i < index + count; ++i) {
  2606. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2607. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2608. SBAL_FLAGS_LAST_ENTRY;
  2609. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2610. continue;
  2611. if (!queue->do_pack) {
  2612. if ((atomic_read(&queue->used_buffers) >=
  2613. (QETH_HIGH_WATERMARK_PACK -
  2614. QETH_WATERMARK_PACK_FUZZ)) &&
  2615. !atomic_read(&queue->set_pci_flags_count)) {
  2616. /* it's likely that we'll go to packing
  2617. * mode soon */
  2618. atomic_inc(&queue->set_pci_flags_count);
  2619. buf->buffer->element[0].flags |= 0x40;
  2620. }
  2621. } else {
  2622. if (!atomic_read(&queue->set_pci_flags_count)) {
  2623. /*
  2624. * there's no outstanding PCI any more, so we
  2625. * have to request a PCI to be sure the the PCI
  2626. * will wake at some time in the future then we
  2627. * can flush packed buffers that might still be
  2628. * hanging around, which can happen if no
  2629. * further send was requested by the stack
  2630. */
  2631. atomic_inc(&queue->set_pci_flags_count);
  2632. buf->buffer->element[0].flags |= 0x40;
  2633. }
  2634. }
  2635. }
  2636. queue->card->dev->trans_start = jiffies;
  2637. if (queue->card->options.performance_stats) {
  2638. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2639. queue->card->perf_stats.outbound_do_qdio_start_time =
  2640. qeth_get_micros();
  2641. }
  2642. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2643. if (atomic_read(&queue->set_pci_flags_count))
  2644. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2645. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2646. queue->queue_no, index, count);
  2647. if (queue->card->options.performance_stats)
  2648. queue->card->perf_stats.outbound_do_qdio_time +=
  2649. qeth_get_micros() -
  2650. queue->card->perf_stats.outbound_do_qdio_start_time;
  2651. atomic_add(count, &queue->used_buffers);
  2652. if (rc) {
  2653. queue->card->stats.tx_errors += count;
  2654. /* ignore temporary SIGA errors without busy condition */
  2655. if (rc == QDIO_ERROR_SIGA_TARGET)
  2656. return;
  2657. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2658. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2659. /* this must not happen under normal circumstances. if it
  2660. * happens something is really wrong -> recover */
  2661. qeth_schedule_recovery(queue->card);
  2662. return;
  2663. }
  2664. if (queue->card->options.performance_stats)
  2665. queue->card->perf_stats.bufs_sent += count;
  2666. }
  2667. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2668. {
  2669. int index;
  2670. int flush_cnt = 0;
  2671. int q_was_packing = 0;
  2672. /*
  2673. * check if weed have to switch to non-packing mode or if
  2674. * we have to get a pci flag out on the queue
  2675. */
  2676. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2677. !atomic_read(&queue->set_pci_flags_count)) {
  2678. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2679. QETH_OUT_Q_UNLOCKED) {
  2680. /*
  2681. * If we get in here, there was no action in
  2682. * do_send_packet. So, we check if there is a
  2683. * packing buffer to be flushed here.
  2684. */
  2685. netif_stop_queue(queue->card->dev);
  2686. index = queue->next_buf_to_fill;
  2687. q_was_packing = queue->do_pack;
  2688. /* queue->do_pack may change */
  2689. barrier();
  2690. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2691. if (!flush_cnt &&
  2692. !atomic_read(&queue->set_pci_flags_count))
  2693. flush_cnt +=
  2694. qeth_flush_buffers_on_no_pci(queue);
  2695. if (queue->card->options.performance_stats &&
  2696. q_was_packing)
  2697. queue->card->perf_stats.bufs_sent_pack +=
  2698. flush_cnt;
  2699. if (flush_cnt)
  2700. qeth_flush_buffers(queue, index, flush_cnt);
  2701. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2702. }
  2703. }
  2704. }
  2705. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  2706. unsigned long card_ptr)
  2707. {
  2708. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2709. if (card->dev && (card->dev->flags & IFF_UP))
  2710. napi_schedule(&card->napi);
  2711. }
  2712. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  2713. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  2714. unsigned int queue, int first_element, int count,
  2715. unsigned long card_ptr)
  2716. {
  2717. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2718. if (qdio_err)
  2719. qeth_schedule_recovery(card);
  2720. }
  2721. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  2722. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2723. unsigned int qdio_error, int __queue, int first_element,
  2724. int count, unsigned long card_ptr)
  2725. {
  2726. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2727. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2728. struct qeth_qdio_out_buffer *buffer;
  2729. int i;
  2730. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2731. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2732. QETH_CARD_TEXT(card, 2, "achkcond");
  2733. netif_stop_queue(card->dev);
  2734. qeth_schedule_recovery(card);
  2735. return;
  2736. }
  2737. if (card->options.performance_stats) {
  2738. card->perf_stats.outbound_handler_cnt++;
  2739. card->perf_stats.outbound_handler_start_time =
  2740. qeth_get_micros();
  2741. }
  2742. for (i = first_element; i < (first_element + count); ++i) {
  2743. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2744. qeth_handle_send_error(card, buffer, qdio_error);
  2745. qeth_clear_output_buffer(queue, buffer);
  2746. }
  2747. atomic_sub(count, &queue->used_buffers);
  2748. /* check if we need to do something on this outbound queue */
  2749. if (card->info.type != QETH_CARD_TYPE_IQD)
  2750. qeth_check_outbound_queue(queue);
  2751. netif_wake_queue(queue->card->dev);
  2752. if (card->options.performance_stats)
  2753. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2754. card->perf_stats.outbound_handler_start_time;
  2755. }
  2756. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2757. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2758. int ipv, int cast_type)
  2759. {
  2760. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2761. card->info.type == QETH_CARD_TYPE_OSX))
  2762. return card->qdio.default_out_queue;
  2763. switch (card->qdio.no_out_queues) {
  2764. case 4:
  2765. if (cast_type && card->info.is_multicast_different)
  2766. return card->info.is_multicast_different &
  2767. (card->qdio.no_out_queues - 1);
  2768. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2769. const u8 tos = ip_hdr(skb)->tos;
  2770. if (card->qdio.do_prio_queueing ==
  2771. QETH_PRIO_Q_ING_TOS) {
  2772. if (tos & IP_TOS_NOTIMPORTANT)
  2773. return 3;
  2774. if (tos & IP_TOS_HIGHRELIABILITY)
  2775. return 2;
  2776. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2777. return 1;
  2778. if (tos & IP_TOS_LOWDELAY)
  2779. return 0;
  2780. }
  2781. if (card->qdio.do_prio_queueing ==
  2782. QETH_PRIO_Q_ING_PREC)
  2783. return 3 - (tos >> 6);
  2784. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2785. /* TODO: IPv6!!! */
  2786. }
  2787. return card->qdio.default_out_queue;
  2788. case 1: /* fallthrough for single-out-queue 1920-device */
  2789. default:
  2790. return card->qdio.default_out_queue;
  2791. }
  2792. }
  2793. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2794. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2795. struct sk_buff *skb, int elems)
  2796. {
  2797. int dlen = skb->len - skb->data_len;
  2798. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2799. PFN_DOWN((unsigned long)skb->data);
  2800. elements_needed += skb_shinfo(skb)->nr_frags;
  2801. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2802. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2803. "(Number=%d / Length=%d). Discarded.\n",
  2804. (elements_needed+elems), skb->len);
  2805. return 0;
  2806. }
  2807. return elements_needed;
  2808. }
  2809. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2810. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2811. {
  2812. int hroom, inpage, rest;
  2813. if (((unsigned long)skb->data & PAGE_MASK) !=
  2814. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2815. hroom = skb_headroom(skb);
  2816. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2817. rest = len - inpage;
  2818. if (rest > hroom)
  2819. return 1;
  2820. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2821. skb->data -= rest;
  2822. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2823. }
  2824. return 0;
  2825. }
  2826. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2827. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2828. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2829. int offset)
  2830. {
  2831. int length = skb->len - skb->data_len;
  2832. int length_here;
  2833. int element;
  2834. char *data;
  2835. int first_lap, cnt;
  2836. struct skb_frag_struct *frag;
  2837. element = *next_element_to_fill;
  2838. data = skb->data;
  2839. first_lap = (is_tso == 0 ? 1 : 0);
  2840. if (offset >= 0) {
  2841. data = skb->data + offset;
  2842. length -= offset;
  2843. first_lap = 0;
  2844. }
  2845. while (length > 0) {
  2846. /* length_here is the remaining amount of data in this page */
  2847. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2848. if (length < length_here)
  2849. length_here = length;
  2850. buffer->element[element].addr = data;
  2851. buffer->element[element].length = length_here;
  2852. length -= length_here;
  2853. if (!length) {
  2854. if (first_lap)
  2855. if (skb_shinfo(skb)->nr_frags)
  2856. buffer->element[element].flags =
  2857. SBAL_FLAGS_FIRST_FRAG;
  2858. else
  2859. buffer->element[element].flags = 0;
  2860. else
  2861. buffer->element[element].flags =
  2862. SBAL_FLAGS_MIDDLE_FRAG;
  2863. } else {
  2864. if (first_lap)
  2865. buffer->element[element].flags =
  2866. SBAL_FLAGS_FIRST_FRAG;
  2867. else
  2868. buffer->element[element].flags =
  2869. SBAL_FLAGS_MIDDLE_FRAG;
  2870. }
  2871. data += length_here;
  2872. element++;
  2873. first_lap = 0;
  2874. }
  2875. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2876. frag = &skb_shinfo(skb)->frags[cnt];
  2877. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2878. + frag->page_offset;
  2879. buffer->element[element].length = frag->size;
  2880. buffer->element[element].flags = SBAL_FLAGS_MIDDLE_FRAG;
  2881. element++;
  2882. }
  2883. if (buffer->element[element - 1].flags)
  2884. buffer->element[element - 1].flags = SBAL_FLAGS_LAST_FRAG;
  2885. *next_element_to_fill = element;
  2886. }
  2887. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2888. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2889. struct qeth_hdr *hdr, int offset, int hd_len)
  2890. {
  2891. struct qdio_buffer *buffer;
  2892. int flush_cnt = 0, hdr_len, large_send = 0;
  2893. buffer = buf->buffer;
  2894. atomic_inc(&skb->users);
  2895. skb_queue_tail(&buf->skb_list, skb);
  2896. /*check first on TSO ....*/
  2897. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2898. int element = buf->next_element_to_fill;
  2899. hdr_len = sizeof(struct qeth_hdr_tso) +
  2900. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2901. /*fill first buffer entry only with header information */
  2902. buffer->element[element].addr = skb->data;
  2903. buffer->element[element].length = hdr_len;
  2904. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2905. buf->next_element_to_fill++;
  2906. skb->data += hdr_len;
  2907. skb->len -= hdr_len;
  2908. large_send = 1;
  2909. }
  2910. if (offset >= 0) {
  2911. int element = buf->next_element_to_fill;
  2912. buffer->element[element].addr = hdr;
  2913. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2914. hd_len;
  2915. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2916. buf->is_header[element] = 1;
  2917. buf->next_element_to_fill++;
  2918. }
  2919. __qeth_fill_buffer(skb, buffer, large_send,
  2920. (int *)&buf->next_element_to_fill, offset);
  2921. if (!queue->do_pack) {
  2922. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2923. /* set state to PRIMED -> will be flushed */
  2924. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2925. flush_cnt = 1;
  2926. } else {
  2927. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2928. if (queue->card->options.performance_stats)
  2929. queue->card->perf_stats.skbs_sent_pack++;
  2930. if (buf->next_element_to_fill >=
  2931. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2932. /*
  2933. * packed buffer if full -> set state PRIMED
  2934. * -> will be flushed
  2935. */
  2936. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2937. flush_cnt = 1;
  2938. }
  2939. }
  2940. return flush_cnt;
  2941. }
  2942. int qeth_do_send_packet_fast(struct qeth_card *card,
  2943. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2944. struct qeth_hdr *hdr, int elements_needed,
  2945. int offset, int hd_len)
  2946. {
  2947. struct qeth_qdio_out_buffer *buffer;
  2948. int index;
  2949. /* spin until we get the queue ... */
  2950. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2951. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2952. /* ... now we've got the queue */
  2953. index = queue->next_buf_to_fill;
  2954. buffer = &queue->bufs[queue->next_buf_to_fill];
  2955. /*
  2956. * check if buffer is empty to make sure that we do not 'overtake'
  2957. * ourselves and try to fill a buffer that is already primed
  2958. */
  2959. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2960. goto out;
  2961. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2962. QDIO_MAX_BUFFERS_PER_Q;
  2963. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2964. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2965. qeth_flush_buffers(queue, index, 1);
  2966. return 0;
  2967. out:
  2968. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2969. return -EBUSY;
  2970. }
  2971. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2972. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2973. struct sk_buff *skb, struct qeth_hdr *hdr,
  2974. int elements_needed)
  2975. {
  2976. struct qeth_qdio_out_buffer *buffer;
  2977. int start_index;
  2978. int flush_count = 0;
  2979. int do_pack = 0;
  2980. int tmp;
  2981. int rc = 0;
  2982. /* spin until we get the queue ... */
  2983. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2984. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2985. start_index = queue->next_buf_to_fill;
  2986. buffer = &queue->bufs[queue->next_buf_to_fill];
  2987. /*
  2988. * check if buffer is empty to make sure that we do not 'overtake'
  2989. * ourselves and try to fill a buffer that is already primed
  2990. */
  2991. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2992. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2993. return -EBUSY;
  2994. }
  2995. /* check if we need to switch packing state of this queue */
  2996. qeth_switch_to_packing_if_needed(queue);
  2997. if (queue->do_pack) {
  2998. do_pack = 1;
  2999. /* does packet fit in current buffer? */
  3000. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3001. buffer->next_element_to_fill) < elements_needed) {
  3002. /* ... no -> set state PRIMED */
  3003. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3004. flush_count++;
  3005. queue->next_buf_to_fill =
  3006. (queue->next_buf_to_fill + 1) %
  3007. QDIO_MAX_BUFFERS_PER_Q;
  3008. buffer = &queue->bufs[queue->next_buf_to_fill];
  3009. /* we did a step forward, so check buffer state
  3010. * again */
  3011. if (atomic_read(&buffer->state) !=
  3012. QETH_QDIO_BUF_EMPTY) {
  3013. qeth_flush_buffers(queue, start_index,
  3014. flush_count);
  3015. atomic_set(&queue->state,
  3016. QETH_OUT_Q_UNLOCKED);
  3017. return -EBUSY;
  3018. }
  3019. }
  3020. }
  3021. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3022. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3023. QDIO_MAX_BUFFERS_PER_Q;
  3024. flush_count += tmp;
  3025. if (flush_count)
  3026. qeth_flush_buffers(queue, start_index, flush_count);
  3027. else if (!atomic_read(&queue->set_pci_flags_count))
  3028. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3029. /*
  3030. * queue->state will go from LOCKED -> UNLOCKED or from
  3031. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3032. * (switch packing state or flush buffer to get another pci flag out).
  3033. * In that case we will enter this loop
  3034. */
  3035. while (atomic_dec_return(&queue->state)) {
  3036. flush_count = 0;
  3037. start_index = queue->next_buf_to_fill;
  3038. /* check if we can go back to non-packing state */
  3039. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3040. /*
  3041. * check if we need to flush a packing buffer to get a pci
  3042. * flag out on the queue
  3043. */
  3044. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3045. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3046. if (flush_count)
  3047. qeth_flush_buffers(queue, start_index, flush_count);
  3048. }
  3049. /* at this point the queue is UNLOCKED again */
  3050. if (queue->card->options.performance_stats && do_pack)
  3051. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3052. return rc;
  3053. }
  3054. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3055. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3056. struct qeth_reply *reply, unsigned long data)
  3057. {
  3058. struct qeth_ipa_cmd *cmd;
  3059. struct qeth_ipacmd_setadpparms *setparms;
  3060. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3061. cmd = (struct qeth_ipa_cmd *) data;
  3062. setparms = &(cmd->data.setadapterparms);
  3063. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3064. if (cmd->hdr.return_code) {
  3065. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3066. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3067. }
  3068. card->info.promisc_mode = setparms->data.mode;
  3069. return 0;
  3070. }
  3071. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3072. {
  3073. enum qeth_ipa_promisc_modes mode;
  3074. struct net_device *dev = card->dev;
  3075. struct qeth_cmd_buffer *iob;
  3076. struct qeth_ipa_cmd *cmd;
  3077. QETH_CARD_TEXT(card, 4, "setprom");
  3078. if (((dev->flags & IFF_PROMISC) &&
  3079. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3080. (!(dev->flags & IFF_PROMISC) &&
  3081. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3082. return;
  3083. mode = SET_PROMISC_MODE_OFF;
  3084. if (dev->flags & IFF_PROMISC)
  3085. mode = SET_PROMISC_MODE_ON;
  3086. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3087. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3088. sizeof(struct qeth_ipacmd_setadpparms));
  3089. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3090. cmd->data.setadapterparms.data.mode = mode;
  3091. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3092. }
  3093. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3094. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3095. {
  3096. struct qeth_card *card;
  3097. char dbf_text[15];
  3098. card = dev->ml_priv;
  3099. QETH_CARD_TEXT(card, 4, "chgmtu");
  3100. sprintf(dbf_text, "%8x", new_mtu);
  3101. QETH_CARD_TEXT(card, 4, dbf_text);
  3102. if (new_mtu < 64)
  3103. return -EINVAL;
  3104. if (new_mtu > 65535)
  3105. return -EINVAL;
  3106. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3107. (!qeth_mtu_is_valid(card, new_mtu)))
  3108. return -EINVAL;
  3109. dev->mtu = new_mtu;
  3110. return 0;
  3111. }
  3112. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3113. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3114. {
  3115. struct qeth_card *card;
  3116. card = dev->ml_priv;
  3117. QETH_CARD_TEXT(card, 5, "getstat");
  3118. return &card->stats;
  3119. }
  3120. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3121. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3122. struct qeth_reply *reply, unsigned long data)
  3123. {
  3124. struct qeth_ipa_cmd *cmd;
  3125. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3126. cmd = (struct qeth_ipa_cmd *) data;
  3127. if (!card->options.layer2 ||
  3128. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3129. memcpy(card->dev->dev_addr,
  3130. &cmd->data.setadapterparms.data.change_addr.addr,
  3131. OSA_ADDR_LEN);
  3132. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3133. }
  3134. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3135. return 0;
  3136. }
  3137. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3138. {
  3139. int rc;
  3140. struct qeth_cmd_buffer *iob;
  3141. struct qeth_ipa_cmd *cmd;
  3142. QETH_CARD_TEXT(card, 4, "chgmac");
  3143. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3144. sizeof(struct qeth_ipacmd_setadpparms));
  3145. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3146. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3147. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3148. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3149. card->dev->dev_addr, OSA_ADDR_LEN);
  3150. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3151. NULL);
  3152. return rc;
  3153. }
  3154. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3155. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3156. struct qeth_reply *reply, unsigned long data)
  3157. {
  3158. struct qeth_ipa_cmd *cmd;
  3159. struct qeth_set_access_ctrl *access_ctrl_req;
  3160. QETH_CARD_TEXT(card, 4, "setaccb");
  3161. cmd = (struct qeth_ipa_cmd *) data;
  3162. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3163. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3164. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3165. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3166. cmd->data.setadapterparms.hdr.return_code);
  3167. switch (cmd->data.setadapterparms.hdr.return_code) {
  3168. case SET_ACCESS_CTRL_RC_SUCCESS:
  3169. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3170. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3171. {
  3172. card->options.isolation = access_ctrl_req->subcmd_code;
  3173. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3174. dev_info(&card->gdev->dev,
  3175. "QDIO data connection isolation is deactivated\n");
  3176. } else {
  3177. dev_info(&card->gdev->dev,
  3178. "QDIO data connection isolation is activated\n");
  3179. }
  3180. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3181. card->gdev->dev.kobj.name,
  3182. access_ctrl_req->subcmd_code,
  3183. cmd->data.setadapterparms.hdr.return_code);
  3184. break;
  3185. }
  3186. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3187. {
  3188. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3189. card->gdev->dev.kobj.name,
  3190. access_ctrl_req->subcmd_code,
  3191. cmd->data.setadapterparms.hdr.return_code);
  3192. dev_err(&card->gdev->dev, "Adapter does not "
  3193. "support QDIO data connection isolation\n");
  3194. /* ensure isolation mode is "none" */
  3195. card->options.isolation = ISOLATION_MODE_NONE;
  3196. break;
  3197. }
  3198. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3199. {
  3200. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3201. card->gdev->dev.kobj.name,
  3202. access_ctrl_req->subcmd_code,
  3203. cmd->data.setadapterparms.hdr.return_code);
  3204. dev_err(&card->gdev->dev,
  3205. "Adapter is dedicated. "
  3206. "QDIO data connection isolation not supported\n");
  3207. /* ensure isolation mode is "none" */
  3208. card->options.isolation = ISOLATION_MODE_NONE;
  3209. break;
  3210. }
  3211. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3212. {
  3213. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3214. card->gdev->dev.kobj.name,
  3215. access_ctrl_req->subcmd_code,
  3216. cmd->data.setadapterparms.hdr.return_code);
  3217. dev_err(&card->gdev->dev,
  3218. "TSO does not permit QDIO data connection isolation\n");
  3219. /* ensure isolation mode is "none" */
  3220. card->options.isolation = ISOLATION_MODE_NONE;
  3221. break;
  3222. }
  3223. default:
  3224. {
  3225. /* this should never happen */
  3226. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3227. "==UNKNOWN\n",
  3228. card->gdev->dev.kobj.name,
  3229. access_ctrl_req->subcmd_code,
  3230. cmd->data.setadapterparms.hdr.return_code);
  3231. /* ensure isolation mode is "none" */
  3232. card->options.isolation = ISOLATION_MODE_NONE;
  3233. break;
  3234. }
  3235. }
  3236. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3237. return 0;
  3238. }
  3239. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3240. enum qeth_ipa_isolation_modes isolation)
  3241. {
  3242. int rc;
  3243. struct qeth_cmd_buffer *iob;
  3244. struct qeth_ipa_cmd *cmd;
  3245. struct qeth_set_access_ctrl *access_ctrl_req;
  3246. QETH_CARD_TEXT(card, 4, "setacctl");
  3247. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3248. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3249. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3250. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3251. sizeof(struct qeth_set_access_ctrl));
  3252. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3253. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3254. access_ctrl_req->subcmd_code = isolation;
  3255. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3256. NULL);
  3257. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3258. return rc;
  3259. }
  3260. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3261. {
  3262. int rc = 0;
  3263. QETH_CARD_TEXT(card, 4, "setactlo");
  3264. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3265. card->info.type == QETH_CARD_TYPE_OSX) &&
  3266. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3267. rc = qeth_setadpparms_set_access_ctrl(card,
  3268. card->options.isolation);
  3269. if (rc) {
  3270. QETH_DBF_MESSAGE(3,
  3271. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3272. card->gdev->dev.kobj.name,
  3273. rc);
  3274. }
  3275. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3276. card->options.isolation = ISOLATION_MODE_NONE;
  3277. dev_err(&card->gdev->dev, "Adapter does not "
  3278. "support QDIO data connection isolation\n");
  3279. rc = -EOPNOTSUPP;
  3280. }
  3281. return rc;
  3282. }
  3283. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3284. void qeth_tx_timeout(struct net_device *dev)
  3285. {
  3286. struct qeth_card *card;
  3287. card = dev->ml_priv;
  3288. QETH_CARD_TEXT(card, 4, "txtimeo");
  3289. card->stats.tx_errors++;
  3290. qeth_schedule_recovery(card);
  3291. }
  3292. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3293. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3294. {
  3295. struct qeth_card *card = dev->ml_priv;
  3296. int rc = 0;
  3297. switch (regnum) {
  3298. case MII_BMCR: /* Basic mode control register */
  3299. rc = BMCR_FULLDPLX;
  3300. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3301. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3302. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3303. rc |= BMCR_SPEED100;
  3304. break;
  3305. case MII_BMSR: /* Basic mode status register */
  3306. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3307. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3308. BMSR_100BASE4;
  3309. break;
  3310. case MII_PHYSID1: /* PHYS ID 1 */
  3311. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3312. dev->dev_addr[2];
  3313. rc = (rc >> 5) & 0xFFFF;
  3314. break;
  3315. case MII_PHYSID2: /* PHYS ID 2 */
  3316. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3317. break;
  3318. case MII_ADVERTISE: /* Advertisement control reg */
  3319. rc = ADVERTISE_ALL;
  3320. break;
  3321. case MII_LPA: /* Link partner ability reg */
  3322. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3323. LPA_100BASE4 | LPA_LPACK;
  3324. break;
  3325. case MII_EXPANSION: /* Expansion register */
  3326. break;
  3327. case MII_DCOUNTER: /* disconnect counter */
  3328. break;
  3329. case MII_FCSCOUNTER: /* false carrier counter */
  3330. break;
  3331. case MII_NWAYTEST: /* N-way auto-neg test register */
  3332. break;
  3333. case MII_RERRCOUNTER: /* rx error counter */
  3334. rc = card->stats.rx_errors;
  3335. break;
  3336. case MII_SREVISION: /* silicon revision */
  3337. break;
  3338. case MII_RESV1: /* reserved 1 */
  3339. break;
  3340. case MII_LBRERROR: /* loopback, rx, bypass error */
  3341. break;
  3342. case MII_PHYADDR: /* physical address */
  3343. break;
  3344. case MII_RESV2: /* reserved 2 */
  3345. break;
  3346. case MII_TPISTATUS: /* TPI status for 10mbps */
  3347. break;
  3348. case MII_NCONFIG: /* network interface config */
  3349. break;
  3350. default:
  3351. break;
  3352. }
  3353. return rc;
  3354. }
  3355. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3356. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3357. struct qeth_cmd_buffer *iob, int len,
  3358. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3359. unsigned long),
  3360. void *reply_param)
  3361. {
  3362. u16 s1, s2;
  3363. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3364. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3365. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3366. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3367. /* adjust PDU length fields in IPA_PDU_HEADER */
  3368. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3369. s2 = (u32) len;
  3370. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3371. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3372. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3373. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3374. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3375. reply_cb, reply_param);
  3376. }
  3377. static int qeth_snmp_command_cb(struct qeth_card *card,
  3378. struct qeth_reply *reply, unsigned long sdata)
  3379. {
  3380. struct qeth_ipa_cmd *cmd;
  3381. struct qeth_arp_query_info *qinfo;
  3382. struct qeth_snmp_cmd *snmp;
  3383. unsigned char *data;
  3384. __u16 data_len;
  3385. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3386. cmd = (struct qeth_ipa_cmd *) sdata;
  3387. data = (unsigned char *)((char *)cmd - reply->offset);
  3388. qinfo = (struct qeth_arp_query_info *) reply->param;
  3389. snmp = &cmd->data.setadapterparms.data.snmp;
  3390. if (cmd->hdr.return_code) {
  3391. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3392. return 0;
  3393. }
  3394. if (cmd->data.setadapterparms.hdr.return_code) {
  3395. cmd->hdr.return_code =
  3396. cmd->data.setadapterparms.hdr.return_code;
  3397. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3398. return 0;
  3399. }
  3400. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3401. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3402. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3403. else
  3404. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3405. /* check if there is enough room in userspace */
  3406. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3407. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3408. cmd->hdr.return_code = -ENOMEM;
  3409. return 0;
  3410. }
  3411. QETH_CARD_TEXT_(card, 4, "snore%i",
  3412. cmd->data.setadapterparms.hdr.used_total);
  3413. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3414. cmd->data.setadapterparms.hdr.seq_no);
  3415. /*copy entries to user buffer*/
  3416. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3417. memcpy(qinfo->udata + qinfo->udata_offset,
  3418. (char *)snmp,
  3419. data_len + offsetof(struct qeth_snmp_cmd, data));
  3420. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3421. } else {
  3422. memcpy(qinfo->udata + qinfo->udata_offset,
  3423. (char *)&snmp->request, data_len);
  3424. }
  3425. qinfo->udata_offset += data_len;
  3426. /* check if all replies received ... */
  3427. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3428. cmd->data.setadapterparms.hdr.used_total);
  3429. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3430. cmd->data.setadapterparms.hdr.seq_no);
  3431. if (cmd->data.setadapterparms.hdr.seq_no <
  3432. cmd->data.setadapterparms.hdr.used_total)
  3433. return 1;
  3434. return 0;
  3435. }
  3436. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3437. {
  3438. struct qeth_cmd_buffer *iob;
  3439. struct qeth_ipa_cmd *cmd;
  3440. struct qeth_snmp_ureq *ureq;
  3441. int req_len;
  3442. struct qeth_arp_query_info qinfo = {0, };
  3443. int rc = 0;
  3444. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3445. if (card->info.guestlan)
  3446. return -EOPNOTSUPP;
  3447. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3448. (!card->options.layer2)) {
  3449. return -EOPNOTSUPP;
  3450. }
  3451. /* skip 4 bytes (data_len struct member) to get req_len */
  3452. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3453. return -EFAULT;
  3454. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3455. if (IS_ERR(ureq)) {
  3456. QETH_CARD_TEXT(card, 2, "snmpnome");
  3457. return PTR_ERR(ureq);
  3458. }
  3459. qinfo.udata_len = ureq->hdr.data_len;
  3460. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3461. if (!qinfo.udata) {
  3462. kfree(ureq);
  3463. return -ENOMEM;
  3464. }
  3465. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3466. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3467. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3468. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3469. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3470. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3471. qeth_snmp_command_cb, (void *)&qinfo);
  3472. if (rc)
  3473. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3474. QETH_CARD_IFNAME(card), rc);
  3475. else {
  3476. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3477. rc = -EFAULT;
  3478. }
  3479. kfree(ureq);
  3480. kfree(qinfo.udata);
  3481. return rc;
  3482. }
  3483. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3484. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3485. {
  3486. switch (card->info.type) {
  3487. case QETH_CARD_TYPE_IQD:
  3488. return 2;
  3489. default:
  3490. return 0;
  3491. }
  3492. }
  3493. static void qeth_determine_capabilities(struct qeth_card *card)
  3494. {
  3495. int rc;
  3496. int length;
  3497. char *prcd;
  3498. struct ccw_device *ddev;
  3499. int ddev_offline = 0;
  3500. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3501. ddev = CARD_DDEV(card);
  3502. if (!ddev->online) {
  3503. ddev_offline = 1;
  3504. rc = ccw_device_set_online(ddev);
  3505. if (rc) {
  3506. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3507. goto out;
  3508. }
  3509. }
  3510. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3511. if (rc) {
  3512. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3513. dev_name(&card->gdev->dev), rc);
  3514. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3515. goto out_offline;
  3516. }
  3517. qeth_configure_unitaddr(card, prcd);
  3518. qeth_configure_blkt_default(card, prcd);
  3519. kfree(prcd);
  3520. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  3521. if (rc)
  3522. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3523. out_offline:
  3524. if (ddev_offline == 1)
  3525. ccw_device_set_offline(ddev);
  3526. out:
  3527. return;
  3528. }
  3529. static int qeth_qdio_establish(struct qeth_card *card)
  3530. {
  3531. struct qdio_initialize init_data;
  3532. char *qib_param_field;
  3533. struct qdio_buffer **in_sbal_ptrs;
  3534. struct qdio_buffer **out_sbal_ptrs;
  3535. int i, j, k;
  3536. int rc = 0;
  3537. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3538. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3539. GFP_KERNEL);
  3540. if (!qib_param_field)
  3541. return -ENOMEM;
  3542. qeth_create_qib_param_field(card, qib_param_field);
  3543. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3544. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3545. GFP_KERNEL);
  3546. if (!in_sbal_ptrs) {
  3547. kfree(qib_param_field);
  3548. return -ENOMEM;
  3549. }
  3550. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3551. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3552. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3553. out_sbal_ptrs =
  3554. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3555. sizeof(void *), GFP_KERNEL);
  3556. if (!out_sbal_ptrs) {
  3557. kfree(in_sbal_ptrs);
  3558. kfree(qib_param_field);
  3559. return -ENOMEM;
  3560. }
  3561. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3562. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3563. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3564. card->qdio.out_qs[i]->bufs[j].buffer);
  3565. }
  3566. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3567. init_data.cdev = CARD_DDEV(card);
  3568. init_data.q_format = qeth_get_qdio_q_format(card);
  3569. init_data.qib_param_field_format = 0;
  3570. init_data.qib_param_field = qib_param_field;
  3571. init_data.no_input_qs = 1;
  3572. init_data.no_output_qs = card->qdio.no_out_queues;
  3573. init_data.input_handler = card->discipline.input_handler;
  3574. init_data.output_handler = card->discipline.output_handler;
  3575. init_data.queue_start_poll = card->discipline.start_poll;
  3576. init_data.int_parm = (unsigned long) card;
  3577. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3578. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3579. init_data.scan_threshold =
  3580. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  3581. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3582. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3583. rc = qdio_allocate(&init_data);
  3584. if (rc) {
  3585. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3586. goto out;
  3587. }
  3588. rc = qdio_establish(&init_data);
  3589. if (rc) {
  3590. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3591. qdio_free(CARD_DDEV(card));
  3592. }
  3593. }
  3594. out:
  3595. kfree(out_sbal_ptrs);
  3596. kfree(in_sbal_ptrs);
  3597. kfree(qib_param_field);
  3598. return rc;
  3599. }
  3600. static void qeth_core_free_card(struct qeth_card *card)
  3601. {
  3602. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3603. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3604. qeth_clean_channel(&card->read);
  3605. qeth_clean_channel(&card->write);
  3606. if (card->dev)
  3607. free_netdev(card->dev);
  3608. kfree(card->ip_tbd_list);
  3609. qeth_free_qdio_buffers(card);
  3610. unregister_service_level(&card->qeth_service_level);
  3611. kfree(card);
  3612. }
  3613. static struct ccw_device_id qeth_ids[] = {
  3614. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3615. .driver_info = QETH_CARD_TYPE_OSD},
  3616. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3617. .driver_info = QETH_CARD_TYPE_IQD},
  3618. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3619. .driver_info = QETH_CARD_TYPE_OSN},
  3620. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3621. .driver_info = QETH_CARD_TYPE_OSM},
  3622. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3623. .driver_info = QETH_CARD_TYPE_OSX},
  3624. {},
  3625. };
  3626. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3627. static struct ccw_driver qeth_ccw_driver = {
  3628. .driver = {
  3629. .name = "qeth",
  3630. },
  3631. .ids = qeth_ids,
  3632. .probe = ccwgroup_probe_ccwdev,
  3633. .remove = ccwgroup_remove_ccwdev,
  3634. };
  3635. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3636. unsigned long driver_id)
  3637. {
  3638. return ccwgroup_create_from_string(root_dev, driver_id,
  3639. &qeth_ccw_driver, 3, buf);
  3640. }
  3641. int qeth_core_hardsetup_card(struct qeth_card *card)
  3642. {
  3643. int retries = 0;
  3644. int rc;
  3645. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3646. atomic_set(&card->force_alloc_skb, 0);
  3647. qeth_get_channel_path_desc(card);
  3648. retry:
  3649. if (retries)
  3650. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3651. dev_name(&card->gdev->dev));
  3652. ccw_device_set_offline(CARD_DDEV(card));
  3653. ccw_device_set_offline(CARD_WDEV(card));
  3654. ccw_device_set_offline(CARD_RDEV(card));
  3655. rc = ccw_device_set_online(CARD_RDEV(card));
  3656. if (rc)
  3657. goto retriable;
  3658. rc = ccw_device_set_online(CARD_WDEV(card));
  3659. if (rc)
  3660. goto retriable;
  3661. rc = ccw_device_set_online(CARD_DDEV(card));
  3662. if (rc)
  3663. goto retriable;
  3664. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3665. retriable:
  3666. if (rc == -ERESTARTSYS) {
  3667. QETH_DBF_TEXT(SETUP, 2, "break1");
  3668. return rc;
  3669. } else if (rc) {
  3670. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3671. if (++retries > 3)
  3672. goto out;
  3673. else
  3674. goto retry;
  3675. }
  3676. qeth_determine_capabilities(card);
  3677. qeth_init_tokens(card);
  3678. qeth_init_func_level(card);
  3679. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3680. if (rc == -ERESTARTSYS) {
  3681. QETH_DBF_TEXT(SETUP, 2, "break2");
  3682. return rc;
  3683. } else if (rc) {
  3684. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3685. if (--retries < 0)
  3686. goto out;
  3687. else
  3688. goto retry;
  3689. }
  3690. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3691. if (rc == -ERESTARTSYS) {
  3692. QETH_DBF_TEXT(SETUP, 2, "break3");
  3693. return rc;
  3694. } else if (rc) {
  3695. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3696. if (--retries < 0)
  3697. goto out;
  3698. else
  3699. goto retry;
  3700. }
  3701. card->read_or_write_problem = 0;
  3702. rc = qeth_mpc_initialize(card);
  3703. if (rc) {
  3704. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3705. goto out;
  3706. }
  3707. card->options.ipa4.supported_funcs = 0;
  3708. card->options.adp.supported_funcs = 0;
  3709. card->info.diagass_support = 0;
  3710. qeth_query_ipassists(card, QETH_PROT_IPV4);
  3711. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  3712. qeth_query_setadapterparms(card);
  3713. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  3714. qeth_query_setdiagass(card);
  3715. return 0;
  3716. out:
  3717. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3718. "an error on the device\n");
  3719. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3720. dev_name(&card->gdev->dev), rc);
  3721. return rc;
  3722. }
  3723. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3724. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3725. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3726. {
  3727. struct page *page = virt_to_page(element->addr);
  3728. if (*pskb == NULL) {
  3729. /* the upper protocol layers assume that there is data in the
  3730. * skb itself. Copy a small amount (64 bytes) to make them
  3731. * happy. */
  3732. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3733. if (!(*pskb))
  3734. return -ENOMEM;
  3735. skb_reserve(*pskb, ETH_HLEN);
  3736. if (data_len <= 64) {
  3737. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3738. data_len);
  3739. } else {
  3740. get_page(page);
  3741. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3742. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3743. data_len - 64);
  3744. (*pskb)->data_len += data_len - 64;
  3745. (*pskb)->len += data_len - 64;
  3746. (*pskb)->truesize += data_len - 64;
  3747. (*pfrag)++;
  3748. }
  3749. } else {
  3750. get_page(page);
  3751. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3752. (*pskb)->data_len += data_len;
  3753. (*pskb)->len += data_len;
  3754. (*pskb)->truesize += data_len;
  3755. (*pfrag)++;
  3756. }
  3757. return 0;
  3758. }
  3759. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3760. struct qdio_buffer *buffer,
  3761. struct qdio_buffer_element **__element, int *__offset,
  3762. struct qeth_hdr **hdr)
  3763. {
  3764. struct qdio_buffer_element *element = *__element;
  3765. int offset = *__offset;
  3766. struct sk_buff *skb = NULL;
  3767. int skb_len = 0;
  3768. void *data_ptr;
  3769. int data_len;
  3770. int headroom = 0;
  3771. int use_rx_sg = 0;
  3772. int frag = 0;
  3773. /* qeth_hdr must not cross element boundaries */
  3774. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3775. if (qeth_is_last_sbale(element))
  3776. return NULL;
  3777. element++;
  3778. offset = 0;
  3779. if (element->length < sizeof(struct qeth_hdr))
  3780. return NULL;
  3781. }
  3782. *hdr = element->addr + offset;
  3783. offset += sizeof(struct qeth_hdr);
  3784. switch ((*hdr)->hdr.l2.id) {
  3785. case QETH_HEADER_TYPE_LAYER2:
  3786. skb_len = (*hdr)->hdr.l2.pkt_length;
  3787. break;
  3788. case QETH_HEADER_TYPE_LAYER3:
  3789. skb_len = (*hdr)->hdr.l3.length;
  3790. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3791. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3792. headroom = TR_HLEN;
  3793. else
  3794. headroom = ETH_HLEN;
  3795. break;
  3796. case QETH_HEADER_TYPE_OSN:
  3797. skb_len = (*hdr)->hdr.osn.pdu_length;
  3798. headroom = sizeof(struct qeth_hdr);
  3799. break;
  3800. default:
  3801. break;
  3802. }
  3803. if (!skb_len)
  3804. return NULL;
  3805. if ((skb_len >= card->options.rx_sg_cb) &&
  3806. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3807. (!atomic_read(&card->force_alloc_skb))) {
  3808. use_rx_sg = 1;
  3809. } else {
  3810. skb = dev_alloc_skb(skb_len + headroom);
  3811. if (!skb)
  3812. goto no_mem;
  3813. if (headroom)
  3814. skb_reserve(skb, headroom);
  3815. }
  3816. data_ptr = element->addr + offset;
  3817. while (skb_len) {
  3818. data_len = min(skb_len, (int)(element->length - offset));
  3819. if (data_len) {
  3820. if (use_rx_sg) {
  3821. if (qeth_create_skb_frag(element, &skb, offset,
  3822. &frag, data_len))
  3823. goto no_mem;
  3824. } else {
  3825. memcpy(skb_put(skb, data_len), data_ptr,
  3826. data_len);
  3827. }
  3828. }
  3829. skb_len -= data_len;
  3830. if (skb_len) {
  3831. if (qeth_is_last_sbale(element)) {
  3832. QETH_CARD_TEXT(card, 4, "unexeob");
  3833. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3834. dev_kfree_skb_any(skb);
  3835. card->stats.rx_errors++;
  3836. return NULL;
  3837. }
  3838. element++;
  3839. offset = 0;
  3840. data_ptr = element->addr;
  3841. } else {
  3842. offset += data_len;
  3843. }
  3844. }
  3845. *__element = element;
  3846. *__offset = offset;
  3847. if (use_rx_sg && card->options.performance_stats) {
  3848. card->perf_stats.sg_skbs_rx++;
  3849. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3850. }
  3851. return skb;
  3852. no_mem:
  3853. if (net_ratelimit()) {
  3854. QETH_CARD_TEXT(card, 2, "noskbmem");
  3855. }
  3856. card->stats.rx_dropped++;
  3857. return NULL;
  3858. }
  3859. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3860. static void qeth_unregister_dbf_views(void)
  3861. {
  3862. int x;
  3863. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3864. debug_unregister(qeth_dbf[x].id);
  3865. qeth_dbf[x].id = NULL;
  3866. }
  3867. }
  3868. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3869. {
  3870. char dbf_txt_buf[32];
  3871. va_list args;
  3872. if (level > id->level)
  3873. return;
  3874. va_start(args, fmt);
  3875. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3876. va_end(args);
  3877. debug_text_event(id, level, dbf_txt_buf);
  3878. }
  3879. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3880. static int qeth_register_dbf_views(void)
  3881. {
  3882. int ret;
  3883. int x;
  3884. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3885. /* register the areas */
  3886. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3887. qeth_dbf[x].pages,
  3888. qeth_dbf[x].areas,
  3889. qeth_dbf[x].len);
  3890. if (qeth_dbf[x].id == NULL) {
  3891. qeth_unregister_dbf_views();
  3892. return -ENOMEM;
  3893. }
  3894. /* register a view */
  3895. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3896. if (ret) {
  3897. qeth_unregister_dbf_views();
  3898. return ret;
  3899. }
  3900. /* set a passing level */
  3901. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3902. }
  3903. return 0;
  3904. }
  3905. int qeth_core_load_discipline(struct qeth_card *card,
  3906. enum qeth_discipline_id discipline)
  3907. {
  3908. int rc = 0;
  3909. switch (discipline) {
  3910. case QETH_DISCIPLINE_LAYER3:
  3911. card->discipline.ccwgdriver = try_then_request_module(
  3912. symbol_get(qeth_l3_ccwgroup_driver),
  3913. "qeth_l3");
  3914. break;
  3915. case QETH_DISCIPLINE_LAYER2:
  3916. card->discipline.ccwgdriver = try_then_request_module(
  3917. symbol_get(qeth_l2_ccwgroup_driver),
  3918. "qeth_l2");
  3919. break;
  3920. }
  3921. if (!card->discipline.ccwgdriver) {
  3922. dev_err(&card->gdev->dev, "There is no kernel module to "
  3923. "support discipline %d\n", discipline);
  3924. rc = -EINVAL;
  3925. }
  3926. return rc;
  3927. }
  3928. void qeth_core_free_discipline(struct qeth_card *card)
  3929. {
  3930. if (card->options.layer2)
  3931. symbol_put(qeth_l2_ccwgroup_driver);
  3932. else
  3933. symbol_put(qeth_l3_ccwgroup_driver);
  3934. card->discipline.ccwgdriver = NULL;
  3935. }
  3936. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3937. {
  3938. struct qeth_card *card;
  3939. struct device *dev;
  3940. int rc;
  3941. unsigned long flags;
  3942. char dbf_name[20];
  3943. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3944. dev = &gdev->dev;
  3945. if (!get_device(dev))
  3946. return -ENODEV;
  3947. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3948. card = qeth_alloc_card();
  3949. if (!card) {
  3950. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3951. rc = -ENOMEM;
  3952. goto err_dev;
  3953. }
  3954. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3955. dev_name(&gdev->dev));
  3956. card->debug = debug_register(dbf_name, 2, 1, 8);
  3957. if (!card->debug) {
  3958. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3959. rc = -ENOMEM;
  3960. goto err_card;
  3961. }
  3962. debug_register_view(card->debug, &debug_hex_ascii_view);
  3963. card->read.ccwdev = gdev->cdev[0];
  3964. card->write.ccwdev = gdev->cdev[1];
  3965. card->data.ccwdev = gdev->cdev[2];
  3966. dev_set_drvdata(&gdev->dev, card);
  3967. card->gdev = gdev;
  3968. gdev->cdev[0]->handler = qeth_irq;
  3969. gdev->cdev[1]->handler = qeth_irq;
  3970. gdev->cdev[2]->handler = qeth_irq;
  3971. rc = qeth_determine_card_type(card);
  3972. if (rc) {
  3973. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3974. goto err_dbf;
  3975. }
  3976. rc = qeth_setup_card(card);
  3977. if (rc) {
  3978. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3979. goto err_dbf;
  3980. }
  3981. if (card->info.type == QETH_CARD_TYPE_OSN)
  3982. rc = qeth_core_create_osn_attributes(dev);
  3983. else
  3984. rc = qeth_core_create_device_attributes(dev);
  3985. if (rc)
  3986. goto err_dbf;
  3987. switch (card->info.type) {
  3988. case QETH_CARD_TYPE_OSN:
  3989. case QETH_CARD_TYPE_OSM:
  3990. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3991. if (rc)
  3992. goto err_attr;
  3993. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3994. if (rc)
  3995. goto err_disc;
  3996. case QETH_CARD_TYPE_OSD:
  3997. case QETH_CARD_TYPE_OSX:
  3998. default:
  3999. break;
  4000. }
  4001. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4002. list_add_tail(&card->list, &qeth_core_card_list.list);
  4003. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4004. qeth_determine_capabilities(card);
  4005. return 0;
  4006. err_disc:
  4007. qeth_core_free_discipline(card);
  4008. err_attr:
  4009. if (card->info.type == QETH_CARD_TYPE_OSN)
  4010. qeth_core_remove_osn_attributes(dev);
  4011. else
  4012. qeth_core_remove_device_attributes(dev);
  4013. err_dbf:
  4014. debug_unregister(card->debug);
  4015. err_card:
  4016. qeth_core_free_card(card);
  4017. err_dev:
  4018. put_device(dev);
  4019. return rc;
  4020. }
  4021. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4022. {
  4023. unsigned long flags;
  4024. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4025. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4026. if (card->info.type == QETH_CARD_TYPE_OSN) {
  4027. qeth_core_remove_osn_attributes(&gdev->dev);
  4028. } else {
  4029. qeth_core_remove_device_attributes(&gdev->dev);
  4030. }
  4031. if (card->discipline.ccwgdriver) {
  4032. card->discipline.ccwgdriver->remove(gdev);
  4033. qeth_core_free_discipline(card);
  4034. }
  4035. debug_unregister(card->debug);
  4036. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4037. list_del(&card->list);
  4038. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4039. qeth_core_free_card(card);
  4040. dev_set_drvdata(&gdev->dev, NULL);
  4041. put_device(&gdev->dev);
  4042. return;
  4043. }
  4044. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4045. {
  4046. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4047. int rc = 0;
  4048. int def_discipline;
  4049. if (!card->discipline.ccwgdriver) {
  4050. if (card->info.type == QETH_CARD_TYPE_IQD)
  4051. def_discipline = QETH_DISCIPLINE_LAYER3;
  4052. else
  4053. def_discipline = QETH_DISCIPLINE_LAYER2;
  4054. rc = qeth_core_load_discipline(card, def_discipline);
  4055. if (rc)
  4056. goto err;
  4057. rc = card->discipline.ccwgdriver->probe(card->gdev);
  4058. if (rc)
  4059. goto err;
  4060. }
  4061. rc = card->discipline.ccwgdriver->set_online(gdev);
  4062. err:
  4063. return rc;
  4064. }
  4065. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4066. {
  4067. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4068. return card->discipline.ccwgdriver->set_offline(gdev);
  4069. }
  4070. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4071. {
  4072. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4073. if (card->discipline.ccwgdriver &&
  4074. card->discipline.ccwgdriver->shutdown)
  4075. card->discipline.ccwgdriver->shutdown(gdev);
  4076. }
  4077. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4078. {
  4079. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4080. if (card->discipline.ccwgdriver &&
  4081. card->discipline.ccwgdriver->prepare)
  4082. return card->discipline.ccwgdriver->prepare(gdev);
  4083. return 0;
  4084. }
  4085. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4086. {
  4087. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4088. if (card->discipline.ccwgdriver &&
  4089. card->discipline.ccwgdriver->complete)
  4090. card->discipline.ccwgdriver->complete(gdev);
  4091. }
  4092. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4093. {
  4094. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4095. if (card->discipline.ccwgdriver &&
  4096. card->discipline.ccwgdriver->freeze)
  4097. return card->discipline.ccwgdriver->freeze(gdev);
  4098. return 0;
  4099. }
  4100. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4101. {
  4102. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4103. if (card->discipline.ccwgdriver &&
  4104. card->discipline.ccwgdriver->thaw)
  4105. return card->discipline.ccwgdriver->thaw(gdev);
  4106. return 0;
  4107. }
  4108. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4109. {
  4110. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4111. if (card->discipline.ccwgdriver &&
  4112. card->discipline.ccwgdriver->restore)
  4113. return card->discipline.ccwgdriver->restore(gdev);
  4114. return 0;
  4115. }
  4116. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4117. .driver = {
  4118. .owner = THIS_MODULE,
  4119. .name = "qeth",
  4120. },
  4121. .driver_id = 0xD8C5E3C8,
  4122. .probe = qeth_core_probe_device,
  4123. .remove = qeth_core_remove_device,
  4124. .set_online = qeth_core_set_online,
  4125. .set_offline = qeth_core_set_offline,
  4126. .shutdown = qeth_core_shutdown,
  4127. .prepare = qeth_core_prepare,
  4128. .complete = qeth_core_complete,
  4129. .freeze = qeth_core_freeze,
  4130. .thaw = qeth_core_thaw,
  4131. .restore = qeth_core_restore,
  4132. };
  4133. static ssize_t
  4134. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4135. size_t count)
  4136. {
  4137. int err;
  4138. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4139. qeth_core_ccwgroup_driver.driver_id);
  4140. if (err)
  4141. return err;
  4142. else
  4143. return count;
  4144. }
  4145. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4146. static struct {
  4147. const char str[ETH_GSTRING_LEN];
  4148. } qeth_ethtool_stats_keys[] = {
  4149. /* 0 */{"rx skbs"},
  4150. {"rx buffers"},
  4151. {"tx skbs"},
  4152. {"tx buffers"},
  4153. {"tx skbs no packing"},
  4154. {"tx buffers no packing"},
  4155. {"tx skbs packing"},
  4156. {"tx buffers packing"},
  4157. {"tx sg skbs"},
  4158. {"tx sg frags"},
  4159. /* 10 */{"rx sg skbs"},
  4160. {"rx sg frags"},
  4161. {"rx sg page allocs"},
  4162. {"tx large kbytes"},
  4163. {"tx large count"},
  4164. {"tx pk state ch n->p"},
  4165. {"tx pk state ch p->n"},
  4166. {"tx pk watermark low"},
  4167. {"tx pk watermark high"},
  4168. {"queue 0 buffer usage"},
  4169. /* 20 */{"queue 1 buffer usage"},
  4170. {"queue 2 buffer usage"},
  4171. {"queue 3 buffer usage"},
  4172. {"rx poll time"},
  4173. {"rx poll count"},
  4174. {"rx do_QDIO time"},
  4175. {"rx do_QDIO count"},
  4176. {"tx handler time"},
  4177. {"tx handler count"},
  4178. {"tx time"},
  4179. /* 30 */{"tx count"},
  4180. {"tx do_QDIO time"},
  4181. {"tx do_QDIO count"},
  4182. {"tx csum"},
  4183. {"tx lin"},
  4184. };
  4185. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4186. {
  4187. switch (stringset) {
  4188. case ETH_SS_STATS:
  4189. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4190. default:
  4191. return -EINVAL;
  4192. }
  4193. }
  4194. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4195. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4196. struct ethtool_stats *stats, u64 *data)
  4197. {
  4198. struct qeth_card *card = dev->ml_priv;
  4199. data[0] = card->stats.rx_packets -
  4200. card->perf_stats.initial_rx_packets;
  4201. data[1] = card->perf_stats.bufs_rec;
  4202. data[2] = card->stats.tx_packets -
  4203. card->perf_stats.initial_tx_packets;
  4204. data[3] = card->perf_stats.bufs_sent;
  4205. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4206. - card->perf_stats.skbs_sent_pack;
  4207. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4208. data[6] = card->perf_stats.skbs_sent_pack;
  4209. data[7] = card->perf_stats.bufs_sent_pack;
  4210. data[8] = card->perf_stats.sg_skbs_sent;
  4211. data[9] = card->perf_stats.sg_frags_sent;
  4212. data[10] = card->perf_stats.sg_skbs_rx;
  4213. data[11] = card->perf_stats.sg_frags_rx;
  4214. data[12] = card->perf_stats.sg_alloc_page_rx;
  4215. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4216. data[14] = card->perf_stats.large_send_cnt;
  4217. data[15] = card->perf_stats.sc_dp_p;
  4218. data[16] = card->perf_stats.sc_p_dp;
  4219. data[17] = QETH_LOW_WATERMARK_PACK;
  4220. data[18] = QETH_HIGH_WATERMARK_PACK;
  4221. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4222. data[20] = (card->qdio.no_out_queues > 1) ?
  4223. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4224. data[21] = (card->qdio.no_out_queues > 2) ?
  4225. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4226. data[22] = (card->qdio.no_out_queues > 3) ?
  4227. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4228. data[23] = card->perf_stats.inbound_time;
  4229. data[24] = card->perf_stats.inbound_cnt;
  4230. data[25] = card->perf_stats.inbound_do_qdio_time;
  4231. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4232. data[27] = card->perf_stats.outbound_handler_time;
  4233. data[28] = card->perf_stats.outbound_handler_cnt;
  4234. data[29] = card->perf_stats.outbound_time;
  4235. data[30] = card->perf_stats.outbound_cnt;
  4236. data[31] = card->perf_stats.outbound_do_qdio_time;
  4237. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4238. data[33] = card->perf_stats.tx_csum;
  4239. data[34] = card->perf_stats.tx_lin;
  4240. }
  4241. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4242. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4243. {
  4244. switch (stringset) {
  4245. case ETH_SS_STATS:
  4246. memcpy(data, &qeth_ethtool_stats_keys,
  4247. sizeof(qeth_ethtool_stats_keys));
  4248. break;
  4249. default:
  4250. WARN_ON(1);
  4251. break;
  4252. }
  4253. }
  4254. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4255. void qeth_core_get_drvinfo(struct net_device *dev,
  4256. struct ethtool_drvinfo *info)
  4257. {
  4258. struct qeth_card *card = dev->ml_priv;
  4259. if (card->options.layer2)
  4260. strcpy(info->driver, "qeth_l2");
  4261. else
  4262. strcpy(info->driver, "qeth_l3");
  4263. strcpy(info->version, "1.0");
  4264. strcpy(info->fw_version, card->info.mcl_level);
  4265. sprintf(info->bus_info, "%s/%s/%s",
  4266. CARD_RDEV_ID(card),
  4267. CARD_WDEV_ID(card),
  4268. CARD_DDEV_ID(card));
  4269. }
  4270. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4271. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4272. struct ethtool_cmd *ecmd)
  4273. {
  4274. struct qeth_card *card = netdev->ml_priv;
  4275. enum qeth_link_types link_type;
  4276. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4277. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4278. else
  4279. link_type = card->info.link_type;
  4280. ecmd->transceiver = XCVR_INTERNAL;
  4281. ecmd->supported = SUPPORTED_Autoneg;
  4282. ecmd->advertising = ADVERTISED_Autoneg;
  4283. ecmd->duplex = DUPLEX_FULL;
  4284. ecmd->autoneg = AUTONEG_ENABLE;
  4285. switch (link_type) {
  4286. case QETH_LINK_TYPE_FAST_ETH:
  4287. case QETH_LINK_TYPE_LANE_ETH100:
  4288. ecmd->supported |= SUPPORTED_10baseT_Half |
  4289. SUPPORTED_10baseT_Full |
  4290. SUPPORTED_100baseT_Half |
  4291. SUPPORTED_100baseT_Full |
  4292. SUPPORTED_TP;
  4293. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4294. ADVERTISED_10baseT_Full |
  4295. ADVERTISED_100baseT_Half |
  4296. ADVERTISED_100baseT_Full |
  4297. ADVERTISED_TP;
  4298. ecmd->speed = SPEED_100;
  4299. ecmd->port = PORT_TP;
  4300. break;
  4301. case QETH_LINK_TYPE_GBIT_ETH:
  4302. case QETH_LINK_TYPE_LANE_ETH1000:
  4303. ecmd->supported |= SUPPORTED_10baseT_Half |
  4304. SUPPORTED_10baseT_Full |
  4305. SUPPORTED_100baseT_Half |
  4306. SUPPORTED_100baseT_Full |
  4307. SUPPORTED_1000baseT_Half |
  4308. SUPPORTED_1000baseT_Full |
  4309. SUPPORTED_FIBRE;
  4310. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4311. ADVERTISED_10baseT_Full |
  4312. ADVERTISED_100baseT_Half |
  4313. ADVERTISED_100baseT_Full |
  4314. ADVERTISED_1000baseT_Half |
  4315. ADVERTISED_1000baseT_Full |
  4316. ADVERTISED_FIBRE;
  4317. ecmd->speed = SPEED_1000;
  4318. ecmd->port = PORT_FIBRE;
  4319. break;
  4320. case QETH_LINK_TYPE_10GBIT_ETH:
  4321. ecmd->supported |= SUPPORTED_10baseT_Half |
  4322. SUPPORTED_10baseT_Full |
  4323. SUPPORTED_100baseT_Half |
  4324. SUPPORTED_100baseT_Full |
  4325. SUPPORTED_1000baseT_Half |
  4326. SUPPORTED_1000baseT_Full |
  4327. SUPPORTED_10000baseT_Full |
  4328. SUPPORTED_FIBRE;
  4329. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4330. ADVERTISED_10baseT_Full |
  4331. ADVERTISED_100baseT_Half |
  4332. ADVERTISED_100baseT_Full |
  4333. ADVERTISED_1000baseT_Half |
  4334. ADVERTISED_1000baseT_Full |
  4335. ADVERTISED_10000baseT_Full |
  4336. ADVERTISED_FIBRE;
  4337. ecmd->speed = SPEED_10000;
  4338. ecmd->port = PORT_FIBRE;
  4339. break;
  4340. default:
  4341. ecmd->supported |= SUPPORTED_10baseT_Half |
  4342. SUPPORTED_10baseT_Full |
  4343. SUPPORTED_TP;
  4344. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4345. ADVERTISED_10baseT_Full |
  4346. ADVERTISED_TP;
  4347. ecmd->speed = SPEED_10;
  4348. ecmd->port = PORT_TP;
  4349. }
  4350. return 0;
  4351. }
  4352. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4353. static int __init qeth_core_init(void)
  4354. {
  4355. int rc;
  4356. pr_info("loading core functions\n");
  4357. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4358. rwlock_init(&qeth_core_card_list.rwlock);
  4359. rc = qeth_register_dbf_views();
  4360. if (rc)
  4361. goto out_err;
  4362. rc = ccw_driver_register(&qeth_ccw_driver);
  4363. if (rc)
  4364. goto ccw_err;
  4365. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4366. if (rc)
  4367. goto ccwgroup_err;
  4368. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4369. &driver_attr_group);
  4370. if (rc)
  4371. goto driver_err;
  4372. qeth_core_root_dev = root_device_register("qeth");
  4373. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4374. if (rc)
  4375. goto register_err;
  4376. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4377. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4378. if (!qeth_core_header_cache) {
  4379. rc = -ENOMEM;
  4380. goto slab_err;
  4381. }
  4382. return 0;
  4383. slab_err:
  4384. root_device_unregister(qeth_core_root_dev);
  4385. register_err:
  4386. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4387. &driver_attr_group);
  4388. driver_err:
  4389. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4390. ccwgroup_err:
  4391. ccw_driver_unregister(&qeth_ccw_driver);
  4392. ccw_err:
  4393. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4394. qeth_unregister_dbf_views();
  4395. out_err:
  4396. pr_err("Initializing the qeth device driver failed\n");
  4397. return rc;
  4398. }
  4399. static void __exit qeth_core_exit(void)
  4400. {
  4401. root_device_unregister(qeth_core_root_dev);
  4402. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4403. &driver_attr_group);
  4404. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4405. ccw_driver_unregister(&qeth_ccw_driver);
  4406. kmem_cache_destroy(qeth_core_header_cache);
  4407. qeth_unregister_dbf_views();
  4408. pr_info("core functions removed\n");
  4409. }
  4410. module_init(qeth_core_init);
  4411. module_exit(qeth_core_exit);
  4412. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4413. MODULE_DESCRIPTION("qeth core functions");
  4414. MODULE_LICENSE("GPL");