dwc3-omap.c 11 KB

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  1. /**
  2. * dwc3-omap.c - OMAP Specific Glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions, and the following disclaimer,
  14. * without modification.
  15. * 2. Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * 3. The names of the above-listed copyright holders may not be used
  19. * to endorse or promote products derived from this software without
  20. * specific prior written permission.
  21. *
  22. * ALTERNATIVELY, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2, as published by the Free
  24. * Software Foundation.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. */
  38. #include <linux/module.h>
  39. #include <linux/kernel.h>
  40. #include <linux/slab.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/platform_device.h>
  44. #include <linux/platform_data/dwc3-omap.h>
  45. #include <linux/usb/dwc3-omap.h>
  46. #include <linux/pm_runtime.h>
  47. #include <linux/dma-mapping.h>
  48. #include <linux/ioport.h>
  49. #include <linux/io.h>
  50. #include <linux/of.h>
  51. #include <linux/of_platform.h>
  52. #include <linux/usb/otg.h>
  53. /*
  54. * All these registers belong to OMAP's Wrapper around the
  55. * DesignWare USB3 Core.
  56. */
  57. #define USBOTGSS_REVISION 0x0000
  58. #define USBOTGSS_SYSCONFIG 0x0010
  59. #define USBOTGSS_IRQ_EOI 0x0020
  60. #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
  61. #define USBOTGSS_IRQSTATUS_0 0x0028
  62. #define USBOTGSS_IRQENABLE_SET_0 0x002c
  63. #define USBOTGSS_IRQENABLE_CLR_0 0x0030
  64. #define USBOTGSS_IRQSTATUS_RAW_1 0x0034
  65. #define USBOTGSS_IRQSTATUS_1 0x0038
  66. #define USBOTGSS_IRQENABLE_SET_1 0x003c
  67. #define USBOTGSS_IRQENABLE_CLR_1 0x0040
  68. #define USBOTGSS_UTMI_OTG_CTRL 0x0080
  69. #define USBOTGSS_UTMI_OTG_STATUS 0x0084
  70. #define USBOTGSS_MMRAM_OFFSET 0x0100
  71. #define USBOTGSS_FLADJ 0x0104
  72. #define USBOTGSS_DEBUG_CFG 0x0108
  73. #define USBOTGSS_DEBUG_DATA 0x010c
  74. /* SYSCONFIG REGISTER */
  75. #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
  76. /* IRQ_EOI REGISTER */
  77. #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
  78. /* IRQS0 BITS */
  79. #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
  80. /* IRQ1 BITS */
  81. #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
  82. #define USBOTGSS_IRQ1_OEVT (1 << 16)
  83. #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
  84. #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
  85. #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
  86. #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
  87. #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
  88. #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
  89. #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
  90. #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
  91. /* UTMI_OTG_CTRL REGISTER */
  92. #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
  93. #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
  94. #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
  95. #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
  96. /* UTMI_OTG_STATUS REGISTER */
  97. #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
  98. #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
  99. #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
  100. #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
  101. #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
  102. #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
  103. #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
  104. struct dwc3_omap {
  105. /* device lock */
  106. spinlock_t lock;
  107. struct device *dev;
  108. int irq;
  109. void __iomem *base;
  110. u32 dma_status:1;
  111. };
  112. struct dwc3_omap *_omap;
  113. static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
  114. {
  115. return readl(base + offset);
  116. }
  117. static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
  118. {
  119. writel(value, base + offset);
  120. }
  121. void dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
  122. {
  123. u32 val;
  124. struct dwc3_omap *omap = _omap;
  125. switch (status) {
  126. case OMAP_DWC3_ID_GROUND:
  127. dev_dbg(omap->dev, "ID GND\n");
  128. val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
  129. val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
  130. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  131. | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
  132. val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  133. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  134. dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
  135. break;
  136. case OMAP_DWC3_VBUS_VALID:
  137. dev_dbg(omap->dev, "VBUS Connect\n");
  138. val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
  139. val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
  140. val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
  141. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  142. | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  143. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  144. dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
  145. break;
  146. case OMAP_DWC3_ID_FLOAT:
  147. case OMAP_DWC3_VBUS_OFF:
  148. dev_dbg(omap->dev, "VBUS Disconnect\n");
  149. val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
  150. val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  151. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  152. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
  153. val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
  154. | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
  155. dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
  156. break;
  157. default:
  158. dev_dbg(omap->dev, "ID float\n");
  159. }
  160. return;
  161. }
  162. EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);
  163. static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
  164. {
  165. struct dwc3_omap *omap = _omap;
  166. u32 reg;
  167. spin_lock(&omap->lock);
  168. reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
  169. if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
  170. dev_dbg(omap->dev, "DMA Disable was Cleared\n");
  171. omap->dma_status = false;
  172. }
  173. if (reg & USBOTGSS_IRQ1_OEVT)
  174. dev_dbg(omap->dev, "OTG Event\n");
  175. if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
  176. dev_dbg(omap->dev, "DRVVBUS Rise\n");
  177. if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
  178. dev_dbg(omap->dev, "CHRGVBUS Rise\n");
  179. if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
  180. dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
  181. if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
  182. dev_dbg(omap->dev, "IDPULLUP Rise\n");
  183. if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
  184. dev_dbg(omap->dev, "DRVVBUS Fall\n");
  185. if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
  186. dev_dbg(omap->dev, "CHRGVBUS Fall\n");
  187. if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
  188. dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
  189. if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
  190. dev_dbg(omap->dev, "IDPULLUP Fall\n");
  191. dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
  192. reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
  193. dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
  194. spin_unlock(&omap->lock);
  195. return IRQ_HANDLED;
  196. }
  197. static int dwc3_omap_remove_core(struct device *dev, void *c)
  198. {
  199. struct platform_device *pdev = to_platform_device(dev);
  200. platform_device_unregister(pdev);
  201. return 0;
  202. }
  203. static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
  204. {
  205. u32 reg;
  206. /* enable all IRQs */
  207. reg = USBOTGSS_IRQO_COREIRQ_ST;
  208. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
  209. reg = (USBOTGSS_IRQ1_OEVT |
  210. USBOTGSS_IRQ1_DRVVBUS_RISE |
  211. USBOTGSS_IRQ1_CHRGVBUS_RISE |
  212. USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
  213. USBOTGSS_IRQ1_IDPULLUP_RISE |
  214. USBOTGSS_IRQ1_DRVVBUS_FALL |
  215. USBOTGSS_IRQ1_CHRGVBUS_FALL |
  216. USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
  217. USBOTGSS_IRQ1_IDPULLUP_FALL);
  218. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
  219. }
  220. static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
  221. {
  222. /* disable all IRQs */
  223. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, 0x00);
  224. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x00);
  225. }
  226. static int dwc3_omap_probe(struct platform_device *pdev)
  227. {
  228. struct device_node *node = pdev->dev.of_node;
  229. struct dwc3_omap *omap;
  230. struct resource *res;
  231. struct device *dev = &pdev->dev;
  232. int ret = -ENOMEM;
  233. int irq;
  234. int utmi_mode = 0;
  235. u32 reg;
  236. void __iomem *base;
  237. if (!node) {
  238. dev_err(dev, "device node not found\n");
  239. return -EINVAL;
  240. }
  241. omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
  242. if (!omap) {
  243. dev_err(dev, "not enough memory\n");
  244. return -ENOMEM;
  245. }
  246. platform_set_drvdata(pdev, omap);
  247. irq = platform_get_irq(pdev, 0);
  248. if (irq < 0) {
  249. dev_err(dev, "missing IRQ resource\n");
  250. return -EINVAL;
  251. }
  252. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  253. if (!res) {
  254. dev_err(dev, "missing memory base resource\n");
  255. return -EINVAL;
  256. }
  257. base = devm_ioremap_nocache(dev, res->start, resource_size(res));
  258. if (!base) {
  259. dev_err(dev, "ioremap failed\n");
  260. return -ENOMEM;
  261. }
  262. spin_lock_init(&omap->lock);
  263. omap->dev = dev;
  264. omap->irq = irq;
  265. omap->base = base;
  266. /*
  267. * REVISIT if we ever have two instances of the wrapper, we will be
  268. * in big trouble
  269. */
  270. _omap = omap;
  271. pm_runtime_enable(dev);
  272. ret = pm_runtime_get_sync(dev);
  273. if (ret < 0) {
  274. dev_err(dev, "get_sync failed with err %d\n", ret);
  275. return ret;
  276. }
  277. reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
  278. of_property_read_u32(node, "utmi-mode", &utmi_mode);
  279. switch (utmi_mode) {
  280. case DWC3_OMAP_UTMI_MODE_SW:
  281. reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  282. break;
  283. case DWC3_OMAP_UTMI_MODE_HW:
  284. reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  285. break;
  286. default:
  287. dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
  288. }
  289. dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
  290. /* check the DMA Status */
  291. reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
  292. omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
  293. ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
  294. "dwc3-omap", omap);
  295. if (ret) {
  296. dev_err(dev, "failed to request IRQ #%d --> %d\n",
  297. omap->irq, ret);
  298. return ret;
  299. }
  300. dwc3_omap_enable_irqs(omap);
  301. ret = of_platform_populate(node, NULL, NULL, dev);
  302. if (ret) {
  303. dev_err(&pdev->dev, "failed to create dwc3 core\n");
  304. return ret;
  305. }
  306. return 0;
  307. }
  308. static int dwc3_omap_remove(struct platform_device *pdev)
  309. {
  310. struct dwc3_omap *omap = platform_get_drvdata(pdev);
  311. dwc3_omap_disable_irqs(omap);
  312. pm_runtime_put_sync(&pdev->dev);
  313. pm_runtime_disable(&pdev->dev);
  314. device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
  315. return 0;
  316. }
  317. static const struct of_device_id of_dwc3_match[] = {
  318. {
  319. .compatible = "ti,dwc3"
  320. },
  321. { },
  322. };
  323. MODULE_DEVICE_TABLE(of, of_dwc3_match);
  324. static struct platform_driver dwc3_omap_driver = {
  325. .probe = dwc3_omap_probe,
  326. .remove = dwc3_omap_remove,
  327. .driver = {
  328. .name = "omap-dwc3",
  329. .of_match_table = of_dwc3_match,
  330. },
  331. };
  332. module_platform_driver(dwc3_omap_driver);
  333. MODULE_ALIAS("platform:omap-dwc3");
  334. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  335. MODULE_LICENSE("Dual BSD/GPL");
  336. MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");