wm8994.c 91 KB

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  1. /*
  2. * wm8994.c -- WM8994 ALSA SoC Audio driver
  3. *
  4. * Copyright 2009 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <sound/core.h>
  24. #include <sound/jack.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/soc.h>
  28. #include <sound/initval.h>
  29. #include <sound/tlv.h>
  30. #include <trace/events/asoc.h>
  31. #include <linux/mfd/wm8994/core.h>
  32. #include <linux/mfd/wm8994/registers.h>
  33. #include <linux/mfd/wm8994/pdata.h>
  34. #include <linux/mfd/wm8994/gpio.h>
  35. #include "wm8994.h"
  36. #include "wm_hubs.h"
  37. #define WM8994_NUM_DRC 3
  38. #define WM8994_NUM_EQ 3
  39. static int wm8994_drc_base[] = {
  40. WM8994_AIF1_DRC1_1,
  41. WM8994_AIF1_DRC2_1,
  42. WM8994_AIF2_DRC_1,
  43. };
  44. static int wm8994_retune_mobile_base[] = {
  45. WM8994_AIF1_DAC1_EQ_GAINS_1,
  46. WM8994_AIF1_DAC2_EQ_GAINS_1,
  47. WM8994_AIF2_EQ_GAINS_1,
  48. };
  49. static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  50. {
  51. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  52. struct wm8994 *control = wm8994->control_data;
  53. switch (reg) {
  54. case WM8994_GPIO_1:
  55. case WM8994_GPIO_2:
  56. case WM8994_GPIO_3:
  57. case WM8994_GPIO_4:
  58. case WM8994_GPIO_5:
  59. case WM8994_GPIO_6:
  60. case WM8994_GPIO_7:
  61. case WM8994_GPIO_8:
  62. case WM8994_GPIO_9:
  63. case WM8994_GPIO_10:
  64. case WM8994_GPIO_11:
  65. case WM8994_INTERRUPT_STATUS_1:
  66. case WM8994_INTERRUPT_STATUS_2:
  67. case WM8994_INTERRUPT_RAW_STATUS_2:
  68. return 1;
  69. case WM8958_DSP2_PROGRAM:
  70. case WM8958_DSP2_CONFIG:
  71. case WM8958_DSP2_EXECCONTROL:
  72. if (control->type == WM8958)
  73. return 1;
  74. else
  75. return 0;
  76. default:
  77. break;
  78. }
  79. if (reg >= WM8994_CACHE_SIZE)
  80. return 0;
  81. return wm8994_access_masks[reg].readable != 0;
  82. }
  83. static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  84. {
  85. if (reg >= WM8994_CACHE_SIZE)
  86. return 1;
  87. switch (reg) {
  88. case WM8994_SOFTWARE_RESET:
  89. case WM8994_CHIP_REVISION:
  90. case WM8994_DC_SERVO_1:
  91. case WM8994_DC_SERVO_READBACK:
  92. case WM8994_RATE_STATUS:
  93. case WM8994_LDO_1:
  94. case WM8994_LDO_2:
  95. case WM8958_DSP2_EXECCONTROL:
  96. case WM8958_MIC_DETECT_3:
  97. return 1;
  98. default:
  99. return 0;
  100. }
  101. }
  102. static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
  103. unsigned int value)
  104. {
  105. int ret;
  106. BUG_ON(reg > WM8994_MAX_REGISTER);
  107. if (!wm8994_volatile(codec, reg)) {
  108. ret = snd_soc_cache_write(codec, reg, value);
  109. if (ret != 0)
  110. dev_err(codec->dev, "Cache write to %x failed: %d\n",
  111. reg, ret);
  112. }
  113. return wm8994_reg_write(codec->control_data, reg, value);
  114. }
  115. static unsigned int wm8994_read(struct snd_soc_codec *codec,
  116. unsigned int reg)
  117. {
  118. unsigned int val;
  119. int ret;
  120. BUG_ON(reg > WM8994_MAX_REGISTER);
  121. if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
  122. reg < codec->driver->reg_cache_size) {
  123. ret = snd_soc_cache_read(codec, reg, &val);
  124. if (ret >= 0)
  125. return val;
  126. else
  127. dev_err(codec->dev, "Cache read from %x failed: %d\n",
  128. reg, ret);
  129. }
  130. return wm8994_reg_read(codec->control_data, reg);
  131. }
  132. static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
  133. {
  134. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  135. int rate;
  136. int reg1 = 0;
  137. int offset;
  138. if (aif)
  139. offset = 4;
  140. else
  141. offset = 0;
  142. switch (wm8994->sysclk[aif]) {
  143. case WM8994_SYSCLK_MCLK1:
  144. rate = wm8994->mclk[0];
  145. break;
  146. case WM8994_SYSCLK_MCLK2:
  147. reg1 |= 0x8;
  148. rate = wm8994->mclk[1];
  149. break;
  150. case WM8994_SYSCLK_FLL1:
  151. reg1 |= 0x10;
  152. rate = wm8994->fll[0].out;
  153. break;
  154. case WM8994_SYSCLK_FLL2:
  155. reg1 |= 0x18;
  156. rate = wm8994->fll[1].out;
  157. break;
  158. default:
  159. return -EINVAL;
  160. }
  161. if (rate >= 13500000) {
  162. rate /= 2;
  163. reg1 |= WM8994_AIF1CLK_DIV;
  164. dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
  165. aif + 1, rate);
  166. }
  167. if (rate && rate < 3000000)
  168. dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
  169. aif + 1, rate);
  170. wm8994->aifclk[aif] = rate;
  171. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
  172. WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
  173. reg1);
  174. return 0;
  175. }
  176. static int configure_clock(struct snd_soc_codec *codec)
  177. {
  178. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  179. int old, new;
  180. /* Bring up the AIF clocks first */
  181. configure_aif_clock(codec, 0);
  182. configure_aif_clock(codec, 1);
  183. /* Then switch CLK_SYS over to the higher of them; a change
  184. * can only happen as a result of a clocking change which can
  185. * only be made outside of DAPM so we can safely redo the
  186. * clocking.
  187. */
  188. /* If they're equal it doesn't matter which is used */
  189. if (wm8994->aifclk[0] == wm8994->aifclk[1])
  190. return 0;
  191. if (wm8994->aifclk[0] < wm8994->aifclk[1])
  192. new = WM8994_SYSCLK_SRC;
  193. else
  194. new = 0;
  195. old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
  196. /* If there's no change then we're done. */
  197. if (old == new)
  198. return 0;
  199. snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
  200. snd_soc_dapm_sync(&codec->dapm);
  201. return 0;
  202. }
  203. static int check_clk_sys(struct snd_soc_dapm_widget *source,
  204. struct snd_soc_dapm_widget *sink)
  205. {
  206. int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
  207. const char *clk;
  208. /* Check what we're currently using for CLK_SYS */
  209. if (reg & WM8994_SYSCLK_SRC)
  210. clk = "AIF2CLK";
  211. else
  212. clk = "AIF1CLK";
  213. return strcmp(source->name, clk) == 0;
  214. }
  215. static const char *sidetone_hpf_text[] = {
  216. "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
  217. };
  218. static const struct soc_enum sidetone_hpf =
  219. SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
  220. static const char *adc_hpf_text[] = {
  221. "HiFi", "Voice 1", "Voice 2", "Voice 3"
  222. };
  223. static const struct soc_enum aif1adc1_hpf =
  224. SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
  225. static const struct soc_enum aif1adc2_hpf =
  226. SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
  227. static const struct soc_enum aif2adc_hpf =
  228. SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
  229. static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
  230. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  231. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  232. static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
  233. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  234. #define WM8994_DRC_SWITCH(xname, reg, shift) \
  235. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  236. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  237. .put = wm8994_put_drc_sw, \
  238. .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
  239. static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
  240. struct snd_ctl_elem_value *ucontrol)
  241. {
  242. struct soc_mixer_control *mc =
  243. (struct soc_mixer_control *)kcontrol->private_value;
  244. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  245. int mask, ret;
  246. /* Can't enable both ADC and DAC paths simultaneously */
  247. if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
  248. mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
  249. WM8994_AIF1ADC1R_DRC_ENA_MASK;
  250. else
  251. mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
  252. ret = snd_soc_read(codec, mc->reg);
  253. if (ret < 0)
  254. return ret;
  255. if (ret & mask)
  256. return -EINVAL;
  257. return snd_soc_put_volsw(kcontrol, ucontrol);
  258. }
  259. static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
  260. {
  261. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  262. struct wm8994_pdata *pdata = wm8994->pdata;
  263. int base = wm8994_drc_base[drc];
  264. int cfg = wm8994->drc_cfg[drc];
  265. int save, i;
  266. /* Save any enables; the configuration should clear them. */
  267. save = snd_soc_read(codec, base);
  268. save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
  269. WM8994_AIF1ADC1R_DRC_ENA;
  270. for (i = 0; i < WM8994_DRC_REGS; i++)
  271. snd_soc_update_bits(codec, base + i, 0xffff,
  272. pdata->drc_cfgs[cfg].regs[i]);
  273. snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
  274. WM8994_AIF1ADC1L_DRC_ENA |
  275. WM8994_AIF1ADC1R_DRC_ENA, save);
  276. }
  277. /* Icky as hell but saves code duplication */
  278. static int wm8994_get_drc(const char *name)
  279. {
  280. if (strcmp(name, "AIF1DRC1 Mode") == 0)
  281. return 0;
  282. if (strcmp(name, "AIF1DRC2 Mode") == 0)
  283. return 1;
  284. if (strcmp(name, "AIF2DRC Mode") == 0)
  285. return 2;
  286. return -EINVAL;
  287. }
  288. static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
  289. struct snd_ctl_elem_value *ucontrol)
  290. {
  291. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  292. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  293. struct wm8994_pdata *pdata = wm8994->pdata;
  294. int drc = wm8994_get_drc(kcontrol->id.name);
  295. int value = ucontrol->value.integer.value[0];
  296. if (drc < 0)
  297. return drc;
  298. if (value >= pdata->num_drc_cfgs)
  299. return -EINVAL;
  300. wm8994->drc_cfg[drc] = value;
  301. wm8994_set_drc(codec, drc);
  302. return 0;
  303. }
  304. static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
  305. struct snd_ctl_elem_value *ucontrol)
  306. {
  307. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  308. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  309. int drc = wm8994_get_drc(kcontrol->id.name);
  310. ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
  311. return 0;
  312. }
  313. static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
  314. {
  315. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  316. struct wm8994_pdata *pdata = wm8994->pdata;
  317. int base = wm8994_retune_mobile_base[block];
  318. int iface, best, best_val, save, i, cfg;
  319. if (!pdata || !wm8994->num_retune_mobile_texts)
  320. return;
  321. switch (block) {
  322. case 0:
  323. case 1:
  324. iface = 0;
  325. break;
  326. case 2:
  327. iface = 1;
  328. break;
  329. default:
  330. return;
  331. }
  332. /* Find the version of the currently selected configuration
  333. * with the nearest sample rate. */
  334. cfg = wm8994->retune_mobile_cfg[block];
  335. best = 0;
  336. best_val = INT_MAX;
  337. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  338. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  339. wm8994->retune_mobile_texts[cfg]) == 0 &&
  340. abs(pdata->retune_mobile_cfgs[i].rate
  341. - wm8994->dac_rates[iface]) < best_val) {
  342. best = i;
  343. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  344. - wm8994->dac_rates[iface]);
  345. }
  346. }
  347. dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
  348. block,
  349. pdata->retune_mobile_cfgs[best].name,
  350. pdata->retune_mobile_cfgs[best].rate,
  351. wm8994->dac_rates[iface]);
  352. /* The EQ will be disabled while reconfiguring it, remember the
  353. * current configuration.
  354. */
  355. save = snd_soc_read(codec, base);
  356. save &= WM8994_AIF1DAC1_EQ_ENA;
  357. for (i = 0; i < WM8994_EQ_REGS; i++)
  358. snd_soc_update_bits(codec, base + i, 0xffff,
  359. pdata->retune_mobile_cfgs[best].regs[i]);
  360. snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
  361. }
  362. /* Icky as hell but saves code duplication */
  363. static int wm8994_get_retune_mobile_block(const char *name)
  364. {
  365. if (strcmp(name, "AIF1.1 EQ Mode") == 0)
  366. return 0;
  367. if (strcmp(name, "AIF1.2 EQ Mode") == 0)
  368. return 1;
  369. if (strcmp(name, "AIF2 EQ Mode") == 0)
  370. return 2;
  371. return -EINVAL;
  372. }
  373. static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  374. struct snd_ctl_elem_value *ucontrol)
  375. {
  376. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  377. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  378. struct wm8994_pdata *pdata = wm8994->pdata;
  379. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  380. int value = ucontrol->value.integer.value[0];
  381. if (block < 0)
  382. return block;
  383. if (value >= pdata->num_retune_mobile_cfgs)
  384. return -EINVAL;
  385. wm8994->retune_mobile_cfg[block] = value;
  386. wm8994_set_retune_mobile(codec, block);
  387. return 0;
  388. }
  389. static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  390. struct snd_ctl_elem_value *ucontrol)
  391. {
  392. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  393. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  394. int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
  395. ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
  396. return 0;
  397. }
  398. static const char *aif_chan_src_text[] = {
  399. "Left", "Right"
  400. };
  401. static const struct soc_enum aif1adcl_src =
  402. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
  403. static const struct soc_enum aif1adcr_src =
  404. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
  405. static const struct soc_enum aif2adcl_src =
  406. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
  407. static const struct soc_enum aif2adcr_src =
  408. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
  409. static const struct soc_enum aif1dacl_src =
  410. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
  411. static const struct soc_enum aif1dacr_src =
  412. SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
  413. static const struct soc_enum aif2dacl_src =
  414. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
  415. static const struct soc_enum aif2dacr_src =
  416. SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
  417. static const char *osr_text[] = {
  418. "Low Power", "High Performance",
  419. };
  420. static const struct soc_enum dac_osr =
  421. SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
  422. static const struct soc_enum adc_osr =
  423. SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
  424. static const struct snd_kcontrol_new wm8994_snd_controls[] = {
  425. SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
  426. WM8994_AIF1_ADC1_RIGHT_VOLUME,
  427. 1, 119, 0, digital_tlv),
  428. SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
  429. WM8994_AIF1_ADC2_RIGHT_VOLUME,
  430. 1, 119, 0, digital_tlv),
  431. SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
  432. WM8994_AIF2_ADC_RIGHT_VOLUME,
  433. 1, 119, 0, digital_tlv),
  434. SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
  435. SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
  436. SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
  437. SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
  438. SOC_ENUM("AIF1DACL Source", aif1dacl_src),
  439. SOC_ENUM("AIF1DACR Source", aif1dacr_src),
  440. SOC_ENUM("AIF2DACL Source", aif2dacl_src),
  441. SOC_ENUM("AIF2DACR Source", aif2dacr_src),
  442. SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
  443. WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  444. SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
  445. WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  446. SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
  447. WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  448. SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
  449. SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
  450. SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
  451. SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
  452. SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
  453. WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
  454. WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
  455. WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
  456. WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
  457. WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
  458. WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
  459. WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
  460. WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
  461. WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
  462. SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  463. 5, 12, 0, st_tlv),
  464. SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
  465. 0, 12, 0, st_tlv),
  466. SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  467. 5, 12, 0, st_tlv),
  468. SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
  469. 0, 12, 0, st_tlv),
  470. SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
  471. SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
  472. SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
  473. SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
  474. SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
  475. SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
  476. SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
  477. SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
  478. SOC_ENUM("ADC OSR", adc_osr),
  479. SOC_ENUM("DAC OSR", dac_osr),
  480. SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
  481. WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  482. SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
  483. WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
  484. SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
  485. WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
  486. SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
  487. WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
  488. SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
  489. 6, 1, 1, wm_hubs_spkmix_tlv),
  490. SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
  491. 2, 1, 1, wm_hubs_spkmix_tlv),
  492. SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
  493. 6, 1, 1, wm_hubs_spkmix_tlv),
  494. SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
  495. 2, 1, 1, wm_hubs_spkmix_tlv),
  496. SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
  497. 10, 15, 0, wm8994_3d_tlv),
  498. SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
  499. 8, 1, 0),
  500. SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
  501. 10, 15, 0, wm8994_3d_tlv),
  502. SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
  503. 8, 1, 0),
  504. SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
  505. 10, 15, 0, wm8994_3d_tlv),
  506. SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
  507. 8, 1, 0),
  508. };
  509. static const struct snd_kcontrol_new wm8994_eq_controls[] = {
  510. SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
  511. eq_tlv),
  512. SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
  513. eq_tlv),
  514. SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
  515. eq_tlv),
  516. SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
  517. eq_tlv),
  518. SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
  519. eq_tlv),
  520. SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
  521. eq_tlv),
  522. SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
  523. eq_tlv),
  524. SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
  525. eq_tlv),
  526. SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
  527. eq_tlv),
  528. SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
  529. eq_tlv),
  530. SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
  531. eq_tlv),
  532. SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
  533. eq_tlv),
  534. SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
  535. eq_tlv),
  536. SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
  537. eq_tlv),
  538. SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
  539. eq_tlv),
  540. };
  541. static const struct snd_kcontrol_new wm8958_snd_controls[] = {
  542. SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
  543. };
  544. static int clk_sys_event(struct snd_soc_dapm_widget *w,
  545. struct snd_kcontrol *kcontrol, int event)
  546. {
  547. struct snd_soc_codec *codec = w->codec;
  548. switch (event) {
  549. case SND_SOC_DAPM_PRE_PMU:
  550. return configure_clock(codec);
  551. case SND_SOC_DAPM_POST_PMD:
  552. configure_clock(codec);
  553. break;
  554. }
  555. return 0;
  556. }
  557. static void wm8994_update_class_w(struct snd_soc_codec *codec)
  558. {
  559. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  560. int enable = 1;
  561. int source = 0; /* GCC flow analysis can't track enable */
  562. int reg, reg_r;
  563. /* Only support direct DAC->headphone paths */
  564. reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
  565. if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
  566. dev_vdbg(codec->dev, "HPL connected to output mixer\n");
  567. enable = 0;
  568. }
  569. reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
  570. if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
  571. dev_vdbg(codec->dev, "HPR connected to output mixer\n");
  572. enable = 0;
  573. }
  574. /* We also need the same setting for L/R and only one path */
  575. reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
  576. switch (reg) {
  577. case WM8994_AIF2DACL_TO_DAC1L:
  578. dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
  579. source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  580. break;
  581. case WM8994_AIF1DAC2L_TO_DAC1L:
  582. dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
  583. source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  584. break;
  585. case WM8994_AIF1DAC1L_TO_DAC1L:
  586. dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
  587. source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
  588. break;
  589. default:
  590. dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
  591. enable = 0;
  592. break;
  593. }
  594. reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
  595. if (reg_r != reg) {
  596. dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
  597. enable = 0;
  598. }
  599. if (enable) {
  600. dev_dbg(codec->dev, "Class W enabled\n");
  601. snd_soc_update_bits(codec, WM8994_CLASS_W_1,
  602. WM8994_CP_DYN_PWR |
  603. WM8994_CP_DYN_SRC_SEL_MASK,
  604. source | WM8994_CP_DYN_PWR);
  605. wm8994->hubs.class_w = true;
  606. } else {
  607. dev_dbg(codec->dev, "Class W disabled\n");
  608. snd_soc_update_bits(codec, WM8994_CLASS_W_1,
  609. WM8994_CP_DYN_PWR, 0);
  610. wm8994->hubs.class_w = false;
  611. }
  612. }
  613. static int late_enable_ev(struct snd_soc_dapm_widget *w,
  614. struct snd_kcontrol *kcontrol, int event)
  615. {
  616. struct snd_soc_codec *codec = w->codec;
  617. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  618. switch (event) {
  619. case SND_SOC_DAPM_PRE_PMU:
  620. if (wm8994->aif1clk_enable) {
  621. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  622. WM8994_AIF1CLK_ENA_MASK,
  623. WM8994_AIF1CLK_ENA);
  624. wm8994->aif1clk_enable = 0;
  625. }
  626. if (wm8994->aif2clk_enable) {
  627. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  628. WM8994_AIF2CLK_ENA_MASK,
  629. WM8994_AIF2CLK_ENA);
  630. wm8994->aif2clk_enable = 0;
  631. }
  632. break;
  633. }
  634. /* We may also have postponed startup of DSP, handle that. */
  635. wm8958_aif_ev(w, kcontrol, event);
  636. return 0;
  637. }
  638. static int late_disable_ev(struct snd_soc_dapm_widget *w,
  639. struct snd_kcontrol *kcontrol, int event)
  640. {
  641. struct snd_soc_codec *codec = w->codec;
  642. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  643. switch (event) {
  644. case SND_SOC_DAPM_POST_PMD:
  645. if (wm8994->aif1clk_disable) {
  646. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  647. WM8994_AIF1CLK_ENA_MASK, 0);
  648. wm8994->aif1clk_disable = 0;
  649. }
  650. if (wm8994->aif2clk_disable) {
  651. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  652. WM8994_AIF2CLK_ENA_MASK, 0);
  653. wm8994->aif2clk_disable = 0;
  654. }
  655. break;
  656. }
  657. return 0;
  658. }
  659. static int aif1clk_ev(struct snd_soc_dapm_widget *w,
  660. struct snd_kcontrol *kcontrol, int event)
  661. {
  662. struct snd_soc_codec *codec = w->codec;
  663. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  664. switch (event) {
  665. case SND_SOC_DAPM_PRE_PMU:
  666. wm8994->aif1clk_enable = 1;
  667. break;
  668. case SND_SOC_DAPM_POST_PMD:
  669. wm8994->aif1clk_disable = 1;
  670. break;
  671. }
  672. return 0;
  673. }
  674. static int aif2clk_ev(struct snd_soc_dapm_widget *w,
  675. struct snd_kcontrol *kcontrol, int event)
  676. {
  677. struct snd_soc_codec *codec = w->codec;
  678. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  679. switch (event) {
  680. case SND_SOC_DAPM_PRE_PMU:
  681. wm8994->aif2clk_enable = 1;
  682. break;
  683. case SND_SOC_DAPM_POST_PMD:
  684. wm8994->aif2clk_disable = 1;
  685. break;
  686. }
  687. return 0;
  688. }
  689. static int adc_mux_ev(struct snd_soc_dapm_widget *w,
  690. struct snd_kcontrol *kcontrol, int event)
  691. {
  692. late_enable_ev(w, kcontrol, event);
  693. return 0;
  694. }
  695. static int micbias_ev(struct snd_soc_dapm_widget *w,
  696. struct snd_kcontrol *kcontrol, int event)
  697. {
  698. late_enable_ev(w, kcontrol, event);
  699. return 0;
  700. }
  701. static int dac_ev(struct snd_soc_dapm_widget *w,
  702. struct snd_kcontrol *kcontrol, int event)
  703. {
  704. struct snd_soc_codec *codec = w->codec;
  705. unsigned int mask = 1 << w->shift;
  706. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  707. mask, mask);
  708. return 0;
  709. }
  710. static const char *hp_mux_text[] = {
  711. "Mixer",
  712. "DAC",
  713. };
  714. #define WM8994_HP_ENUM(xname, xenum) \
  715. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  716. .info = snd_soc_info_enum_double, \
  717. .get = snd_soc_dapm_get_enum_double, \
  718. .put = wm8994_put_hp_enum, \
  719. .private_value = (unsigned long)&xenum }
  720. static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
  721. struct snd_ctl_elem_value *ucontrol)
  722. {
  723. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  724. struct snd_soc_dapm_widget *w = wlist->widgets[0];
  725. struct snd_soc_codec *codec = w->codec;
  726. int ret;
  727. ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
  728. wm8994_update_class_w(codec);
  729. return ret;
  730. }
  731. static const struct soc_enum hpl_enum =
  732. SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
  733. static const struct snd_kcontrol_new hpl_mux =
  734. WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
  735. static const struct soc_enum hpr_enum =
  736. SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
  737. static const struct snd_kcontrol_new hpr_mux =
  738. WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
  739. static const char *adc_mux_text[] = {
  740. "ADC",
  741. "DMIC",
  742. };
  743. static const struct soc_enum adc_enum =
  744. SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
  745. static const struct snd_kcontrol_new adcl_mux =
  746. SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
  747. static const struct snd_kcontrol_new adcr_mux =
  748. SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
  749. static const struct snd_kcontrol_new left_speaker_mixer[] = {
  750. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
  751. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
  752. SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
  753. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
  754. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
  755. };
  756. static const struct snd_kcontrol_new right_speaker_mixer[] = {
  757. SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
  758. SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
  759. SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
  760. SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
  761. SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
  762. };
  763. /* Debugging; dump chip status after DAPM transitions */
  764. static int post_ev(struct snd_soc_dapm_widget *w,
  765. struct snd_kcontrol *kcontrol, int event)
  766. {
  767. struct snd_soc_codec *codec = w->codec;
  768. dev_dbg(codec->dev, "SRC status: %x\n",
  769. snd_soc_read(codec,
  770. WM8994_RATE_STATUS));
  771. return 0;
  772. }
  773. static const struct snd_kcontrol_new aif1adc1l_mix[] = {
  774. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  775. 1, 1, 0),
  776. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
  777. 0, 1, 0),
  778. };
  779. static const struct snd_kcontrol_new aif1adc1r_mix[] = {
  780. SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  781. 1, 1, 0),
  782. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
  783. 0, 1, 0),
  784. };
  785. static const struct snd_kcontrol_new aif1adc2l_mix[] = {
  786. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  787. 1, 1, 0),
  788. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
  789. 0, 1, 0),
  790. };
  791. static const struct snd_kcontrol_new aif1adc2r_mix[] = {
  792. SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  793. 1, 1, 0),
  794. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
  795. 0, 1, 0),
  796. };
  797. static const struct snd_kcontrol_new aif2dac2l_mix[] = {
  798. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  799. 5, 1, 0),
  800. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  801. 4, 1, 0),
  802. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  803. 2, 1, 0),
  804. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  805. 1, 1, 0),
  806. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
  807. 0, 1, 0),
  808. };
  809. static const struct snd_kcontrol_new aif2dac2r_mix[] = {
  810. SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  811. 5, 1, 0),
  812. SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  813. 4, 1, 0),
  814. SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  815. 2, 1, 0),
  816. SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  817. 1, 1, 0),
  818. SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
  819. 0, 1, 0),
  820. };
  821. #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
  822. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  823. .info = snd_soc_info_volsw, \
  824. .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
  825. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
  826. static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
  827. struct snd_ctl_elem_value *ucontrol)
  828. {
  829. struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
  830. struct snd_soc_dapm_widget *w = wlist->widgets[0];
  831. struct snd_soc_codec *codec = w->codec;
  832. int ret;
  833. ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
  834. wm8994_update_class_w(codec);
  835. return ret;
  836. }
  837. static const struct snd_kcontrol_new dac1l_mix[] = {
  838. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  839. 5, 1, 0),
  840. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  841. 4, 1, 0),
  842. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  843. 2, 1, 0),
  844. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  845. 1, 1, 0),
  846. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
  847. 0, 1, 0),
  848. };
  849. static const struct snd_kcontrol_new dac1r_mix[] = {
  850. WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  851. 5, 1, 0),
  852. WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  853. 4, 1, 0),
  854. WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  855. 2, 1, 0),
  856. WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  857. 1, 1, 0),
  858. WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
  859. 0, 1, 0),
  860. };
  861. static const char *sidetone_text[] = {
  862. "ADC/DMIC1", "DMIC2",
  863. };
  864. static const struct soc_enum sidetone1_enum =
  865. SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
  866. static const struct snd_kcontrol_new sidetone1_mux =
  867. SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
  868. static const struct soc_enum sidetone2_enum =
  869. SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
  870. static const struct snd_kcontrol_new sidetone2_mux =
  871. SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
  872. static const char *aif1dac_text[] = {
  873. "AIF1DACDAT", "AIF3DACDAT",
  874. };
  875. static const struct soc_enum aif1dac_enum =
  876. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
  877. static const struct snd_kcontrol_new aif1dac_mux =
  878. SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
  879. static const char *aif2dac_text[] = {
  880. "AIF2DACDAT", "AIF3DACDAT",
  881. };
  882. static const struct soc_enum aif2dac_enum =
  883. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
  884. static const struct snd_kcontrol_new aif2dac_mux =
  885. SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
  886. static const char *aif2adc_text[] = {
  887. "AIF2ADCDAT", "AIF3DACDAT",
  888. };
  889. static const struct soc_enum aif2adc_enum =
  890. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
  891. static const struct snd_kcontrol_new aif2adc_mux =
  892. SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
  893. static const char *aif3adc_text[] = {
  894. "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
  895. };
  896. static const struct soc_enum wm8994_aif3adc_enum =
  897. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
  898. static const struct snd_kcontrol_new wm8994_aif3adc_mux =
  899. SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
  900. static const struct soc_enum wm8958_aif3adc_enum =
  901. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
  902. static const struct snd_kcontrol_new wm8958_aif3adc_mux =
  903. SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
  904. static const char *mono_pcm_out_text[] = {
  905. "None", "AIF2ADCL", "AIF2ADCR",
  906. };
  907. static const struct soc_enum mono_pcm_out_enum =
  908. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
  909. static const struct snd_kcontrol_new mono_pcm_out_mux =
  910. SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
  911. static const char *aif2dac_src_text[] = {
  912. "AIF2", "AIF3",
  913. };
  914. /* Note that these two control shouldn't be simultaneously switched to AIF3 */
  915. static const struct soc_enum aif2dacl_src_enum =
  916. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
  917. static const struct snd_kcontrol_new aif2dacl_src_mux =
  918. SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
  919. static const struct soc_enum aif2dacr_src_enum =
  920. SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
  921. static const struct snd_kcontrol_new aif2dacr_src_mux =
  922. SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
  923. static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
  924. SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
  925. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  926. SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
  927. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  928. SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  929. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  930. SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  931. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  932. SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  933. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  934. SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  935. late_enable_ev, SND_SOC_DAPM_PRE_PMU),
  936. SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
  937. };
  938. static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
  939. SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
  940. SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
  941. };
  942. static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
  943. SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
  944. dac_ev, SND_SOC_DAPM_PRE_PMU),
  945. SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
  946. dac_ev, SND_SOC_DAPM_PRE_PMU),
  947. SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
  948. dac_ev, SND_SOC_DAPM_PRE_PMU),
  949. SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
  950. dac_ev, SND_SOC_DAPM_PRE_PMU),
  951. };
  952. static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
  953. SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
  954. SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
  955. SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
  956. SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
  957. };
  958. static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
  959. SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
  960. adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
  961. SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
  962. adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
  963. };
  964. static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
  965. SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
  966. SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
  967. };
  968. static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
  969. SND_SOC_DAPM_INPUT("DMIC1DAT"),
  970. SND_SOC_DAPM_INPUT("DMIC2DAT"),
  971. SND_SOC_DAPM_INPUT("Clock"),
  972. SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
  973. SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
  974. SND_SOC_DAPM_PRE_PMU),
  975. SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
  976. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  977. SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
  978. SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
  979. SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
  980. SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
  981. 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
  982. SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
  983. 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
  984. SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
  985. WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
  986. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  987. SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
  988. WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
  989. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  990. SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
  991. 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
  992. SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
  993. 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
  994. SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
  995. WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
  996. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  997. SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
  998. WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
  999. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  1000. SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
  1001. aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
  1002. SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
  1003. aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
  1004. SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
  1005. aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
  1006. SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
  1007. aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
  1008. SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
  1009. aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
  1010. SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
  1011. aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
  1012. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
  1013. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
  1014. SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
  1015. dac1l_mix, ARRAY_SIZE(dac1l_mix)),
  1016. SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
  1017. dac1r_mix, ARRAY_SIZE(dac1r_mix)),
  1018. SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
  1019. WM8994_POWER_MANAGEMENT_4, 13, 0),
  1020. SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
  1021. WM8994_POWER_MANAGEMENT_4, 12, 0),
  1022. SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
  1023. WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
  1024. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1025. SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
  1026. WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
  1027. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  1028. SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  1029. SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  1030. SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  1031. SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  1032. SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
  1033. SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
  1034. SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
  1035. SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
  1036. SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
  1037. SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
  1038. SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
  1039. SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
  1040. SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
  1041. SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
  1042. /* Power is done with the muxes since the ADC power also controls the
  1043. * downsampling chain, the chip will automatically manage the analogue
  1044. * specific portions.
  1045. */
  1046. SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
  1047. SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
  1048. SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
  1049. SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
  1050. SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
  1051. left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
  1052. SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
  1053. right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
  1054. SND_SOC_DAPM_POST("Debug log", post_ev),
  1055. };
  1056. static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
  1057. SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
  1058. };
  1059. static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
  1060. SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
  1061. SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
  1062. SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
  1063. SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
  1064. };
  1065. static const struct snd_soc_dapm_route intercon[] = {
  1066. { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
  1067. { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
  1068. { "DSP1CLK", NULL, "CLK_SYS" },
  1069. { "DSP2CLK", NULL, "CLK_SYS" },
  1070. { "DSPINTCLK", NULL, "CLK_SYS" },
  1071. { "AIF1ADC1L", NULL, "AIF1CLK" },
  1072. { "AIF1ADC1L", NULL, "DSP1CLK" },
  1073. { "AIF1ADC1R", NULL, "AIF1CLK" },
  1074. { "AIF1ADC1R", NULL, "DSP1CLK" },
  1075. { "AIF1ADC1R", NULL, "DSPINTCLK" },
  1076. { "AIF1DAC1L", NULL, "AIF1CLK" },
  1077. { "AIF1DAC1L", NULL, "DSP1CLK" },
  1078. { "AIF1DAC1R", NULL, "AIF1CLK" },
  1079. { "AIF1DAC1R", NULL, "DSP1CLK" },
  1080. { "AIF1DAC1R", NULL, "DSPINTCLK" },
  1081. { "AIF1ADC2L", NULL, "AIF1CLK" },
  1082. { "AIF1ADC2L", NULL, "DSP1CLK" },
  1083. { "AIF1ADC2R", NULL, "AIF1CLK" },
  1084. { "AIF1ADC2R", NULL, "DSP1CLK" },
  1085. { "AIF1ADC2R", NULL, "DSPINTCLK" },
  1086. { "AIF1DAC2L", NULL, "AIF1CLK" },
  1087. { "AIF1DAC2L", NULL, "DSP1CLK" },
  1088. { "AIF1DAC2R", NULL, "AIF1CLK" },
  1089. { "AIF1DAC2R", NULL, "DSP1CLK" },
  1090. { "AIF1DAC2R", NULL, "DSPINTCLK" },
  1091. { "AIF2ADCL", NULL, "AIF2CLK" },
  1092. { "AIF2ADCL", NULL, "DSP2CLK" },
  1093. { "AIF2ADCR", NULL, "AIF2CLK" },
  1094. { "AIF2ADCR", NULL, "DSP2CLK" },
  1095. { "AIF2ADCR", NULL, "DSPINTCLK" },
  1096. { "AIF2DACL", NULL, "AIF2CLK" },
  1097. { "AIF2DACL", NULL, "DSP2CLK" },
  1098. { "AIF2DACR", NULL, "AIF2CLK" },
  1099. { "AIF2DACR", NULL, "DSP2CLK" },
  1100. { "AIF2DACR", NULL, "DSPINTCLK" },
  1101. { "DMIC1L", NULL, "DMIC1DAT" },
  1102. { "DMIC1L", NULL, "CLK_SYS" },
  1103. { "DMIC1R", NULL, "DMIC1DAT" },
  1104. { "DMIC1R", NULL, "CLK_SYS" },
  1105. { "DMIC2L", NULL, "DMIC2DAT" },
  1106. { "DMIC2L", NULL, "CLK_SYS" },
  1107. { "DMIC2R", NULL, "DMIC2DAT" },
  1108. { "DMIC2R", NULL, "CLK_SYS" },
  1109. { "ADCL", NULL, "AIF1CLK" },
  1110. { "ADCL", NULL, "DSP1CLK" },
  1111. { "ADCL", NULL, "DSPINTCLK" },
  1112. { "ADCR", NULL, "AIF1CLK" },
  1113. { "ADCR", NULL, "DSP1CLK" },
  1114. { "ADCR", NULL, "DSPINTCLK" },
  1115. { "ADCL Mux", "ADC", "ADCL" },
  1116. { "ADCL Mux", "DMIC", "DMIC1L" },
  1117. { "ADCR Mux", "ADC", "ADCR" },
  1118. { "ADCR Mux", "DMIC", "DMIC1R" },
  1119. { "DAC1L", NULL, "AIF1CLK" },
  1120. { "DAC1L", NULL, "DSP1CLK" },
  1121. { "DAC1L", NULL, "DSPINTCLK" },
  1122. { "DAC1R", NULL, "AIF1CLK" },
  1123. { "DAC1R", NULL, "DSP1CLK" },
  1124. { "DAC1R", NULL, "DSPINTCLK" },
  1125. { "DAC2L", NULL, "AIF2CLK" },
  1126. { "DAC2L", NULL, "DSP2CLK" },
  1127. { "DAC2L", NULL, "DSPINTCLK" },
  1128. { "DAC2R", NULL, "AIF2DACR" },
  1129. { "DAC2R", NULL, "AIF2CLK" },
  1130. { "DAC2R", NULL, "DSP2CLK" },
  1131. { "DAC2R", NULL, "DSPINTCLK" },
  1132. { "TOCLK", NULL, "CLK_SYS" },
  1133. /* AIF1 outputs */
  1134. { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
  1135. { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
  1136. { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  1137. { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
  1138. { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
  1139. { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  1140. { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
  1141. { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
  1142. { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  1143. { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
  1144. { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
  1145. { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  1146. /* Pin level routing for AIF3 */
  1147. { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
  1148. { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
  1149. { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
  1150. { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
  1151. { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
  1152. { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  1153. { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
  1154. { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
  1155. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
  1156. { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
  1157. { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
  1158. /* DAC1 inputs */
  1159. { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
  1160. { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  1161. { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  1162. { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1163. { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1164. { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
  1165. { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  1166. { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  1167. { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1168. { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1169. /* DAC2/AIF2 outputs */
  1170. { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
  1171. { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
  1172. { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
  1173. { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
  1174. { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1175. { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1176. { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
  1177. { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
  1178. { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
  1179. { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
  1180. { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
  1181. { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
  1182. { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
  1183. { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
  1184. { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
  1185. { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
  1186. { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
  1187. /* AIF3 output */
  1188. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
  1189. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
  1190. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
  1191. { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
  1192. { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
  1193. { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
  1194. { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
  1195. { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
  1196. /* Sidetone */
  1197. { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
  1198. { "Left Sidetone", "DMIC2", "DMIC2L" },
  1199. { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
  1200. { "Right Sidetone", "DMIC2", "DMIC2R" },
  1201. /* Output stages */
  1202. { "Left Output Mixer", "DAC Switch", "DAC1L" },
  1203. { "Right Output Mixer", "DAC Switch", "DAC1R" },
  1204. { "SPKL", "DAC1 Switch", "DAC1L" },
  1205. { "SPKL", "DAC2 Switch", "DAC2L" },
  1206. { "SPKR", "DAC1 Switch", "DAC1R" },
  1207. { "SPKR", "DAC2 Switch", "DAC2R" },
  1208. { "Left Headphone Mux", "DAC", "DAC1L" },
  1209. { "Right Headphone Mux", "DAC", "DAC1R" },
  1210. };
  1211. static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
  1212. { "DAC1L", NULL, "Late DAC1L Enable PGA" },
  1213. { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
  1214. { "DAC1R", NULL, "Late DAC1R Enable PGA" },
  1215. { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
  1216. { "DAC2L", NULL, "Late DAC2L Enable PGA" },
  1217. { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
  1218. { "DAC2R", NULL, "Late DAC2R Enable PGA" },
  1219. { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
  1220. };
  1221. static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
  1222. { "DAC1L", NULL, "DAC1L Mixer" },
  1223. { "DAC1R", NULL, "DAC1R Mixer" },
  1224. { "DAC2L", NULL, "AIF2DAC2L Mixer" },
  1225. { "DAC2R", NULL, "AIF2DAC2R Mixer" },
  1226. };
  1227. static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
  1228. { "AIF1DACDAT", NULL, "AIF2DACDAT" },
  1229. { "AIF2DACDAT", NULL, "AIF1DACDAT" },
  1230. { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
  1231. { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
  1232. { "MICBIAS", NULL, "CLK_SYS" },
  1233. { "MICBIAS", NULL, "MICBIAS Supply" },
  1234. };
  1235. static const struct snd_soc_dapm_route wm8994_intercon[] = {
  1236. { "AIF2DACL", NULL, "AIF2DAC Mux" },
  1237. { "AIF2DACR", NULL, "AIF2DAC Mux" },
  1238. };
  1239. static const struct snd_soc_dapm_route wm8958_intercon[] = {
  1240. { "AIF2DACL", NULL, "AIF2DACL Mux" },
  1241. { "AIF2DACR", NULL, "AIF2DACR Mux" },
  1242. { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
  1243. { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
  1244. { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
  1245. { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
  1246. { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
  1247. { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
  1248. { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
  1249. };
  1250. /* The size in bits of the FLL divide multiplied by 10
  1251. * to allow rounding later */
  1252. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1253. struct fll_div {
  1254. u16 outdiv;
  1255. u16 n;
  1256. u16 k;
  1257. u16 clk_ref_div;
  1258. u16 fll_fratio;
  1259. };
  1260. static int wm8994_get_fll_config(struct fll_div *fll,
  1261. int freq_in, int freq_out)
  1262. {
  1263. u64 Kpart;
  1264. unsigned int K, Ndiv, Nmod;
  1265. pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
  1266. /* Scale the input frequency down to <= 13.5MHz */
  1267. fll->clk_ref_div = 0;
  1268. while (freq_in > 13500000) {
  1269. fll->clk_ref_div++;
  1270. freq_in /= 2;
  1271. if (fll->clk_ref_div > 3)
  1272. return -EINVAL;
  1273. }
  1274. pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
  1275. /* Scale the output to give 90MHz<=Fvco<=100MHz */
  1276. fll->outdiv = 3;
  1277. while (freq_out * (fll->outdiv + 1) < 90000000) {
  1278. fll->outdiv++;
  1279. if (fll->outdiv > 63)
  1280. return -EINVAL;
  1281. }
  1282. freq_out *= fll->outdiv + 1;
  1283. pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
  1284. if (freq_in > 1000000) {
  1285. fll->fll_fratio = 0;
  1286. } else if (freq_in > 256000) {
  1287. fll->fll_fratio = 1;
  1288. freq_in *= 2;
  1289. } else if (freq_in > 128000) {
  1290. fll->fll_fratio = 2;
  1291. freq_in *= 4;
  1292. } else if (freq_in > 64000) {
  1293. fll->fll_fratio = 3;
  1294. freq_in *= 8;
  1295. } else {
  1296. fll->fll_fratio = 4;
  1297. freq_in *= 16;
  1298. }
  1299. pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
  1300. /* Now, calculate N.K */
  1301. Ndiv = freq_out / freq_in;
  1302. fll->n = Ndiv;
  1303. Nmod = freq_out % freq_in;
  1304. pr_debug("Nmod=%d\n", Nmod);
  1305. /* Calculate fractional part - scale up so we can round. */
  1306. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  1307. do_div(Kpart, freq_in);
  1308. K = Kpart & 0xFFFFFFFF;
  1309. if ((K % 10) >= 5)
  1310. K += 5;
  1311. /* Move down to proper range now rounding is done */
  1312. fll->k = K / 10;
  1313. pr_debug("N=%x K=%x\n", fll->n, fll->k);
  1314. return 0;
  1315. }
  1316. static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
  1317. unsigned int freq_in, unsigned int freq_out)
  1318. {
  1319. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1320. int reg_offset, ret;
  1321. struct fll_div fll;
  1322. u16 reg, aif1, aif2;
  1323. aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  1324. & WM8994_AIF1CLK_ENA;
  1325. aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  1326. & WM8994_AIF2CLK_ENA;
  1327. switch (id) {
  1328. case WM8994_FLL1:
  1329. reg_offset = 0;
  1330. id = 0;
  1331. break;
  1332. case WM8994_FLL2:
  1333. reg_offset = 0x20;
  1334. id = 1;
  1335. break;
  1336. default:
  1337. return -EINVAL;
  1338. }
  1339. switch (src) {
  1340. case 0:
  1341. /* Allow no source specification when stopping */
  1342. if (freq_out)
  1343. return -EINVAL;
  1344. src = wm8994->fll[id].src;
  1345. break;
  1346. case WM8994_FLL_SRC_MCLK1:
  1347. case WM8994_FLL_SRC_MCLK2:
  1348. case WM8994_FLL_SRC_LRCLK:
  1349. case WM8994_FLL_SRC_BCLK:
  1350. break;
  1351. default:
  1352. return -EINVAL;
  1353. }
  1354. /* Are we changing anything? */
  1355. if (wm8994->fll[id].src == src &&
  1356. wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
  1357. return 0;
  1358. /* If we're stopping the FLL redo the old config - no
  1359. * registers will actually be written but we avoid GCC flow
  1360. * analysis bugs spewing warnings.
  1361. */
  1362. if (freq_out)
  1363. ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
  1364. else
  1365. ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
  1366. wm8994->fll[id].out);
  1367. if (ret < 0)
  1368. return ret;
  1369. /* Gate the AIF clocks while we reclock */
  1370. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  1371. WM8994_AIF1CLK_ENA, 0);
  1372. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  1373. WM8994_AIF2CLK_ENA, 0);
  1374. /* We always need to disable the FLL while reconfiguring */
  1375. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
  1376. WM8994_FLL1_ENA, 0);
  1377. reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
  1378. (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
  1379. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
  1380. WM8994_FLL1_OUTDIV_MASK |
  1381. WM8994_FLL1_FRATIO_MASK, reg);
  1382. snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
  1383. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
  1384. WM8994_FLL1_N_MASK,
  1385. fll.n << WM8994_FLL1_N_SHIFT);
  1386. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
  1387. WM8994_FLL1_REFCLK_DIV_MASK |
  1388. WM8994_FLL1_REFCLK_SRC_MASK,
  1389. (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
  1390. (src - 1));
  1391. /* Enable (with fractional mode if required) */
  1392. if (freq_out) {
  1393. if (fll.k)
  1394. reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
  1395. else
  1396. reg = WM8994_FLL1_ENA;
  1397. snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
  1398. WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
  1399. reg);
  1400. }
  1401. wm8994->fll[id].in = freq_in;
  1402. wm8994->fll[id].out = freq_out;
  1403. wm8994->fll[id].src = src;
  1404. /* Enable any gated AIF clocks */
  1405. snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
  1406. WM8994_AIF1CLK_ENA, aif1);
  1407. snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
  1408. WM8994_AIF2CLK_ENA, aif2);
  1409. configure_clock(codec);
  1410. return 0;
  1411. }
  1412. static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
  1413. static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
  1414. unsigned int freq_in, unsigned int freq_out)
  1415. {
  1416. return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
  1417. }
  1418. static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
  1419. int clk_id, unsigned int freq, int dir)
  1420. {
  1421. struct snd_soc_codec *codec = dai->codec;
  1422. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1423. int i;
  1424. switch (dai->id) {
  1425. case 1:
  1426. case 2:
  1427. break;
  1428. default:
  1429. /* AIF3 shares clocking with AIF1/2 */
  1430. return -EINVAL;
  1431. }
  1432. switch (clk_id) {
  1433. case WM8994_SYSCLK_MCLK1:
  1434. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
  1435. wm8994->mclk[0] = freq;
  1436. dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
  1437. dai->id, freq);
  1438. break;
  1439. case WM8994_SYSCLK_MCLK2:
  1440. /* TODO: Set GPIO AF */
  1441. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
  1442. wm8994->mclk[1] = freq;
  1443. dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
  1444. dai->id, freq);
  1445. break;
  1446. case WM8994_SYSCLK_FLL1:
  1447. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
  1448. dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
  1449. break;
  1450. case WM8994_SYSCLK_FLL2:
  1451. wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
  1452. dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
  1453. break;
  1454. case WM8994_SYSCLK_OPCLK:
  1455. /* Special case - a division (times 10) is given and
  1456. * no effect on main clocking.
  1457. */
  1458. if (freq) {
  1459. for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
  1460. if (opclk_divs[i] == freq)
  1461. break;
  1462. if (i == ARRAY_SIZE(opclk_divs))
  1463. return -EINVAL;
  1464. snd_soc_update_bits(codec, WM8994_CLOCKING_2,
  1465. WM8994_OPCLK_DIV_MASK, i);
  1466. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
  1467. WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
  1468. } else {
  1469. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
  1470. WM8994_OPCLK_ENA, 0);
  1471. }
  1472. default:
  1473. return -EINVAL;
  1474. }
  1475. configure_clock(codec);
  1476. return 0;
  1477. }
  1478. static int wm8994_set_bias_level(struct snd_soc_codec *codec,
  1479. enum snd_soc_bias_level level)
  1480. {
  1481. struct wm8994 *control = codec->control_data;
  1482. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1483. switch (level) {
  1484. case SND_SOC_BIAS_ON:
  1485. break;
  1486. case SND_SOC_BIAS_PREPARE:
  1487. /* VMID=2x40k */
  1488. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  1489. WM8994_VMID_SEL_MASK, 0x2);
  1490. break;
  1491. case SND_SOC_BIAS_STANDBY:
  1492. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  1493. pm_runtime_get_sync(codec->dev);
  1494. switch (control->type) {
  1495. case WM8994:
  1496. if (wm8994->revision < 4) {
  1497. /* Tweak DC servo and DSP
  1498. * configuration for improved
  1499. * performance. */
  1500. snd_soc_write(codec, 0x102, 0x3);
  1501. snd_soc_write(codec, 0x56, 0x3);
  1502. snd_soc_write(codec, 0x817, 0);
  1503. snd_soc_write(codec, 0x102, 0);
  1504. }
  1505. break;
  1506. case WM8958:
  1507. if (wm8994->revision == 0) {
  1508. /* Optimise performance for rev A */
  1509. snd_soc_write(codec, 0x102, 0x3);
  1510. snd_soc_write(codec, 0xcb, 0x81);
  1511. snd_soc_write(codec, 0x817, 0);
  1512. snd_soc_write(codec, 0x102, 0);
  1513. snd_soc_update_bits(codec,
  1514. WM8958_CHARGE_PUMP_2,
  1515. WM8958_CP_DISCH,
  1516. WM8958_CP_DISCH);
  1517. }
  1518. break;
  1519. }
  1520. /* Discharge LINEOUT1 & 2 */
  1521. snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
  1522. WM8994_LINEOUT1_DISCH |
  1523. WM8994_LINEOUT2_DISCH,
  1524. WM8994_LINEOUT1_DISCH |
  1525. WM8994_LINEOUT2_DISCH);
  1526. /* Startup bias, VMID ramp & buffer */
  1527. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  1528. WM8994_STARTUP_BIAS_ENA |
  1529. WM8994_VMID_BUF_ENA |
  1530. WM8994_VMID_RAMP_MASK,
  1531. WM8994_STARTUP_BIAS_ENA |
  1532. WM8994_VMID_BUF_ENA |
  1533. (0x11 << WM8994_VMID_RAMP_SHIFT));
  1534. /* Main bias enable, VMID=2x40k */
  1535. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  1536. WM8994_BIAS_ENA |
  1537. WM8994_VMID_SEL_MASK,
  1538. WM8994_BIAS_ENA | 0x2);
  1539. msleep(20);
  1540. }
  1541. /* VMID=2x500k */
  1542. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  1543. WM8994_VMID_SEL_MASK, 0x4);
  1544. break;
  1545. case SND_SOC_BIAS_OFF:
  1546. if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
  1547. /* Switch over to startup biases */
  1548. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  1549. WM8994_BIAS_SRC |
  1550. WM8994_STARTUP_BIAS_ENA |
  1551. WM8994_VMID_BUF_ENA |
  1552. WM8994_VMID_RAMP_MASK,
  1553. WM8994_BIAS_SRC |
  1554. WM8994_STARTUP_BIAS_ENA |
  1555. WM8994_VMID_BUF_ENA |
  1556. (1 << WM8994_VMID_RAMP_SHIFT));
  1557. /* Disable main biases */
  1558. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
  1559. WM8994_BIAS_ENA |
  1560. WM8994_VMID_SEL_MASK, 0);
  1561. /* Discharge line */
  1562. snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
  1563. WM8994_LINEOUT1_DISCH |
  1564. WM8994_LINEOUT2_DISCH,
  1565. WM8994_LINEOUT1_DISCH |
  1566. WM8994_LINEOUT2_DISCH);
  1567. msleep(5);
  1568. /* Switch off startup biases */
  1569. snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
  1570. WM8994_BIAS_SRC |
  1571. WM8994_STARTUP_BIAS_ENA |
  1572. WM8994_VMID_BUF_ENA |
  1573. WM8994_VMID_RAMP_MASK, 0);
  1574. wm8994->cur_fw = NULL;
  1575. pm_runtime_put(codec->dev);
  1576. }
  1577. break;
  1578. }
  1579. codec->dapm.bias_level = level;
  1580. return 0;
  1581. }
  1582. static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1583. {
  1584. struct snd_soc_codec *codec = dai->codec;
  1585. struct wm8994 *control = codec->control_data;
  1586. int ms_reg;
  1587. int aif1_reg;
  1588. int ms = 0;
  1589. int aif1 = 0;
  1590. switch (dai->id) {
  1591. case 1:
  1592. ms_reg = WM8994_AIF1_MASTER_SLAVE;
  1593. aif1_reg = WM8994_AIF1_CONTROL_1;
  1594. break;
  1595. case 2:
  1596. ms_reg = WM8994_AIF2_MASTER_SLAVE;
  1597. aif1_reg = WM8994_AIF2_CONTROL_1;
  1598. break;
  1599. default:
  1600. return -EINVAL;
  1601. }
  1602. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1603. case SND_SOC_DAIFMT_CBS_CFS:
  1604. break;
  1605. case SND_SOC_DAIFMT_CBM_CFM:
  1606. ms = WM8994_AIF1_MSTR;
  1607. break;
  1608. default:
  1609. return -EINVAL;
  1610. }
  1611. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1612. case SND_SOC_DAIFMT_DSP_B:
  1613. aif1 |= WM8994_AIF1_LRCLK_INV;
  1614. case SND_SOC_DAIFMT_DSP_A:
  1615. aif1 |= 0x18;
  1616. break;
  1617. case SND_SOC_DAIFMT_I2S:
  1618. aif1 |= 0x10;
  1619. break;
  1620. case SND_SOC_DAIFMT_RIGHT_J:
  1621. break;
  1622. case SND_SOC_DAIFMT_LEFT_J:
  1623. aif1 |= 0x8;
  1624. break;
  1625. default:
  1626. return -EINVAL;
  1627. }
  1628. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1629. case SND_SOC_DAIFMT_DSP_A:
  1630. case SND_SOC_DAIFMT_DSP_B:
  1631. /* frame inversion not valid for DSP modes */
  1632. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1633. case SND_SOC_DAIFMT_NB_NF:
  1634. break;
  1635. case SND_SOC_DAIFMT_IB_NF:
  1636. aif1 |= WM8994_AIF1_BCLK_INV;
  1637. break;
  1638. default:
  1639. return -EINVAL;
  1640. }
  1641. break;
  1642. case SND_SOC_DAIFMT_I2S:
  1643. case SND_SOC_DAIFMT_RIGHT_J:
  1644. case SND_SOC_DAIFMT_LEFT_J:
  1645. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1646. case SND_SOC_DAIFMT_NB_NF:
  1647. break;
  1648. case SND_SOC_DAIFMT_IB_IF:
  1649. aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
  1650. break;
  1651. case SND_SOC_DAIFMT_IB_NF:
  1652. aif1 |= WM8994_AIF1_BCLK_INV;
  1653. break;
  1654. case SND_SOC_DAIFMT_NB_IF:
  1655. aif1 |= WM8994_AIF1_LRCLK_INV;
  1656. break;
  1657. default:
  1658. return -EINVAL;
  1659. }
  1660. break;
  1661. default:
  1662. return -EINVAL;
  1663. }
  1664. /* The AIF2 format configuration needs to be mirrored to AIF3
  1665. * on WM8958 if it's in use so just do it all the time. */
  1666. if (control->type == WM8958 && dai->id == 2)
  1667. snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
  1668. WM8994_AIF1_LRCLK_INV |
  1669. WM8958_AIF3_FMT_MASK, aif1);
  1670. snd_soc_update_bits(codec, aif1_reg,
  1671. WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
  1672. WM8994_AIF1_FMT_MASK,
  1673. aif1);
  1674. snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
  1675. ms);
  1676. return 0;
  1677. }
  1678. static struct {
  1679. int val, rate;
  1680. } srs[] = {
  1681. { 0, 8000 },
  1682. { 1, 11025 },
  1683. { 2, 12000 },
  1684. { 3, 16000 },
  1685. { 4, 22050 },
  1686. { 5, 24000 },
  1687. { 6, 32000 },
  1688. { 7, 44100 },
  1689. { 8, 48000 },
  1690. { 9, 88200 },
  1691. { 10, 96000 },
  1692. };
  1693. static int fs_ratios[] = {
  1694. 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
  1695. };
  1696. static int bclk_divs[] = {
  1697. 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
  1698. 640, 880, 960, 1280, 1760, 1920
  1699. };
  1700. static int wm8994_hw_params(struct snd_pcm_substream *substream,
  1701. struct snd_pcm_hw_params *params,
  1702. struct snd_soc_dai *dai)
  1703. {
  1704. struct snd_soc_codec *codec = dai->codec;
  1705. struct wm8994 *control = codec->control_data;
  1706. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  1707. int aif1_reg;
  1708. int aif2_reg;
  1709. int bclk_reg;
  1710. int lrclk_reg;
  1711. int rate_reg;
  1712. int aif1 = 0;
  1713. int aif2 = 0;
  1714. int bclk = 0;
  1715. int lrclk = 0;
  1716. int rate_val = 0;
  1717. int id = dai->id - 1;
  1718. int i, cur_val, best_val, bclk_rate, best;
  1719. switch (dai->id) {
  1720. case 1:
  1721. aif1_reg = WM8994_AIF1_CONTROL_1;
  1722. aif2_reg = WM8994_AIF1_CONTROL_2;
  1723. bclk_reg = WM8994_AIF1_BCLK;
  1724. rate_reg = WM8994_AIF1_RATE;
  1725. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  1726. wm8994->lrclk_shared[0]) {
  1727. lrclk_reg = WM8994_AIF1DAC_LRCLK;
  1728. } else {
  1729. lrclk_reg = WM8994_AIF1ADC_LRCLK;
  1730. dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
  1731. }
  1732. break;
  1733. case 2:
  1734. aif1_reg = WM8994_AIF2_CONTROL_1;
  1735. aif2_reg = WM8994_AIF2_CONTROL_2;
  1736. bclk_reg = WM8994_AIF2_BCLK;
  1737. rate_reg = WM8994_AIF2_RATE;
  1738. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
  1739. wm8994->lrclk_shared[1]) {
  1740. lrclk_reg = WM8994_AIF2DAC_LRCLK;
  1741. } else {
  1742. lrclk_reg = WM8994_AIF2ADC_LRCLK;
  1743. dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
  1744. }
  1745. break;
  1746. case 3:
  1747. switch (control->type) {
  1748. case WM8958:
  1749. aif1_reg = WM8958_AIF3_CONTROL_1;
  1750. break;
  1751. default:
  1752. return 0;
  1753. }
  1754. default:
  1755. return -EINVAL;
  1756. }
  1757. bclk_rate = params_rate(params) * 2;
  1758. switch (params_format(params)) {
  1759. case SNDRV_PCM_FORMAT_S16_LE:
  1760. bclk_rate *= 16;
  1761. break;
  1762. case SNDRV_PCM_FORMAT_S20_3LE:
  1763. bclk_rate *= 20;
  1764. aif1 |= 0x20;
  1765. break;
  1766. case SNDRV_PCM_FORMAT_S24_LE:
  1767. bclk_rate *= 24;
  1768. aif1 |= 0x40;
  1769. break;
  1770. case SNDRV_PCM_FORMAT_S32_LE:
  1771. bclk_rate *= 32;
  1772. aif1 |= 0x60;
  1773. break;
  1774. default:
  1775. return -EINVAL;
  1776. }
  1777. /* Try to find an appropriate sample rate; look for an exact match. */
  1778. for (i = 0; i < ARRAY_SIZE(srs); i++)
  1779. if (srs[i].rate == params_rate(params))
  1780. break;
  1781. if (i == ARRAY_SIZE(srs))
  1782. return -EINVAL;
  1783. rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
  1784. dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
  1785. dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
  1786. dai->id, wm8994->aifclk[id], bclk_rate);
  1787. if (params_channels(params) == 1 &&
  1788. (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
  1789. aif2 |= WM8994_AIF1_MONO;
  1790. if (wm8994->aifclk[id] == 0) {
  1791. dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
  1792. return -EINVAL;
  1793. }
  1794. /* AIFCLK/fs ratio; look for a close match in either direction */
  1795. best = 0;
  1796. best_val = abs((fs_ratios[0] * params_rate(params))
  1797. - wm8994->aifclk[id]);
  1798. for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
  1799. cur_val = abs((fs_ratios[i] * params_rate(params))
  1800. - wm8994->aifclk[id]);
  1801. if (cur_val >= best_val)
  1802. continue;
  1803. best = i;
  1804. best_val = cur_val;
  1805. }
  1806. dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
  1807. dai->id, fs_ratios[best]);
  1808. rate_val |= best;
  1809. /* We may not get quite the right frequency if using
  1810. * approximate clocks so look for the closest match that is
  1811. * higher than the target (we need to ensure that there enough
  1812. * BCLKs to clock out the samples).
  1813. */
  1814. best = 0;
  1815. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1816. cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
  1817. if (cur_val < 0) /* BCLK table is sorted */
  1818. break;
  1819. best = i;
  1820. }
  1821. bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
  1822. dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
  1823. bclk_divs[best], bclk_rate);
  1824. bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
  1825. lrclk = bclk_rate / params_rate(params);
  1826. dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
  1827. lrclk, bclk_rate / lrclk);
  1828. snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  1829. snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
  1830. snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
  1831. snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
  1832. lrclk);
  1833. snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
  1834. WM8994_AIF1CLK_RATE_MASK, rate_val);
  1835. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  1836. switch (dai->id) {
  1837. case 1:
  1838. wm8994->dac_rates[0] = params_rate(params);
  1839. wm8994_set_retune_mobile(codec, 0);
  1840. wm8994_set_retune_mobile(codec, 1);
  1841. break;
  1842. case 2:
  1843. wm8994->dac_rates[1] = params_rate(params);
  1844. wm8994_set_retune_mobile(codec, 2);
  1845. break;
  1846. }
  1847. }
  1848. return 0;
  1849. }
  1850. static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
  1851. struct snd_pcm_hw_params *params,
  1852. struct snd_soc_dai *dai)
  1853. {
  1854. struct snd_soc_codec *codec = dai->codec;
  1855. struct wm8994 *control = codec->control_data;
  1856. int aif1_reg;
  1857. int aif1 = 0;
  1858. switch (dai->id) {
  1859. case 3:
  1860. switch (control->type) {
  1861. case WM8958:
  1862. aif1_reg = WM8958_AIF3_CONTROL_1;
  1863. break;
  1864. default:
  1865. return 0;
  1866. }
  1867. default:
  1868. return 0;
  1869. }
  1870. switch (params_format(params)) {
  1871. case SNDRV_PCM_FORMAT_S16_LE:
  1872. break;
  1873. case SNDRV_PCM_FORMAT_S20_3LE:
  1874. aif1 |= 0x20;
  1875. break;
  1876. case SNDRV_PCM_FORMAT_S24_LE:
  1877. aif1 |= 0x40;
  1878. break;
  1879. case SNDRV_PCM_FORMAT_S32_LE:
  1880. aif1 |= 0x60;
  1881. break;
  1882. default:
  1883. return -EINVAL;
  1884. }
  1885. return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
  1886. }
  1887. static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
  1888. {
  1889. struct snd_soc_codec *codec = codec_dai->codec;
  1890. int mute_reg;
  1891. int reg;
  1892. switch (codec_dai->id) {
  1893. case 1:
  1894. mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
  1895. break;
  1896. case 2:
  1897. mute_reg = WM8994_AIF2_DAC_FILTERS_1;
  1898. break;
  1899. default:
  1900. return -EINVAL;
  1901. }
  1902. if (mute)
  1903. reg = WM8994_AIF1DAC1_MUTE;
  1904. else
  1905. reg = 0;
  1906. snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
  1907. return 0;
  1908. }
  1909. static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
  1910. {
  1911. struct snd_soc_codec *codec = codec_dai->codec;
  1912. int reg, val, mask;
  1913. switch (codec_dai->id) {
  1914. case 1:
  1915. reg = WM8994_AIF1_MASTER_SLAVE;
  1916. mask = WM8994_AIF1_TRI;
  1917. break;
  1918. case 2:
  1919. reg = WM8994_AIF2_MASTER_SLAVE;
  1920. mask = WM8994_AIF2_TRI;
  1921. break;
  1922. case 3:
  1923. reg = WM8994_POWER_MANAGEMENT_6;
  1924. mask = WM8994_AIF3_TRI;
  1925. break;
  1926. default:
  1927. return -EINVAL;
  1928. }
  1929. if (tristate)
  1930. val = mask;
  1931. else
  1932. val = 0;
  1933. return snd_soc_update_bits(codec, reg, mask, val);
  1934. }
  1935. #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
  1936. #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1937. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1938. static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
  1939. .set_sysclk = wm8994_set_dai_sysclk,
  1940. .set_fmt = wm8994_set_dai_fmt,
  1941. .hw_params = wm8994_hw_params,
  1942. .digital_mute = wm8994_aif_mute,
  1943. .set_pll = wm8994_set_fll,
  1944. .set_tristate = wm8994_set_tristate,
  1945. };
  1946. static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
  1947. .set_sysclk = wm8994_set_dai_sysclk,
  1948. .set_fmt = wm8994_set_dai_fmt,
  1949. .hw_params = wm8994_hw_params,
  1950. .digital_mute = wm8994_aif_mute,
  1951. .set_pll = wm8994_set_fll,
  1952. .set_tristate = wm8994_set_tristate,
  1953. };
  1954. static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
  1955. .hw_params = wm8994_aif3_hw_params,
  1956. .set_tristate = wm8994_set_tristate,
  1957. };
  1958. static struct snd_soc_dai_driver wm8994_dai[] = {
  1959. {
  1960. .name = "wm8994-aif1",
  1961. .id = 1,
  1962. .playback = {
  1963. .stream_name = "AIF1 Playback",
  1964. .channels_min = 1,
  1965. .channels_max = 2,
  1966. .rates = WM8994_RATES,
  1967. .formats = WM8994_FORMATS,
  1968. },
  1969. .capture = {
  1970. .stream_name = "AIF1 Capture",
  1971. .channels_min = 1,
  1972. .channels_max = 2,
  1973. .rates = WM8994_RATES,
  1974. .formats = WM8994_FORMATS,
  1975. },
  1976. .ops = &wm8994_aif1_dai_ops,
  1977. },
  1978. {
  1979. .name = "wm8994-aif2",
  1980. .id = 2,
  1981. .playback = {
  1982. .stream_name = "AIF2 Playback",
  1983. .channels_min = 1,
  1984. .channels_max = 2,
  1985. .rates = WM8994_RATES,
  1986. .formats = WM8994_FORMATS,
  1987. },
  1988. .capture = {
  1989. .stream_name = "AIF2 Capture",
  1990. .channels_min = 1,
  1991. .channels_max = 2,
  1992. .rates = WM8994_RATES,
  1993. .formats = WM8994_FORMATS,
  1994. },
  1995. .ops = &wm8994_aif2_dai_ops,
  1996. },
  1997. {
  1998. .name = "wm8994-aif3",
  1999. .id = 3,
  2000. .playback = {
  2001. .stream_name = "AIF3 Playback",
  2002. .channels_min = 1,
  2003. .channels_max = 2,
  2004. .rates = WM8994_RATES,
  2005. .formats = WM8994_FORMATS,
  2006. },
  2007. .capture = {
  2008. .stream_name = "AIF3 Capture",
  2009. .channels_min = 1,
  2010. .channels_max = 2,
  2011. .rates = WM8994_RATES,
  2012. .formats = WM8994_FORMATS,
  2013. },
  2014. .ops = &wm8994_aif3_dai_ops,
  2015. }
  2016. };
  2017. #ifdef CONFIG_PM
  2018. static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
  2019. {
  2020. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2021. struct wm8994 *control = codec->control_data;
  2022. int i, ret;
  2023. switch (control->type) {
  2024. case WM8994:
  2025. snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
  2026. break;
  2027. case WM8958:
  2028. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  2029. WM8958_MICD_ENA, 0);
  2030. break;
  2031. }
  2032. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  2033. memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
  2034. sizeof(struct wm8994_fll_config));
  2035. ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
  2036. if (ret < 0)
  2037. dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
  2038. i + 1, ret);
  2039. }
  2040. wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
  2041. return 0;
  2042. }
  2043. static int wm8994_resume(struct snd_soc_codec *codec)
  2044. {
  2045. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2046. struct wm8994 *control = codec->control_data;
  2047. int i, ret;
  2048. unsigned int val, mask;
  2049. if (wm8994->revision < 4) {
  2050. /* force a HW read */
  2051. val = wm8994_reg_read(codec->control_data,
  2052. WM8994_POWER_MANAGEMENT_5);
  2053. /* modify the cache only */
  2054. codec->cache_only = 1;
  2055. mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
  2056. WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
  2057. val &= mask;
  2058. snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
  2059. mask, val);
  2060. codec->cache_only = 0;
  2061. }
  2062. /* Restore the registers */
  2063. ret = snd_soc_cache_sync(codec);
  2064. if (ret != 0)
  2065. dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
  2066. wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  2067. for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
  2068. if (!wm8994->fll_suspend[i].out)
  2069. continue;
  2070. ret = _wm8994_set_fll(codec, i + 1,
  2071. wm8994->fll_suspend[i].src,
  2072. wm8994->fll_suspend[i].in,
  2073. wm8994->fll_suspend[i].out);
  2074. if (ret < 0)
  2075. dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
  2076. i + 1, ret);
  2077. }
  2078. switch (control->type) {
  2079. case WM8994:
  2080. if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
  2081. snd_soc_update_bits(codec, WM8994_MICBIAS,
  2082. WM8994_MICD_ENA, WM8994_MICD_ENA);
  2083. break;
  2084. case WM8958:
  2085. if (wm8994->jack_cb)
  2086. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  2087. WM8958_MICD_ENA, WM8958_MICD_ENA);
  2088. break;
  2089. }
  2090. return 0;
  2091. }
  2092. #else
  2093. #define wm8994_suspend NULL
  2094. #define wm8994_resume NULL
  2095. #endif
  2096. static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
  2097. {
  2098. struct snd_soc_codec *codec = wm8994->codec;
  2099. struct wm8994_pdata *pdata = wm8994->pdata;
  2100. struct snd_kcontrol_new controls[] = {
  2101. SOC_ENUM_EXT("AIF1.1 EQ Mode",
  2102. wm8994->retune_mobile_enum,
  2103. wm8994_get_retune_mobile_enum,
  2104. wm8994_put_retune_mobile_enum),
  2105. SOC_ENUM_EXT("AIF1.2 EQ Mode",
  2106. wm8994->retune_mobile_enum,
  2107. wm8994_get_retune_mobile_enum,
  2108. wm8994_put_retune_mobile_enum),
  2109. SOC_ENUM_EXT("AIF2 EQ Mode",
  2110. wm8994->retune_mobile_enum,
  2111. wm8994_get_retune_mobile_enum,
  2112. wm8994_put_retune_mobile_enum),
  2113. };
  2114. int ret, i, j;
  2115. const char **t;
  2116. /* We need an array of texts for the enum API but the number
  2117. * of texts is likely to be less than the number of
  2118. * configurations due to the sample rate dependency of the
  2119. * configurations. */
  2120. wm8994->num_retune_mobile_texts = 0;
  2121. wm8994->retune_mobile_texts = NULL;
  2122. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  2123. for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
  2124. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  2125. wm8994->retune_mobile_texts[j]) == 0)
  2126. break;
  2127. }
  2128. if (j != wm8994->num_retune_mobile_texts)
  2129. continue;
  2130. /* Expand the array... */
  2131. t = krealloc(wm8994->retune_mobile_texts,
  2132. sizeof(char *) *
  2133. (wm8994->num_retune_mobile_texts + 1),
  2134. GFP_KERNEL);
  2135. if (t == NULL)
  2136. continue;
  2137. /* ...store the new entry... */
  2138. t[wm8994->num_retune_mobile_texts] =
  2139. pdata->retune_mobile_cfgs[i].name;
  2140. /* ...and remember the new version. */
  2141. wm8994->num_retune_mobile_texts++;
  2142. wm8994->retune_mobile_texts = t;
  2143. }
  2144. dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
  2145. wm8994->num_retune_mobile_texts);
  2146. wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
  2147. wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
  2148. ret = snd_soc_add_controls(wm8994->codec, controls,
  2149. ARRAY_SIZE(controls));
  2150. if (ret != 0)
  2151. dev_err(wm8994->codec->dev,
  2152. "Failed to add ReTune Mobile controls: %d\n", ret);
  2153. }
  2154. static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
  2155. {
  2156. struct snd_soc_codec *codec = wm8994->codec;
  2157. struct wm8994_pdata *pdata = wm8994->pdata;
  2158. int ret, i;
  2159. if (!pdata)
  2160. return;
  2161. wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
  2162. pdata->lineout2_diff,
  2163. pdata->lineout1fb,
  2164. pdata->lineout2fb,
  2165. pdata->jd_scthr,
  2166. pdata->jd_thr,
  2167. pdata->micbias1_lvl,
  2168. pdata->micbias2_lvl);
  2169. dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
  2170. if (pdata->num_drc_cfgs) {
  2171. struct snd_kcontrol_new controls[] = {
  2172. SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
  2173. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2174. SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
  2175. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2176. SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
  2177. wm8994_get_drc_enum, wm8994_put_drc_enum),
  2178. };
  2179. /* We need an array of texts for the enum API */
  2180. wm8994->drc_texts = kmalloc(sizeof(char *)
  2181. * pdata->num_drc_cfgs, GFP_KERNEL);
  2182. if (!wm8994->drc_texts) {
  2183. dev_err(wm8994->codec->dev,
  2184. "Failed to allocate %d DRC config texts\n",
  2185. pdata->num_drc_cfgs);
  2186. return;
  2187. }
  2188. for (i = 0; i < pdata->num_drc_cfgs; i++)
  2189. wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
  2190. wm8994->drc_enum.max = pdata->num_drc_cfgs;
  2191. wm8994->drc_enum.texts = wm8994->drc_texts;
  2192. ret = snd_soc_add_controls(wm8994->codec, controls,
  2193. ARRAY_SIZE(controls));
  2194. if (ret != 0)
  2195. dev_err(wm8994->codec->dev,
  2196. "Failed to add DRC mode controls: %d\n", ret);
  2197. for (i = 0; i < WM8994_NUM_DRC; i++)
  2198. wm8994_set_drc(codec, i);
  2199. }
  2200. dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
  2201. pdata->num_retune_mobile_cfgs);
  2202. if (pdata->num_retune_mobile_cfgs)
  2203. wm8994_handle_retune_mobile_pdata(wm8994);
  2204. else
  2205. snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
  2206. ARRAY_SIZE(wm8994_eq_controls));
  2207. for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
  2208. if (pdata->micbias[i]) {
  2209. snd_soc_write(codec, WM8958_MICBIAS1 + i,
  2210. pdata->micbias[i] & 0xffff);
  2211. }
  2212. }
  2213. }
  2214. /**
  2215. * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
  2216. *
  2217. * @codec: WM8994 codec
  2218. * @jack: jack to report detection events on
  2219. * @micbias: microphone bias to detect on
  2220. * @det: value to report for presence detection
  2221. * @shrt: value to report for short detection
  2222. *
  2223. * Enable microphone detection via IRQ on the WM8994. If GPIOs are
  2224. * being used to bring out signals to the processor then only platform
  2225. * data configuration is needed for WM8994 and processor GPIOs should
  2226. * be configured using snd_soc_jack_add_gpios() instead.
  2227. *
  2228. * Configuration of detection levels is available via the micbias1_lvl
  2229. * and micbias2_lvl platform data members.
  2230. */
  2231. int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
  2232. int micbias, int det, int shrt)
  2233. {
  2234. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2235. struct wm8994_micdet *micdet;
  2236. struct wm8994 *control = codec->control_data;
  2237. int reg;
  2238. if (control->type != WM8994)
  2239. return -EINVAL;
  2240. switch (micbias) {
  2241. case 1:
  2242. micdet = &wm8994->micdet[0];
  2243. break;
  2244. case 2:
  2245. micdet = &wm8994->micdet[1];
  2246. break;
  2247. default:
  2248. return -EINVAL;
  2249. }
  2250. dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
  2251. micbias, det, shrt);
  2252. /* Store the configuration */
  2253. micdet->jack = jack;
  2254. micdet->det = det;
  2255. micdet->shrt = shrt;
  2256. /* If either of the jacks is set up then enable detection */
  2257. if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
  2258. reg = WM8994_MICD_ENA;
  2259. else
  2260. reg = 0;
  2261. snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
  2262. return 0;
  2263. }
  2264. EXPORT_SYMBOL_GPL(wm8994_mic_detect);
  2265. static irqreturn_t wm8994_mic_irq(int irq, void *data)
  2266. {
  2267. struct wm8994_priv *priv = data;
  2268. struct snd_soc_codec *codec = priv->codec;
  2269. int reg;
  2270. int report;
  2271. #ifndef CONFIG_SND_SOC_WM8994_MODULE
  2272. trace_snd_soc_jack_irq(dev_name(codec->dev));
  2273. #endif
  2274. reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
  2275. if (reg < 0) {
  2276. dev_err(codec->dev, "Failed to read microphone status: %d\n",
  2277. reg);
  2278. return IRQ_HANDLED;
  2279. }
  2280. dev_dbg(codec->dev, "Microphone status: %x\n", reg);
  2281. report = 0;
  2282. if (reg & WM8994_MIC1_DET_STS)
  2283. report |= priv->micdet[0].det;
  2284. if (reg & WM8994_MIC1_SHRT_STS)
  2285. report |= priv->micdet[0].shrt;
  2286. snd_soc_jack_report(priv->micdet[0].jack, report,
  2287. priv->micdet[0].det | priv->micdet[0].shrt);
  2288. report = 0;
  2289. if (reg & WM8994_MIC2_DET_STS)
  2290. report |= priv->micdet[1].det;
  2291. if (reg & WM8994_MIC2_SHRT_STS)
  2292. report |= priv->micdet[1].shrt;
  2293. snd_soc_jack_report(priv->micdet[1].jack, report,
  2294. priv->micdet[1].det | priv->micdet[1].shrt);
  2295. return IRQ_HANDLED;
  2296. }
  2297. /* Default microphone detection handler for WM8958 - the user can
  2298. * override this if they wish.
  2299. */
  2300. static void wm8958_default_micdet(u16 status, void *data)
  2301. {
  2302. struct snd_soc_codec *codec = data;
  2303. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2304. int report = 0;
  2305. /* If nothing present then clear our statuses */
  2306. if (!(status & WM8958_MICD_STS))
  2307. goto done;
  2308. report = SND_JACK_MICROPHONE;
  2309. /* Everything else is buttons; just assign slots */
  2310. if (status & 0x1c0)
  2311. report |= SND_JACK_BTN_0;
  2312. done:
  2313. snd_soc_jack_report(wm8994->micdet[0].jack, report,
  2314. SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
  2315. }
  2316. /**
  2317. * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
  2318. *
  2319. * @codec: WM8958 codec
  2320. * @jack: jack to report detection events on
  2321. *
  2322. * Enable microphone detection functionality for the WM8958. By
  2323. * default simple detection which supports the detection of up to 6
  2324. * buttons plus video and microphone functionality is supported.
  2325. *
  2326. * The WM8958 has an advanced jack detection facility which is able to
  2327. * support complex accessory detection, especially when used in
  2328. * conjunction with external circuitry. In order to provide maximum
  2329. * flexiblity a callback is provided which allows a completely custom
  2330. * detection algorithm.
  2331. */
  2332. int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
  2333. wm8958_micdet_cb cb, void *cb_data)
  2334. {
  2335. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2336. struct wm8994 *control = codec->control_data;
  2337. if (control->type != WM8958)
  2338. return -EINVAL;
  2339. if (jack) {
  2340. if (!cb) {
  2341. dev_dbg(codec->dev, "Using default micdet callback\n");
  2342. cb = wm8958_default_micdet;
  2343. cb_data = codec;
  2344. }
  2345. wm8994->micdet[0].jack = jack;
  2346. wm8994->jack_cb = cb;
  2347. wm8994->jack_cb_data = cb_data;
  2348. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  2349. WM8958_MICD_ENA, WM8958_MICD_ENA);
  2350. } else {
  2351. snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
  2352. WM8958_MICD_ENA, 0);
  2353. }
  2354. return 0;
  2355. }
  2356. EXPORT_SYMBOL_GPL(wm8958_mic_detect);
  2357. static irqreturn_t wm8958_mic_irq(int irq, void *data)
  2358. {
  2359. struct wm8994_priv *wm8994 = data;
  2360. struct snd_soc_codec *codec = wm8994->codec;
  2361. int reg;
  2362. reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
  2363. if (reg < 0) {
  2364. dev_err(codec->dev, "Failed to read mic detect status: %d\n",
  2365. reg);
  2366. return IRQ_NONE;
  2367. }
  2368. if (!(reg & WM8958_MICD_VALID)) {
  2369. dev_dbg(codec->dev, "Mic detect data not valid\n");
  2370. goto out;
  2371. }
  2372. #ifndef CONFIG_SND_SOC_WM8994_MODULE
  2373. trace_snd_soc_jack_irq(dev_name(codec->dev));
  2374. #endif
  2375. if (wm8994->jack_cb)
  2376. wm8994->jack_cb(reg, wm8994->jack_cb_data);
  2377. else
  2378. dev_warn(codec->dev, "Accessory detection with no callback\n");
  2379. out:
  2380. return IRQ_HANDLED;
  2381. }
  2382. static int wm8994_codec_probe(struct snd_soc_codec *codec)
  2383. {
  2384. struct wm8994 *control;
  2385. struct wm8994_priv *wm8994;
  2386. struct snd_soc_dapm_context *dapm = &codec->dapm;
  2387. int ret, i;
  2388. codec->control_data = dev_get_drvdata(codec->dev->parent);
  2389. control = codec->control_data;
  2390. wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
  2391. if (wm8994 == NULL)
  2392. return -ENOMEM;
  2393. snd_soc_codec_set_drvdata(codec, wm8994);
  2394. wm8994->pdata = dev_get_platdata(codec->dev->parent);
  2395. wm8994->codec = codec;
  2396. if (wm8994->pdata && wm8994->pdata->micdet_irq)
  2397. wm8994->micdet_irq = wm8994->pdata->micdet_irq;
  2398. else if (wm8994->pdata && wm8994->pdata->irq_base)
  2399. wm8994->micdet_irq = wm8994->pdata->irq_base +
  2400. WM8994_IRQ_MIC1_DET;
  2401. pm_runtime_enable(codec->dev);
  2402. pm_runtime_resume(codec->dev);
  2403. /* Read our current status back from the chip - we don't want to
  2404. * reset as this may interfere with the GPIO or LDO operation. */
  2405. for (i = 0; i < WM8994_CACHE_SIZE; i++) {
  2406. if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
  2407. continue;
  2408. ret = wm8994_reg_read(codec->control_data, i);
  2409. if (ret <= 0)
  2410. continue;
  2411. ret = snd_soc_cache_write(codec, i, ret);
  2412. if (ret != 0) {
  2413. dev_err(codec->dev,
  2414. "Failed to initialise cache for 0x%x: %d\n",
  2415. i, ret);
  2416. goto err;
  2417. }
  2418. }
  2419. /* Set revision-specific configuration */
  2420. wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
  2421. switch (control->type) {
  2422. case WM8994:
  2423. switch (wm8994->revision) {
  2424. case 2:
  2425. case 3:
  2426. wm8994->hubs.dcs_codes = -5;
  2427. wm8994->hubs.hp_startup_mode = 1;
  2428. wm8994->hubs.dcs_readback_mode = 1;
  2429. break;
  2430. default:
  2431. wm8994->hubs.dcs_readback_mode = 1;
  2432. break;
  2433. }
  2434. case WM8958:
  2435. wm8994->hubs.dcs_readback_mode = 1;
  2436. break;
  2437. default:
  2438. break;
  2439. }
  2440. switch (control->type) {
  2441. case WM8994:
  2442. if (wm8994->micdet_irq) {
  2443. ret = request_threaded_irq(wm8994->micdet_irq, NULL,
  2444. wm8994_mic_irq,
  2445. IRQF_TRIGGER_RISING,
  2446. "Mic1 detect",
  2447. wm8994);
  2448. if (ret != 0)
  2449. dev_warn(codec->dev,
  2450. "Failed to request Mic1 detect IRQ: %d\n",
  2451. ret);
  2452. }
  2453. ret = wm8994_request_irq(codec->control_data,
  2454. WM8994_IRQ_MIC1_SHRT,
  2455. wm8994_mic_irq, "Mic 1 short",
  2456. wm8994);
  2457. if (ret != 0)
  2458. dev_warn(codec->dev,
  2459. "Failed to request Mic1 short IRQ: %d\n",
  2460. ret);
  2461. ret = wm8994_request_irq(codec->control_data,
  2462. WM8994_IRQ_MIC2_DET,
  2463. wm8994_mic_irq, "Mic 2 detect",
  2464. wm8994);
  2465. if (ret != 0)
  2466. dev_warn(codec->dev,
  2467. "Failed to request Mic2 detect IRQ: %d\n",
  2468. ret);
  2469. ret = wm8994_request_irq(codec->control_data,
  2470. WM8994_IRQ_MIC2_SHRT,
  2471. wm8994_mic_irq, "Mic 2 short",
  2472. wm8994);
  2473. if (ret != 0)
  2474. dev_warn(codec->dev,
  2475. "Failed to request Mic2 short IRQ: %d\n",
  2476. ret);
  2477. break;
  2478. case WM8958:
  2479. if (wm8994->micdet_irq) {
  2480. ret = request_threaded_irq(wm8994->micdet_irq, NULL,
  2481. wm8958_mic_irq,
  2482. IRQF_TRIGGER_RISING,
  2483. "Mic detect",
  2484. wm8994);
  2485. if (ret != 0)
  2486. dev_warn(codec->dev,
  2487. "Failed to request Mic detect IRQ: %d\n",
  2488. ret);
  2489. }
  2490. }
  2491. /* Remember if AIFnLRCLK is configured as a GPIO. This should be
  2492. * configured on init - if a system wants to do this dynamically
  2493. * at runtime we can deal with that then.
  2494. */
  2495. ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
  2496. if (ret < 0) {
  2497. dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
  2498. goto err_irq;
  2499. }
  2500. if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  2501. wm8994->lrclk_shared[0] = 1;
  2502. wm8994_dai[0].symmetric_rates = 1;
  2503. } else {
  2504. wm8994->lrclk_shared[0] = 0;
  2505. }
  2506. ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
  2507. if (ret < 0) {
  2508. dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
  2509. goto err_irq;
  2510. }
  2511. if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
  2512. wm8994->lrclk_shared[1] = 1;
  2513. wm8994_dai[1].symmetric_rates = 1;
  2514. } else {
  2515. wm8994->lrclk_shared[1] = 0;
  2516. }
  2517. wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  2518. /* Latch volume updates (right only; we always do left then right). */
  2519. snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
  2520. WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
  2521. snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
  2522. WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
  2523. snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
  2524. WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
  2525. snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
  2526. WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
  2527. snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
  2528. WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
  2529. snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
  2530. WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
  2531. snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
  2532. WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
  2533. snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
  2534. WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
  2535. snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
  2536. WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
  2537. snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
  2538. WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
  2539. snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
  2540. WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
  2541. snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
  2542. WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
  2543. snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
  2544. WM8994_DAC1_VU, WM8994_DAC1_VU);
  2545. snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
  2546. WM8994_DAC1_VU, WM8994_DAC1_VU);
  2547. snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
  2548. WM8994_DAC2_VU, WM8994_DAC2_VU);
  2549. snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
  2550. WM8994_DAC2_VU, WM8994_DAC2_VU);
  2551. /* Set the low bit of the 3D stereo depth so TLV matches */
  2552. snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
  2553. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
  2554. 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
  2555. snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
  2556. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
  2557. 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
  2558. snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
  2559. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
  2560. 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
  2561. /* Unconditionally enable AIF1 ADC TDM mode; it only affects
  2562. * behaviour on idle TDM clock cycles. */
  2563. snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
  2564. WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
  2565. wm8994_update_class_w(codec);
  2566. wm8994_handle_pdata(wm8994);
  2567. wm_hubs_add_analogue_controls(codec);
  2568. snd_soc_add_controls(codec, wm8994_snd_controls,
  2569. ARRAY_SIZE(wm8994_snd_controls));
  2570. snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
  2571. ARRAY_SIZE(wm8994_dapm_widgets));
  2572. switch (control->type) {
  2573. case WM8994:
  2574. snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
  2575. ARRAY_SIZE(wm8994_specific_dapm_widgets));
  2576. if (wm8994->revision < 4) {
  2577. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
  2578. ARRAY_SIZE(wm8994_lateclk_revd_widgets));
  2579. snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
  2580. ARRAY_SIZE(wm8994_adc_revd_widgets));
  2581. snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
  2582. ARRAY_SIZE(wm8994_dac_revd_widgets));
  2583. } else {
  2584. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  2585. ARRAY_SIZE(wm8994_lateclk_widgets));
  2586. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  2587. ARRAY_SIZE(wm8994_adc_widgets));
  2588. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  2589. ARRAY_SIZE(wm8994_dac_widgets));
  2590. }
  2591. break;
  2592. case WM8958:
  2593. snd_soc_add_controls(codec, wm8958_snd_controls,
  2594. ARRAY_SIZE(wm8958_snd_controls));
  2595. snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
  2596. ARRAY_SIZE(wm8958_dapm_widgets));
  2597. if (wm8994->revision < 1) {
  2598. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
  2599. ARRAY_SIZE(wm8994_lateclk_revd_widgets));
  2600. snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
  2601. ARRAY_SIZE(wm8994_adc_revd_widgets));
  2602. snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
  2603. ARRAY_SIZE(wm8994_dac_revd_widgets));
  2604. } else {
  2605. snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
  2606. ARRAY_SIZE(wm8994_lateclk_widgets));
  2607. snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
  2608. ARRAY_SIZE(wm8994_adc_widgets));
  2609. snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
  2610. ARRAY_SIZE(wm8994_dac_widgets));
  2611. }
  2612. break;
  2613. }
  2614. wm_hubs_add_analogue_routes(codec, 0, 0);
  2615. snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
  2616. switch (control->type) {
  2617. case WM8994:
  2618. snd_soc_dapm_add_routes(dapm, wm8994_intercon,
  2619. ARRAY_SIZE(wm8994_intercon));
  2620. if (wm8994->revision < 4) {
  2621. snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
  2622. ARRAY_SIZE(wm8994_revd_intercon));
  2623. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
  2624. ARRAY_SIZE(wm8994_lateclk_revd_intercon));
  2625. } else {
  2626. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  2627. ARRAY_SIZE(wm8994_lateclk_intercon));
  2628. }
  2629. break;
  2630. case WM8958:
  2631. if (wm8994->revision < 1) {
  2632. snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
  2633. ARRAY_SIZE(wm8994_revd_intercon));
  2634. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
  2635. ARRAY_SIZE(wm8994_lateclk_revd_intercon));
  2636. } else {
  2637. snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
  2638. ARRAY_SIZE(wm8994_lateclk_intercon));
  2639. snd_soc_dapm_add_routes(dapm, wm8958_intercon,
  2640. ARRAY_SIZE(wm8958_intercon));
  2641. }
  2642. wm8958_dsp2_init(codec);
  2643. break;
  2644. }
  2645. return 0;
  2646. err_irq:
  2647. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
  2648. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
  2649. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
  2650. if (wm8994->micdet_irq)
  2651. free_irq(wm8994->micdet_irq, wm8994);
  2652. err:
  2653. kfree(wm8994);
  2654. return ret;
  2655. }
  2656. static int wm8994_codec_remove(struct snd_soc_codec *codec)
  2657. {
  2658. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  2659. struct wm8994 *control = codec->control_data;
  2660. wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
  2661. pm_runtime_disable(codec->dev);
  2662. switch (control->type) {
  2663. case WM8994:
  2664. if (wm8994->micdet_irq)
  2665. free_irq(wm8994->micdet_irq, wm8994);
  2666. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
  2667. wm8994);
  2668. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
  2669. wm8994);
  2670. wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
  2671. wm8994);
  2672. break;
  2673. case WM8958:
  2674. if (wm8994->micdet_irq)
  2675. free_irq(wm8994->micdet_irq, wm8994);
  2676. break;
  2677. }
  2678. if (wm8994->mbc)
  2679. release_firmware(wm8994->mbc);
  2680. if (wm8994->mbc_vss)
  2681. release_firmware(wm8994->mbc_vss);
  2682. if (wm8994->enh_eq)
  2683. release_firmware(wm8994->enh_eq);
  2684. kfree(wm8994->retune_mobile_texts);
  2685. kfree(wm8994->drc_texts);
  2686. kfree(wm8994);
  2687. return 0;
  2688. }
  2689. static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
  2690. .probe = wm8994_codec_probe,
  2691. .remove = wm8994_codec_remove,
  2692. .suspend = wm8994_suspend,
  2693. .resume = wm8994_resume,
  2694. .read = wm8994_read,
  2695. .write = wm8994_write,
  2696. .readable_register = wm8994_readable,
  2697. .volatile_register = wm8994_volatile,
  2698. .set_bias_level = wm8994_set_bias_level,
  2699. .reg_cache_size = WM8994_CACHE_SIZE,
  2700. .reg_cache_default = wm8994_reg_defaults,
  2701. .reg_word_size = 2,
  2702. .compress_type = SND_SOC_RBTREE_COMPRESSION,
  2703. };
  2704. static int __devinit wm8994_probe(struct platform_device *pdev)
  2705. {
  2706. return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
  2707. wm8994_dai, ARRAY_SIZE(wm8994_dai));
  2708. }
  2709. static int __devexit wm8994_remove(struct platform_device *pdev)
  2710. {
  2711. snd_soc_unregister_codec(&pdev->dev);
  2712. return 0;
  2713. }
  2714. static struct platform_driver wm8994_codec_driver = {
  2715. .driver = {
  2716. .name = "wm8994-codec",
  2717. .owner = THIS_MODULE,
  2718. },
  2719. .probe = wm8994_probe,
  2720. .remove = __devexit_p(wm8994_remove),
  2721. };
  2722. static __init int wm8994_init(void)
  2723. {
  2724. return platform_driver_register(&wm8994_codec_driver);
  2725. }
  2726. module_init(wm8994_init);
  2727. static __exit void wm8994_exit(void)
  2728. {
  2729. platform_driver_unregister(&wm8994_codec_driver);
  2730. }
  2731. module_exit(wm8994_exit);
  2732. MODULE_DESCRIPTION("ASoC WM8994 driver");
  2733. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  2734. MODULE_LICENSE("GPL");
  2735. MODULE_ALIAS("platform:wm8994-codec");