hpi6000.c 49 KB

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  1. /******************************************************************************
  2. AudioScience HPI driver
  3. Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of version 2 of the GNU General Public License as
  6. published by the Free Software Foundation;
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. GNU General Public License for more details.
  11. You should have received a copy of the GNU General Public License
  12. along with this program; if not, write to the Free Software
  13. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  14. Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
  15. These PCI bus adapters are based on the TI C6711 DSP.
  16. Exported functions:
  17. void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
  18. #defines
  19. HIDE_PCI_ASSERTS to show the PCI asserts
  20. PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
  21. (C) Copyright AudioScience Inc. 1998-2003
  22. *******************************************************************************/
  23. #define SOURCEFILE_NAME "hpi6000.c"
  24. #include "hpi_internal.h"
  25. #include "hpimsginit.h"
  26. #include "hpidebug.h"
  27. #include "hpi6000.h"
  28. #include "hpidspcd.h"
  29. #include "hpicmn.h"
  30. #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
  31. #define HPI_HIF_ADDR(member) \
  32. (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
  33. #define HPI_HIF_ERROR_MASK 0x4000
  34. /* HPI6000 specific error codes */
  35. #define HPI6000_ERROR_BASE 900 /* not actually used anywhere */
  36. /* operational/messaging errors */
  37. #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
  38. #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
  39. #define HPI6000_ERROR_MSG_GET_ADR 904
  40. #define HPI6000_ERROR_RESP_GET_ADR 905
  41. #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
  42. #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
  43. #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
  44. #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
  45. #define HPI6000_ERROR_SEND_DATA_ACK 912
  46. #define HPI6000_ERROR_SEND_DATA_ADR 913
  47. #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
  48. #define HPI6000_ERROR_SEND_DATA_CMD 915
  49. #define HPI6000_ERROR_SEND_DATA_WRITE 916
  50. #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
  51. #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
  52. #define HPI6000_ERROR_GET_DATA_ACK 922
  53. #define HPI6000_ERROR_GET_DATA_CMD 923
  54. #define HPI6000_ERROR_GET_DATA_READ 924
  55. #define HPI6000_ERROR_GET_DATA_IDLECMD 925
  56. #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
  57. #define HPI6000_ERROR_CONTROL_CACHE_READ 952
  58. #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
  59. #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
  60. #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
  61. /* Initialisation/bootload errors */
  62. #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
  63. /* can't access PCI2040 */
  64. #define HPI6000_ERROR_INIT_PCI2040 931
  65. /* can't access DSP HPI i/f */
  66. #define HPI6000_ERROR_INIT_DSPHPI 932
  67. /* can't access internal DSP memory */
  68. #define HPI6000_ERROR_INIT_DSPINTMEM 933
  69. /* can't access SDRAM - test#1 */
  70. #define HPI6000_ERROR_INIT_SDRAM1 934
  71. /* can't access SDRAM - test#2 */
  72. #define HPI6000_ERROR_INIT_SDRAM2 935
  73. #define HPI6000_ERROR_INIT_VERIFY 938
  74. #define HPI6000_ERROR_INIT_NOACK 939
  75. #define HPI6000_ERROR_INIT_PLDTEST1 941
  76. #define HPI6000_ERROR_INIT_PLDTEST2 942
  77. /* local defines */
  78. #define HIDE_PCI_ASSERTS
  79. #define PROFILE_DSP2
  80. /* for PCI2040 i/f chip */
  81. /* HPI CSR registers */
  82. /* word offsets from CSR base */
  83. /* use when io addresses defined as u32 * */
  84. #define INTERRUPT_EVENT_SET 0
  85. #define INTERRUPT_EVENT_CLEAR 1
  86. #define INTERRUPT_MASK_SET 2
  87. #define INTERRUPT_MASK_CLEAR 3
  88. #define HPI_ERROR_REPORT 4
  89. #define HPI_RESET 5
  90. #define HPI_DATA_WIDTH 6
  91. #define MAX_DSPS 2
  92. /* HPI registers, spaced 8K bytes = 2K words apart */
  93. #define DSP_SPACING 0x800
  94. #define CONTROL 0x0000
  95. #define ADDRESS 0x0200
  96. #define DATA_AUTOINC 0x0400
  97. #define DATA 0x0600
  98. #define TIMEOUT 500000
  99. struct dsp_obj {
  100. __iomem u32 *prHPI_control;
  101. __iomem u32 *prHPI_address;
  102. __iomem u32 *prHPI_data;
  103. __iomem u32 *prHPI_data_auto_inc;
  104. char c_dsp_rev; /*A, B */
  105. u32 control_cache_address_on_dsp;
  106. u32 control_cache_length_on_dsp;
  107. struct hpi_adapter_obj *pa_parent_adapter;
  108. };
  109. struct hpi_hw_obj {
  110. __iomem u32 *dw2040_HPICSR;
  111. __iomem u32 *dw2040_HPIDSP;
  112. u16 num_dsp;
  113. struct dsp_obj ado[MAX_DSPS];
  114. u32 message_buffer_address_on_dsp;
  115. u32 response_buffer_address_on_dsp;
  116. u32 pCI2040HPI_error_count;
  117. struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
  118. struct hpi_control_cache *p_cache;
  119. };
  120. static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
  121. u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
  122. static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
  123. u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
  124. static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
  125. u32 *pos_error_code);
  126. static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
  127. u16 read_or_write);
  128. #define H6READ 1
  129. #define H6WRITE 0
  130. static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
  131. struct hpi_message *phm);
  132. static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
  133. u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
  134. static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
  135. struct hpi_response *phr);
  136. static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
  137. u32 ack_value);
  138. static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
  139. u16 dsp_index, u32 host_cmd);
  140. static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
  141. static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  142. struct hpi_message *phm, struct hpi_response *phr);
  143. static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  144. struct hpi_message *phm, struct hpi_response *phr);
  145. static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
  146. static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
  147. static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  148. u32 length);
  149. static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  150. u32 length);
  151. static void subsys_create_adapter(struct hpi_message *phm,
  152. struct hpi_response *phr);
  153. static void adapter_delete(struct hpi_adapter_obj *pao,
  154. struct hpi_message *phm, struct hpi_response *phr);
  155. static void adapter_get_asserts(struct hpi_adapter_obj *pao,
  156. struct hpi_message *phm, struct hpi_response *phr);
  157. static short create_adapter_obj(struct hpi_adapter_obj *pao,
  158. u32 *pos_error_code);
  159. static void delete_adapter_obj(struct hpi_adapter_obj *pao);
  160. /* local globals */
  161. static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
  162. static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
  163. static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
  164. {
  165. switch (phm->function) {
  166. case HPI_SUBSYS_CREATE_ADAPTER:
  167. subsys_create_adapter(phm, phr);
  168. break;
  169. default:
  170. phr->error = HPI_ERROR_INVALID_FUNC;
  171. break;
  172. }
  173. }
  174. static void control_message(struct hpi_adapter_obj *pao,
  175. struct hpi_message *phm, struct hpi_response *phr)
  176. {
  177. switch (phm->function) {
  178. case HPI_CONTROL_GET_STATE:
  179. if (pao->has_control_cache) {
  180. u16 err;
  181. err = hpi6000_update_control_cache(pao, phm);
  182. if (err) {
  183. if (err >= HPI_ERROR_BACKEND_BASE) {
  184. phr->error =
  185. HPI_ERROR_CONTROL_CACHING;
  186. phr->specific_error = err;
  187. } else {
  188. phr->error = err;
  189. }
  190. break;
  191. }
  192. if (hpi_check_control_cache(((struct hpi_hw_obj *)
  193. pao->priv)->p_cache, phm,
  194. phr))
  195. break;
  196. }
  197. hw_message(pao, phm, phr);
  198. break;
  199. case HPI_CONTROL_SET_STATE:
  200. hw_message(pao, phm, phr);
  201. hpi_cmn_control_cache_sync_to_msg(((struct hpi_hw_obj *)pao->
  202. priv)->p_cache, phm, phr);
  203. break;
  204. case HPI_CONTROL_GET_INFO:
  205. default:
  206. hw_message(pao, phm, phr);
  207. break;
  208. }
  209. }
  210. static void adapter_message(struct hpi_adapter_obj *pao,
  211. struct hpi_message *phm, struct hpi_response *phr)
  212. {
  213. switch (phm->function) {
  214. case HPI_ADAPTER_GET_ASSERT:
  215. adapter_get_asserts(pao, phm, phr);
  216. break;
  217. case HPI_ADAPTER_DELETE:
  218. adapter_delete(pao, phm, phr);
  219. break;
  220. default:
  221. hw_message(pao, phm, phr);
  222. break;
  223. }
  224. }
  225. static void outstream_message(struct hpi_adapter_obj *pao,
  226. struct hpi_message *phm, struct hpi_response *phr)
  227. {
  228. switch (phm->function) {
  229. case HPI_OSTREAM_HOSTBUFFER_ALLOC:
  230. case HPI_OSTREAM_HOSTBUFFER_FREE:
  231. /* Don't let these messages go to the HW function because
  232. * they're called without locking the spinlock.
  233. * For the HPI6000 adapters the HW would return
  234. * HPI_ERROR_INVALID_FUNC anyway.
  235. */
  236. phr->error = HPI_ERROR_INVALID_FUNC;
  237. break;
  238. default:
  239. hw_message(pao, phm, phr);
  240. return;
  241. }
  242. }
  243. static void instream_message(struct hpi_adapter_obj *pao,
  244. struct hpi_message *phm, struct hpi_response *phr)
  245. {
  246. switch (phm->function) {
  247. case HPI_ISTREAM_HOSTBUFFER_ALLOC:
  248. case HPI_ISTREAM_HOSTBUFFER_FREE:
  249. /* Don't let these messages go to the HW function because
  250. * they're called without locking the spinlock.
  251. * For the HPI6000 adapters the HW would return
  252. * HPI_ERROR_INVALID_FUNC anyway.
  253. */
  254. phr->error = HPI_ERROR_INVALID_FUNC;
  255. break;
  256. default:
  257. hw_message(pao, phm, phr);
  258. return;
  259. }
  260. }
  261. /************************************************************************/
  262. /** HPI_6000()
  263. * Entry point from HPIMAN
  264. * All calls to the HPI start here
  265. */
  266. void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
  267. {
  268. struct hpi_adapter_obj *pao = NULL;
  269. if (phm->object != HPI_OBJ_SUBSYSTEM) {
  270. pao = hpi_find_adapter(phm->adapter_index);
  271. if (!pao) {
  272. hpi_init_response(phr, phm->object, phm->function,
  273. HPI_ERROR_BAD_ADAPTER_NUMBER);
  274. HPI_DEBUG_LOG(DEBUG, "invalid adapter index: %d \n",
  275. phm->adapter_index);
  276. return;
  277. }
  278. /* Don't even try to communicate with crashed DSP */
  279. if (pao->dsp_crashed >= 10) {
  280. hpi_init_response(phr, phm->object, phm->function,
  281. HPI_ERROR_DSP_HARDWARE);
  282. HPI_DEBUG_LOG(DEBUG, "adapter %d dsp crashed\n",
  283. phm->adapter_index);
  284. return;
  285. }
  286. }
  287. /* Init default response including the size field */
  288. if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
  289. hpi_init_response(phr, phm->object, phm->function,
  290. HPI_ERROR_PROCESSING_MESSAGE);
  291. switch (phm->type) {
  292. case HPI_TYPE_MESSAGE:
  293. switch (phm->object) {
  294. case HPI_OBJ_SUBSYSTEM:
  295. subsys_message(phm, phr);
  296. break;
  297. case HPI_OBJ_ADAPTER:
  298. phr->size =
  299. sizeof(struct hpi_response_header) +
  300. sizeof(struct hpi_adapter_res);
  301. adapter_message(pao, phm, phr);
  302. break;
  303. case HPI_OBJ_CONTROL:
  304. control_message(pao, phm, phr);
  305. break;
  306. case HPI_OBJ_OSTREAM:
  307. outstream_message(pao, phm, phr);
  308. break;
  309. case HPI_OBJ_ISTREAM:
  310. instream_message(pao, phm, phr);
  311. break;
  312. default:
  313. hw_message(pao, phm, phr);
  314. break;
  315. }
  316. break;
  317. default:
  318. phr->error = HPI_ERROR_INVALID_TYPE;
  319. break;
  320. }
  321. }
  322. /************************************************************************/
  323. /* SUBSYSTEM */
  324. /* create an adapter object and initialise it based on resource information
  325. * passed in in the message
  326. * NOTE - you cannot use this function AND the FindAdapters function at the
  327. * same time, the application must use only one of them to get the adapters
  328. */
  329. static void subsys_create_adapter(struct hpi_message *phm,
  330. struct hpi_response *phr)
  331. {
  332. /* create temp adapter obj, because we don't know what index yet */
  333. struct hpi_adapter_obj ao;
  334. struct hpi_adapter_obj *pao;
  335. u32 os_error_code;
  336. u16 err = 0;
  337. u32 dsp_index = 0;
  338. HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
  339. memset(&ao, 0, sizeof(ao));
  340. ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
  341. if (!ao.priv) {
  342. HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
  343. phr->error = HPI_ERROR_MEMORY_ALLOC;
  344. return;
  345. }
  346. /* create the adapter object based on the resource information */
  347. ao.pci = *phm->u.s.resource.r.pci;
  348. err = create_adapter_obj(&ao, &os_error_code);
  349. if (err) {
  350. delete_adapter_obj(&ao);
  351. if (err >= HPI_ERROR_BACKEND_BASE) {
  352. phr->error = HPI_ERROR_DSP_BOOTLOAD;
  353. phr->specific_error = err;
  354. } else {
  355. phr->error = err;
  356. }
  357. phr->u.s.data = os_error_code;
  358. return;
  359. }
  360. /* need to update paParentAdapter */
  361. pao = hpi_find_adapter(ao.index);
  362. if (!pao) {
  363. /* We just added this adapter, why can't we find it!? */
  364. HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
  365. phr->error = HPI_ERROR_BAD_ADAPTER;
  366. return;
  367. }
  368. for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
  369. struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
  370. phw->ado[dsp_index].pa_parent_adapter = pao;
  371. }
  372. phr->u.s.adapter_type = ao.adapter_type;
  373. phr->u.s.adapter_index = ao.index;
  374. phr->error = 0;
  375. }
  376. static void adapter_delete(struct hpi_adapter_obj *pao,
  377. struct hpi_message *phm, struct hpi_response *phr)
  378. {
  379. delete_adapter_obj(pao);
  380. hpi_delete_adapter(pao);
  381. phr->error = 0;
  382. }
  383. /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
  384. static short create_adapter_obj(struct hpi_adapter_obj *pao,
  385. u32 *pos_error_code)
  386. {
  387. short boot_error = 0;
  388. u32 dsp_index = 0;
  389. u32 control_cache_size = 0;
  390. u32 control_cache_count = 0;
  391. struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
  392. /* The PCI2040 has the following address map */
  393. /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
  394. /* BAR1 - 32K = HPI registers on DSP */
  395. phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
  396. phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
  397. HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
  398. phw->dw2040_HPIDSP);
  399. /* set addresses for the possible DSP HPI interfaces */
  400. for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
  401. phw->ado[dsp_index].prHPI_control =
  402. phw->dw2040_HPIDSP + (CONTROL +
  403. DSP_SPACING * dsp_index);
  404. phw->ado[dsp_index].prHPI_address =
  405. phw->dw2040_HPIDSP + (ADDRESS +
  406. DSP_SPACING * dsp_index);
  407. phw->ado[dsp_index].prHPI_data =
  408. phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
  409. phw->ado[dsp_index].prHPI_data_auto_inc =
  410. phw->dw2040_HPIDSP + (DATA_AUTOINC +
  411. DSP_SPACING * dsp_index);
  412. HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
  413. phw->ado[dsp_index].prHPI_control,
  414. phw->ado[dsp_index].prHPI_address,
  415. phw->ado[dsp_index].prHPI_data,
  416. phw->ado[dsp_index].prHPI_data_auto_inc);
  417. phw->ado[dsp_index].pa_parent_adapter = pao;
  418. }
  419. phw->pCI2040HPI_error_count = 0;
  420. pao->has_control_cache = 0;
  421. /* Set the default number of DSPs on this card */
  422. /* This is (conditionally) adjusted after bootloading */
  423. /* of the first DSP in the bootload section. */
  424. phw->num_dsp = 1;
  425. boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
  426. if (boot_error)
  427. return boot_error;
  428. HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
  429. phw->message_buffer_address_on_dsp = 0L;
  430. phw->response_buffer_address_on_dsp = 0L;
  431. /* get info about the adapter by asking the adapter */
  432. /* send a HPI_ADAPTER_GET_INFO message */
  433. {
  434. struct hpi_message hm;
  435. struct hpi_response hr0; /* response from DSP 0 */
  436. struct hpi_response hr1; /* response from DSP 1 */
  437. u16 error = 0;
  438. HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
  439. memset(&hm, 0, sizeof(hm));
  440. hm.type = HPI_TYPE_MESSAGE;
  441. hm.size = sizeof(struct hpi_message);
  442. hm.object = HPI_OBJ_ADAPTER;
  443. hm.function = HPI_ADAPTER_GET_INFO;
  444. hm.adapter_index = 0;
  445. memset(&hr0, 0, sizeof(hr0));
  446. memset(&hr1, 0, sizeof(hr1));
  447. hr0.size = sizeof(hr0);
  448. hr1.size = sizeof(hr1);
  449. error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0);
  450. if (hr0.error) {
  451. HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error);
  452. return hr0.error;
  453. }
  454. if (phw->num_dsp == 2) {
  455. error = hpi6000_message_response_sequence(pao, 1, &hm,
  456. &hr1);
  457. if (error)
  458. return error;
  459. }
  460. pao->adapter_type = hr0.u.ax.info.adapter_type;
  461. pao->index = hr0.u.ax.info.adapter_index;
  462. }
  463. memset(&phw->control_cache[0], 0,
  464. sizeof(struct hpi_control_cache_single) *
  465. HPI_NMIXER_CONTROLS);
  466. /* Read the control cache length to figure out if it is turned on */
  467. control_cache_size =
  468. hpi_read_word(&phw->ado[0],
  469. HPI_HIF_ADDR(control_cache_size_in_bytes));
  470. if (control_cache_size) {
  471. control_cache_count =
  472. hpi_read_word(&phw->ado[0],
  473. HPI_HIF_ADDR(control_cache_count));
  474. phw->p_cache =
  475. hpi_alloc_control_cache(control_cache_count,
  476. control_cache_size, (unsigned char *)
  477. &phw->control_cache[0]
  478. );
  479. if (phw->p_cache)
  480. pao->has_control_cache = 1;
  481. }
  482. HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n",
  483. pao->adapter_type, pao->index);
  484. pao->open = 0; /* upon creation the adapter is closed */
  485. if (phw->p_cache)
  486. phw->p_cache->adap_idx = pao->index;
  487. return hpi_add_adapter(pao);
  488. }
  489. static void delete_adapter_obj(struct hpi_adapter_obj *pao)
  490. {
  491. struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
  492. if (pao->has_control_cache)
  493. hpi_free_control_cache(phw->p_cache);
  494. /* reset DSPs on adapter */
  495. iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET);
  496. kfree(phw);
  497. }
  498. /************************************************************************/
  499. /* ADAPTER */
  500. static void adapter_get_asserts(struct hpi_adapter_obj *pao,
  501. struct hpi_message *phm, struct hpi_response *phr)
  502. {
  503. #ifndef HIDE_PCI_ASSERTS
  504. /* if we have PCI2040 asserts then collect them */
  505. if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
  506. phr->u.ax.assert.p1 =
  507. gw_pci_read_asserts * 100 + gw_pci_write_asserts;
  508. phr->u.ax.assert.p2 = 0;
  509. phr->u.ax.assert.count = 1; /* assert count */
  510. phr->u.ax.assert.dsp_index = -1; /* "dsp index" */
  511. strcpy(phr->u.ax.assert.sz_message, "PCI2040 error");
  512. phr->u.ax.assert.dsp_msg_addr = 0;
  513. gw_pci_read_asserts = 0;
  514. gw_pci_write_asserts = 0;
  515. phr->error = 0;
  516. } else
  517. #endif
  518. hw_message(pao, phm, phr); /*get DSP asserts */
  519. return;
  520. }
  521. /************************************************************************/
  522. /* LOW-LEVEL */
  523. static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
  524. u32 *pos_error_code)
  525. {
  526. struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
  527. short error;
  528. u32 timeout;
  529. u32 read = 0;
  530. u32 i = 0;
  531. u32 data = 0;
  532. u32 j = 0;
  533. u32 test_addr = 0x80000000;
  534. u32 test_data = 0x00000001;
  535. u32 dw2040_reset = 0;
  536. u32 dsp_index = 0;
  537. u32 endian = 0;
  538. u32 adapter_info = 0;
  539. u32 delay = 0;
  540. struct dsp_code dsp_code;
  541. u16 boot_load_family = 0;
  542. /* NOTE don't use wAdapterType in this routine. It is not setup yet */
  543. switch (pao->pci.pci_dev->subsystem_device) {
  544. case 0x5100:
  545. case 0x5110: /* ASI5100 revB or higher with C6711D */
  546. case 0x5200: /* ASI5200 PCIe version of ASI5100 */
  547. case 0x6100:
  548. case 0x6200:
  549. boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
  550. break;
  551. default:
  552. return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
  553. }
  554. /* reset all DSPs, indicate two DSPs are present
  555. * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
  556. */
  557. endian = 0;
  558. dw2040_reset = 0x0003000F;
  559. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  560. /* read back register to make sure PCI2040 chip is functioning
  561. * note that bits 4..15 are read-only and so should always return zero,
  562. * even though we wrote 1 to them
  563. */
  564. hpios_delay_micro_seconds(1000);
  565. delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
  566. if (delay != dw2040_reset) {
  567. HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
  568. delay);
  569. return HPI6000_ERROR_INIT_PCI2040;
  570. }
  571. /* Indicate that DSP#0,1 is a C6X */
  572. iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
  573. /* set Bit30 and 29 - which will prevent Target aborts from being
  574. * issued upon HPI or GP error
  575. */
  576. iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
  577. /* isolate DSP HAD8 line from PCI2040 so that
  578. * Little endian can be set by pullup
  579. */
  580. dw2040_reset = dw2040_reset & (~(endian << 3));
  581. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  582. phw->ado[0].c_dsp_rev = 'B'; /* revB */
  583. phw->ado[1].c_dsp_rev = 'B'; /* revB */
  584. /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
  585. dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
  586. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  587. dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
  588. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  589. /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
  590. dw2040_reset = dw2040_reset & (~0x00000008);
  591. iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
  592. /*delay to allow DSP to get going */
  593. hpios_delay_micro_seconds(100);
  594. /* loop through all DSPs, downloading DSP code */
  595. for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
  596. struct dsp_obj *pdo = &phw->ado[dsp_index];
  597. /* configure DSP so that we download code into the SRAM */
  598. /* set control reg for little endian, HWOB=1 */
  599. iowrite32(0x00010001, pdo->prHPI_control);
  600. /* test access to the HPI address register (HPIA) */
  601. test_data = 0x00000001;
  602. for (j = 0; j < 32; j++) {
  603. iowrite32(test_data, pdo->prHPI_address);
  604. data = ioread32(pdo->prHPI_address);
  605. if (data != test_data) {
  606. HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
  607. test_data, data, dsp_index);
  608. return HPI6000_ERROR_INIT_DSPHPI;
  609. }
  610. test_data = test_data << 1;
  611. }
  612. /* if C6713 the setup PLL to generate 225MHz from 25MHz.
  613. * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
  614. * we're going to do this unconditionally
  615. */
  616. /* PLLDIV1 should have a value of 8000 after reset */
  617. /*
  618. if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
  619. */
  620. {
  621. /* C6713 datasheet says we cannot program PLL from HPI,
  622. * and indeed if we try to set the PLL multiply from the
  623. * HPI, the PLL does not seem to lock,
  624. * so we enable the PLL and use the default of x 7
  625. */
  626. /* bypass PLL */
  627. hpi_write_word(pdo, 0x01B7C100, 0x0000);
  628. hpios_delay_micro_seconds(100);
  629. /* ** use default of PLL x7 ** */
  630. /* EMIF = 225/3=75MHz */
  631. hpi_write_word(pdo, 0x01B7C120, 0x8002);
  632. hpios_delay_micro_seconds(100);
  633. /* peri = 225/2 */
  634. hpi_write_word(pdo, 0x01B7C11C, 0x8001);
  635. hpios_delay_micro_seconds(100);
  636. /* cpu = 225/1 */
  637. hpi_write_word(pdo, 0x01B7C118, 0x8000);
  638. /* ~2ms delay */
  639. hpios_delay_micro_seconds(2000);
  640. /* PLL not bypassed */
  641. hpi_write_word(pdo, 0x01B7C100, 0x0001);
  642. /* ~2ms delay */
  643. hpios_delay_micro_seconds(2000);
  644. }
  645. /* test r/w to internal DSP memory
  646. * C6711 has L2 cache mapped to 0x0 when reset
  647. *
  648. * revB - because of bug 3.0.1 last HPI read
  649. * (before HPI address issued) must be non-autoinc
  650. */
  651. /* test each bit in the 32bit word */
  652. for (i = 0; i < 100; i++) {
  653. test_addr = 0x00000000;
  654. test_data = 0x00000001;
  655. for (j = 0; j < 32; j++) {
  656. hpi_write_word(pdo, test_addr + i, test_data);
  657. data = hpi_read_word(pdo, test_addr + i);
  658. if (data != test_data) {
  659. HPI_DEBUG_LOG(ERROR,
  660. "DSP mem %x %x %x %x\n",
  661. test_addr + i, test_data,
  662. data, dsp_index);
  663. return HPI6000_ERROR_INIT_DSPINTMEM;
  664. }
  665. test_data = test_data << 1;
  666. }
  667. }
  668. /* memory map of ASI6200
  669. 00000000-0000FFFF 16Kx32 internal program
  670. 01800000-019FFFFF Internal peripheral
  671. 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
  672. 90000000-9000FFFF CE1 Async peripherals:
  673. EMIF config
  674. ------------
  675. Global EMIF control
  676. 0 -
  677. 1 -
  678. 2 -
  679. 3 CLK2EN = 1 CLKOUT2 enabled
  680. 4 CLK1EN = 0 CLKOUT1 disabled
  681. 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
  682. 6 -
  683. 7 NOHOLD = 1 external HOLD disabled
  684. 8 HOLDA = 0 HOLDA output is low
  685. 9 HOLD = 0 HOLD input is low
  686. 10 ARDY = 1 ARDY input is high
  687. 11 BUSREQ = 0 BUSREQ output is low
  688. 12,13 Reserved = 1
  689. */
  690. hpi_write_word(pdo, 0x01800000, 0x34A8);
  691. /* EMIF CE0 setup - 2Mx32 Sync DRAM
  692. 31..28 Wr setup
  693. 27..22 Wr strobe
  694. 21..20 Wr hold
  695. 19..16 Rd setup
  696. 15..14 -
  697. 13..8 Rd strobe
  698. 7..4 MTYPE 0011 Sync DRAM 32bits
  699. 3 Wr hold MSB
  700. 2..0 Rd hold
  701. */
  702. hpi_write_word(pdo, 0x01800008, 0x00000030);
  703. /* EMIF SDRAM Extension
  704. 31-21 0
  705. 20 WR2RD = 0
  706. 19-18 WR2DEAC = 1
  707. 17 WR2WR = 0
  708. 16-15 R2WDQM = 2
  709. 14-12 RD2WR = 4
  710. 11-10 RD2DEAC = 1
  711. 9 RD2RD = 1
  712. 8-7 THZP = 10b
  713. 6-5 TWR = 2-1 = 01b (tWR = 10ns)
  714. 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
  715. 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
  716. 1 CAS latency = 3 ECLK
  717. (for Micron 2M32-7 operating at 100Mhz)
  718. */
  719. /* need to use this else DSP code crashes */
  720. hpi_write_word(pdo, 0x01800020, 0x001BDF29);
  721. /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
  722. 31 - -
  723. 30 SDBSZ 1 4 bank
  724. 29..28 SDRSZ 00 11 row address pins
  725. 27..26 SDCSZ 01 8 column address pins
  726. 25 RFEN 1 refersh enabled
  727. 24 INIT 1 init SDRAM
  728. 23..20 TRCD 0001
  729. 19..16 TRP 0001
  730. 15..12 TRC 0110
  731. 11..0 - -
  732. */
  733. /* need to use this else DSP code crashes */
  734. hpi_write_word(pdo, 0x01800018, 0x47117000);
  735. /* EMIF SDRAM Refresh Timing */
  736. hpi_write_word(pdo, 0x0180001C, 0x00000410);
  737. /*MIF CE1 setup - Async peripherals
  738. @100MHz bus speed, each cycle is 10ns,
  739. 31..28 Wr setup = 1
  740. 27..22 Wr strobe = 3 30ns
  741. 21..20 Wr hold = 1
  742. 19..16 Rd setup =1
  743. 15..14 Ta = 2
  744. 13..8 Rd strobe = 3 30ns
  745. 7..4 MTYPE 0010 Async 32bits
  746. 3 Wr hold MSB =0
  747. 2..0 Rd hold = 1
  748. */
  749. {
  750. u32 cE1 =
  751. (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
  752. 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
  753. hpi_write_word(pdo, 0x01800004, cE1);
  754. }
  755. /* delay a little to allow SDRAM and DSP to "get going" */
  756. hpios_delay_micro_seconds(1000);
  757. /* test access to SDRAM */
  758. {
  759. test_addr = 0x80000000;
  760. test_data = 0x00000001;
  761. /* test each bit in the 32bit word */
  762. for (j = 0; j < 32; j++) {
  763. hpi_write_word(pdo, test_addr, test_data);
  764. data = hpi_read_word(pdo, test_addr);
  765. if (data != test_data) {
  766. HPI_DEBUG_LOG(ERROR,
  767. "DSP dram %x %x %x %x\n",
  768. test_addr, test_data, data,
  769. dsp_index);
  770. return HPI6000_ERROR_INIT_SDRAM1;
  771. }
  772. test_data = test_data << 1;
  773. }
  774. /* test every Nth address in the DRAM */
  775. #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
  776. #define DRAM_INC 1024
  777. test_addr = 0x80000000;
  778. test_data = 0x0;
  779. for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
  780. hpi_write_word(pdo, test_addr + i, test_data);
  781. test_data++;
  782. }
  783. test_addr = 0x80000000;
  784. test_data = 0x0;
  785. for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
  786. data = hpi_read_word(pdo, test_addr + i);
  787. if (data != test_data) {
  788. HPI_DEBUG_LOG(ERROR,
  789. "DSP dram %x %x %x %x\n",
  790. test_addr + i, test_data,
  791. data, dsp_index);
  792. return HPI6000_ERROR_INIT_SDRAM2;
  793. }
  794. test_data++;
  795. }
  796. }
  797. /* write the DSP code down into the DSPs memory */
  798. /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
  799. dsp_code.ps_dev = pao->pci.pci_dev;
  800. error = hpi_dsp_code_open(boot_load_family, &dsp_code,
  801. pos_error_code);
  802. if (error)
  803. return error;
  804. while (1) {
  805. u32 length;
  806. u32 address;
  807. u32 type;
  808. u32 *pcode;
  809. error = hpi_dsp_code_read_word(&dsp_code, &length);
  810. if (error)
  811. break;
  812. if (length == 0xFFFFFFFF)
  813. break; /* end of code */
  814. error = hpi_dsp_code_read_word(&dsp_code, &address);
  815. if (error)
  816. break;
  817. error = hpi_dsp_code_read_word(&dsp_code, &type);
  818. if (error)
  819. break;
  820. error = hpi_dsp_code_read_block(length, &dsp_code,
  821. &pcode);
  822. if (error)
  823. break;
  824. error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
  825. address, pcode, length);
  826. if (error)
  827. break;
  828. }
  829. if (error) {
  830. hpi_dsp_code_close(&dsp_code);
  831. return error;
  832. }
  833. /* verify that code was written correctly */
  834. /* this time through, assume no errors in DSP code file/array */
  835. hpi_dsp_code_rewind(&dsp_code);
  836. while (1) {
  837. u32 length;
  838. u32 address;
  839. u32 type;
  840. u32 *pcode;
  841. hpi_dsp_code_read_word(&dsp_code, &length);
  842. if (length == 0xFFFFFFFF)
  843. break; /* end of code */
  844. hpi_dsp_code_read_word(&dsp_code, &address);
  845. hpi_dsp_code_read_word(&dsp_code, &type);
  846. hpi_dsp_code_read_block(length, &dsp_code, &pcode);
  847. for (i = 0; i < length; i++) {
  848. data = hpi_read_word(pdo, address);
  849. if (data != *pcode) {
  850. error = HPI6000_ERROR_INIT_VERIFY;
  851. HPI_DEBUG_LOG(ERROR,
  852. "DSP verify %x %x %x %x\n",
  853. address, *pcode, data,
  854. dsp_index);
  855. break;
  856. }
  857. pcode++;
  858. address += 4;
  859. }
  860. if (error)
  861. break;
  862. }
  863. hpi_dsp_code_close(&dsp_code);
  864. if (error)
  865. return error;
  866. /* zero out the hostmailbox */
  867. {
  868. u32 address = HPI_HIF_ADDR(host_cmd);
  869. for (i = 0; i < 4; i++) {
  870. hpi_write_word(pdo, address, 0);
  871. address += 4;
  872. }
  873. }
  874. /* write the DSP number into the hostmailbox */
  875. /* structure before starting the DSP */
  876. hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
  877. /* write the DSP adapter Info into the */
  878. /* hostmailbox before starting the DSP */
  879. if (dsp_index > 0)
  880. hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
  881. adapter_info);
  882. /* step 3. Start code by sending interrupt */
  883. iowrite32(0x00030003, pdo->prHPI_control);
  884. hpios_delay_micro_seconds(10000);
  885. /* wait for a non-zero value in hostcmd -
  886. * indicating initialization is complete
  887. *
  888. * Init could take a while if DSP checks SDRAM memory
  889. * Was 200000. Increased to 2000000 for ASI8801 so we
  890. * don't get 938 errors.
  891. */
  892. timeout = 2000000;
  893. while (timeout) {
  894. do {
  895. read = hpi_read_word(pdo,
  896. HPI_HIF_ADDR(host_cmd));
  897. } while (--timeout
  898. && hpi6000_check_PCI2040_error_flag(pao,
  899. H6READ));
  900. if (read)
  901. break;
  902. /* The following is a workaround for bug #94:
  903. * Bluescreen on install and subsequent boots on a
  904. * DELL PowerEdge 600SC PC with 1.8GHz P4 and
  905. * ServerWorks chipset. Without this delay the system
  906. * locks up with a bluescreen (NOT GPF or pagefault).
  907. */
  908. else
  909. hpios_delay_micro_seconds(10000);
  910. }
  911. if (timeout == 0)
  912. return HPI6000_ERROR_INIT_NOACK;
  913. /* read the DSP adapter Info from the */
  914. /* hostmailbox structure after starting the DSP */
  915. if (dsp_index == 0) {
  916. /*u32 dwTestData=0; */
  917. u32 mask = 0;
  918. adapter_info =
  919. hpi_read_word(pdo,
  920. HPI_HIF_ADDR(adapter_info));
  921. if (HPI_ADAPTER_FAMILY_ASI
  922. (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
  923. (adapter_info)) ==
  924. HPI_ADAPTER_FAMILY_ASI(0x6200))
  925. /* all 6200 cards have this many DSPs */
  926. phw->num_dsp = 2;
  927. /* test that the PLD is programmed */
  928. /* and we can read/write 24bits */
  929. #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
  930. switch (boot_load_family) {
  931. case HPI_ADAPTER_FAMILY_ASI(0x6200):
  932. /* ASI6100/6200 has 24bit path to FPGA */
  933. mask = 0xFFFFFF00L;
  934. /* ASI5100 uses AX6 code, */
  935. /* but has no PLD r/w register to test */
  936. if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
  937. subsystem_device) ==
  938. HPI_ADAPTER_FAMILY_ASI(0x5100))
  939. mask = 0x00000000L;
  940. /* ASI5200 uses AX6 code, */
  941. /* but has no PLD r/w register to test */
  942. if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
  943. subsystem_device) ==
  944. HPI_ADAPTER_FAMILY_ASI(0x5200))
  945. mask = 0x00000000L;
  946. break;
  947. case HPI_ADAPTER_FAMILY_ASI(0x8800):
  948. /* ASI8800 has 16bit path to FPGA */
  949. mask = 0xFFFF0000L;
  950. break;
  951. }
  952. test_data = 0xAAAAAA00L & mask;
  953. /* write to 24 bit Debug register (D31-D8) */
  954. hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
  955. read = hpi_read_word(pdo,
  956. PLD_BASE_ADDRESS + 4L) & mask;
  957. if (read != test_data) {
  958. HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
  959. read);
  960. return HPI6000_ERROR_INIT_PLDTEST1;
  961. }
  962. test_data = 0x55555500L & mask;
  963. hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
  964. read = hpi_read_word(pdo,
  965. PLD_BASE_ADDRESS + 4L) & mask;
  966. if (read != test_data) {
  967. HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
  968. read);
  969. return HPI6000_ERROR_INIT_PLDTEST2;
  970. }
  971. }
  972. } /* for numDSP */
  973. return 0;
  974. }
  975. #define PCI_TIMEOUT 100
  976. static int hpi_set_address(struct dsp_obj *pdo, u32 address)
  977. {
  978. u32 timeout = PCI_TIMEOUT;
  979. do {
  980. iowrite32(address, pdo->prHPI_address);
  981. } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
  982. H6WRITE)
  983. && --timeout);
  984. if (timeout)
  985. return 0;
  986. return 1;
  987. }
  988. /* write one word to the HPI port */
  989. static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
  990. {
  991. if (hpi_set_address(pdo, address))
  992. return;
  993. iowrite32(data, pdo->prHPI_data);
  994. }
  995. /* read one word from the HPI port */
  996. static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
  997. {
  998. u32 data = 0;
  999. if (hpi_set_address(pdo, address))
  1000. return 0; /*? No way to return error */
  1001. /* take care of errata in revB DSP (2.0.1) */
  1002. data = ioread32(pdo->prHPI_data);
  1003. return data;
  1004. }
  1005. /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
  1006. static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  1007. u32 length)
  1008. {
  1009. u16 length16 = length - 1;
  1010. if (length == 0)
  1011. return;
  1012. if (hpi_set_address(pdo, address))
  1013. return;
  1014. iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
  1015. /* take care of errata in revB DSP (2.0.1) */
  1016. /* must end with non auto-inc */
  1017. iowrite32(*(pdata + length - 1), pdo->prHPI_data);
  1018. }
  1019. /** read a block of 32bit words from the DSP HPI port using auto-inc mode
  1020. */
  1021. static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
  1022. u32 length)
  1023. {
  1024. u16 length16 = length - 1;
  1025. if (length == 0)
  1026. return;
  1027. if (hpi_set_address(pdo, address))
  1028. return;
  1029. ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
  1030. /* take care of errata in revB DSP (2.0.1) */
  1031. /* must end with non auto-inc */
  1032. *(pdata + length - 1) = ioread32(pdo->prHPI_data);
  1033. }
  1034. static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
  1035. u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
  1036. {
  1037. struct dsp_obj *pdo =
  1038. &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
  1039. u32 time_out = PCI_TIMEOUT;
  1040. int c6711_burst_size = 128;
  1041. u32 local_hpi_address = hpi_address;
  1042. int local_count = count;
  1043. int xfer_size;
  1044. u32 *pdata = source;
  1045. while (local_count) {
  1046. if (local_count > c6711_burst_size)
  1047. xfer_size = c6711_burst_size;
  1048. else
  1049. xfer_size = local_count;
  1050. time_out = PCI_TIMEOUT;
  1051. do {
  1052. hpi_write_block(pdo, local_hpi_address, pdata,
  1053. xfer_size);
  1054. } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
  1055. && --time_out);
  1056. if (!time_out)
  1057. break;
  1058. pdata += xfer_size;
  1059. local_hpi_address += sizeof(u32) * xfer_size;
  1060. local_count -= xfer_size;
  1061. }
  1062. if (time_out)
  1063. return 0;
  1064. else
  1065. return 1;
  1066. }
  1067. static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
  1068. u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
  1069. {
  1070. struct dsp_obj *pdo =
  1071. &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
  1072. u32 time_out = PCI_TIMEOUT;
  1073. int c6711_burst_size = 16;
  1074. u32 local_hpi_address = hpi_address;
  1075. int local_count = count;
  1076. int xfer_size;
  1077. u32 *pdata = dest;
  1078. u32 loop_count = 0;
  1079. while (local_count) {
  1080. if (local_count > c6711_burst_size)
  1081. xfer_size = c6711_burst_size;
  1082. else
  1083. xfer_size = local_count;
  1084. time_out = PCI_TIMEOUT;
  1085. do {
  1086. hpi_read_block(pdo, local_hpi_address, pdata,
  1087. xfer_size);
  1088. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1089. && --time_out);
  1090. if (!time_out)
  1091. break;
  1092. pdata += xfer_size;
  1093. local_hpi_address += sizeof(u32) * xfer_size;
  1094. local_count -= xfer_size;
  1095. loop_count++;
  1096. }
  1097. if (time_out)
  1098. return 0;
  1099. else
  1100. return 1;
  1101. }
  1102. static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
  1103. u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
  1104. {
  1105. struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
  1106. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1107. u32 timeout;
  1108. u16 ack;
  1109. u32 address;
  1110. u32 length;
  1111. u32 *p_data;
  1112. u16 error = 0;
  1113. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
  1114. if (ack & HPI_HIF_ERROR_MASK) {
  1115. pao->dsp_crashed++;
  1116. return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
  1117. }
  1118. pao->dsp_crashed = 0;
  1119. /* get the message address and size */
  1120. if (phw->message_buffer_address_on_dsp == 0) {
  1121. timeout = TIMEOUT;
  1122. do {
  1123. address =
  1124. hpi_read_word(pdo,
  1125. HPI_HIF_ADDR(message_buffer_address));
  1126. phw->message_buffer_address_on_dsp = address;
  1127. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1128. && --timeout);
  1129. if (!timeout)
  1130. return HPI6000_ERROR_MSG_GET_ADR;
  1131. } else
  1132. address = phw->message_buffer_address_on_dsp;
  1133. length = phm->size;
  1134. /* send the message */
  1135. p_data = (u32 *)phm;
  1136. if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
  1137. (u16)length / 4))
  1138. return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
  1139. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
  1140. return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
  1141. hpi6000_send_dsp_interrupt(pdo);
  1142. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
  1143. if (ack & HPI_HIF_ERROR_MASK)
  1144. return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
  1145. /* get the response address */
  1146. if (phw->response_buffer_address_on_dsp == 0) {
  1147. timeout = TIMEOUT;
  1148. do {
  1149. address =
  1150. hpi_read_word(pdo,
  1151. HPI_HIF_ADDR(response_buffer_address));
  1152. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1153. && --timeout);
  1154. phw->response_buffer_address_on_dsp = address;
  1155. if (!timeout)
  1156. return HPI6000_ERROR_RESP_GET_ADR;
  1157. } else
  1158. address = phw->response_buffer_address_on_dsp;
  1159. /* read the length of the response back from the DSP */
  1160. timeout = TIMEOUT;
  1161. do {
  1162. length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
  1163. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
  1164. if (!timeout)
  1165. length = sizeof(struct hpi_response);
  1166. /* get the response */
  1167. p_data = (u32 *)phr;
  1168. if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
  1169. (u16)length / 4))
  1170. return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
  1171. /* set i/f back to idle */
  1172. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
  1173. return HPI6000_ERROR_MSG_RESP_IDLECMD;
  1174. hpi6000_send_dsp_interrupt(pdo);
  1175. error = hpi_validate_response(phm, phr);
  1176. return error;
  1177. }
  1178. /* have to set up the below defines to match stuff in the MAP file */
  1179. #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
  1180. #define MSG_LENGTH 11
  1181. #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
  1182. #define RESP_LENGTH 16
  1183. #define QUEUE_START (HPI_HIF_BASE+0x88)
  1184. #define QUEUE_SIZE 0x8000
  1185. static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
  1186. {
  1187. /*#define CHECKING // comment this line in to enable checking */
  1188. #ifdef CHECKING
  1189. if (address < (u32)MSG_ADDRESS)
  1190. return 0;
  1191. if (address > (u32)(QUEUE_START + QUEUE_SIZE))
  1192. return 0;
  1193. if ((address + (length_in_dwords << 2)) >
  1194. (u32)(QUEUE_START + QUEUE_SIZE))
  1195. return 0;
  1196. #else
  1197. (void)address;
  1198. (void)length_in_dwords;
  1199. return 1;
  1200. #endif
  1201. }
  1202. static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  1203. struct hpi_message *phm, struct hpi_response *phr)
  1204. {
  1205. struct dsp_obj *pdo =
  1206. &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
  1207. u32 data_sent = 0;
  1208. u16 ack;
  1209. u32 length, address;
  1210. u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
  1211. u16 time_out = 8;
  1212. (void)phr;
  1213. /* round dwDataSize down to nearest 4 bytes */
  1214. while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
  1215. && --time_out) {
  1216. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
  1217. if (ack & HPI_HIF_ERROR_MASK)
  1218. return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
  1219. if (hpi6000_send_host_command(pao, dsp_index,
  1220. HPI_HIF_SEND_DATA))
  1221. return HPI6000_ERROR_SEND_DATA_CMD;
  1222. hpi6000_send_dsp_interrupt(pdo);
  1223. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
  1224. if (ack & HPI_HIF_ERROR_MASK)
  1225. return HPI6000_ERROR_SEND_DATA_ACK;
  1226. do {
  1227. /* get the address and size */
  1228. address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
  1229. /* DSP returns number of DWORDS */
  1230. length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
  1231. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
  1232. if (!hpi6000_send_data_check_adr(address, length))
  1233. return HPI6000_ERROR_SEND_DATA_ADR;
  1234. /* send the data. break data into 512 DWORD blocks (2K bytes)
  1235. * and send using block write. 2Kbytes is the max as this is the
  1236. * memory window given to the HPI data register by the PCI2040
  1237. */
  1238. {
  1239. u32 len = length;
  1240. u32 blk_len = 512;
  1241. while (len) {
  1242. if (len < blk_len)
  1243. blk_len = len;
  1244. if (hpi6000_dsp_block_write32(pao, dsp_index,
  1245. address, p_data, blk_len))
  1246. return HPI6000_ERROR_SEND_DATA_WRITE;
  1247. address += blk_len * 4;
  1248. p_data += blk_len;
  1249. len -= blk_len;
  1250. }
  1251. }
  1252. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
  1253. return HPI6000_ERROR_SEND_DATA_IDLECMD;
  1254. hpi6000_send_dsp_interrupt(pdo);
  1255. data_sent += length * 4;
  1256. }
  1257. if (!time_out)
  1258. return HPI6000_ERROR_SEND_DATA_TIMEOUT;
  1259. return 0;
  1260. }
  1261. static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
  1262. struct hpi_message *phm, struct hpi_response *phr)
  1263. {
  1264. struct dsp_obj *pdo =
  1265. &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
  1266. u32 data_got = 0;
  1267. u16 ack;
  1268. u32 length, address;
  1269. u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
  1270. (void)phr; /* this parameter not used! */
  1271. /* round dwDataSize down to nearest 4 bytes */
  1272. while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
  1273. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
  1274. if (ack & HPI_HIF_ERROR_MASK)
  1275. return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
  1276. if (hpi6000_send_host_command(pao, dsp_index,
  1277. HPI_HIF_GET_DATA))
  1278. return HPI6000_ERROR_GET_DATA_CMD;
  1279. hpi6000_send_dsp_interrupt(pdo);
  1280. ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
  1281. if (ack & HPI_HIF_ERROR_MASK)
  1282. return HPI6000_ERROR_GET_DATA_ACK;
  1283. /* get the address and size */
  1284. do {
  1285. address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
  1286. length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
  1287. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
  1288. /* read the data */
  1289. {
  1290. u32 len = length;
  1291. u32 blk_len = 512;
  1292. while (len) {
  1293. if (len < blk_len)
  1294. blk_len = len;
  1295. if (hpi6000_dsp_block_read32(pao, dsp_index,
  1296. address, p_data, blk_len))
  1297. return HPI6000_ERROR_GET_DATA_READ;
  1298. address += blk_len * 4;
  1299. p_data += blk_len;
  1300. len -= blk_len;
  1301. }
  1302. }
  1303. if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
  1304. return HPI6000_ERROR_GET_DATA_IDLECMD;
  1305. hpi6000_send_dsp_interrupt(pdo);
  1306. data_got += length * 4;
  1307. }
  1308. return 0;
  1309. }
  1310. static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
  1311. {
  1312. iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
  1313. }
  1314. static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
  1315. u16 dsp_index, u32 host_cmd)
  1316. {
  1317. struct dsp_obj *pdo =
  1318. &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
  1319. u32 timeout = TIMEOUT;
  1320. /* set command */
  1321. do {
  1322. hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
  1323. /* flush the FIFO */
  1324. hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
  1325. } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
  1326. /* reset the interrupt bit */
  1327. iowrite32(0x00040004, pdo->prHPI_control);
  1328. if (timeout)
  1329. return 0;
  1330. else
  1331. return 1;
  1332. }
  1333. /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
  1334. static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
  1335. u16 read_or_write)
  1336. {
  1337. u32 hPI_error;
  1338. struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
  1339. /* read the error bits from the PCI2040 */
  1340. hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
  1341. if (hPI_error) {
  1342. /* reset the error flag */
  1343. iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
  1344. phw->pCI2040HPI_error_count++;
  1345. if (read_or_write == 1)
  1346. gw_pci_read_asserts++; /************* inc global */
  1347. else
  1348. gw_pci_write_asserts++;
  1349. return 1;
  1350. } else
  1351. return 0;
  1352. }
  1353. static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
  1354. u32 ack_value)
  1355. {
  1356. struct dsp_obj *pdo =
  1357. &(*(struct hpi_hw_obj *)pao->priv).ado[dsp_index];
  1358. u32 ack = 0L;
  1359. u32 timeout;
  1360. u32 hPIC = 0L;
  1361. /* wait for host interrupt to signal ack is ready */
  1362. timeout = TIMEOUT;
  1363. while (--timeout) {
  1364. hPIC = ioread32(pdo->prHPI_control);
  1365. if (hPIC & 0x04) /* 0x04 = HINT from DSP */
  1366. break;
  1367. }
  1368. if (timeout == 0)
  1369. return HPI_HIF_ERROR_MASK;
  1370. /* wait for dwAckValue */
  1371. timeout = TIMEOUT;
  1372. while (--timeout) {
  1373. /* read the ack mailbox */
  1374. ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
  1375. if (ack == ack_value)
  1376. break;
  1377. if ((ack & HPI_HIF_ERROR_MASK)
  1378. && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
  1379. break;
  1380. /*for (i=0;i<1000;i++) */
  1381. /* dwPause=i+1; */
  1382. }
  1383. if (ack & HPI_HIF_ERROR_MASK)
  1384. /* indicates bad read from DSP -
  1385. typically 0xffffff is read for some reason */
  1386. ack = HPI_HIF_ERROR_MASK;
  1387. if (timeout == 0)
  1388. ack = HPI_HIF_ERROR_MASK;
  1389. return (short)ack;
  1390. }
  1391. static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
  1392. struct hpi_message *phm)
  1393. {
  1394. const u16 dsp_index = 0;
  1395. struct hpi_hw_obj *phw = (struct hpi_hw_obj *)pao->priv;
  1396. struct dsp_obj *pdo = &phw->ado[dsp_index];
  1397. u32 timeout;
  1398. u32 cache_dirty_flag;
  1399. u16 err;
  1400. hpios_dsplock_lock(pao);
  1401. timeout = TIMEOUT;
  1402. do {
  1403. cache_dirty_flag =
  1404. hpi_read_word((struct dsp_obj *)pdo,
  1405. HPI_HIF_ADDR(control_cache_is_dirty));
  1406. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
  1407. if (!timeout) {
  1408. err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
  1409. goto unlock;
  1410. }
  1411. if (cache_dirty_flag) {
  1412. /* read the cached controls */
  1413. u32 address;
  1414. u32 length;
  1415. timeout = TIMEOUT;
  1416. if (pdo->control_cache_address_on_dsp == 0) {
  1417. do {
  1418. address =
  1419. hpi_read_word((struct dsp_obj *)pdo,
  1420. HPI_HIF_ADDR(control_cache_address));
  1421. length = hpi_read_word((struct dsp_obj *)pdo,
  1422. HPI_HIF_ADDR
  1423. (control_cache_size_in_bytes));
  1424. } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
  1425. && --timeout);
  1426. if (!timeout) {
  1427. err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
  1428. goto unlock;
  1429. }
  1430. pdo->control_cache_address_on_dsp = address;
  1431. pdo->control_cache_length_on_dsp = length;
  1432. } else {
  1433. address = pdo->control_cache_address_on_dsp;
  1434. length = pdo->control_cache_length_on_dsp;
  1435. }
  1436. if (hpi6000_dsp_block_read32(pao, dsp_index, address,
  1437. (u32 *)&phw->control_cache[0],
  1438. length / sizeof(u32))) {
  1439. err = HPI6000_ERROR_CONTROL_CACHE_READ;
  1440. goto unlock;
  1441. }
  1442. do {
  1443. hpi_write_word((struct dsp_obj *)pdo,
  1444. HPI_HIF_ADDR(control_cache_is_dirty), 0);
  1445. /* flush the FIFO */
  1446. hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
  1447. } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
  1448. && --timeout);
  1449. if (!timeout) {
  1450. err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
  1451. goto unlock;
  1452. }
  1453. }
  1454. err = 0;
  1455. unlock:
  1456. hpios_dsplock_unlock(pao);
  1457. return err;
  1458. }
  1459. /** Get dsp index for multi DSP adapters only */
  1460. static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
  1461. {
  1462. u16 ret = 0;
  1463. switch (phm->object) {
  1464. case HPI_OBJ_ISTREAM:
  1465. if (phm->obj_index < 2)
  1466. ret = 1;
  1467. break;
  1468. case HPI_OBJ_PROFILE:
  1469. ret = phm->obj_index;
  1470. break;
  1471. default:
  1472. break;
  1473. }
  1474. return ret;
  1475. }
  1476. /** Complete transaction with DSP
  1477. Send message, get response, send or get stream data if any.
  1478. */
  1479. static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
  1480. struct hpi_response *phr)
  1481. {
  1482. u16 error = 0;
  1483. u16 dsp_index = 0;
  1484. u16 num_dsp = ((struct hpi_hw_obj *)pao->priv)->num_dsp;
  1485. if (num_dsp < 2)
  1486. dsp_index = 0;
  1487. else {
  1488. dsp_index = get_dsp_index(pao, phm);
  1489. /* is this checked on the DSP anyway? */
  1490. if ((phm->function == HPI_ISTREAM_GROUP_ADD)
  1491. || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
  1492. struct hpi_message hm;
  1493. u16 add_index;
  1494. hm.obj_index = phm->u.d.u.stream.stream_index;
  1495. hm.object = phm->u.d.u.stream.object_type;
  1496. add_index = get_dsp_index(pao, &hm);
  1497. if (add_index != dsp_index) {
  1498. phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
  1499. return;
  1500. }
  1501. }
  1502. }
  1503. hpios_dsplock_lock(pao);
  1504. error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
  1505. if (error) /* something failed in the HPI/DSP interface */
  1506. goto err;
  1507. if (phr->error) /* something failed in the DSP */
  1508. goto out;
  1509. switch (phm->function) {
  1510. case HPI_OSTREAM_WRITE:
  1511. case HPI_ISTREAM_ANC_WRITE:
  1512. error = hpi6000_send_data(pao, dsp_index, phm, phr);
  1513. break;
  1514. case HPI_ISTREAM_READ:
  1515. case HPI_OSTREAM_ANC_READ:
  1516. error = hpi6000_get_data(pao, dsp_index, phm, phr);
  1517. break;
  1518. case HPI_ADAPTER_GET_ASSERT:
  1519. phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */
  1520. if (num_dsp == 2) {
  1521. if (!phr->u.ax.assert.count) {
  1522. /* no assert from dsp 0, check dsp 1 */
  1523. error = hpi6000_message_response_sequence(pao,
  1524. 1, phm, phr);
  1525. phr->u.ax.assert.dsp_index = 1;
  1526. }
  1527. }
  1528. }
  1529. err:
  1530. if (error) {
  1531. if (error >= HPI_ERROR_BACKEND_BASE) {
  1532. phr->error = HPI_ERROR_DSP_COMMUNICATION;
  1533. phr->specific_error = error;
  1534. } else {
  1535. phr->error = error;
  1536. }
  1537. /* just the header of the response is valid */
  1538. phr->size = sizeof(struct hpi_response_header);
  1539. }
  1540. out:
  1541. hpios_dsplock_unlock(pao);
  1542. return;
  1543. }