Kconfig 9.8 KB

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  1. menu "Platform support"
  2. source "arch/powerpc/platforms/pseries/Kconfig"
  3. source "arch/powerpc/platforms/iseries/Kconfig"
  4. source "arch/powerpc/platforms/chrp/Kconfig"
  5. source "arch/powerpc/platforms/512x/Kconfig"
  6. source "arch/powerpc/platforms/52xx/Kconfig"
  7. source "arch/powerpc/platforms/powermac/Kconfig"
  8. source "arch/powerpc/platforms/prep/Kconfig"
  9. source "arch/powerpc/platforms/maple/Kconfig"
  10. source "arch/powerpc/platforms/pasemi/Kconfig"
  11. source "arch/powerpc/platforms/ps3/Kconfig"
  12. source "arch/powerpc/platforms/cell/Kconfig"
  13. source "arch/powerpc/platforms/8xx/Kconfig"
  14. source "arch/powerpc/platforms/82xx/Kconfig"
  15. source "arch/powerpc/platforms/83xx/Kconfig"
  16. source "arch/powerpc/platforms/85xx/Kconfig"
  17. source "arch/powerpc/platforms/86xx/Kconfig"
  18. source "arch/powerpc/platforms/embedded6xx/Kconfig"
  19. source "arch/powerpc/platforms/44x/Kconfig"
  20. source "arch/powerpc/platforms/40x/Kconfig"
  21. source "arch/powerpc/platforms/amigaone/Kconfig"
  22. source "arch/powerpc/platforms/wsp/Kconfig"
  23. config KVM_GUEST
  24. bool "KVM Guest support"
  25. default y
  26. ---help---
  27. This option enables various optimizations for running under the KVM
  28. hypervisor. Overhead for the kernel when not running inside KVM should
  29. be minimal.
  30. In case of doubt, say Y
  31. config PPC_NATIVE
  32. bool
  33. depends on 6xx || PPC64
  34. help
  35. Support for running natively on the hardware, i.e. without
  36. a hypervisor. This option is not user-selectable but should
  37. be selected by all platforms that need it.
  38. config PPC_OF_BOOT_TRAMPOLINE
  39. bool "Support booting from Open Firmware or yaboot"
  40. depends on 6xx || PPC64
  41. default y
  42. help
  43. Support from booting from Open Firmware or yaboot using an
  44. Open Firmware client interface. This enables the kernel to
  45. communicate with open firmware to retrieve system information
  46. such as the device tree.
  47. In case of doubt, say Y
  48. config UDBG_RTAS_CONSOLE
  49. bool "RTAS based debug console"
  50. depends on PPC_RTAS
  51. default n
  52. config PPC_SMP_MUXED_IPI
  53. bool
  54. help
  55. Select this opton if your platform supports SMP and your
  56. interrupt controller provides less than 4 interrupts to each
  57. cpu. This will enable the generic code to multiplex the 4
  58. messages on to one ipi.
  59. config PPC_UDBG_BEAT
  60. bool "BEAT based debug console"
  61. depends on PPC_CELLEB
  62. default n
  63. config IPIC
  64. bool
  65. default n
  66. config MPIC
  67. bool
  68. default n
  69. config MPIC_WEIRD
  70. bool
  71. default n
  72. config PPC_I8259
  73. bool
  74. default n
  75. config U3_DART
  76. bool
  77. depends on PPC64
  78. default n
  79. config PPC_RTAS
  80. bool
  81. default n
  82. config RTAS_ERROR_LOGGING
  83. bool
  84. depends on PPC_RTAS
  85. default n
  86. config PPC_RTAS_DAEMON
  87. bool
  88. depends on PPC_RTAS
  89. default n
  90. config RTAS_PROC
  91. bool "Proc interface to RTAS"
  92. depends on PPC_RTAS
  93. default y
  94. config RTAS_FLASH
  95. tristate "Firmware flash interface"
  96. depends on PPC64 && RTAS_PROC
  97. config MMIO_NVRAM
  98. bool
  99. default n
  100. config MPIC_U3_HT_IRQS
  101. bool
  102. default n
  103. config MPIC_BROKEN_REGREAD
  104. bool
  105. depends on MPIC
  106. help
  107. This option enables a MPIC driver workaround for some chips
  108. that have a bug that causes some interrupt source information
  109. to not read back properly. It is safe to use on other chips as
  110. well, but enabling it uses about 8KB of memory to keep copies
  111. of the register contents in software.
  112. config IBMVIO
  113. depends on PPC_PSERIES || PPC_ISERIES
  114. bool
  115. default y
  116. config IBMEBUS
  117. depends on PPC_PSERIES
  118. bool "Support for GX bus based adapters"
  119. help
  120. Bus device driver for GX bus based adapters.
  121. config PPC_MPC106
  122. bool
  123. default n
  124. config PPC_970_NAP
  125. bool
  126. default n
  127. config PPC_P7_NAP
  128. bool
  129. default n
  130. config PPC_INDIRECT_IO
  131. bool
  132. select GENERIC_IOMAP
  133. config PPC_INDIRECT_PIO
  134. bool
  135. select PPC_INDIRECT_IO
  136. config PPC_INDIRECT_MMIO
  137. bool
  138. select PPC_INDIRECT_IO
  139. config PPC_IO_WORKAROUNDS
  140. bool
  141. config GENERIC_IOMAP
  142. bool
  143. source "drivers/cpufreq/Kconfig"
  144. menu "CPU Frequency drivers"
  145. depends on CPU_FREQ
  146. config CPU_FREQ_PMAC
  147. bool "Support for Apple PowerBooks"
  148. depends on ADB_PMU && PPC32
  149. select CPU_FREQ_TABLE
  150. help
  151. This adds support for frequency switching on Apple PowerBooks,
  152. this currently includes some models of iBook & Titanium
  153. PowerBook.
  154. config CPU_FREQ_PMAC64
  155. bool "Support for some Apple G5s"
  156. depends on PPC_PMAC && PPC64
  157. select CPU_FREQ_TABLE
  158. help
  159. This adds support for frequency switching on Apple iMac G5,
  160. and some of the more recent desktop G5 machines as well.
  161. config PPC_PASEMI_CPUFREQ
  162. bool "Support for PA Semi PWRficient"
  163. depends on PPC_PASEMI
  164. default y
  165. select CPU_FREQ_TABLE
  166. help
  167. This adds the support for frequency switching on PA Semi
  168. PWRficient processors.
  169. endmenu
  170. config PPC601_SYNC_FIX
  171. bool "Workarounds for PPC601 bugs"
  172. depends on 6xx && (PPC_PREP || PPC_PMAC)
  173. help
  174. Some versions of the PPC601 (the first PowerPC chip) have bugs which
  175. mean that extra synchronization instructions are required near
  176. certain instructions, typically those that make major changes to the
  177. CPU state. These extra instructions reduce performance slightly.
  178. If you say N here, these extra instructions will not be included,
  179. resulting in a kernel which will run faster but may not run at all
  180. on some systems with the PPC601 chip.
  181. If in doubt, say Y here.
  182. config TAU
  183. bool "On-chip CPU temperature sensor support"
  184. depends on 6xx
  185. help
  186. G3 and G4 processors have an on-chip temperature sensor called the
  187. 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
  188. temperature within 2-4 degrees Celsius. This option shows the current
  189. on-die temperature in /proc/cpuinfo if the cpu supports it.
  190. Unfortunately, on some chip revisions, this sensor is very inaccurate
  191. and in many cases, does not work at all, so don't assume the cpu
  192. temp is actually what /proc/cpuinfo says it is.
  193. config TAU_INT
  194. bool "Interrupt driven TAU driver (DANGEROUS)"
  195. depends on TAU
  196. ---help---
  197. The TAU supports an interrupt driven mode which causes an interrupt
  198. whenever the temperature goes out of range. This is the fastest way
  199. to get notified the temp has exceeded a range. With this option off,
  200. a timer is used to re-check the temperature periodically.
  201. However, on some cpus it appears that the TAU interrupt hardware
  202. is buggy and can cause a situation which would lead unexplained hard
  203. lockups.
  204. Unless you are extending the TAU driver, or enjoy kernel/hardware
  205. debugging, leave this option off.
  206. config TAU_AVERAGE
  207. bool "Average high and low temp"
  208. depends on TAU
  209. ---help---
  210. The TAU hardware can compare the temperature to an upper and lower
  211. bound. The default behavior is to show both the upper and lower
  212. bound in /proc/cpuinfo. If the range is large, the temperature is
  213. either changing a lot, or the TAU hardware is broken (likely on some
  214. G4's). If the range is small (around 4 degrees), the temperature is
  215. relatively stable. If you say Y here, a single temperature value,
  216. halfway between the upper and lower bounds, will be reported in
  217. /proc/cpuinfo.
  218. If in doubt, say N here.
  219. config QUICC_ENGINE
  220. bool "Freescale QUICC Engine (QE) Support"
  221. depends on FSL_SOC
  222. select PPC_LIB_RHEAP
  223. select CRC32
  224. help
  225. The QUICC Engine (QE) is a new generation of communications
  226. coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
  227. Selecting this option means that you wish to build a kernel
  228. for a machine with a QE coprocessor.
  229. config QE_GPIO
  230. bool "QE GPIO support"
  231. depends on QUICC_ENGINE
  232. select GENERIC_GPIO
  233. select ARCH_REQUIRE_GPIOLIB
  234. help
  235. Say Y here if you're going to use hardware that connects to the
  236. QE GPIOs.
  237. config CPM2
  238. bool "Enable support for the CPM2 (Communications Processor Module)"
  239. depends on (FSL_SOC_BOOKE && PPC32) || 8260
  240. select CPM
  241. select PPC_LIB_RHEAP
  242. select PPC_PCI_CHOICE
  243. select ARCH_REQUIRE_GPIOLIB
  244. select GENERIC_GPIO
  245. help
  246. The CPM2 (Communications Processor Module) is a coprocessor on
  247. embedded CPUs made by Freescale. Selecting this option means that
  248. you wish to build a kernel for a machine with a CPM2 coprocessor
  249. on it (826x, 827x, 8560).
  250. config AXON_RAM
  251. tristate "Axon DDR2 memory device driver"
  252. depends on PPC_IBM_CELL_BLADE && BLOCK
  253. default m
  254. help
  255. It registers one block device per Axon's DDR2 memory bank found
  256. on a system. Block devices are called axonram?, their major and
  257. minor numbers are available in /proc/devices, /proc/partitions or
  258. in /sys/block/axonram?/dev.
  259. config FSL_ULI1575
  260. bool
  261. default n
  262. select GENERIC_ISA_DMA
  263. help
  264. Supports for the ULI1575 PCIe south bridge that exists on some
  265. Freescale reference boards. The boards all use the ULI in pretty
  266. much the same way.
  267. config CPM
  268. bool
  269. select PPC_CLOCK
  270. config OF_RTC
  271. bool
  272. help
  273. Uses information from the OF or flattened device tree to instantiate
  274. platform devices for direct mapped RTC chips like the DS1742 or DS1743.
  275. source "arch/powerpc/sysdev/bestcomm/Kconfig"
  276. config MPC8xxx_GPIO
  277. bool "MPC512x/MPC8xxx GPIO support"
  278. depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
  279. FSL_SOC_BOOKE || PPC_86xx
  280. select GENERIC_GPIO
  281. select ARCH_REQUIRE_GPIOLIB
  282. help
  283. Say Y here if you're going to use hardware that connects to the
  284. MPC512x/831x/834x/837x/8572/8610 GPIOs.
  285. config SIMPLE_GPIO
  286. bool "Support for simple, memory-mapped GPIO controllers"
  287. depends on PPC
  288. select GENERIC_GPIO
  289. select ARCH_REQUIRE_GPIOLIB
  290. help
  291. Say Y here to support simple, memory-mapped GPIO controllers.
  292. These are usually BCSRs used to control board's switches, LEDs,
  293. chip-selects, Ethernet/USB PHY's power and various other small
  294. on-board peripherals.
  295. config MCU_MPC8349EMITX
  296. tristate "MPC8349E-mITX MCU driver"
  297. depends on I2C && PPC_83xx
  298. select GENERIC_GPIO
  299. select ARCH_REQUIRE_GPIOLIB
  300. help
  301. Say Y here to enable soft power-off functionality on the Freescale
  302. boards with the MPC8349E-mITX-compatible MCU chips. This driver will
  303. also register MCU GPIOs with the generic GPIO API, so you'll able
  304. to use MCU pins as GPIOs.
  305. config XILINX_PCI
  306. bool "Xilinx PCI host bridge support"
  307. depends on PCI && XILINX_VIRTEX
  308. endmenu