intel_hdmi.c 17 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2009 Intel Corporation
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Jesse Barnes <jesse.barnes@intel.com>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_crtc.h"
  34. #include "drm_edid.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. struct intel_hdmi {
  39. struct intel_encoder base;
  40. u32 sdvox_reg;
  41. int ddc_bus;
  42. uint32_t color_range;
  43. bool has_hdmi_sink;
  44. bool has_audio;
  45. enum hdmi_force_audio force_audio;
  46. void (*write_infoframe)(struct drm_encoder *encoder,
  47. struct dip_infoframe *frame);
  48. };
  49. static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  50. {
  51. return container_of(encoder, struct intel_hdmi, base.base);
  52. }
  53. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  54. {
  55. return container_of(intel_attached_encoder(connector),
  56. struct intel_hdmi, base);
  57. }
  58. void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  59. {
  60. uint8_t *data = (uint8_t *)frame;
  61. uint8_t sum = 0;
  62. unsigned i;
  63. frame->checksum = 0;
  64. frame->ecc = 0;
  65. for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  66. sum += data[i];
  67. frame->checksum = 0x100 - sum;
  68. }
  69. static u32 intel_infoframe_index(struct dip_infoframe *frame)
  70. {
  71. u32 flags = 0;
  72. switch (frame->type) {
  73. case DIP_TYPE_AVI:
  74. flags |= VIDEO_DIP_SELECT_AVI;
  75. break;
  76. case DIP_TYPE_SPD:
  77. flags |= VIDEO_DIP_SELECT_SPD;
  78. break;
  79. default:
  80. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  81. break;
  82. }
  83. return flags;
  84. }
  85. static u32 intel_infoframe_flags(struct dip_infoframe *frame)
  86. {
  87. u32 flags = 0;
  88. switch (frame->type) {
  89. case DIP_TYPE_AVI:
  90. flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
  91. break;
  92. case DIP_TYPE_SPD:
  93. flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC;
  94. break;
  95. default:
  96. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  97. break;
  98. }
  99. return flags;
  100. }
  101. static void i9xx_write_infoframe(struct drm_encoder *encoder,
  102. struct dip_infoframe *frame)
  103. {
  104. uint32_t *data = (uint32_t *)frame;
  105. struct drm_device *dev = encoder->dev;
  106. struct drm_i915_private *dev_priv = dev->dev_private;
  107. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  108. u32 val = I915_READ(VIDEO_DIP_CTL);
  109. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  110. /* XXX first guess at handling video port, is this corrent? */
  111. if (intel_hdmi->sdvox_reg == SDVOB)
  112. val |= VIDEO_DIP_PORT_B;
  113. else if (intel_hdmi->sdvox_reg == SDVOC)
  114. val |= VIDEO_DIP_PORT_C;
  115. else
  116. return;
  117. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  118. val |= intel_infoframe_index(frame);
  119. val |= VIDEO_DIP_ENABLE;
  120. I915_WRITE(VIDEO_DIP_CTL, val);
  121. for (i = 0; i < len; i += 4) {
  122. I915_WRITE(VIDEO_DIP_DATA, *data);
  123. data++;
  124. }
  125. val |= intel_infoframe_flags(frame);
  126. I915_WRITE(VIDEO_DIP_CTL, val);
  127. }
  128. static void ironlake_write_infoframe(struct drm_encoder *encoder,
  129. struct dip_infoframe *frame)
  130. {
  131. uint32_t *data = (uint32_t *)frame;
  132. struct drm_device *dev = encoder->dev;
  133. struct drm_i915_private *dev_priv = dev->dev_private;
  134. struct drm_crtc *crtc = encoder->crtc;
  135. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  136. int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  137. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  138. u32 val = I915_READ(reg);
  139. intel_wait_for_vblank(dev, intel_crtc->pipe);
  140. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  141. val |= intel_infoframe_index(frame);
  142. val |= VIDEO_DIP_ENABLE;
  143. I915_WRITE(reg, val);
  144. for (i = 0; i < len; i += 4) {
  145. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  146. data++;
  147. }
  148. val |= intel_infoframe_flags(frame);
  149. I915_WRITE(reg, val);
  150. }
  151. static void vlv_write_infoframe(struct drm_encoder *encoder,
  152. struct dip_infoframe *frame)
  153. {
  154. uint32_t *data = (uint32_t *)frame;
  155. struct drm_device *dev = encoder->dev;
  156. struct drm_i915_private *dev_priv = dev->dev_private;
  157. struct drm_crtc *crtc = encoder->crtc;
  158. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  159. int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  160. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  161. u32 val = I915_READ(reg);
  162. intel_wait_for_vblank(dev, intel_crtc->pipe);
  163. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  164. val |= intel_infoframe_index(frame);
  165. val |= VIDEO_DIP_ENABLE;
  166. I915_WRITE(reg, val);
  167. for (i = 0; i < len; i += 4) {
  168. I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  169. data++;
  170. }
  171. val |= intel_infoframe_flags(frame);
  172. I915_WRITE(reg, val);
  173. }
  174. static void intel_set_infoframe(struct drm_encoder *encoder,
  175. struct dip_infoframe *frame)
  176. {
  177. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  178. if (!intel_hdmi->has_hdmi_sink)
  179. return;
  180. intel_dip_infoframe_csum(frame);
  181. intel_hdmi->write_infoframe(encoder, frame);
  182. }
  183. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  184. struct drm_display_mode *adjusted_mode)
  185. {
  186. struct dip_infoframe avi_if = {
  187. .type = DIP_TYPE_AVI,
  188. .ver = DIP_VERSION_AVI,
  189. .len = DIP_LEN_AVI,
  190. };
  191. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  192. avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
  193. intel_set_infoframe(encoder, &avi_if);
  194. }
  195. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  196. {
  197. struct dip_infoframe spd_if;
  198. memset(&spd_if, 0, sizeof(spd_if));
  199. spd_if.type = DIP_TYPE_SPD;
  200. spd_if.ver = DIP_VERSION_SPD;
  201. spd_if.len = DIP_LEN_SPD;
  202. strcpy(spd_if.body.spd.vn, "Intel");
  203. strcpy(spd_if.body.spd.pd, "Integrated gfx");
  204. spd_if.body.spd.sdi = DIP_SPD_PC;
  205. intel_set_infoframe(encoder, &spd_if);
  206. }
  207. static void intel_hdmi_mode_set(struct drm_encoder *encoder,
  208. struct drm_display_mode *mode,
  209. struct drm_display_mode *adjusted_mode)
  210. {
  211. struct drm_device *dev = encoder->dev;
  212. struct drm_i915_private *dev_priv = dev->dev_private;
  213. struct drm_crtc *crtc = encoder->crtc;
  214. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  215. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  216. u32 sdvox;
  217. sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
  218. if (!HAS_PCH_SPLIT(dev))
  219. sdvox |= intel_hdmi->color_range;
  220. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  221. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  222. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  223. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  224. if (intel_crtc->bpp > 24)
  225. sdvox |= COLOR_FORMAT_12bpc;
  226. else
  227. sdvox |= COLOR_FORMAT_8bpc;
  228. /* Required on CPT */
  229. if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
  230. sdvox |= HDMI_MODE_SELECT;
  231. if (intel_hdmi->has_audio) {
  232. DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  233. pipe_name(intel_crtc->pipe));
  234. sdvox |= SDVO_AUDIO_ENABLE;
  235. sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
  236. intel_write_eld(encoder, adjusted_mode);
  237. }
  238. if (HAS_PCH_CPT(dev))
  239. sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  240. else if (intel_crtc->pipe == 1)
  241. sdvox |= SDVO_PIPE_B_SELECT;
  242. I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
  243. POSTING_READ(intel_hdmi->sdvox_reg);
  244. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  245. intel_hdmi_set_spd_infoframe(encoder);
  246. }
  247. static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
  248. {
  249. struct drm_device *dev = encoder->dev;
  250. struct drm_i915_private *dev_priv = dev->dev_private;
  251. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  252. u32 temp;
  253. u32 enable_bits = SDVO_ENABLE;
  254. if (intel_hdmi->has_audio)
  255. enable_bits |= SDVO_AUDIO_ENABLE;
  256. temp = I915_READ(intel_hdmi->sdvox_reg);
  257. /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  258. * we do this anyway which shows more stable in testing.
  259. */
  260. if (HAS_PCH_SPLIT(dev)) {
  261. I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
  262. POSTING_READ(intel_hdmi->sdvox_reg);
  263. }
  264. if (mode != DRM_MODE_DPMS_ON) {
  265. temp &= ~enable_bits;
  266. } else {
  267. temp |= enable_bits;
  268. }
  269. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  270. POSTING_READ(intel_hdmi->sdvox_reg);
  271. /* HW workaround, need to write this twice for issue that may result
  272. * in first write getting masked.
  273. */
  274. if (HAS_PCH_SPLIT(dev)) {
  275. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  276. POSTING_READ(intel_hdmi->sdvox_reg);
  277. }
  278. }
  279. static int intel_hdmi_mode_valid(struct drm_connector *connector,
  280. struct drm_display_mode *mode)
  281. {
  282. if (mode->clock > 165000)
  283. return MODE_CLOCK_HIGH;
  284. if (mode->clock < 20000)
  285. return MODE_CLOCK_LOW;
  286. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  287. return MODE_NO_DBLESCAN;
  288. return MODE_OK;
  289. }
  290. static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
  291. struct drm_display_mode *mode,
  292. struct drm_display_mode *adjusted_mode)
  293. {
  294. return true;
  295. }
  296. static enum drm_connector_status
  297. intel_hdmi_detect(struct drm_connector *connector, bool force)
  298. {
  299. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  300. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  301. struct edid *edid;
  302. enum drm_connector_status status = connector_status_disconnected;
  303. intel_hdmi->has_hdmi_sink = false;
  304. intel_hdmi->has_audio = false;
  305. edid = drm_get_edid(connector,
  306. intel_gmbus_get_adapter(dev_priv,
  307. intel_hdmi->ddc_bus));
  308. if (edid) {
  309. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  310. status = connector_status_connected;
  311. if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  312. intel_hdmi->has_hdmi_sink =
  313. drm_detect_hdmi_monitor(edid);
  314. intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  315. }
  316. connector->display_info.raw_edid = NULL;
  317. kfree(edid);
  318. }
  319. if (status == connector_status_connected) {
  320. if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  321. intel_hdmi->has_audio =
  322. (intel_hdmi->force_audio == HDMI_AUDIO_ON);
  323. }
  324. return status;
  325. }
  326. static int intel_hdmi_get_modes(struct drm_connector *connector)
  327. {
  328. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  329. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  330. /* We should parse the EDID data and find out if it's an HDMI sink so
  331. * we can send audio to it.
  332. */
  333. return intel_ddc_get_modes(connector,
  334. intel_gmbus_get_adapter(dev_priv,
  335. intel_hdmi->ddc_bus));
  336. }
  337. static bool
  338. intel_hdmi_detect_audio(struct drm_connector *connector)
  339. {
  340. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  341. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  342. struct edid *edid;
  343. bool has_audio = false;
  344. edid = drm_get_edid(connector,
  345. intel_gmbus_get_adapter(dev_priv,
  346. intel_hdmi->ddc_bus));
  347. if (edid) {
  348. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  349. has_audio = drm_detect_monitor_audio(edid);
  350. connector->display_info.raw_edid = NULL;
  351. kfree(edid);
  352. }
  353. return has_audio;
  354. }
  355. static int
  356. intel_hdmi_set_property(struct drm_connector *connector,
  357. struct drm_property *property,
  358. uint64_t val)
  359. {
  360. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  361. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  362. int ret;
  363. ret = drm_connector_property_set_value(connector, property, val);
  364. if (ret)
  365. return ret;
  366. if (property == dev_priv->force_audio_property) {
  367. enum hdmi_force_audio i = val;
  368. bool has_audio;
  369. if (i == intel_hdmi->force_audio)
  370. return 0;
  371. intel_hdmi->force_audio = i;
  372. if (i == HDMI_AUDIO_AUTO)
  373. has_audio = intel_hdmi_detect_audio(connector);
  374. else
  375. has_audio = (i == HDMI_AUDIO_ON);
  376. if (i == HDMI_AUDIO_OFF_DVI)
  377. intel_hdmi->has_hdmi_sink = 0;
  378. intel_hdmi->has_audio = has_audio;
  379. goto done;
  380. }
  381. if (property == dev_priv->broadcast_rgb_property) {
  382. if (val == !!intel_hdmi->color_range)
  383. return 0;
  384. intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  385. goto done;
  386. }
  387. return -EINVAL;
  388. done:
  389. if (intel_hdmi->base.base.crtc) {
  390. struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
  391. drm_crtc_helper_set_mode(crtc, &crtc->mode,
  392. crtc->x, crtc->y,
  393. crtc->fb);
  394. }
  395. return 0;
  396. }
  397. static void intel_hdmi_destroy(struct drm_connector *connector)
  398. {
  399. drm_sysfs_connector_remove(connector);
  400. drm_connector_cleanup(connector);
  401. kfree(connector);
  402. }
  403. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
  404. .dpms = intel_hdmi_dpms,
  405. .mode_fixup = intel_hdmi_mode_fixup,
  406. .prepare = intel_encoder_prepare,
  407. .mode_set = intel_hdmi_mode_set,
  408. .commit = intel_encoder_commit,
  409. };
  410. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  411. .dpms = drm_helper_connector_dpms,
  412. .detect = intel_hdmi_detect,
  413. .fill_modes = drm_helper_probe_single_connector_modes,
  414. .set_property = intel_hdmi_set_property,
  415. .destroy = intel_hdmi_destroy,
  416. };
  417. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  418. .get_modes = intel_hdmi_get_modes,
  419. .mode_valid = intel_hdmi_mode_valid,
  420. .best_encoder = intel_best_encoder,
  421. };
  422. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  423. .destroy = intel_encoder_destroy,
  424. };
  425. static void
  426. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  427. {
  428. intel_attach_force_audio_property(connector);
  429. intel_attach_broadcast_rgb_property(connector);
  430. }
  431. void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
  432. {
  433. struct drm_i915_private *dev_priv = dev->dev_private;
  434. struct drm_connector *connector;
  435. struct intel_encoder *intel_encoder;
  436. struct intel_connector *intel_connector;
  437. struct intel_hdmi *intel_hdmi;
  438. int i;
  439. intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
  440. if (!intel_hdmi)
  441. return;
  442. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  443. if (!intel_connector) {
  444. kfree(intel_hdmi);
  445. return;
  446. }
  447. intel_encoder = &intel_hdmi->base;
  448. drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  449. DRM_MODE_ENCODER_TMDS);
  450. connector = &intel_connector->base;
  451. drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  452. DRM_MODE_CONNECTOR_HDMIA);
  453. drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  454. intel_encoder->type = INTEL_OUTPUT_HDMI;
  455. connector->polled = DRM_CONNECTOR_POLL_HPD;
  456. connector->interlace_allowed = 1;
  457. connector->doublescan_allowed = 0;
  458. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  459. /* Set up the DDC bus. */
  460. if (sdvox_reg == SDVOB) {
  461. intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
  462. intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  463. dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  464. } else if (sdvox_reg == SDVOC) {
  465. intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
  466. intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  467. dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  468. } else if (sdvox_reg == HDMIB) {
  469. intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
  470. intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  471. dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  472. } else if (sdvox_reg == HDMIC) {
  473. intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
  474. intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  475. dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  476. } else if (sdvox_reg == HDMID) {
  477. intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
  478. intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  479. dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
  480. }
  481. intel_hdmi->sdvox_reg = sdvox_reg;
  482. if (!HAS_PCH_SPLIT(dev)) {
  483. intel_hdmi->write_infoframe = i9xx_write_infoframe;
  484. I915_WRITE(VIDEO_DIP_CTL, 0);
  485. } else if (IS_VALLEYVIEW(dev)) {
  486. intel_hdmi->write_infoframe = vlv_write_infoframe;
  487. for_each_pipe(i)
  488. I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
  489. } else {
  490. intel_hdmi->write_infoframe = ironlake_write_infoframe;
  491. for_each_pipe(i)
  492. I915_WRITE(TVIDEO_DIP_CTL(i), 0);
  493. }
  494. drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
  495. intel_hdmi_add_properties(intel_hdmi, connector);
  496. intel_connector_attach_encoder(intel_connector, intel_encoder);
  497. drm_sysfs_connector_add(connector);
  498. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  499. * 0xd. Failure to do so will result in spurious interrupts being
  500. * generated on the port when a cable is not attached.
  501. */
  502. if (IS_G4X(dev) && !IS_GM45(dev)) {
  503. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  504. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  505. }
  506. }