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linux-vybrid_pu...
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arch
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arm
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mach-exynos4
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include
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mach
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regs-clock.h

regs-clock.h 6.5 KB
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  1. /* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
    4. 

  4.  *		http://www.samsung.com
    5. 

  5.  *
    6. 

  6.  * EXYNOS4 - Clock register definitions
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_ARCH_REGS_CLOCK_H
    14. 

  14. #define __ASM_ARCH_REGS_CLOCK_H __FILE__
    15. 

  15. 

  16. #include <mach/map.h>
    17. 

  17. 

  18. #define S5P_CLKREG(x)			(S5P_VA_CMU + (x))
    19. 

  19. 

  20. #define S5P_INFORM0			S5P_CLKREG(0x800)
    21. 

  21. 

  22. #define S5P_CLKDIV_LEFTBUS		S5P_CLKREG(0x04500)
    23. 

  23. #define S5P_CLKDIV_STAT_LEFTBUS		S5P_CLKREG(0x04600)
    24. 

  24. 

  25. #define S5P_CLKDIV_RIGHTBUS		S5P_CLKREG(0x08500)
    26. 

  26. #define S5P_CLKDIV_STAT_RIGHTBUS	S5P_CLKREG(0x08600)
    27. 

  27. 

  28. #define S5P_EPLL_CON0			S5P_CLKREG(0x0C110)
    29. 

  29. #define S5P_EPLL_CON1			S5P_CLKREG(0x0C114)
    30. 

  30. #define S5P_VPLL_CON0			S5P_CLKREG(0x0C120)
    31. 

  31. #define S5P_VPLL_CON1			S5P_CLKREG(0x0C124)
    32. 

  32. 

  33. #define S5P_CLKSRC_TOP0			S5P_CLKREG(0x0C210)
    34. 

  34. #define S5P_CLKSRC_TOP1			S5P_CLKREG(0x0C214)
    35. 

  35. #define S5P_CLKSRC_CAM			S5P_CLKREG(0x0C220)
    36. 

  36. #define S5P_CLKSRC_IMAGE		S5P_CLKREG(0x0C230)
    37. 

  37. #define S5P_CLKSRC_LCD0			S5P_CLKREG(0x0C234)
    38. 

  38. #define S5P_CLKSRC_LCD1			S5P_CLKREG(0x0C238)
    39. 

  39. #define S5P_CLKSRC_FSYS			S5P_CLKREG(0x0C240)
    40. 

  40. #define S5P_CLKSRC_PERIL0		S5P_CLKREG(0x0C250)
    41. 

  41. #define S5P_CLKSRC_PERIL1		S5P_CLKREG(0x0C254)
    42. 

  42. 

  43. #define S5P_CLKDIV_TOP			S5P_CLKREG(0x0C510)
    44. 

  44. #define S5P_CLKDIV_CAM			S5P_CLKREG(0x0C520)
    45. 

  45. #define S5P_CLKDIV_IMAGE		S5P_CLKREG(0x0C530)
    46. 

  46. #define S5P_CLKDIV_LCD0			S5P_CLKREG(0x0C534)
    47. 

  47. #define S5P_CLKDIV_LCD1			S5P_CLKREG(0x0C538)
    48. 

  48. #define S5P_CLKDIV_FSYS0		S5P_CLKREG(0x0C540)
    49. 

  49. #define S5P_CLKDIV_FSYS1		S5P_CLKREG(0x0C544)
    50. 

  50. #define S5P_CLKDIV_FSYS2		S5P_CLKREG(0x0C548)
    51. 

  51. #define S5P_CLKDIV_FSYS3		S5P_CLKREG(0x0C54C)
    52. 

  52. #define S5P_CLKDIV_PERIL0		S5P_CLKREG(0x0C550)
    53. 

  53. #define S5P_CLKDIV_PERIL1		S5P_CLKREG(0x0C554)
    54. 

  54. #define S5P_CLKDIV_PERIL2		S5P_CLKREG(0x0C558)
    55. 

  55. #define S5P_CLKDIV_PERIL3		S5P_CLKREG(0x0C55C)
    56. 

  56. #define S5P_CLKDIV_PERIL4		S5P_CLKREG(0x0C560)
    57. 

  57. #define S5P_CLKDIV_PERIL5		S5P_CLKREG(0x0C564)
    58. 

  58. 

  59. #define S5P_CLKSRC_MASK_TOP		S5P_CLKREG(0x0C310)
    60. 

  60. #define S5P_CLKSRC_MASK_CAM		S5P_CLKREG(0x0C320)
    61. 

  61. #define S5P_CLKSRC_MASK_LCD0		S5P_CLKREG(0x0C334)
    62. 

  62. #define S5P_CLKSRC_MASK_LCD1		S5P_CLKREG(0x0C338)
    63. 

  63. #define S5P_CLKSRC_MASK_FSYS		S5P_CLKREG(0x0C340)
    64. 

  64. #define S5P_CLKSRC_MASK_PERIL0		S5P_CLKREG(0x0C350)
    65. 

  65. #define S5P_CLKSRC_MASK_PERIL1		S5P_CLKREG(0x0C354)
    66. 

  66. 

  67. #define S5P_CLKDIV_STAT_TOP		S5P_CLKREG(0x0C610)
    68. 

  68. 

  69. #define S5P_CLKGATE_IP_CAM		S5P_CLKREG(0x0C920)
    70. 

  70. #define S5P_CLKGATE_IP_IMAGE		S5P_CLKREG(0x0C930)
    71. 

  71. #define S5P_CLKGATE_IP_LCD0		S5P_CLKREG(0x0C934)
    72. 

  72. #define S5P_CLKGATE_IP_LCD1		S5P_CLKREG(0x0C938)
    73. 

  73. #define S5P_CLKGATE_IP_FSYS		S5P_CLKREG(0x0C940)
    74. 

  74. #define S5P_CLKGATE_IP_PERIL		S5P_CLKREG(0x0C950)
    75. 

  75. #define S5P_CLKGATE_IP_PERIR		S5P_CLKREG(0x0C960)
    76. 

  76. 

  77. #define S5P_CLKSRC_DMC			S5P_CLKREG(0x10200)
    78. 

  78. #define S5P_CLKDIV_DMC0			S5P_CLKREG(0x10500)
    79. 

  79. #define S5P_CLKDIV_STAT_DMC0		S5P_CLKREG(0x10600)
    80. 

  80. 

  81. #define S5P_APLL_LOCK			S5P_CLKREG(0x14000)
    82. 

  82. #define S5P_MPLL_LOCK			S5P_CLKREG(0x14004)
    83. 

  83. #define S5P_APLL_CON0			S5P_CLKREG(0x14100)
    84. 

  84. #define S5P_APLL_CON1			S5P_CLKREG(0x14104)
    85. 

  85. #define S5P_MPLL_CON0			S5P_CLKREG(0x14108)
    86. 

  86. #define S5P_MPLL_CON1			S5P_CLKREG(0x1410C)
    87. 

  87. 

  88. #define S5P_CLKSRC_CPU			S5P_CLKREG(0x14200)
    89. 

  89. #define S5P_CLKMUX_STATCPU		S5P_CLKREG(0x14400)
    90. 

  90. 

  91. #define S5P_CLKDIV_CPU			S5P_CLKREG(0x14500)
    92. 

  92. #define S5P_CLKDIV_CPU1			S5P_CLKREG(0x14504)
    93. 

  93. #define S5P_CLKDIV_STATCPU		S5P_CLKREG(0x14600)
    94. 

  94. #define S5P_CLKDIV_STATCPU1		S5P_CLKREG(0x14604)
    95. 

  95. 

  96. #define S5P_CLKGATE_SCLKCPU		S5P_CLKREG(0x14800)
    97. 

  97. 

  98. /* APLL_LOCK */
    99. 

  99. #define S5P_APLL_LOCKTIME		(0x1C20)	/* 300us */
    100. 

  100. 

  101. /* APLL_CON0 */
    102. 

  102. #define S5P_APLLCON0_ENABLE_SHIFT	(31)
    103. 

  103. #define S5P_APLLCON0_LOCKED_SHIFT	(29)
    104. 

  104. #define S5P_APLL_VAL_1000		((250 << 16) | (6 << 8) | 1)
    105. 

  105. #define S5P_APLL_VAL_800		((200 << 16) | (6 << 8) | 1)
    106. 

  106. 

  107. /* CLK_SRC_CPU */
    108. 

  108. #define S5P_CLKSRC_CPU_MUXCORE_SHIFT	(16)
    109. 

  109. #define S5P_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
    110. 

  110. 

  111. /* CLKDIV_CPU0 */
    112. 

  112. #define S5P_CLKDIV_CPU0_CORE_SHIFT	(0)
    113. 

  113. #define S5P_CLKDIV_CPU0_CORE_MASK	(0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
    114. 

  114. #define S5P_CLKDIV_CPU0_COREM0_SHIFT	(4)
    115. 

  115. #define S5P_CLKDIV_CPU0_COREM0_MASK	(0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
    116. 

  116. #define S5P_CLKDIV_CPU0_COREM1_SHIFT	(8)
    117. 

  117. #define S5P_CLKDIV_CPU0_COREM1_MASK	(0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
    118. 

  118. #define S5P_CLKDIV_CPU0_PERIPH_SHIFT	(12)
    119. 

  119. #define S5P_CLKDIV_CPU0_PERIPH_MASK	(0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
    120. 

  120. #define S5P_CLKDIV_CPU0_ATB_SHIFT	(16)
    121. 

  121. #define S5P_CLKDIV_CPU0_ATB_MASK	(0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
    122. 

  122. #define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT	(20)
    123. 

  123. #define S5P_CLKDIV_CPU0_PCLKDBG_MASK	(0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
    124. 

  124. #define S5P_CLKDIV_CPU0_APLL_SHIFT	(24)
    125. 

  125. #define S5P_CLKDIV_CPU0_APLL_MASK	(0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
    126. 

  126. 

  127. /* CLKDIV_DMC0 */
    128. 

  128. #define S5P_CLKDIV_DMC0_ACP_SHIFT	(0)
    129. 

  129. #define S5P_CLKDIV_DMC0_ACP_MASK	(0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
    130. 

  130. #define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)
    131. 

  131. #define S5P_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
    132. 

  132. #define S5P_CLKDIV_DMC0_DPHY_SHIFT	(8)
    133. 

  133. #define S5P_CLKDIV_DMC0_DPHY_MASK	(0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
    134. 

  134. #define S5P_CLKDIV_DMC0_DMC_SHIFT	(12)
    135. 

  135. #define S5P_CLKDIV_DMC0_DMC_MASK	(0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
    136. 

  136. #define S5P_CLKDIV_DMC0_DMCD_SHIFT	(16)
    137. 

  137. #define S5P_CLKDIV_DMC0_DMCD_MASK	(0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
    138. 

  138. #define S5P_CLKDIV_DMC0_DMCP_SHIFT	(20)
    139. 

  139. #define S5P_CLKDIV_DMC0_DMCP_MASK	(0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
    140. 

  140. #define S5P_CLKDIV_DMC0_COPY2_SHIFT	(24)
    141. 

  141. #define S5P_CLKDIV_DMC0_COPY2_MASK	(0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
    142. 

  142. #define S5P_CLKDIV_DMC0_CORETI_SHIFT	(28)
    143. 

  143. #define S5P_CLKDIV_DMC0_CORETI_MASK	(0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
    144. 

  144. 

  145. /* CLKDIV_TOP */
    146. 

  146. #define S5P_CLKDIV_TOP_ACLK200_SHIFT	(0)
    147. 

  147. #define S5P_CLKDIV_TOP_ACLK200_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
    148. 

  148. #define S5P_CLKDIV_TOP_ACLK100_SHIFT	(4)
    149. 

  149. #define S5P_CLKDIV_TOP_ACLK100_MASK	(0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
    150. 

  150. #define S5P_CLKDIV_TOP_ACLK160_SHIFT	(8)
    151. 

  151. #define S5P_CLKDIV_TOP_ACLK160_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
    152. 

  152. #define S5P_CLKDIV_TOP_ACLK133_SHIFT	(12)
    153. 

  153. #define S5P_CLKDIV_TOP_ACLK133_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
    154. 

  154. #define S5P_CLKDIV_TOP_ONENAND_SHIFT	(16)
    155. 

  155. #define S5P_CLKDIV_TOP_ONENAND_MASK	(0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
    156. 

  156. 

  157. /* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
    158. 

  158. #define S5P_CLKDIV_BUS_GDLR_SHIFT	(0)
    159. 

  159. #define S5P_CLKDIV_BUS_GDLR_MASK	(0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
    160. 

  160. #define S5P_CLKDIV_BUS_GPLR_SHIFT	(4)
    161. 

  161. #define S5P_CLKDIV_BUS_GPLR_MASK	(0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
    162. 

  162. 

  163. /* Compatibility defines and inclusion */
    164. 

  164. 

  165. #include <mach/regs-pmu.h>
    166. 

  166. 

  167. #define S5P_EPLL_CON			S5P_EPLL_CON0
    168. 

  168. 

  169. #endif /* __ASM_ARCH_REGS_CLOCK_H */
    170.