cputable.c 63 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. struct cpu_spec* cur_cpu_spec = NULL;
  22. EXPORT_SYMBOL(cur_cpu_spec);
  23. /* The platform string corresponding to the real PVR */
  24. const char *powerpc_base_platform;
  25. /* NOTE:
  26. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  27. * the responsibility of the appropriate CPU save/restore functions to
  28. * eventually copy these settings over. Those save/restore aren't yet
  29. * part of the cputable though. That has to be fixed for both ppc32
  30. * and ppc64
  31. */
  32. #ifdef CONFIG_PPC32
  33. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  46. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  48. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  55. #endif /* CONFIG_PPC32 */
  56. #ifdef CONFIG_PPC64
  57. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  58. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  60. extern void __restore_cpu_pa6t(void);
  61. extern void __restore_cpu_ppc970(void);
  62. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  63. extern void __restore_cpu_power7(void);
  64. #endif /* CONFIG_PPC64 */
  65. #if defined(CONFIG_E500)
  66. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_e5500(void);
  68. #endif /* CONFIG_E500 */
  69. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  70. * ones as well...
  71. */
  72. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  73. PPC_FEATURE_HAS_MMU)
  74. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  75. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  76. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  77. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  78. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  79. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  80. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  81. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  82. PPC_FEATURE_TRUE_LE | \
  83. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  84. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  85. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  86. PPC_FEATURE_TRUE_LE | \
  87. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  88. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  89. PPC_FEATURE_TRUE_LE | \
  90. PPC_FEATURE_HAS_ALTIVEC_COMP)
  91. #ifdef CONFIG_PPC_BOOK3E_64
  92. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  93. #else
  94. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  95. PPC_FEATURE_BOOKE)
  96. #endif
  97. static struct cpu_spec __initdata cpu_specs[] = {
  98. #ifdef CONFIG_PPC_BOOK3S_64
  99. { /* Power3 */
  100. .pvr_mask = 0xffff0000,
  101. .pvr_value = 0x00400000,
  102. .cpu_name = "POWER3 (630)",
  103. .cpu_features = CPU_FTRS_POWER3,
  104. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  105. .mmu_features = MMU_FTR_HPTE_TABLE,
  106. .icache_bsize = 128,
  107. .dcache_bsize = 128,
  108. .num_pmcs = 8,
  109. .pmc_type = PPC_PMC_IBM,
  110. .oprofile_cpu_type = "ppc64/power3",
  111. .oprofile_type = PPC_OPROFILE_RS64,
  112. .machine_check = machine_check_generic,
  113. .platform = "power3",
  114. },
  115. { /* Power3+ */
  116. .pvr_mask = 0xffff0000,
  117. .pvr_value = 0x00410000,
  118. .cpu_name = "POWER3 (630+)",
  119. .cpu_features = CPU_FTRS_POWER3,
  120. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  121. .mmu_features = MMU_FTR_HPTE_TABLE,
  122. .icache_bsize = 128,
  123. .dcache_bsize = 128,
  124. .num_pmcs = 8,
  125. .pmc_type = PPC_PMC_IBM,
  126. .oprofile_cpu_type = "ppc64/power3",
  127. .oprofile_type = PPC_OPROFILE_RS64,
  128. .machine_check = machine_check_generic,
  129. .platform = "power3",
  130. },
  131. { /* Northstar */
  132. .pvr_mask = 0xffff0000,
  133. .pvr_value = 0x00330000,
  134. .cpu_name = "RS64-II (northstar)",
  135. .cpu_features = CPU_FTRS_RS64,
  136. .cpu_user_features = COMMON_USER_PPC64,
  137. .mmu_features = MMU_FTR_HPTE_TABLE,
  138. .icache_bsize = 128,
  139. .dcache_bsize = 128,
  140. .num_pmcs = 8,
  141. .pmc_type = PPC_PMC_IBM,
  142. .oprofile_cpu_type = "ppc64/rs64",
  143. .oprofile_type = PPC_OPROFILE_RS64,
  144. .machine_check = machine_check_generic,
  145. .platform = "rs64",
  146. },
  147. { /* Pulsar */
  148. .pvr_mask = 0xffff0000,
  149. .pvr_value = 0x00340000,
  150. .cpu_name = "RS64-III (pulsar)",
  151. .cpu_features = CPU_FTRS_RS64,
  152. .cpu_user_features = COMMON_USER_PPC64,
  153. .mmu_features = MMU_FTR_HPTE_TABLE,
  154. .icache_bsize = 128,
  155. .dcache_bsize = 128,
  156. .num_pmcs = 8,
  157. .pmc_type = PPC_PMC_IBM,
  158. .oprofile_cpu_type = "ppc64/rs64",
  159. .oprofile_type = PPC_OPROFILE_RS64,
  160. .machine_check = machine_check_generic,
  161. .platform = "rs64",
  162. },
  163. { /* I-star */
  164. .pvr_mask = 0xffff0000,
  165. .pvr_value = 0x00360000,
  166. .cpu_name = "RS64-III (icestar)",
  167. .cpu_features = CPU_FTRS_RS64,
  168. .cpu_user_features = COMMON_USER_PPC64,
  169. .mmu_features = MMU_FTR_HPTE_TABLE,
  170. .icache_bsize = 128,
  171. .dcache_bsize = 128,
  172. .num_pmcs = 8,
  173. .pmc_type = PPC_PMC_IBM,
  174. .oprofile_cpu_type = "ppc64/rs64",
  175. .oprofile_type = PPC_OPROFILE_RS64,
  176. .machine_check = machine_check_generic,
  177. .platform = "rs64",
  178. },
  179. { /* S-star */
  180. .pvr_mask = 0xffff0000,
  181. .pvr_value = 0x00370000,
  182. .cpu_name = "RS64-IV (sstar)",
  183. .cpu_features = CPU_FTRS_RS64,
  184. .cpu_user_features = COMMON_USER_PPC64,
  185. .mmu_features = MMU_FTR_HPTE_TABLE,
  186. .icache_bsize = 128,
  187. .dcache_bsize = 128,
  188. .num_pmcs = 8,
  189. .pmc_type = PPC_PMC_IBM,
  190. .oprofile_cpu_type = "ppc64/rs64",
  191. .oprofile_type = PPC_OPROFILE_RS64,
  192. .machine_check = machine_check_generic,
  193. .platform = "rs64",
  194. },
  195. { /* Power4 */
  196. .pvr_mask = 0xffff0000,
  197. .pvr_value = 0x00350000,
  198. .cpu_name = "POWER4 (gp)",
  199. .cpu_features = CPU_FTRS_POWER4,
  200. .cpu_user_features = COMMON_USER_POWER4,
  201. .mmu_features = MMU_FTR_HPTE_TABLE,
  202. .icache_bsize = 128,
  203. .dcache_bsize = 128,
  204. .num_pmcs = 8,
  205. .pmc_type = PPC_PMC_IBM,
  206. .oprofile_cpu_type = "ppc64/power4",
  207. .oprofile_type = PPC_OPROFILE_POWER4,
  208. .machine_check = machine_check_generic,
  209. .platform = "power4",
  210. },
  211. { /* Power4+ */
  212. .pvr_mask = 0xffff0000,
  213. .pvr_value = 0x00380000,
  214. .cpu_name = "POWER4+ (gq)",
  215. .cpu_features = CPU_FTRS_POWER4,
  216. .cpu_user_features = COMMON_USER_POWER4,
  217. .mmu_features = MMU_FTR_HPTE_TABLE,
  218. .icache_bsize = 128,
  219. .dcache_bsize = 128,
  220. .num_pmcs = 8,
  221. .pmc_type = PPC_PMC_IBM,
  222. .oprofile_cpu_type = "ppc64/power4",
  223. .oprofile_type = PPC_OPROFILE_POWER4,
  224. .machine_check = machine_check_generic,
  225. .platform = "power4",
  226. },
  227. { /* PPC970 */
  228. .pvr_mask = 0xffff0000,
  229. .pvr_value = 0x00390000,
  230. .cpu_name = "PPC970",
  231. .cpu_features = CPU_FTRS_PPC970,
  232. .cpu_user_features = COMMON_USER_POWER4 |
  233. PPC_FEATURE_HAS_ALTIVEC_COMP,
  234. .mmu_features = MMU_FTR_HPTE_TABLE,
  235. .icache_bsize = 128,
  236. .dcache_bsize = 128,
  237. .num_pmcs = 8,
  238. .pmc_type = PPC_PMC_IBM,
  239. .cpu_setup = __setup_cpu_ppc970,
  240. .cpu_restore = __restore_cpu_ppc970,
  241. .oprofile_cpu_type = "ppc64/970",
  242. .oprofile_type = PPC_OPROFILE_POWER4,
  243. .machine_check = machine_check_generic,
  244. .platform = "ppc970",
  245. },
  246. { /* PPC970FX */
  247. .pvr_mask = 0xffff0000,
  248. .pvr_value = 0x003c0000,
  249. .cpu_name = "PPC970FX",
  250. .cpu_features = CPU_FTRS_PPC970,
  251. .cpu_user_features = COMMON_USER_POWER4 |
  252. PPC_FEATURE_HAS_ALTIVEC_COMP,
  253. .mmu_features = MMU_FTR_HPTE_TABLE,
  254. .icache_bsize = 128,
  255. .dcache_bsize = 128,
  256. .num_pmcs = 8,
  257. .pmc_type = PPC_PMC_IBM,
  258. .cpu_setup = __setup_cpu_ppc970,
  259. .cpu_restore = __restore_cpu_ppc970,
  260. .oprofile_cpu_type = "ppc64/970",
  261. .oprofile_type = PPC_OPROFILE_POWER4,
  262. .machine_check = machine_check_generic,
  263. .platform = "ppc970",
  264. },
  265. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  266. .pvr_mask = 0xffffffff,
  267. .pvr_value = 0x00440100,
  268. .cpu_name = "PPC970MP",
  269. .cpu_features = CPU_FTRS_PPC970,
  270. .cpu_user_features = COMMON_USER_POWER4 |
  271. PPC_FEATURE_HAS_ALTIVEC_COMP,
  272. .mmu_features = MMU_FTR_HPTE_TABLE,
  273. .icache_bsize = 128,
  274. .dcache_bsize = 128,
  275. .num_pmcs = 8,
  276. .pmc_type = PPC_PMC_IBM,
  277. .cpu_setup = __setup_cpu_ppc970,
  278. .cpu_restore = __restore_cpu_ppc970,
  279. .oprofile_cpu_type = "ppc64/970MP",
  280. .oprofile_type = PPC_OPROFILE_POWER4,
  281. .machine_check = machine_check_generic,
  282. .platform = "ppc970",
  283. },
  284. { /* PPC970MP */
  285. .pvr_mask = 0xffff0000,
  286. .pvr_value = 0x00440000,
  287. .cpu_name = "PPC970MP",
  288. .cpu_features = CPU_FTRS_PPC970,
  289. .cpu_user_features = COMMON_USER_POWER4 |
  290. PPC_FEATURE_HAS_ALTIVEC_COMP,
  291. .mmu_features = MMU_FTR_HPTE_TABLE,
  292. .icache_bsize = 128,
  293. .dcache_bsize = 128,
  294. .num_pmcs = 8,
  295. .pmc_type = PPC_PMC_IBM,
  296. .cpu_setup = __setup_cpu_ppc970MP,
  297. .cpu_restore = __restore_cpu_ppc970,
  298. .oprofile_cpu_type = "ppc64/970MP",
  299. .oprofile_type = PPC_OPROFILE_POWER4,
  300. .machine_check = machine_check_generic,
  301. .platform = "ppc970",
  302. },
  303. { /* PPC970GX */
  304. .pvr_mask = 0xffff0000,
  305. .pvr_value = 0x00450000,
  306. .cpu_name = "PPC970GX",
  307. .cpu_features = CPU_FTRS_PPC970,
  308. .cpu_user_features = COMMON_USER_POWER4 |
  309. PPC_FEATURE_HAS_ALTIVEC_COMP,
  310. .mmu_features = MMU_FTR_HPTE_TABLE,
  311. .icache_bsize = 128,
  312. .dcache_bsize = 128,
  313. .num_pmcs = 8,
  314. .pmc_type = PPC_PMC_IBM,
  315. .cpu_setup = __setup_cpu_ppc970,
  316. .oprofile_cpu_type = "ppc64/970",
  317. .oprofile_type = PPC_OPROFILE_POWER4,
  318. .machine_check = machine_check_generic,
  319. .platform = "ppc970",
  320. },
  321. { /* Power5 GR */
  322. .pvr_mask = 0xffff0000,
  323. .pvr_value = 0x003a0000,
  324. .cpu_name = "POWER5 (gr)",
  325. .cpu_features = CPU_FTRS_POWER5,
  326. .cpu_user_features = COMMON_USER_POWER5,
  327. .mmu_features = MMU_FTR_HPTE_TABLE,
  328. .icache_bsize = 128,
  329. .dcache_bsize = 128,
  330. .num_pmcs = 6,
  331. .pmc_type = PPC_PMC_IBM,
  332. .oprofile_cpu_type = "ppc64/power5",
  333. .oprofile_type = PPC_OPROFILE_POWER4,
  334. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  335. * and above but only works on POWER5 and above
  336. */
  337. .oprofile_mmcra_sihv = MMCRA_SIHV,
  338. .oprofile_mmcra_sipr = MMCRA_SIPR,
  339. .machine_check = machine_check_generic,
  340. .platform = "power5",
  341. },
  342. { /* Power5++ */
  343. .pvr_mask = 0xffffff00,
  344. .pvr_value = 0x003b0300,
  345. .cpu_name = "POWER5+ (gs)",
  346. .cpu_features = CPU_FTRS_POWER5,
  347. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  348. .mmu_features = MMU_FTR_HPTE_TABLE,
  349. .icache_bsize = 128,
  350. .dcache_bsize = 128,
  351. .num_pmcs = 6,
  352. .oprofile_cpu_type = "ppc64/power5++",
  353. .oprofile_type = PPC_OPROFILE_POWER4,
  354. .oprofile_mmcra_sihv = MMCRA_SIHV,
  355. .oprofile_mmcra_sipr = MMCRA_SIPR,
  356. .machine_check = machine_check_generic,
  357. .platform = "power5+",
  358. },
  359. { /* Power5 GS */
  360. .pvr_mask = 0xffff0000,
  361. .pvr_value = 0x003b0000,
  362. .cpu_name = "POWER5+ (gs)",
  363. .cpu_features = CPU_FTRS_POWER5,
  364. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  365. .mmu_features = MMU_FTR_HPTE_TABLE,
  366. .icache_bsize = 128,
  367. .dcache_bsize = 128,
  368. .num_pmcs = 6,
  369. .pmc_type = PPC_PMC_IBM,
  370. .oprofile_cpu_type = "ppc64/power5+",
  371. .oprofile_type = PPC_OPROFILE_POWER4,
  372. .oprofile_mmcra_sihv = MMCRA_SIHV,
  373. .oprofile_mmcra_sipr = MMCRA_SIPR,
  374. .machine_check = machine_check_generic,
  375. .platform = "power5+",
  376. },
  377. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  378. .pvr_mask = 0xffffffff,
  379. .pvr_value = 0x0f000001,
  380. .cpu_name = "POWER5+",
  381. .cpu_features = CPU_FTRS_POWER5,
  382. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  383. .mmu_features = MMU_FTR_HPTE_TABLE,
  384. .icache_bsize = 128,
  385. .dcache_bsize = 128,
  386. .machine_check = machine_check_generic,
  387. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  388. .oprofile_type = PPC_OPROFILE_POWER4,
  389. .platform = "power5+",
  390. },
  391. { /* Power6 */
  392. .pvr_mask = 0xffff0000,
  393. .pvr_value = 0x003e0000,
  394. .cpu_name = "POWER6 (raw)",
  395. .cpu_features = CPU_FTRS_POWER6,
  396. .cpu_user_features = COMMON_USER_POWER6 |
  397. PPC_FEATURE_POWER6_EXT,
  398. .mmu_features = MMU_FTR_HPTE_TABLE,
  399. .icache_bsize = 128,
  400. .dcache_bsize = 128,
  401. .num_pmcs = 6,
  402. .pmc_type = PPC_PMC_IBM,
  403. .oprofile_cpu_type = "ppc64/power6",
  404. .oprofile_type = PPC_OPROFILE_POWER4,
  405. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  406. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  407. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  408. POWER6_MMCRA_OTHER,
  409. .machine_check = machine_check_generic,
  410. .platform = "power6x",
  411. },
  412. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  413. .pvr_mask = 0xffffffff,
  414. .pvr_value = 0x0f000002,
  415. .cpu_name = "POWER6 (architected)",
  416. .cpu_features = CPU_FTRS_POWER6,
  417. .cpu_user_features = COMMON_USER_POWER6,
  418. .mmu_features = MMU_FTR_HPTE_TABLE,
  419. .icache_bsize = 128,
  420. .dcache_bsize = 128,
  421. .machine_check = machine_check_generic,
  422. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  423. .oprofile_type = PPC_OPROFILE_POWER4,
  424. .platform = "power6",
  425. },
  426. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  427. .pvr_mask = 0xffffffff,
  428. .pvr_value = 0x0f000003,
  429. .cpu_name = "POWER7 (architected)",
  430. .cpu_features = CPU_FTRS_POWER7,
  431. .cpu_user_features = COMMON_USER_POWER7,
  432. .mmu_features = MMU_FTR_HPTE_TABLE |
  433. MMU_FTR_TLBIE_206,
  434. .icache_bsize = 128,
  435. .dcache_bsize = 128,
  436. .machine_check = machine_check_generic,
  437. .oprofile_type = PPC_OPROFILE_POWER4,
  438. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  439. .platform = "power7",
  440. },
  441. { /* Power7 */
  442. .pvr_mask = 0xffff0000,
  443. .pvr_value = 0x003f0000,
  444. .cpu_name = "POWER7 (raw)",
  445. .cpu_features = CPU_FTRS_POWER7,
  446. .cpu_user_features = COMMON_USER_POWER7,
  447. .mmu_features = MMU_FTR_HPTE_TABLE |
  448. MMU_FTR_TLBIE_206,
  449. .icache_bsize = 128,
  450. .dcache_bsize = 128,
  451. .num_pmcs = 6,
  452. .pmc_type = PPC_PMC_IBM,
  453. .oprofile_cpu_type = "ppc64/power7",
  454. .oprofile_type = PPC_OPROFILE_POWER4,
  455. .platform = "power7",
  456. },
  457. { /* Cell Broadband Engine */
  458. .pvr_mask = 0xffff0000,
  459. .pvr_value = 0x00700000,
  460. .cpu_name = "Cell Broadband Engine",
  461. .cpu_features = CPU_FTRS_CELL,
  462. .cpu_user_features = COMMON_USER_PPC64 |
  463. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  464. PPC_FEATURE_SMT,
  465. .mmu_features = MMU_FTR_HPTE_TABLE,
  466. .icache_bsize = 128,
  467. .dcache_bsize = 128,
  468. .num_pmcs = 4,
  469. .pmc_type = PPC_PMC_IBM,
  470. .oprofile_cpu_type = "ppc64/cell-be",
  471. .oprofile_type = PPC_OPROFILE_CELL,
  472. .machine_check = machine_check_generic,
  473. .platform = "ppc-cell-be",
  474. },
  475. { /* PA Semi PA6T */
  476. .pvr_mask = 0x7fff0000,
  477. .pvr_value = 0x00900000,
  478. .cpu_name = "PA6T",
  479. .cpu_features = CPU_FTRS_PA6T,
  480. .cpu_user_features = COMMON_USER_PA6T,
  481. .mmu_features = MMU_FTR_HPTE_TABLE,
  482. .icache_bsize = 64,
  483. .dcache_bsize = 64,
  484. .num_pmcs = 6,
  485. .pmc_type = PPC_PMC_PA6T,
  486. .cpu_setup = __setup_cpu_pa6t,
  487. .cpu_restore = __restore_cpu_pa6t,
  488. .oprofile_cpu_type = "ppc64/pa6t",
  489. .oprofile_type = PPC_OPROFILE_PA6T,
  490. .machine_check = machine_check_generic,
  491. .platform = "pa6t",
  492. },
  493. { /* default match */
  494. .pvr_mask = 0x00000000,
  495. .pvr_value = 0x00000000,
  496. .cpu_name = "POWER4 (compatible)",
  497. .cpu_features = CPU_FTRS_COMPATIBLE,
  498. .cpu_user_features = COMMON_USER_PPC64,
  499. .mmu_features = MMU_FTR_HPTE_TABLE,
  500. .icache_bsize = 128,
  501. .dcache_bsize = 128,
  502. .num_pmcs = 6,
  503. .pmc_type = PPC_PMC_IBM,
  504. .machine_check = machine_check_generic,
  505. .platform = "power4",
  506. }
  507. #endif /* CONFIG_PPC_BOOK3S_64 */
  508. #ifdef CONFIG_PPC32
  509. #if CLASSIC_PPC
  510. { /* 601 */
  511. .pvr_mask = 0xffff0000,
  512. .pvr_value = 0x00010000,
  513. .cpu_name = "601",
  514. .cpu_features = CPU_FTRS_PPC601,
  515. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  516. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  517. .mmu_features = MMU_FTR_HPTE_TABLE,
  518. .icache_bsize = 32,
  519. .dcache_bsize = 32,
  520. .machine_check = machine_check_generic,
  521. .platform = "ppc601",
  522. },
  523. { /* 603 */
  524. .pvr_mask = 0xffff0000,
  525. .pvr_value = 0x00030000,
  526. .cpu_name = "603",
  527. .cpu_features = CPU_FTRS_603,
  528. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  529. .mmu_features = 0,
  530. .icache_bsize = 32,
  531. .dcache_bsize = 32,
  532. .cpu_setup = __setup_cpu_603,
  533. .machine_check = machine_check_generic,
  534. .platform = "ppc603",
  535. },
  536. { /* 603e */
  537. .pvr_mask = 0xffff0000,
  538. .pvr_value = 0x00060000,
  539. .cpu_name = "603e",
  540. .cpu_features = CPU_FTRS_603,
  541. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  542. .mmu_features = 0,
  543. .icache_bsize = 32,
  544. .dcache_bsize = 32,
  545. .cpu_setup = __setup_cpu_603,
  546. .machine_check = machine_check_generic,
  547. .platform = "ppc603",
  548. },
  549. { /* 603ev */
  550. .pvr_mask = 0xffff0000,
  551. .pvr_value = 0x00070000,
  552. .cpu_name = "603ev",
  553. .cpu_features = CPU_FTRS_603,
  554. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  555. .mmu_features = 0,
  556. .icache_bsize = 32,
  557. .dcache_bsize = 32,
  558. .cpu_setup = __setup_cpu_603,
  559. .machine_check = machine_check_generic,
  560. .platform = "ppc603",
  561. },
  562. { /* 604 */
  563. .pvr_mask = 0xffff0000,
  564. .pvr_value = 0x00040000,
  565. .cpu_name = "604",
  566. .cpu_features = CPU_FTRS_604,
  567. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  568. .mmu_features = MMU_FTR_HPTE_TABLE,
  569. .icache_bsize = 32,
  570. .dcache_bsize = 32,
  571. .num_pmcs = 2,
  572. .cpu_setup = __setup_cpu_604,
  573. .machine_check = machine_check_generic,
  574. .platform = "ppc604",
  575. },
  576. { /* 604e */
  577. .pvr_mask = 0xfffff000,
  578. .pvr_value = 0x00090000,
  579. .cpu_name = "604e",
  580. .cpu_features = CPU_FTRS_604,
  581. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  582. .mmu_features = MMU_FTR_HPTE_TABLE,
  583. .icache_bsize = 32,
  584. .dcache_bsize = 32,
  585. .num_pmcs = 4,
  586. .cpu_setup = __setup_cpu_604,
  587. .machine_check = machine_check_generic,
  588. .platform = "ppc604",
  589. },
  590. { /* 604r */
  591. .pvr_mask = 0xffff0000,
  592. .pvr_value = 0x00090000,
  593. .cpu_name = "604r",
  594. .cpu_features = CPU_FTRS_604,
  595. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  596. .mmu_features = MMU_FTR_HPTE_TABLE,
  597. .icache_bsize = 32,
  598. .dcache_bsize = 32,
  599. .num_pmcs = 4,
  600. .cpu_setup = __setup_cpu_604,
  601. .machine_check = machine_check_generic,
  602. .platform = "ppc604",
  603. },
  604. { /* 604ev */
  605. .pvr_mask = 0xffff0000,
  606. .pvr_value = 0x000a0000,
  607. .cpu_name = "604ev",
  608. .cpu_features = CPU_FTRS_604,
  609. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  610. .mmu_features = MMU_FTR_HPTE_TABLE,
  611. .icache_bsize = 32,
  612. .dcache_bsize = 32,
  613. .num_pmcs = 4,
  614. .cpu_setup = __setup_cpu_604,
  615. .machine_check = machine_check_generic,
  616. .platform = "ppc604",
  617. },
  618. { /* 740/750 (0x4202, don't support TAU ?) */
  619. .pvr_mask = 0xffffffff,
  620. .pvr_value = 0x00084202,
  621. .cpu_name = "740/750",
  622. .cpu_features = CPU_FTRS_740_NOTAU,
  623. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  624. .mmu_features = MMU_FTR_HPTE_TABLE,
  625. .icache_bsize = 32,
  626. .dcache_bsize = 32,
  627. .num_pmcs = 4,
  628. .cpu_setup = __setup_cpu_750,
  629. .machine_check = machine_check_generic,
  630. .platform = "ppc750",
  631. },
  632. { /* 750CX (80100 and 8010x?) */
  633. .pvr_mask = 0xfffffff0,
  634. .pvr_value = 0x00080100,
  635. .cpu_name = "750CX",
  636. .cpu_features = CPU_FTRS_750,
  637. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  638. .mmu_features = MMU_FTR_HPTE_TABLE,
  639. .icache_bsize = 32,
  640. .dcache_bsize = 32,
  641. .num_pmcs = 4,
  642. .cpu_setup = __setup_cpu_750cx,
  643. .machine_check = machine_check_generic,
  644. .platform = "ppc750",
  645. },
  646. { /* 750CX (82201 and 82202) */
  647. .pvr_mask = 0xfffffff0,
  648. .pvr_value = 0x00082200,
  649. .cpu_name = "750CX",
  650. .cpu_features = CPU_FTRS_750,
  651. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  652. .mmu_features = MMU_FTR_HPTE_TABLE,
  653. .icache_bsize = 32,
  654. .dcache_bsize = 32,
  655. .num_pmcs = 4,
  656. .pmc_type = PPC_PMC_IBM,
  657. .cpu_setup = __setup_cpu_750cx,
  658. .machine_check = machine_check_generic,
  659. .platform = "ppc750",
  660. },
  661. { /* 750CXe (82214) */
  662. .pvr_mask = 0xfffffff0,
  663. .pvr_value = 0x00082210,
  664. .cpu_name = "750CXe",
  665. .cpu_features = CPU_FTRS_750,
  666. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  667. .mmu_features = MMU_FTR_HPTE_TABLE,
  668. .icache_bsize = 32,
  669. .dcache_bsize = 32,
  670. .num_pmcs = 4,
  671. .pmc_type = PPC_PMC_IBM,
  672. .cpu_setup = __setup_cpu_750cx,
  673. .machine_check = machine_check_generic,
  674. .platform = "ppc750",
  675. },
  676. { /* 750CXe "Gekko" (83214) */
  677. .pvr_mask = 0xffffffff,
  678. .pvr_value = 0x00083214,
  679. .cpu_name = "750CXe",
  680. .cpu_features = CPU_FTRS_750,
  681. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  682. .mmu_features = MMU_FTR_HPTE_TABLE,
  683. .icache_bsize = 32,
  684. .dcache_bsize = 32,
  685. .num_pmcs = 4,
  686. .pmc_type = PPC_PMC_IBM,
  687. .cpu_setup = __setup_cpu_750cx,
  688. .machine_check = machine_check_generic,
  689. .platform = "ppc750",
  690. },
  691. { /* 750CL (and "Broadway") */
  692. .pvr_mask = 0xfffff0e0,
  693. .pvr_value = 0x00087000,
  694. .cpu_name = "750CL",
  695. .cpu_features = CPU_FTRS_750CL,
  696. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  697. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  698. .icache_bsize = 32,
  699. .dcache_bsize = 32,
  700. .num_pmcs = 4,
  701. .pmc_type = PPC_PMC_IBM,
  702. .cpu_setup = __setup_cpu_750,
  703. .machine_check = machine_check_generic,
  704. .platform = "ppc750",
  705. .oprofile_cpu_type = "ppc/750",
  706. .oprofile_type = PPC_OPROFILE_G4,
  707. },
  708. { /* 745/755 */
  709. .pvr_mask = 0xfffff000,
  710. .pvr_value = 0x00083000,
  711. .cpu_name = "745/755",
  712. .cpu_features = CPU_FTRS_750,
  713. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  714. .mmu_features = MMU_FTR_HPTE_TABLE,
  715. .icache_bsize = 32,
  716. .dcache_bsize = 32,
  717. .num_pmcs = 4,
  718. .pmc_type = PPC_PMC_IBM,
  719. .cpu_setup = __setup_cpu_750,
  720. .machine_check = machine_check_generic,
  721. .platform = "ppc750",
  722. },
  723. { /* 750FX rev 1.x */
  724. .pvr_mask = 0xffffff00,
  725. .pvr_value = 0x70000100,
  726. .cpu_name = "750FX",
  727. .cpu_features = CPU_FTRS_750FX1,
  728. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  729. .mmu_features = MMU_FTR_HPTE_TABLE,
  730. .icache_bsize = 32,
  731. .dcache_bsize = 32,
  732. .num_pmcs = 4,
  733. .pmc_type = PPC_PMC_IBM,
  734. .cpu_setup = __setup_cpu_750,
  735. .machine_check = machine_check_generic,
  736. .platform = "ppc750",
  737. .oprofile_cpu_type = "ppc/750",
  738. .oprofile_type = PPC_OPROFILE_G4,
  739. },
  740. { /* 750FX rev 2.0 must disable HID0[DPM] */
  741. .pvr_mask = 0xffffffff,
  742. .pvr_value = 0x70000200,
  743. .cpu_name = "750FX",
  744. .cpu_features = CPU_FTRS_750FX2,
  745. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  746. .mmu_features = MMU_FTR_HPTE_TABLE,
  747. .icache_bsize = 32,
  748. .dcache_bsize = 32,
  749. .num_pmcs = 4,
  750. .pmc_type = PPC_PMC_IBM,
  751. .cpu_setup = __setup_cpu_750,
  752. .machine_check = machine_check_generic,
  753. .platform = "ppc750",
  754. .oprofile_cpu_type = "ppc/750",
  755. .oprofile_type = PPC_OPROFILE_G4,
  756. },
  757. { /* 750FX (All revs except 2.0) */
  758. .pvr_mask = 0xffff0000,
  759. .pvr_value = 0x70000000,
  760. .cpu_name = "750FX",
  761. .cpu_features = CPU_FTRS_750FX,
  762. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  763. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  764. .icache_bsize = 32,
  765. .dcache_bsize = 32,
  766. .num_pmcs = 4,
  767. .pmc_type = PPC_PMC_IBM,
  768. .cpu_setup = __setup_cpu_750fx,
  769. .machine_check = machine_check_generic,
  770. .platform = "ppc750",
  771. .oprofile_cpu_type = "ppc/750",
  772. .oprofile_type = PPC_OPROFILE_G4,
  773. },
  774. { /* 750GX */
  775. .pvr_mask = 0xffff0000,
  776. .pvr_value = 0x70020000,
  777. .cpu_name = "750GX",
  778. .cpu_features = CPU_FTRS_750GX,
  779. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  780. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  781. .icache_bsize = 32,
  782. .dcache_bsize = 32,
  783. .num_pmcs = 4,
  784. .pmc_type = PPC_PMC_IBM,
  785. .cpu_setup = __setup_cpu_750fx,
  786. .machine_check = machine_check_generic,
  787. .platform = "ppc750",
  788. .oprofile_cpu_type = "ppc/750",
  789. .oprofile_type = PPC_OPROFILE_G4,
  790. },
  791. { /* 740/750 (L2CR bit need fixup for 740) */
  792. .pvr_mask = 0xffff0000,
  793. .pvr_value = 0x00080000,
  794. .cpu_name = "740/750",
  795. .cpu_features = CPU_FTRS_740,
  796. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  797. .mmu_features = MMU_FTR_HPTE_TABLE,
  798. .icache_bsize = 32,
  799. .dcache_bsize = 32,
  800. .num_pmcs = 4,
  801. .pmc_type = PPC_PMC_IBM,
  802. .cpu_setup = __setup_cpu_750,
  803. .machine_check = machine_check_generic,
  804. .platform = "ppc750",
  805. },
  806. { /* 7400 rev 1.1 ? (no TAU) */
  807. .pvr_mask = 0xffffffff,
  808. .pvr_value = 0x000c1101,
  809. .cpu_name = "7400 (1.1)",
  810. .cpu_features = CPU_FTRS_7400_NOTAU,
  811. .cpu_user_features = COMMON_USER |
  812. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  813. .mmu_features = MMU_FTR_HPTE_TABLE,
  814. .icache_bsize = 32,
  815. .dcache_bsize = 32,
  816. .num_pmcs = 4,
  817. .pmc_type = PPC_PMC_G4,
  818. .cpu_setup = __setup_cpu_7400,
  819. .machine_check = machine_check_generic,
  820. .platform = "ppc7400",
  821. },
  822. { /* 7400 */
  823. .pvr_mask = 0xffff0000,
  824. .pvr_value = 0x000c0000,
  825. .cpu_name = "7400",
  826. .cpu_features = CPU_FTRS_7400,
  827. .cpu_user_features = COMMON_USER |
  828. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  829. .mmu_features = MMU_FTR_HPTE_TABLE,
  830. .icache_bsize = 32,
  831. .dcache_bsize = 32,
  832. .num_pmcs = 4,
  833. .pmc_type = PPC_PMC_G4,
  834. .cpu_setup = __setup_cpu_7400,
  835. .machine_check = machine_check_generic,
  836. .platform = "ppc7400",
  837. },
  838. { /* 7410 */
  839. .pvr_mask = 0xffff0000,
  840. .pvr_value = 0x800c0000,
  841. .cpu_name = "7410",
  842. .cpu_features = CPU_FTRS_7400,
  843. .cpu_user_features = COMMON_USER |
  844. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  845. .mmu_features = MMU_FTR_HPTE_TABLE,
  846. .icache_bsize = 32,
  847. .dcache_bsize = 32,
  848. .num_pmcs = 4,
  849. .pmc_type = PPC_PMC_G4,
  850. .cpu_setup = __setup_cpu_7410,
  851. .machine_check = machine_check_generic,
  852. .platform = "ppc7400",
  853. },
  854. { /* 7450 2.0 - no doze/nap */
  855. .pvr_mask = 0xffffffff,
  856. .pvr_value = 0x80000200,
  857. .cpu_name = "7450",
  858. .cpu_features = CPU_FTRS_7450_20,
  859. .cpu_user_features = COMMON_USER |
  860. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  861. .mmu_features = MMU_FTR_HPTE_TABLE,
  862. .icache_bsize = 32,
  863. .dcache_bsize = 32,
  864. .num_pmcs = 6,
  865. .pmc_type = PPC_PMC_G4,
  866. .cpu_setup = __setup_cpu_745x,
  867. .oprofile_cpu_type = "ppc/7450",
  868. .oprofile_type = PPC_OPROFILE_G4,
  869. .machine_check = machine_check_generic,
  870. .platform = "ppc7450",
  871. },
  872. { /* 7450 2.1 */
  873. .pvr_mask = 0xffffffff,
  874. .pvr_value = 0x80000201,
  875. .cpu_name = "7450",
  876. .cpu_features = CPU_FTRS_7450_21,
  877. .cpu_user_features = COMMON_USER |
  878. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  879. .mmu_features = MMU_FTR_HPTE_TABLE,
  880. .icache_bsize = 32,
  881. .dcache_bsize = 32,
  882. .num_pmcs = 6,
  883. .pmc_type = PPC_PMC_G4,
  884. .cpu_setup = __setup_cpu_745x,
  885. .oprofile_cpu_type = "ppc/7450",
  886. .oprofile_type = PPC_OPROFILE_G4,
  887. .machine_check = machine_check_generic,
  888. .platform = "ppc7450",
  889. },
  890. { /* 7450 2.3 and newer */
  891. .pvr_mask = 0xffff0000,
  892. .pvr_value = 0x80000000,
  893. .cpu_name = "7450",
  894. .cpu_features = CPU_FTRS_7450_23,
  895. .cpu_user_features = COMMON_USER |
  896. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  897. .mmu_features = MMU_FTR_HPTE_TABLE,
  898. .icache_bsize = 32,
  899. .dcache_bsize = 32,
  900. .num_pmcs = 6,
  901. .pmc_type = PPC_PMC_G4,
  902. .cpu_setup = __setup_cpu_745x,
  903. .oprofile_cpu_type = "ppc/7450",
  904. .oprofile_type = PPC_OPROFILE_G4,
  905. .machine_check = machine_check_generic,
  906. .platform = "ppc7450",
  907. },
  908. { /* 7455 rev 1.x */
  909. .pvr_mask = 0xffffff00,
  910. .pvr_value = 0x80010100,
  911. .cpu_name = "7455",
  912. .cpu_features = CPU_FTRS_7455_1,
  913. .cpu_user_features = COMMON_USER |
  914. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  915. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  916. .icache_bsize = 32,
  917. .dcache_bsize = 32,
  918. .num_pmcs = 6,
  919. .pmc_type = PPC_PMC_G4,
  920. .cpu_setup = __setup_cpu_745x,
  921. .oprofile_cpu_type = "ppc/7450",
  922. .oprofile_type = PPC_OPROFILE_G4,
  923. .machine_check = machine_check_generic,
  924. .platform = "ppc7450",
  925. },
  926. { /* 7455 rev 2.0 */
  927. .pvr_mask = 0xffffffff,
  928. .pvr_value = 0x80010200,
  929. .cpu_name = "7455",
  930. .cpu_features = CPU_FTRS_7455_20,
  931. .cpu_user_features = COMMON_USER |
  932. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  933. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  934. .icache_bsize = 32,
  935. .dcache_bsize = 32,
  936. .num_pmcs = 6,
  937. .pmc_type = PPC_PMC_G4,
  938. .cpu_setup = __setup_cpu_745x,
  939. .oprofile_cpu_type = "ppc/7450",
  940. .oprofile_type = PPC_OPROFILE_G4,
  941. .machine_check = machine_check_generic,
  942. .platform = "ppc7450",
  943. },
  944. { /* 7455 others */
  945. .pvr_mask = 0xffff0000,
  946. .pvr_value = 0x80010000,
  947. .cpu_name = "7455",
  948. .cpu_features = CPU_FTRS_7455,
  949. .cpu_user_features = COMMON_USER |
  950. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  951. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  952. .icache_bsize = 32,
  953. .dcache_bsize = 32,
  954. .num_pmcs = 6,
  955. .pmc_type = PPC_PMC_G4,
  956. .cpu_setup = __setup_cpu_745x,
  957. .oprofile_cpu_type = "ppc/7450",
  958. .oprofile_type = PPC_OPROFILE_G4,
  959. .machine_check = machine_check_generic,
  960. .platform = "ppc7450",
  961. },
  962. { /* 7447/7457 Rev 1.0 */
  963. .pvr_mask = 0xffffffff,
  964. .pvr_value = 0x80020100,
  965. .cpu_name = "7447/7457",
  966. .cpu_features = CPU_FTRS_7447_10,
  967. .cpu_user_features = COMMON_USER |
  968. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  969. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  970. .icache_bsize = 32,
  971. .dcache_bsize = 32,
  972. .num_pmcs = 6,
  973. .pmc_type = PPC_PMC_G4,
  974. .cpu_setup = __setup_cpu_745x,
  975. .oprofile_cpu_type = "ppc/7450",
  976. .oprofile_type = PPC_OPROFILE_G4,
  977. .machine_check = machine_check_generic,
  978. .platform = "ppc7450",
  979. },
  980. { /* 7447/7457 Rev 1.1 */
  981. .pvr_mask = 0xffffffff,
  982. .pvr_value = 0x80020101,
  983. .cpu_name = "7447/7457",
  984. .cpu_features = CPU_FTRS_7447_10,
  985. .cpu_user_features = COMMON_USER |
  986. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  987. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  988. .icache_bsize = 32,
  989. .dcache_bsize = 32,
  990. .num_pmcs = 6,
  991. .pmc_type = PPC_PMC_G4,
  992. .cpu_setup = __setup_cpu_745x,
  993. .oprofile_cpu_type = "ppc/7450",
  994. .oprofile_type = PPC_OPROFILE_G4,
  995. .machine_check = machine_check_generic,
  996. .platform = "ppc7450",
  997. },
  998. { /* 7447/7457 Rev 1.2 and later */
  999. .pvr_mask = 0xffff0000,
  1000. .pvr_value = 0x80020000,
  1001. .cpu_name = "7447/7457",
  1002. .cpu_features = CPU_FTRS_7447,
  1003. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1004. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1005. .icache_bsize = 32,
  1006. .dcache_bsize = 32,
  1007. .num_pmcs = 6,
  1008. .pmc_type = PPC_PMC_G4,
  1009. .cpu_setup = __setup_cpu_745x,
  1010. .oprofile_cpu_type = "ppc/7450",
  1011. .oprofile_type = PPC_OPROFILE_G4,
  1012. .machine_check = machine_check_generic,
  1013. .platform = "ppc7450",
  1014. },
  1015. { /* 7447A */
  1016. .pvr_mask = 0xffff0000,
  1017. .pvr_value = 0x80030000,
  1018. .cpu_name = "7447A",
  1019. .cpu_features = CPU_FTRS_7447A,
  1020. .cpu_user_features = COMMON_USER |
  1021. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1022. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1023. .icache_bsize = 32,
  1024. .dcache_bsize = 32,
  1025. .num_pmcs = 6,
  1026. .pmc_type = PPC_PMC_G4,
  1027. .cpu_setup = __setup_cpu_745x,
  1028. .oprofile_cpu_type = "ppc/7450",
  1029. .oprofile_type = PPC_OPROFILE_G4,
  1030. .machine_check = machine_check_generic,
  1031. .platform = "ppc7450",
  1032. },
  1033. { /* 7448 */
  1034. .pvr_mask = 0xffff0000,
  1035. .pvr_value = 0x80040000,
  1036. .cpu_name = "7448",
  1037. .cpu_features = CPU_FTRS_7448,
  1038. .cpu_user_features = COMMON_USER |
  1039. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1040. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1041. .icache_bsize = 32,
  1042. .dcache_bsize = 32,
  1043. .num_pmcs = 6,
  1044. .pmc_type = PPC_PMC_G4,
  1045. .cpu_setup = __setup_cpu_745x,
  1046. .oprofile_cpu_type = "ppc/7450",
  1047. .oprofile_type = PPC_OPROFILE_G4,
  1048. .machine_check = machine_check_generic,
  1049. .platform = "ppc7450",
  1050. },
  1051. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1052. .pvr_mask = 0x7fff0000,
  1053. .pvr_value = 0x00810000,
  1054. .cpu_name = "82xx",
  1055. .cpu_features = CPU_FTRS_82XX,
  1056. .cpu_user_features = COMMON_USER,
  1057. .mmu_features = 0,
  1058. .icache_bsize = 32,
  1059. .dcache_bsize = 32,
  1060. .cpu_setup = __setup_cpu_603,
  1061. .machine_check = machine_check_generic,
  1062. .platform = "ppc603",
  1063. },
  1064. { /* All G2_LE (603e core, plus some) have the same pvr */
  1065. .pvr_mask = 0x7fff0000,
  1066. .pvr_value = 0x00820000,
  1067. .cpu_name = "G2_LE",
  1068. .cpu_features = CPU_FTRS_G2_LE,
  1069. .cpu_user_features = COMMON_USER,
  1070. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1071. .icache_bsize = 32,
  1072. .dcache_bsize = 32,
  1073. .cpu_setup = __setup_cpu_603,
  1074. .machine_check = machine_check_generic,
  1075. .platform = "ppc603",
  1076. },
  1077. { /* e300c1 (a 603e core, plus some) on 83xx */
  1078. .pvr_mask = 0x7fff0000,
  1079. .pvr_value = 0x00830000,
  1080. .cpu_name = "e300c1",
  1081. .cpu_features = CPU_FTRS_E300,
  1082. .cpu_user_features = COMMON_USER,
  1083. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1084. .icache_bsize = 32,
  1085. .dcache_bsize = 32,
  1086. .cpu_setup = __setup_cpu_603,
  1087. .machine_check = machine_check_generic,
  1088. .platform = "ppc603",
  1089. },
  1090. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1091. .pvr_mask = 0x7fff0000,
  1092. .pvr_value = 0x00840000,
  1093. .cpu_name = "e300c2",
  1094. .cpu_features = CPU_FTRS_E300C2,
  1095. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1096. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1097. MMU_FTR_NEED_DTLB_SW_LRU,
  1098. .icache_bsize = 32,
  1099. .dcache_bsize = 32,
  1100. .cpu_setup = __setup_cpu_603,
  1101. .machine_check = machine_check_generic,
  1102. .platform = "ppc603",
  1103. },
  1104. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1105. .pvr_mask = 0x7fff0000,
  1106. .pvr_value = 0x00850000,
  1107. .cpu_name = "e300c3",
  1108. .cpu_features = CPU_FTRS_E300,
  1109. .cpu_user_features = COMMON_USER,
  1110. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1111. MMU_FTR_NEED_DTLB_SW_LRU,
  1112. .icache_bsize = 32,
  1113. .dcache_bsize = 32,
  1114. .cpu_setup = __setup_cpu_603,
  1115. .num_pmcs = 4,
  1116. .oprofile_cpu_type = "ppc/e300",
  1117. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1118. .platform = "ppc603",
  1119. },
  1120. { /* e300c4 (e300c1, plus one IU) */
  1121. .pvr_mask = 0x7fff0000,
  1122. .pvr_value = 0x00860000,
  1123. .cpu_name = "e300c4",
  1124. .cpu_features = CPU_FTRS_E300,
  1125. .cpu_user_features = COMMON_USER,
  1126. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1127. MMU_FTR_NEED_DTLB_SW_LRU,
  1128. .icache_bsize = 32,
  1129. .dcache_bsize = 32,
  1130. .cpu_setup = __setup_cpu_603,
  1131. .machine_check = machine_check_generic,
  1132. .num_pmcs = 4,
  1133. .oprofile_cpu_type = "ppc/e300",
  1134. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1135. .platform = "ppc603",
  1136. },
  1137. { /* default match, we assume split I/D cache & TB (non-601)... */
  1138. .pvr_mask = 0x00000000,
  1139. .pvr_value = 0x00000000,
  1140. .cpu_name = "(generic PPC)",
  1141. .cpu_features = CPU_FTRS_CLASSIC32,
  1142. .cpu_user_features = COMMON_USER,
  1143. .mmu_features = MMU_FTR_HPTE_TABLE,
  1144. .icache_bsize = 32,
  1145. .dcache_bsize = 32,
  1146. .machine_check = machine_check_generic,
  1147. .platform = "ppc603",
  1148. },
  1149. #endif /* CLASSIC_PPC */
  1150. #ifdef CONFIG_8xx
  1151. { /* 8xx */
  1152. .pvr_mask = 0xffff0000,
  1153. .pvr_value = 0x00500000,
  1154. .cpu_name = "8xx",
  1155. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1156. * if the 8xx code is there.... */
  1157. .cpu_features = CPU_FTRS_8XX,
  1158. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1159. .mmu_features = MMU_FTR_TYPE_8xx,
  1160. .icache_bsize = 16,
  1161. .dcache_bsize = 16,
  1162. .platform = "ppc823",
  1163. },
  1164. #endif /* CONFIG_8xx */
  1165. #ifdef CONFIG_40x
  1166. { /* 403GC */
  1167. .pvr_mask = 0xffffff00,
  1168. .pvr_value = 0x00200200,
  1169. .cpu_name = "403GC",
  1170. .cpu_features = CPU_FTRS_40X,
  1171. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1172. .mmu_features = MMU_FTR_TYPE_40x,
  1173. .icache_bsize = 16,
  1174. .dcache_bsize = 16,
  1175. .machine_check = machine_check_4xx,
  1176. .platform = "ppc403",
  1177. },
  1178. { /* 403GCX */
  1179. .pvr_mask = 0xffffff00,
  1180. .pvr_value = 0x00201400,
  1181. .cpu_name = "403GCX",
  1182. .cpu_features = CPU_FTRS_40X,
  1183. .cpu_user_features = PPC_FEATURE_32 |
  1184. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1185. .mmu_features = MMU_FTR_TYPE_40x,
  1186. .icache_bsize = 16,
  1187. .dcache_bsize = 16,
  1188. .machine_check = machine_check_4xx,
  1189. .platform = "ppc403",
  1190. },
  1191. { /* 403G ?? */
  1192. .pvr_mask = 0xffff0000,
  1193. .pvr_value = 0x00200000,
  1194. .cpu_name = "403G ??",
  1195. .cpu_features = CPU_FTRS_40X,
  1196. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1197. .mmu_features = MMU_FTR_TYPE_40x,
  1198. .icache_bsize = 16,
  1199. .dcache_bsize = 16,
  1200. .machine_check = machine_check_4xx,
  1201. .platform = "ppc403",
  1202. },
  1203. { /* 405GP */
  1204. .pvr_mask = 0xffff0000,
  1205. .pvr_value = 0x40110000,
  1206. .cpu_name = "405GP",
  1207. .cpu_features = CPU_FTRS_40X,
  1208. .cpu_user_features = PPC_FEATURE_32 |
  1209. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1210. .mmu_features = MMU_FTR_TYPE_40x,
  1211. .icache_bsize = 32,
  1212. .dcache_bsize = 32,
  1213. .machine_check = machine_check_4xx,
  1214. .platform = "ppc405",
  1215. },
  1216. { /* STB 03xxx */
  1217. .pvr_mask = 0xffff0000,
  1218. .pvr_value = 0x40130000,
  1219. .cpu_name = "STB03xxx",
  1220. .cpu_features = CPU_FTRS_40X,
  1221. .cpu_user_features = PPC_FEATURE_32 |
  1222. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1223. .mmu_features = MMU_FTR_TYPE_40x,
  1224. .icache_bsize = 32,
  1225. .dcache_bsize = 32,
  1226. .machine_check = machine_check_4xx,
  1227. .platform = "ppc405",
  1228. },
  1229. { /* STB 04xxx */
  1230. .pvr_mask = 0xffff0000,
  1231. .pvr_value = 0x41810000,
  1232. .cpu_name = "STB04xxx",
  1233. .cpu_features = CPU_FTRS_40X,
  1234. .cpu_user_features = PPC_FEATURE_32 |
  1235. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1236. .mmu_features = MMU_FTR_TYPE_40x,
  1237. .icache_bsize = 32,
  1238. .dcache_bsize = 32,
  1239. .machine_check = machine_check_4xx,
  1240. .platform = "ppc405",
  1241. },
  1242. { /* NP405L */
  1243. .pvr_mask = 0xffff0000,
  1244. .pvr_value = 0x41610000,
  1245. .cpu_name = "NP405L",
  1246. .cpu_features = CPU_FTRS_40X,
  1247. .cpu_user_features = PPC_FEATURE_32 |
  1248. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1249. .mmu_features = MMU_FTR_TYPE_40x,
  1250. .icache_bsize = 32,
  1251. .dcache_bsize = 32,
  1252. .machine_check = machine_check_4xx,
  1253. .platform = "ppc405",
  1254. },
  1255. { /* NP4GS3 */
  1256. .pvr_mask = 0xffff0000,
  1257. .pvr_value = 0x40B10000,
  1258. .cpu_name = "NP4GS3",
  1259. .cpu_features = CPU_FTRS_40X,
  1260. .cpu_user_features = PPC_FEATURE_32 |
  1261. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1262. .mmu_features = MMU_FTR_TYPE_40x,
  1263. .icache_bsize = 32,
  1264. .dcache_bsize = 32,
  1265. .machine_check = machine_check_4xx,
  1266. .platform = "ppc405",
  1267. },
  1268. { /* NP405H */
  1269. .pvr_mask = 0xffff0000,
  1270. .pvr_value = 0x41410000,
  1271. .cpu_name = "NP405H",
  1272. .cpu_features = CPU_FTRS_40X,
  1273. .cpu_user_features = PPC_FEATURE_32 |
  1274. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1275. .mmu_features = MMU_FTR_TYPE_40x,
  1276. .icache_bsize = 32,
  1277. .dcache_bsize = 32,
  1278. .machine_check = machine_check_4xx,
  1279. .platform = "ppc405",
  1280. },
  1281. { /* 405GPr */
  1282. .pvr_mask = 0xffff0000,
  1283. .pvr_value = 0x50910000,
  1284. .cpu_name = "405GPr",
  1285. .cpu_features = CPU_FTRS_40X,
  1286. .cpu_user_features = PPC_FEATURE_32 |
  1287. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1288. .mmu_features = MMU_FTR_TYPE_40x,
  1289. .icache_bsize = 32,
  1290. .dcache_bsize = 32,
  1291. .machine_check = machine_check_4xx,
  1292. .platform = "ppc405",
  1293. },
  1294. { /* STBx25xx */
  1295. .pvr_mask = 0xffff0000,
  1296. .pvr_value = 0x51510000,
  1297. .cpu_name = "STBx25xx",
  1298. .cpu_features = CPU_FTRS_40X,
  1299. .cpu_user_features = PPC_FEATURE_32 |
  1300. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1301. .mmu_features = MMU_FTR_TYPE_40x,
  1302. .icache_bsize = 32,
  1303. .dcache_bsize = 32,
  1304. .machine_check = machine_check_4xx,
  1305. .platform = "ppc405",
  1306. },
  1307. { /* 405LP */
  1308. .pvr_mask = 0xffff0000,
  1309. .pvr_value = 0x41F10000,
  1310. .cpu_name = "405LP",
  1311. .cpu_features = CPU_FTRS_40X,
  1312. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1313. .mmu_features = MMU_FTR_TYPE_40x,
  1314. .icache_bsize = 32,
  1315. .dcache_bsize = 32,
  1316. .machine_check = machine_check_4xx,
  1317. .platform = "ppc405",
  1318. },
  1319. { /* Xilinx Virtex-II Pro */
  1320. .pvr_mask = 0xfffff000,
  1321. .pvr_value = 0x20010000,
  1322. .cpu_name = "Virtex-II Pro",
  1323. .cpu_features = CPU_FTRS_40X,
  1324. .cpu_user_features = PPC_FEATURE_32 |
  1325. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1326. .mmu_features = MMU_FTR_TYPE_40x,
  1327. .icache_bsize = 32,
  1328. .dcache_bsize = 32,
  1329. .machine_check = machine_check_4xx,
  1330. .platform = "ppc405",
  1331. },
  1332. { /* Xilinx Virtex-4 FX */
  1333. .pvr_mask = 0xfffff000,
  1334. .pvr_value = 0x20011000,
  1335. .cpu_name = "Virtex-4 FX",
  1336. .cpu_features = CPU_FTRS_40X,
  1337. .cpu_user_features = PPC_FEATURE_32 |
  1338. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1339. .mmu_features = MMU_FTR_TYPE_40x,
  1340. .icache_bsize = 32,
  1341. .dcache_bsize = 32,
  1342. .machine_check = machine_check_4xx,
  1343. .platform = "ppc405",
  1344. },
  1345. { /* 405EP */
  1346. .pvr_mask = 0xffff0000,
  1347. .pvr_value = 0x51210000,
  1348. .cpu_name = "405EP",
  1349. .cpu_features = CPU_FTRS_40X,
  1350. .cpu_user_features = PPC_FEATURE_32 |
  1351. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1352. .mmu_features = MMU_FTR_TYPE_40x,
  1353. .icache_bsize = 32,
  1354. .dcache_bsize = 32,
  1355. .machine_check = machine_check_4xx,
  1356. .platform = "ppc405",
  1357. },
  1358. { /* 405EX Rev. A/B with Security */
  1359. .pvr_mask = 0xffff000f,
  1360. .pvr_value = 0x12910007,
  1361. .cpu_name = "405EX Rev. A/B",
  1362. .cpu_features = CPU_FTRS_40X,
  1363. .cpu_user_features = PPC_FEATURE_32 |
  1364. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1365. .mmu_features = MMU_FTR_TYPE_40x,
  1366. .icache_bsize = 32,
  1367. .dcache_bsize = 32,
  1368. .machine_check = machine_check_4xx,
  1369. .platform = "ppc405",
  1370. },
  1371. { /* 405EX Rev. C without Security */
  1372. .pvr_mask = 0xffff000f,
  1373. .pvr_value = 0x1291000d,
  1374. .cpu_name = "405EX Rev. C",
  1375. .cpu_features = CPU_FTRS_40X,
  1376. .cpu_user_features = PPC_FEATURE_32 |
  1377. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1378. .mmu_features = MMU_FTR_TYPE_40x,
  1379. .icache_bsize = 32,
  1380. .dcache_bsize = 32,
  1381. .machine_check = machine_check_4xx,
  1382. .platform = "ppc405",
  1383. },
  1384. { /* 405EX Rev. C with Security */
  1385. .pvr_mask = 0xffff000f,
  1386. .pvr_value = 0x1291000f,
  1387. .cpu_name = "405EX Rev. C",
  1388. .cpu_features = CPU_FTRS_40X,
  1389. .cpu_user_features = PPC_FEATURE_32 |
  1390. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1391. .mmu_features = MMU_FTR_TYPE_40x,
  1392. .icache_bsize = 32,
  1393. .dcache_bsize = 32,
  1394. .machine_check = machine_check_4xx,
  1395. .platform = "ppc405",
  1396. },
  1397. { /* 405EX Rev. D without Security */
  1398. .pvr_mask = 0xffff000f,
  1399. .pvr_value = 0x12910003,
  1400. .cpu_name = "405EX Rev. D",
  1401. .cpu_features = CPU_FTRS_40X,
  1402. .cpu_user_features = PPC_FEATURE_32 |
  1403. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1404. .mmu_features = MMU_FTR_TYPE_40x,
  1405. .icache_bsize = 32,
  1406. .dcache_bsize = 32,
  1407. .machine_check = machine_check_4xx,
  1408. .platform = "ppc405",
  1409. },
  1410. { /* 405EX Rev. D with Security */
  1411. .pvr_mask = 0xffff000f,
  1412. .pvr_value = 0x12910005,
  1413. .cpu_name = "405EX Rev. D",
  1414. .cpu_features = CPU_FTRS_40X,
  1415. .cpu_user_features = PPC_FEATURE_32 |
  1416. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1417. .mmu_features = MMU_FTR_TYPE_40x,
  1418. .icache_bsize = 32,
  1419. .dcache_bsize = 32,
  1420. .machine_check = machine_check_4xx,
  1421. .platform = "ppc405",
  1422. },
  1423. { /* 405EXr Rev. A/B without Security */
  1424. .pvr_mask = 0xffff000f,
  1425. .pvr_value = 0x12910001,
  1426. .cpu_name = "405EXr Rev. A/B",
  1427. .cpu_features = CPU_FTRS_40X,
  1428. .cpu_user_features = PPC_FEATURE_32 |
  1429. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1430. .mmu_features = MMU_FTR_TYPE_40x,
  1431. .icache_bsize = 32,
  1432. .dcache_bsize = 32,
  1433. .machine_check = machine_check_4xx,
  1434. .platform = "ppc405",
  1435. },
  1436. { /* 405EXr Rev. C without Security */
  1437. .pvr_mask = 0xffff000f,
  1438. .pvr_value = 0x12910009,
  1439. .cpu_name = "405EXr Rev. C",
  1440. .cpu_features = CPU_FTRS_40X,
  1441. .cpu_user_features = PPC_FEATURE_32 |
  1442. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1443. .mmu_features = MMU_FTR_TYPE_40x,
  1444. .icache_bsize = 32,
  1445. .dcache_bsize = 32,
  1446. .machine_check = machine_check_4xx,
  1447. .platform = "ppc405",
  1448. },
  1449. { /* 405EXr Rev. C with Security */
  1450. .pvr_mask = 0xffff000f,
  1451. .pvr_value = 0x1291000b,
  1452. .cpu_name = "405EXr Rev. C",
  1453. .cpu_features = CPU_FTRS_40X,
  1454. .cpu_user_features = PPC_FEATURE_32 |
  1455. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1456. .mmu_features = MMU_FTR_TYPE_40x,
  1457. .icache_bsize = 32,
  1458. .dcache_bsize = 32,
  1459. .machine_check = machine_check_4xx,
  1460. .platform = "ppc405",
  1461. },
  1462. { /* 405EXr Rev. D without Security */
  1463. .pvr_mask = 0xffff000f,
  1464. .pvr_value = 0x12910000,
  1465. .cpu_name = "405EXr Rev. D",
  1466. .cpu_features = CPU_FTRS_40X,
  1467. .cpu_user_features = PPC_FEATURE_32 |
  1468. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1469. .mmu_features = MMU_FTR_TYPE_40x,
  1470. .icache_bsize = 32,
  1471. .dcache_bsize = 32,
  1472. .machine_check = machine_check_4xx,
  1473. .platform = "ppc405",
  1474. },
  1475. { /* 405EXr Rev. D with Security */
  1476. .pvr_mask = 0xffff000f,
  1477. .pvr_value = 0x12910002,
  1478. .cpu_name = "405EXr Rev. D",
  1479. .cpu_features = CPU_FTRS_40X,
  1480. .cpu_user_features = PPC_FEATURE_32 |
  1481. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1482. .mmu_features = MMU_FTR_TYPE_40x,
  1483. .icache_bsize = 32,
  1484. .dcache_bsize = 32,
  1485. .machine_check = machine_check_4xx,
  1486. .platform = "ppc405",
  1487. },
  1488. {
  1489. /* 405EZ */
  1490. .pvr_mask = 0xffff0000,
  1491. .pvr_value = 0x41510000,
  1492. .cpu_name = "405EZ",
  1493. .cpu_features = CPU_FTRS_40X,
  1494. .cpu_user_features = PPC_FEATURE_32 |
  1495. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1496. .mmu_features = MMU_FTR_TYPE_40x,
  1497. .icache_bsize = 32,
  1498. .dcache_bsize = 32,
  1499. .machine_check = machine_check_4xx,
  1500. .platform = "ppc405",
  1501. },
  1502. { /* default match */
  1503. .pvr_mask = 0x00000000,
  1504. .pvr_value = 0x00000000,
  1505. .cpu_name = "(generic 40x PPC)",
  1506. .cpu_features = CPU_FTRS_40X,
  1507. .cpu_user_features = PPC_FEATURE_32 |
  1508. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1509. .mmu_features = MMU_FTR_TYPE_40x,
  1510. .icache_bsize = 32,
  1511. .dcache_bsize = 32,
  1512. .machine_check = machine_check_4xx,
  1513. .platform = "ppc405",
  1514. }
  1515. #endif /* CONFIG_40x */
  1516. #ifdef CONFIG_44x
  1517. {
  1518. .pvr_mask = 0xf0000fff,
  1519. .pvr_value = 0x40000850,
  1520. .cpu_name = "440GR Rev. A",
  1521. .cpu_features = CPU_FTRS_44X,
  1522. .cpu_user_features = COMMON_USER_BOOKE,
  1523. .mmu_features = MMU_FTR_TYPE_44x,
  1524. .icache_bsize = 32,
  1525. .dcache_bsize = 32,
  1526. .machine_check = machine_check_4xx,
  1527. .platform = "ppc440",
  1528. },
  1529. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1530. .pvr_mask = 0xf0000fff,
  1531. .pvr_value = 0x40000858,
  1532. .cpu_name = "440EP Rev. A",
  1533. .cpu_features = CPU_FTRS_44X,
  1534. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1535. .mmu_features = MMU_FTR_TYPE_44x,
  1536. .icache_bsize = 32,
  1537. .dcache_bsize = 32,
  1538. .cpu_setup = __setup_cpu_440ep,
  1539. .machine_check = machine_check_4xx,
  1540. .platform = "ppc440",
  1541. },
  1542. {
  1543. .pvr_mask = 0xf0000fff,
  1544. .pvr_value = 0x400008d3,
  1545. .cpu_name = "440GR Rev. B",
  1546. .cpu_features = CPU_FTRS_44X,
  1547. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1548. .mmu_features = MMU_FTR_TYPE_44x,
  1549. .icache_bsize = 32,
  1550. .dcache_bsize = 32,
  1551. .machine_check = machine_check_4xx,
  1552. .platform = "ppc440",
  1553. },
  1554. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1555. .pvr_mask = 0xf0000ff7,
  1556. .pvr_value = 0x400008d4,
  1557. .cpu_name = "440EP Rev. C",
  1558. .cpu_features = CPU_FTRS_44X,
  1559. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1560. .mmu_features = MMU_FTR_TYPE_44x,
  1561. .icache_bsize = 32,
  1562. .dcache_bsize = 32,
  1563. .cpu_setup = __setup_cpu_440ep,
  1564. .machine_check = machine_check_4xx,
  1565. .platform = "ppc440",
  1566. },
  1567. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1568. .pvr_mask = 0xf0000fff,
  1569. .pvr_value = 0x400008db,
  1570. .cpu_name = "440EP Rev. B",
  1571. .cpu_features = CPU_FTRS_44X,
  1572. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1573. .mmu_features = MMU_FTR_TYPE_44x,
  1574. .icache_bsize = 32,
  1575. .dcache_bsize = 32,
  1576. .cpu_setup = __setup_cpu_440ep,
  1577. .machine_check = machine_check_4xx,
  1578. .platform = "ppc440",
  1579. },
  1580. { /* 440GRX */
  1581. .pvr_mask = 0xf0000ffb,
  1582. .pvr_value = 0x200008D0,
  1583. .cpu_name = "440GRX",
  1584. .cpu_features = CPU_FTRS_44X,
  1585. .cpu_user_features = COMMON_USER_BOOKE,
  1586. .mmu_features = MMU_FTR_TYPE_44x,
  1587. .icache_bsize = 32,
  1588. .dcache_bsize = 32,
  1589. .cpu_setup = __setup_cpu_440grx,
  1590. .machine_check = machine_check_440A,
  1591. .platform = "ppc440",
  1592. },
  1593. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1594. .pvr_mask = 0xf0000ffb,
  1595. .pvr_value = 0x200008D8,
  1596. .cpu_name = "440EPX",
  1597. .cpu_features = CPU_FTRS_44X,
  1598. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1599. .mmu_features = MMU_FTR_TYPE_44x,
  1600. .icache_bsize = 32,
  1601. .dcache_bsize = 32,
  1602. .cpu_setup = __setup_cpu_440epx,
  1603. .machine_check = machine_check_440A,
  1604. .platform = "ppc440",
  1605. },
  1606. { /* 440GP Rev. B */
  1607. .pvr_mask = 0xf0000fff,
  1608. .pvr_value = 0x40000440,
  1609. .cpu_name = "440GP Rev. B",
  1610. .cpu_features = CPU_FTRS_44X,
  1611. .cpu_user_features = COMMON_USER_BOOKE,
  1612. .mmu_features = MMU_FTR_TYPE_44x,
  1613. .icache_bsize = 32,
  1614. .dcache_bsize = 32,
  1615. .machine_check = machine_check_4xx,
  1616. .platform = "ppc440gp",
  1617. },
  1618. { /* 440GP Rev. C */
  1619. .pvr_mask = 0xf0000fff,
  1620. .pvr_value = 0x40000481,
  1621. .cpu_name = "440GP Rev. C",
  1622. .cpu_features = CPU_FTRS_44X,
  1623. .cpu_user_features = COMMON_USER_BOOKE,
  1624. .mmu_features = MMU_FTR_TYPE_44x,
  1625. .icache_bsize = 32,
  1626. .dcache_bsize = 32,
  1627. .machine_check = machine_check_4xx,
  1628. .platform = "ppc440gp",
  1629. },
  1630. { /* 440GX Rev. A */
  1631. .pvr_mask = 0xf0000fff,
  1632. .pvr_value = 0x50000850,
  1633. .cpu_name = "440GX Rev. A",
  1634. .cpu_features = CPU_FTRS_44X,
  1635. .cpu_user_features = COMMON_USER_BOOKE,
  1636. .mmu_features = MMU_FTR_TYPE_44x,
  1637. .icache_bsize = 32,
  1638. .dcache_bsize = 32,
  1639. .cpu_setup = __setup_cpu_440gx,
  1640. .machine_check = machine_check_440A,
  1641. .platform = "ppc440",
  1642. },
  1643. { /* 440GX Rev. B */
  1644. .pvr_mask = 0xf0000fff,
  1645. .pvr_value = 0x50000851,
  1646. .cpu_name = "440GX Rev. B",
  1647. .cpu_features = CPU_FTRS_44X,
  1648. .cpu_user_features = COMMON_USER_BOOKE,
  1649. .mmu_features = MMU_FTR_TYPE_44x,
  1650. .icache_bsize = 32,
  1651. .dcache_bsize = 32,
  1652. .cpu_setup = __setup_cpu_440gx,
  1653. .machine_check = machine_check_440A,
  1654. .platform = "ppc440",
  1655. },
  1656. { /* 440GX Rev. C */
  1657. .pvr_mask = 0xf0000fff,
  1658. .pvr_value = 0x50000892,
  1659. .cpu_name = "440GX Rev. C",
  1660. .cpu_features = CPU_FTRS_44X,
  1661. .cpu_user_features = COMMON_USER_BOOKE,
  1662. .mmu_features = MMU_FTR_TYPE_44x,
  1663. .icache_bsize = 32,
  1664. .dcache_bsize = 32,
  1665. .cpu_setup = __setup_cpu_440gx,
  1666. .machine_check = machine_check_440A,
  1667. .platform = "ppc440",
  1668. },
  1669. { /* 440GX Rev. F */
  1670. .pvr_mask = 0xf0000fff,
  1671. .pvr_value = 0x50000894,
  1672. .cpu_name = "440GX Rev. F",
  1673. .cpu_features = CPU_FTRS_44X,
  1674. .cpu_user_features = COMMON_USER_BOOKE,
  1675. .mmu_features = MMU_FTR_TYPE_44x,
  1676. .icache_bsize = 32,
  1677. .dcache_bsize = 32,
  1678. .cpu_setup = __setup_cpu_440gx,
  1679. .machine_check = machine_check_440A,
  1680. .platform = "ppc440",
  1681. },
  1682. { /* 440SP Rev. A */
  1683. .pvr_mask = 0xfff00fff,
  1684. .pvr_value = 0x53200891,
  1685. .cpu_name = "440SP Rev. A",
  1686. .cpu_features = CPU_FTRS_44X,
  1687. .cpu_user_features = COMMON_USER_BOOKE,
  1688. .mmu_features = MMU_FTR_TYPE_44x,
  1689. .icache_bsize = 32,
  1690. .dcache_bsize = 32,
  1691. .machine_check = machine_check_4xx,
  1692. .platform = "ppc440",
  1693. },
  1694. { /* 440SPe Rev. A */
  1695. .pvr_mask = 0xfff00fff,
  1696. .pvr_value = 0x53400890,
  1697. .cpu_name = "440SPe Rev. A",
  1698. .cpu_features = CPU_FTRS_44X,
  1699. .cpu_user_features = COMMON_USER_BOOKE,
  1700. .mmu_features = MMU_FTR_TYPE_44x,
  1701. .icache_bsize = 32,
  1702. .dcache_bsize = 32,
  1703. .cpu_setup = __setup_cpu_440spe,
  1704. .machine_check = machine_check_440A,
  1705. .platform = "ppc440",
  1706. },
  1707. { /* 440SPe Rev. B */
  1708. .pvr_mask = 0xfff00fff,
  1709. .pvr_value = 0x53400891,
  1710. .cpu_name = "440SPe Rev. B",
  1711. .cpu_features = CPU_FTRS_44X,
  1712. .cpu_user_features = COMMON_USER_BOOKE,
  1713. .mmu_features = MMU_FTR_TYPE_44x,
  1714. .icache_bsize = 32,
  1715. .dcache_bsize = 32,
  1716. .cpu_setup = __setup_cpu_440spe,
  1717. .machine_check = machine_check_440A,
  1718. .platform = "ppc440",
  1719. },
  1720. { /* 440 in Xilinx Virtex-5 FXT */
  1721. .pvr_mask = 0xfffffff0,
  1722. .pvr_value = 0x7ff21910,
  1723. .cpu_name = "440 in Virtex-5 FXT",
  1724. .cpu_features = CPU_FTRS_44X,
  1725. .cpu_user_features = COMMON_USER_BOOKE,
  1726. .mmu_features = MMU_FTR_TYPE_44x,
  1727. .icache_bsize = 32,
  1728. .dcache_bsize = 32,
  1729. .cpu_setup = __setup_cpu_440x5,
  1730. .machine_check = machine_check_440A,
  1731. .platform = "ppc440",
  1732. },
  1733. { /* 460EX */
  1734. .pvr_mask = 0xffff0006,
  1735. .pvr_value = 0x13020002,
  1736. .cpu_name = "460EX",
  1737. .cpu_features = CPU_FTRS_440x6,
  1738. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1739. .mmu_features = MMU_FTR_TYPE_44x,
  1740. .icache_bsize = 32,
  1741. .dcache_bsize = 32,
  1742. .cpu_setup = __setup_cpu_460ex,
  1743. .machine_check = machine_check_440A,
  1744. .platform = "ppc440",
  1745. },
  1746. { /* 460EX Rev B */
  1747. .pvr_mask = 0xffff0007,
  1748. .pvr_value = 0x13020004,
  1749. .cpu_name = "460EX Rev. B",
  1750. .cpu_features = CPU_FTRS_440x6,
  1751. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1752. .mmu_features = MMU_FTR_TYPE_44x,
  1753. .icache_bsize = 32,
  1754. .dcache_bsize = 32,
  1755. .cpu_setup = __setup_cpu_460ex,
  1756. .machine_check = machine_check_440A,
  1757. .platform = "ppc440",
  1758. },
  1759. { /* 460GT */
  1760. .pvr_mask = 0xffff0006,
  1761. .pvr_value = 0x13020000,
  1762. .cpu_name = "460GT",
  1763. .cpu_features = CPU_FTRS_440x6,
  1764. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1765. .mmu_features = MMU_FTR_TYPE_44x,
  1766. .icache_bsize = 32,
  1767. .dcache_bsize = 32,
  1768. .cpu_setup = __setup_cpu_460gt,
  1769. .machine_check = machine_check_440A,
  1770. .platform = "ppc440",
  1771. },
  1772. { /* 460GT Rev B */
  1773. .pvr_mask = 0xffff0007,
  1774. .pvr_value = 0x13020005,
  1775. .cpu_name = "460GT Rev. B",
  1776. .cpu_features = CPU_FTRS_440x6,
  1777. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1778. .mmu_features = MMU_FTR_TYPE_44x,
  1779. .icache_bsize = 32,
  1780. .dcache_bsize = 32,
  1781. .cpu_setup = __setup_cpu_460gt,
  1782. .machine_check = machine_check_440A,
  1783. .platform = "ppc440",
  1784. },
  1785. { /* 460SX */
  1786. .pvr_mask = 0xffffff00,
  1787. .pvr_value = 0x13541800,
  1788. .cpu_name = "460SX",
  1789. .cpu_features = CPU_FTRS_44X,
  1790. .cpu_user_features = COMMON_USER_BOOKE,
  1791. .mmu_features = MMU_FTR_TYPE_44x,
  1792. .icache_bsize = 32,
  1793. .dcache_bsize = 32,
  1794. .cpu_setup = __setup_cpu_460sx,
  1795. .machine_check = machine_check_440A,
  1796. .platform = "ppc440",
  1797. },
  1798. { /* 464 in APM821xx */
  1799. .pvr_mask = 0xffffff00,
  1800. .pvr_value = 0x12C41C80,
  1801. .cpu_name = "APM821XX",
  1802. .cpu_features = CPU_FTRS_44X,
  1803. .cpu_user_features = COMMON_USER_BOOKE |
  1804. PPC_FEATURE_HAS_FPU,
  1805. .mmu_features = MMU_FTR_TYPE_44x,
  1806. .icache_bsize = 32,
  1807. .dcache_bsize = 32,
  1808. .cpu_setup = __setup_cpu_apm821xx,
  1809. .machine_check = machine_check_440A,
  1810. .platform = "ppc440",
  1811. },
  1812. { /* 476 core */
  1813. .pvr_mask = 0xffff0000,
  1814. .pvr_value = 0x11a50000,
  1815. .cpu_name = "476",
  1816. .cpu_features = CPU_FTRS_47X,
  1817. .cpu_user_features = COMMON_USER_BOOKE |
  1818. PPC_FEATURE_HAS_FPU,
  1819. .mmu_features = MMU_FTR_TYPE_47x |
  1820. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1821. .icache_bsize = 32,
  1822. .dcache_bsize = 128,
  1823. .machine_check = machine_check_47x,
  1824. .platform = "ppc470",
  1825. },
  1826. { /* 476 iss */
  1827. .pvr_mask = 0xffff0000,
  1828. .pvr_value = 0x00050000,
  1829. .cpu_name = "476",
  1830. .cpu_features = CPU_FTRS_47X,
  1831. .cpu_user_features = COMMON_USER_BOOKE |
  1832. PPC_FEATURE_HAS_FPU,
  1833. .mmu_features = MMU_FTR_TYPE_47x |
  1834. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1835. .icache_bsize = 32,
  1836. .dcache_bsize = 128,
  1837. .machine_check = machine_check_47x,
  1838. .platform = "ppc470",
  1839. },
  1840. { /* default match */
  1841. .pvr_mask = 0x00000000,
  1842. .pvr_value = 0x00000000,
  1843. .cpu_name = "(generic 44x PPC)",
  1844. .cpu_features = CPU_FTRS_44X,
  1845. .cpu_user_features = COMMON_USER_BOOKE,
  1846. .mmu_features = MMU_FTR_TYPE_44x,
  1847. .icache_bsize = 32,
  1848. .dcache_bsize = 32,
  1849. .machine_check = machine_check_4xx,
  1850. .platform = "ppc440",
  1851. }
  1852. #endif /* CONFIG_44x */
  1853. #ifdef CONFIG_E200
  1854. { /* e200z5 */
  1855. .pvr_mask = 0xfff00000,
  1856. .pvr_value = 0x81000000,
  1857. .cpu_name = "e200z5",
  1858. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1859. .cpu_features = CPU_FTRS_E200,
  1860. .cpu_user_features = COMMON_USER_BOOKE |
  1861. PPC_FEATURE_HAS_EFP_SINGLE |
  1862. PPC_FEATURE_UNIFIED_CACHE,
  1863. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1864. .dcache_bsize = 32,
  1865. .machine_check = machine_check_e200,
  1866. .platform = "ppc5554",
  1867. },
  1868. { /* e200z6 */
  1869. .pvr_mask = 0xfff00000,
  1870. .pvr_value = 0x81100000,
  1871. .cpu_name = "e200z6",
  1872. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1873. .cpu_features = CPU_FTRS_E200,
  1874. .cpu_user_features = COMMON_USER_BOOKE |
  1875. PPC_FEATURE_HAS_SPE_COMP |
  1876. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1877. PPC_FEATURE_UNIFIED_CACHE,
  1878. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1879. .dcache_bsize = 32,
  1880. .machine_check = machine_check_e200,
  1881. .platform = "ppc5554",
  1882. },
  1883. { /* default match */
  1884. .pvr_mask = 0x00000000,
  1885. .pvr_value = 0x00000000,
  1886. .cpu_name = "(generic E200 PPC)",
  1887. .cpu_features = CPU_FTRS_E200,
  1888. .cpu_user_features = COMMON_USER_BOOKE |
  1889. PPC_FEATURE_HAS_EFP_SINGLE |
  1890. PPC_FEATURE_UNIFIED_CACHE,
  1891. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1892. .dcache_bsize = 32,
  1893. .cpu_setup = __setup_cpu_e200,
  1894. .machine_check = machine_check_e200,
  1895. .platform = "ppc5554",
  1896. }
  1897. #endif /* CONFIG_E200 */
  1898. #endif /* CONFIG_PPC32 */
  1899. #ifdef CONFIG_E500
  1900. #ifdef CONFIG_PPC32
  1901. { /* e500 */
  1902. .pvr_mask = 0xffff0000,
  1903. .pvr_value = 0x80200000,
  1904. .cpu_name = "e500",
  1905. .cpu_features = CPU_FTRS_E500,
  1906. .cpu_user_features = COMMON_USER_BOOKE |
  1907. PPC_FEATURE_HAS_SPE_COMP |
  1908. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1909. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1910. .icache_bsize = 32,
  1911. .dcache_bsize = 32,
  1912. .num_pmcs = 4,
  1913. .oprofile_cpu_type = "ppc/e500",
  1914. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1915. .cpu_setup = __setup_cpu_e500v1,
  1916. .machine_check = machine_check_e500,
  1917. .platform = "ppc8540",
  1918. },
  1919. { /* e500v2 */
  1920. .pvr_mask = 0xffff0000,
  1921. .pvr_value = 0x80210000,
  1922. .cpu_name = "e500v2",
  1923. .cpu_features = CPU_FTRS_E500_2,
  1924. .cpu_user_features = COMMON_USER_BOOKE |
  1925. PPC_FEATURE_HAS_SPE_COMP |
  1926. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1927. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1928. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  1929. .icache_bsize = 32,
  1930. .dcache_bsize = 32,
  1931. .num_pmcs = 4,
  1932. .oprofile_cpu_type = "ppc/e500",
  1933. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1934. .cpu_setup = __setup_cpu_e500v2,
  1935. .machine_check = machine_check_e500,
  1936. .platform = "ppc8548",
  1937. },
  1938. { /* e500mc */
  1939. .pvr_mask = 0xffff0000,
  1940. .pvr_value = 0x80230000,
  1941. .cpu_name = "e500mc",
  1942. .cpu_features = CPU_FTRS_E500MC,
  1943. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1944. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1945. MMU_FTR_USE_TLBILX,
  1946. .icache_bsize = 64,
  1947. .dcache_bsize = 64,
  1948. .num_pmcs = 4,
  1949. .oprofile_cpu_type = "ppc/e500mc",
  1950. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1951. .cpu_setup = __setup_cpu_e500mc,
  1952. .machine_check = machine_check_e500mc,
  1953. .platform = "ppce500mc",
  1954. },
  1955. #endif /* CONFIG_PPC32 */
  1956. { /* e5500 */
  1957. .pvr_mask = 0xffff0000,
  1958. .pvr_value = 0x80240000,
  1959. .cpu_name = "e5500",
  1960. .cpu_features = CPU_FTRS_E500MC,
  1961. .cpu_user_features = COMMON_USER_BOOKE,
  1962. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1963. MMU_FTR_USE_TLBILX,
  1964. .icache_bsize = 64,
  1965. .dcache_bsize = 64,
  1966. .num_pmcs = 4,
  1967. .oprofile_cpu_type = "ppc/e500mc",
  1968. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1969. .cpu_setup = __setup_cpu_e5500,
  1970. .cpu_restore = __restore_cpu_e5500,
  1971. .machine_check = machine_check_e500mc,
  1972. .platform = "ppce5500",
  1973. },
  1974. #ifdef CONFIG_PPC32
  1975. { /* default match */
  1976. .pvr_mask = 0x00000000,
  1977. .pvr_value = 0x00000000,
  1978. .cpu_name = "(generic E500 PPC)",
  1979. .cpu_features = CPU_FTRS_E500,
  1980. .cpu_user_features = COMMON_USER_BOOKE |
  1981. PPC_FEATURE_HAS_SPE_COMP |
  1982. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1983. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1984. .icache_bsize = 32,
  1985. .dcache_bsize = 32,
  1986. .machine_check = machine_check_e500,
  1987. .platform = "powerpc",
  1988. }
  1989. #endif /* CONFIG_PPC32 */
  1990. #endif /* CONFIG_E500 */
  1991. #ifdef CONFIG_PPC_BOOK3E_64
  1992. { /* This is a default entry to get going, to be replaced by
  1993. * a real one at some stage
  1994. */
  1995. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  1996. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  1997. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  1998. .pvr_mask = 0x00000000,
  1999. .pvr_value = 0x00000000,
  2000. .cpu_name = "Book3E",
  2001. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  2002. .cpu_user_features = COMMON_USER_PPC64,
  2003. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  2004. MMU_FTR_USE_TLBIVAX_BCAST |
  2005. MMU_FTR_LOCK_BCAST_INVAL,
  2006. .icache_bsize = 64,
  2007. .dcache_bsize = 64,
  2008. .num_pmcs = 0,
  2009. .machine_check = machine_check_generic,
  2010. .platform = "power6",
  2011. },
  2012. #endif
  2013. };
  2014. static struct cpu_spec the_cpu_spec;
  2015. static void __init setup_cpu_spec(unsigned long offset, struct cpu_spec *s)
  2016. {
  2017. struct cpu_spec *t = &the_cpu_spec;
  2018. struct cpu_spec old;
  2019. t = PTRRELOC(t);
  2020. old = *t;
  2021. /* Copy everything, then do fixups */
  2022. *t = *s;
  2023. /*
  2024. * If we are overriding a previous value derived from the real
  2025. * PVR with a new value obtained using a logical PVR value,
  2026. * don't modify the performance monitor fields.
  2027. */
  2028. if (old.num_pmcs && !s->num_pmcs) {
  2029. t->num_pmcs = old.num_pmcs;
  2030. t->pmc_type = old.pmc_type;
  2031. t->oprofile_type = old.oprofile_type;
  2032. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2033. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2034. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2035. /*
  2036. * If we have passed through this logic once before and
  2037. * have pulled the default case because the real PVR was
  2038. * not found inside cpu_specs[], then we are possibly
  2039. * running in compatibility mode. In that case, let the
  2040. * oprofiler know which set of compatibility counters to
  2041. * pull from by making sure the oprofile_cpu_type string
  2042. * is set to that of compatibility mode. If the
  2043. * oprofile_cpu_type already has a value, then we are
  2044. * possibly overriding a real PVR with a logical one,
  2045. * and, in that case, keep the current value for
  2046. * oprofile_cpu_type.
  2047. */
  2048. if (old.oprofile_cpu_type != NULL) {
  2049. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2050. t->oprofile_type = old.oprofile_type;
  2051. }
  2052. }
  2053. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2054. /*
  2055. * Set the base platform string once; assumes
  2056. * we're called with real pvr first.
  2057. */
  2058. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2059. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2060. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2061. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2062. * that processor. I will consolidate that at a later time, for now,
  2063. * just use #ifdef. We also don't need to PTRRELOC the function
  2064. * pointer on ppc64 and booke as we are running at 0 in real mode
  2065. * on ppc64 and reloc_offset is always 0 on booke.
  2066. */
  2067. if (s->cpu_setup) {
  2068. s->cpu_setup(offset, s);
  2069. }
  2070. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2071. }
  2072. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2073. {
  2074. struct cpu_spec *s = cpu_specs;
  2075. int i;
  2076. s = PTRRELOC(s);
  2077. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2078. if ((pvr & s->pvr_mask) == s->pvr_value) {
  2079. setup_cpu_spec(offset, s);
  2080. return s;
  2081. }
  2082. }
  2083. BUG();
  2084. return NULL;
  2085. }