traps.c 47 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834
  1. /*
  2. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  3. * Copyright 2007-2010 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version
  8. * 2 of the License, or (at your option) any later version.
  9. *
  10. * Modified by Cort Dougan (cort@cs.nmt.edu)
  11. * and Paul Mackerras (paulus@samba.org)
  12. */
  13. /*
  14. * This file handles the architecture-dependent parts of hardware exceptions
  15. */
  16. #include <linux/errno.h>
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/mm.h>
  20. #include <linux/stddef.h>
  21. #include <linux/unistd.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/user.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/init.h>
  26. #include <linux/module.h>
  27. #include <linux/prctl.h>
  28. #include <linux/delay.h>
  29. #include <linux/kprobes.h>
  30. #include <linux/kexec.h>
  31. #include <linux/backlight.h>
  32. #include <linux/bug.h>
  33. #include <linux/kdebug.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/ratelimit.h>
  36. #include <linux/context_tracking.h>
  37. #include <asm/emulated_ops.h>
  38. #include <asm/pgtable.h>
  39. #include <asm/uaccess.h>
  40. #include <asm/io.h>
  41. #include <asm/machdep.h>
  42. #include <asm/rtas.h>
  43. #include <asm/pmc.h>
  44. #ifdef CONFIG_PPC32
  45. #include <asm/reg.h>
  46. #endif
  47. #ifdef CONFIG_PMAC_BACKLIGHT
  48. #include <asm/backlight.h>
  49. #endif
  50. #ifdef CONFIG_PPC64
  51. #include <asm/firmware.h>
  52. #include <asm/processor.h>
  53. #include <asm/tm.h>
  54. #endif
  55. #include <asm/kexec.h>
  56. #include <asm/ppc-opcode.h>
  57. #include <asm/rio.h>
  58. #include <asm/fadump.h>
  59. #include <asm/switch_to.h>
  60. #include <asm/tm.h>
  61. #include <asm/debug.h>
  62. #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
  63. int (*__debugger)(struct pt_regs *regs) __read_mostly;
  64. int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
  65. int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
  66. int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
  67. int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
  68. int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
  69. int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
  70. EXPORT_SYMBOL(__debugger);
  71. EXPORT_SYMBOL(__debugger_ipi);
  72. EXPORT_SYMBOL(__debugger_bpt);
  73. EXPORT_SYMBOL(__debugger_sstep);
  74. EXPORT_SYMBOL(__debugger_iabr_match);
  75. EXPORT_SYMBOL(__debugger_break_match);
  76. EXPORT_SYMBOL(__debugger_fault_handler);
  77. #endif
  78. /* Transactional Memory trap debug */
  79. #ifdef TM_DEBUG_SW
  80. #define TM_DEBUG(x...) printk(KERN_INFO x)
  81. #else
  82. #define TM_DEBUG(x...) do { } while(0)
  83. #endif
  84. /*
  85. * Trap & Exception support
  86. */
  87. #ifdef CONFIG_PMAC_BACKLIGHT
  88. static void pmac_backlight_unblank(void)
  89. {
  90. mutex_lock(&pmac_backlight_mutex);
  91. if (pmac_backlight) {
  92. struct backlight_properties *props;
  93. props = &pmac_backlight->props;
  94. props->brightness = props->max_brightness;
  95. props->power = FB_BLANK_UNBLANK;
  96. backlight_update_status(pmac_backlight);
  97. }
  98. mutex_unlock(&pmac_backlight_mutex);
  99. }
  100. #else
  101. static inline void pmac_backlight_unblank(void) { }
  102. #endif
  103. static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
  104. static int die_owner = -1;
  105. static unsigned int die_nest_count;
  106. static int die_counter;
  107. static unsigned __kprobes long oops_begin(struct pt_regs *regs)
  108. {
  109. int cpu;
  110. unsigned long flags;
  111. if (debugger(regs))
  112. return 1;
  113. oops_enter();
  114. /* racy, but better than risking deadlock. */
  115. raw_local_irq_save(flags);
  116. cpu = smp_processor_id();
  117. if (!arch_spin_trylock(&die_lock)) {
  118. if (cpu == die_owner)
  119. /* nested oops. should stop eventually */;
  120. else
  121. arch_spin_lock(&die_lock);
  122. }
  123. die_nest_count++;
  124. die_owner = cpu;
  125. console_verbose();
  126. bust_spinlocks(1);
  127. if (machine_is(powermac))
  128. pmac_backlight_unblank();
  129. return flags;
  130. }
  131. static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
  132. int signr)
  133. {
  134. bust_spinlocks(0);
  135. die_owner = -1;
  136. add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
  137. die_nest_count--;
  138. oops_exit();
  139. printk("\n");
  140. if (!die_nest_count)
  141. /* Nest count reaches zero, release the lock. */
  142. arch_spin_unlock(&die_lock);
  143. raw_local_irq_restore(flags);
  144. crash_fadump(regs, "die oops");
  145. /*
  146. * A system reset (0x100) is a request to dump, so we always send
  147. * it through the crashdump code.
  148. */
  149. if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
  150. crash_kexec(regs);
  151. /*
  152. * We aren't the primary crash CPU. We need to send it
  153. * to a holding pattern to avoid it ending up in the panic
  154. * code.
  155. */
  156. crash_kexec_secondary(regs);
  157. }
  158. if (!signr)
  159. return;
  160. /*
  161. * While our oops output is serialised by a spinlock, output
  162. * from panic() called below can race and corrupt it. If we
  163. * know we are going to panic, delay for 1 second so we have a
  164. * chance to get clean backtraces from all CPUs that are oopsing.
  165. */
  166. if (in_interrupt() || panic_on_oops || !current->pid ||
  167. is_global_init(current)) {
  168. mdelay(MSEC_PER_SEC);
  169. }
  170. if (in_interrupt())
  171. panic("Fatal exception in interrupt");
  172. if (panic_on_oops)
  173. panic("Fatal exception");
  174. do_exit(signr);
  175. }
  176. static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
  177. {
  178. printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  179. #ifdef CONFIG_PREEMPT
  180. printk("PREEMPT ");
  181. #endif
  182. #ifdef CONFIG_SMP
  183. printk("SMP NR_CPUS=%d ", NR_CPUS);
  184. #endif
  185. #ifdef CONFIG_DEBUG_PAGEALLOC
  186. printk("DEBUG_PAGEALLOC ");
  187. #endif
  188. #ifdef CONFIG_NUMA
  189. printk("NUMA ");
  190. #endif
  191. printk("%s\n", ppc_md.name ? ppc_md.name : "");
  192. if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
  193. return 1;
  194. print_modules();
  195. show_regs(regs);
  196. return 0;
  197. }
  198. void die(const char *str, struct pt_regs *regs, long err)
  199. {
  200. unsigned long flags = oops_begin(regs);
  201. if (__die(str, regs, err))
  202. err = 0;
  203. oops_end(flags, regs, err);
  204. }
  205. void user_single_step_siginfo(struct task_struct *tsk,
  206. struct pt_regs *regs, siginfo_t *info)
  207. {
  208. memset(info, 0, sizeof(*info));
  209. info->si_signo = SIGTRAP;
  210. info->si_code = TRAP_TRACE;
  211. info->si_addr = (void __user *)regs->nip;
  212. }
  213. void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
  214. {
  215. siginfo_t info;
  216. const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
  217. "at %08lx nip %08lx lr %08lx code %x\n";
  218. const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
  219. "at %016lx nip %016lx lr %016lx code %x\n";
  220. if (!user_mode(regs)) {
  221. die("Exception in kernel mode", regs, signr);
  222. return;
  223. }
  224. if (show_unhandled_signals && unhandled_signal(current, signr)) {
  225. printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
  226. current->comm, current->pid, signr,
  227. addr, regs->nip, regs->link, code);
  228. }
  229. if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
  230. local_irq_enable();
  231. current->thread.trap_nr = code;
  232. memset(&info, 0, sizeof(info));
  233. info.si_signo = signr;
  234. info.si_code = code;
  235. info.si_addr = (void __user *) addr;
  236. force_sig_info(signr, &info, current);
  237. }
  238. #ifdef CONFIG_PPC64
  239. void system_reset_exception(struct pt_regs *regs)
  240. {
  241. /* See if any machine dependent calls */
  242. if (ppc_md.system_reset_exception) {
  243. if (ppc_md.system_reset_exception(regs))
  244. return;
  245. }
  246. die("System Reset", regs, SIGABRT);
  247. /* Must die if the interrupt is not recoverable */
  248. if (!(regs->msr & MSR_RI))
  249. panic("Unrecoverable System Reset");
  250. /* What should we do here? We could issue a shutdown or hard reset. */
  251. }
  252. #endif
  253. /*
  254. * I/O accesses can cause machine checks on powermacs.
  255. * Check if the NIP corresponds to the address of a sync
  256. * instruction for which there is an entry in the exception
  257. * table.
  258. * Note that the 601 only takes a machine check on TEA
  259. * (transfer error ack) signal assertion, and does not
  260. * set any of the top 16 bits of SRR1.
  261. * -- paulus.
  262. */
  263. static inline int check_io_access(struct pt_regs *regs)
  264. {
  265. #ifdef CONFIG_PPC32
  266. unsigned long msr = regs->msr;
  267. const struct exception_table_entry *entry;
  268. unsigned int *nip = (unsigned int *)regs->nip;
  269. if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
  270. && (entry = search_exception_tables(regs->nip)) != NULL) {
  271. /*
  272. * Check that it's a sync instruction, or somewhere
  273. * in the twi; isync; nop sequence that inb/inw/inl uses.
  274. * As the address is in the exception table
  275. * we should be able to read the instr there.
  276. * For the debug message, we look at the preceding
  277. * load or store.
  278. */
  279. if (*nip == 0x60000000) /* nop */
  280. nip -= 2;
  281. else if (*nip == 0x4c00012c) /* isync */
  282. --nip;
  283. if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
  284. /* sync or twi */
  285. unsigned int rb;
  286. --nip;
  287. rb = (*nip >> 11) & 0x1f;
  288. printk(KERN_DEBUG "%s bad port %lx at %p\n",
  289. (*nip & 0x100)? "OUT to": "IN from",
  290. regs->gpr[rb] - _IO_BASE, nip);
  291. regs->msr |= MSR_RI;
  292. regs->nip = entry->fixup;
  293. return 1;
  294. }
  295. }
  296. #endif /* CONFIG_PPC32 */
  297. return 0;
  298. }
  299. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  300. /* On 4xx, the reason for the machine check or program exception
  301. is in the ESR. */
  302. #define get_reason(regs) ((regs)->dsisr)
  303. #ifndef CONFIG_FSL_BOOKE
  304. #define get_mc_reason(regs) ((regs)->dsisr)
  305. #else
  306. #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
  307. #endif
  308. #define REASON_FP ESR_FP
  309. #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
  310. #define REASON_PRIVILEGED ESR_PPR
  311. #define REASON_TRAP ESR_PTR
  312. /* single-step stuff */
  313. #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
  314. #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
  315. #else
  316. /* On non-4xx, the reason for the machine check or program
  317. exception is in the MSR. */
  318. #define get_reason(regs) ((regs)->msr)
  319. #define get_mc_reason(regs) ((regs)->msr)
  320. #define REASON_TM 0x200000
  321. #define REASON_FP 0x100000
  322. #define REASON_ILLEGAL 0x80000
  323. #define REASON_PRIVILEGED 0x40000
  324. #define REASON_TRAP 0x20000
  325. #define single_stepping(regs) ((regs)->msr & MSR_SE)
  326. #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
  327. #endif
  328. #if defined(CONFIG_4xx)
  329. int machine_check_4xx(struct pt_regs *regs)
  330. {
  331. unsigned long reason = get_mc_reason(regs);
  332. if (reason & ESR_IMCP) {
  333. printk("Instruction");
  334. mtspr(SPRN_ESR, reason & ~ESR_IMCP);
  335. } else
  336. printk("Data");
  337. printk(" machine check in kernel mode.\n");
  338. return 0;
  339. }
  340. int machine_check_440A(struct pt_regs *regs)
  341. {
  342. unsigned long reason = get_mc_reason(regs);
  343. printk("Machine check in kernel mode.\n");
  344. if (reason & ESR_IMCP){
  345. printk("Instruction Synchronous Machine Check exception\n");
  346. mtspr(SPRN_ESR, reason & ~ESR_IMCP);
  347. }
  348. else {
  349. u32 mcsr = mfspr(SPRN_MCSR);
  350. if (mcsr & MCSR_IB)
  351. printk("Instruction Read PLB Error\n");
  352. if (mcsr & MCSR_DRB)
  353. printk("Data Read PLB Error\n");
  354. if (mcsr & MCSR_DWB)
  355. printk("Data Write PLB Error\n");
  356. if (mcsr & MCSR_TLBP)
  357. printk("TLB Parity Error\n");
  358. if (mcsr & MCSR_ICP){
  359. flush_instruction_cache();
  360. printk("I-Cache Parity Error\n");
  361. }
  362. if (mcsr & MCSR_DCSP)
  363. printk("D-Cache Search Parity Error\n");
  364. if (mcsr & MCSR_DCFP)
  365. printk("D-Cache Flush Parity Error\n");
  366. if (mcsr & MCSR_IMPE)
  367. printk("Machine Check exception is imprecise\n");
  368. /* Clear MCSR */
  369. mtspr(SPRN_MCSR, mcsr);
  370. }
  371. return 0;
  372. }
  373. int machine_check_47x(struct pt_regs *regs)
  374. {
  375. unsigned long reason = get_mc_reason(regs);
  376. u32 mcsr;
  377. printk(KERN_ERR "Machine check in kernel mode.\n");
  378. if (reason & ESR_IMCP) {
  379. printk(KERN_ERR
  380. "Instruction Synchronous Machine Check exception\n");
  381. mtspr(SPRN_ESR, reason & ~ESR_IMCP);
  382. return 0;
  383. }
  384. mcsr = mfspr(SPRN_MCSR);
  385. if (mcsr & MCSR_IB)
  386. printk(KERN_ERR "Instruction Read PLB Error\n");
  387. if (mcsr & MCSR_DRB)
  388. printk(KERN_ERR "Data Read PLB Error\n");
  389. if (mcsr & MCSR_DWB)
  390. printk(KERN_ERR "Data Write PLB Error\n");
  391. if (mcsr & MCSR_TLBP)
  392. printk(KERN_ERR "TLB Parity Error\n");
  393. if (mcsr & MCSR_ICP) {
  394. flush_instruction_cache();
  395. printk(KERN_ERR "I-Cache Parity Error\n");
  396. }
  397. if (mcsr & MCSR_DCSP)
  398. printk(KERN_ERR "D-Cache Search Parity Error\n");
  399. if (mcsr & PPC47x_MCSR_GPR)
  400. printk(KERN_ERR "GPR Parity Error\n");
  401. if (mcsr & PPC47x_MCSR_FPR)
  402. printk(KERN_ERR "FPR Parity Error\n");
  403. if (mcsr & PPC47x_MCSR_IPR)
  404. printk(KERN_ERR "Machine Check exception is imprecise\n");
  405. /* Clear MCSR */
  406. mtspr(SPRN_MCSR, mcsr);
  407. return 0;
  408. }
  409. #elif defined(CONFIG_E500)
  410. int machine_check_e500mc(struct pt_regs *regs)
  411. {
  412. unsigned long mcsr = mfspr(SPRN_MCSR);
  413. unsigned long reason = mcsr;
  414. int recoverable = 1;
  415. if (reason & MCSR_LD) {
  416. recoverable = fsl_rio_mcheck_exception(regs);
  417. if (recoverable == 1)
  418. goto silent_out;
  419. }
  420. printk("Machine check in kernel mode.\n");
  421. printk("Caused by (from MCSR=%lx): ", reason);
  422. if (reason & MCSR_MCP)
  423. printk("Machine Check Signal\n");
  424. if (reason & MCSR_ICPERR) {
  425. printk("Instruction Cache Parity Error\n");
  426. /*
  427. * This is recoverable by invalidating the i-cache.
  428. */
  429. mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
  430. while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
  431. ;
  432. /*
  433. * This will generally be accompanied by an instruction
  434. * fetch error report -- only treat MCSR_IF as fatal
  435. * if it wasn't due to an L1 parity error.
  436. */
  437. reason &= ~MCSR_IF;
  438. }
  439. if (reason & MCSR_DCPERR_MC) {
  440. printk("Data Cache Parity Error\n");
  441. /*
  442. * In write shadow mode we auto-recover from the error, but it
  443. * may still get logged and cause a machine check. We should
  444. * only treat the non-write shadow case as non-recoverable.
  445. */
  446. if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
  447. recoverable = 0;
  448. }
  449. if (reason & MCSR_L2MMU_MHIT) {
  450. printk("Hit on multiple TLB entries\n");
  451. recoverable = 0;
  452. }
  453. if (reason & MCSR_NMI)
  454. printk("Non-maskable interrupt\n");
  455. if (reason & MCSR_IF) {
  456. printk("Instruction Fetch Error Report\n");
  457. recoverable = 0;
  458. }
  459. if (reason & MCSR_LD) {
  460. printk("Load Error Report\n");
  461. recoverable = 0;
  462. }
  463. if (reason & MCSR_ST) {
  464. printk("Store Error Report\n");
  465. recoverable = 0;
  466. }
  467. if (reason & MCSR_LDG) {
  468. printk("Guarded Load Error Report\n");
  469. recoverable = 0;
  470. }
  471. if (reason & MCSR_TLBSYNC)
  472. printk("Simultaneous tlbsync operations\n");
  473. if (reason & MCSR_BSL2_ERR) {
  474. printk("Level 2 Cache Error\n");
  475. recoverable = 0;
  476. }
  477. if (reason & MCSR_MAV) {
  478. u64 addr;
  479. addr = mfspr(SPRN_MCAR);
  480. addr |= (u64)mfspr(SPRN_MCARU) << 32;
  481. printk("Machine Check %s Address: %#llx\n",
  482. reason & MCSR_MEA ? "Effective" : "Physical", addr);
  483. }
  484. silent_out:
  485. mtspr(SPRN_MCSR, mcsr);
  486. return mfspr(SPRN_MCSR) == 0 && recoverable;
  487. }
  488. int machine_check_e500(struct pt_regs *regs)
  489. {
  490. unsigned long reason = get_mc_reason(regs);
  491. if (reason & MCSR_BUS_RBERR) {
  492. if (fsl_rio_mcheck_exception(regs))
  493. return 1;
  494. }
  495. printk("Machine check in kernel mode.\n");
  496. printk("Caused by (from MCSR=%lx): ", reason);
  497. if (reason & MCSR_MCP)
  498. printk("Machine Check Signal\n");
  499. if (reason & MCSR_ICPERR)
  500. printk("Instruction Cache Parity Error\n");
  501. if (reason & MCSR_DCP_PERR)
  502. printk("Data Cache Push Parity Error\n");
  503. if (reason & MCSR_DCPERR)
  504. printk("Data Cache Parity Error\n");
  505. if (reason & MCSR_BUS_IAERR)
  506. printk("Bus - Instruction Address Error\n");
  507. if (reason & MCSR_BUS_RAERR)
  508. printk("Bus - Read Address Error\n");
  509. if (reason & MCSR_BUS_WAERR)
  510. printk("Bus - Write Address Error\n");
  511. if (reason & MCSR_BUS_IBERR)
  512. printk("Bus - Instruction Data Error\n");
  513. if (reason & MCSR_BUS_RBERR)
  514. printk("Bus - Read Data Bus Error\n");
  515. if (reason & MCSR_BUS_WBERR)
  516. printk("Bus - Read Data Bus Error\n");
  517. if (reason & MCSR_BUS_IPERR)
  518. printk("Bus - Instruction Parity Error\n");
  519. if (reason & MCSR_BUS_RPERR)
  520. printk("Bus - Read Parity Error\n");
  521. return 0;
  522. }
  523. int machine_check_generic(struct pt_regs *regs)
  524. {
  525. return 0;
  526. }
  527. #elif defined(CONFIG_E200)
  528. int machine_check_e200(struct pt_regs *regs)
  529. {
  530. unsigned long reason = get_mc_reason(regs);
  531. printk("Machine check in kernel mode.\n");
  532. printk("Caused by (from MCSR=%lx): ", reason);
  533. if (reason & MCSR_MCP)
  534. printk("Machine Check Signal\n");
  535. if (reason & MCSR_CP_PERR)
  536. printk("Cache Push Parity Error\n");
  537. if (reason & MCSR_CPERR)
  538. printk("Cache Parity Error\n");
  539. if (reason & MCSR_EXCP_ERR)
  540. printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
  541. if (reason & MCSR_BUS_IRERR)
  542. printk("Bus - Read Bus Error on instruction fetch\n");
  543. if (reason & MCSR_BUS_DRERR)
  544. printk("Bus - Read Bus Error on data load\n");
  545. if (reason & MCSR_BUS_WRERR)
  546. printk("Bus - Write Bus Error on buffered store or cache line push\n");
  547. return 0;
  548. }
  549. #else
  550. int machine_check_generic(struct pt_regs *regs)
  551. {
  552. unsigned long reason = get_mc_reason(regs);
  553. printk("Machine check in kernel mode.\n");
  554. printk("Caused by (from SRR1=%lx): ", reason);
  555. switch (reason & 0x601F0000) {
  556. case 0x80000:
  557. printk("Machine check signal\n");
  558. break;
  559. case 0: /* for 601 */
  560. case 0x40000:
  561. case 0x140000: /* 7450 MSS error and TEA */
  562. printk("Transfer error ack signal\n");
  563. break;
  564. case 0x20000:
  565. printk("Data parity error signal\n");
  566. break;
  567. case 0x10000:
  568. printk("Address parity error signal\n");
  569. break;
  570. case 0x20000000:
  571. printk("L1 Data Cache error\n");
  572. break;
  573. case 0x40000000:
  574. printk("L1 Instruction Cache error\n");
  575. break;
  576. case 0x00100000:
  577. printk("L2 data cache parity error\n");
  578. break;
  579. default:
  580. printk("Unknown values in msr\n");
  581. }
  582. return 0;
  583. }
  584. #endif /* everything else */
  585. void machine_check_exception(struct pt_regs *regs)
  586. {
  587. enum ctx_state prev_state = exception_enter();
  588. int recover = 0;
  589. __get_cpu_var(irq_stat).mce_exceptions++;
  590. /* See if any machine dependent calls. In theory, we would want
  591. * to call the CPU first, and call the ppc_md. one if the CPU
  592. * one returns a positive number. However there is existing code
  593. * that assumes the board gets a first chance, so let's keep it
  594. * that way for now and fix things later. --BenH.
  595. */
  596. if (ppc_md.machine_check_exception)
  597. recover = ppc_md.machine_check_exception(regs);
  598. else if (cur_cpu_spec->machine_check)
  599. recover = cur_cpu_spec->machine_check(regs);
  600. if (recover > 0)
  601. goto bail;
  602. #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
  603. /* the qspan pci read routines can cause machine checks -- Cort
  604. *
  605. * yuck !!! that totally needs to go away ! There are better ways
  606. * to deal with that than having a wart in the mcheck handler.
  607. * -- BenH
  608. */
  609. bad_page_fault(regs, regs->dar, SIGBUS);
  610. goto bail;
  611. #endif
  612. if (debugger_fault_handler(regs))
  613. goto bail;
  614. if (check_io_access(regs))
  615. goto bail;
  616. die("Machine check", regs, SIGBUS);
  617. /* Must die if the interrupt is not recoverable */
  618. if (!(regs->msr & MSR_RI))
  619. panic("Unrecoverable Machine check");
  620. bail:
  621. exception_exit(prev_state);
  622. }
  623. void SMIException(struct pt_regs *regs)
  624. {
  625. die("System Management Interrupt", regs, SIGABRT);
  626. }
  627. void unknown_exception(struct pt_regs *regs)
  628. {
  629. enum ctx_state prev_state = exception_enter();
  630. printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
  631. regs->nip, regs->msr, regs->trap);
  632. _exception(SIGTRAP, regs, 0, 0);
  633. exception_exit(prev_state);
  634. }
  635. void instruction_breakpoint_exception(struct pt_regs *regs)
  636. {
  637. enum ctx_state prev_state = exception_enter();
  638. if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
  639. 5, SIGTRAP) == NOTIFY_STOP)
  640. goto bail;
  641. if (debugger_iabr_match(regs))
  642. goto bail;
  643. _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
  644. bail:
  645. exception_exit(prev_state);
  646. }
  647. void RunModeException(struct pt_regs *regs)
  648. {
  649. _exception(SIGTRAP, regs, 0, 0);
  650. }
  651. void __kprobes single_step_exception(struct pt_regs *regs)
  652. {
  653. enum ctx_state prev_state = exception_enter();
  654. clear_single_step(regs);
  655. if (notify_die(DIE_SSTEP, "single_step", regs, 5,
  656. 5, SIGTRAP) == NOTIFY_STOP)
  657. goto bail;
  658. if (debugger_sstep(regs))
  659. goto bail;
  660. _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
  661. bail:
  662. exception_exit(prev_state);
  663. }
  664. /*
  665. * After we have successfully emulated an instruction, we have to
  666. * check if the instruction was being single-stepped, and if so,
  667. * pretend we got a single-step exception. This was pointed out
  668. * by Kumar Gala. -- paulus
  669. */
  670. static void emulate_single_step(struct pt_regs *regs)
  671. {
  672. if (single_stepping(regs))
  673. single_step_exception(regs);
  674. }
  675. static inline int __parse_fpscr(unsigned long fpscr)
  676. {
  677. int ret = 0;
  678. /* Invalid operation */
  679. if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
  680. ret = FPE_FLTINV;
  681. /* Overflow */
  682. else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
  683. ret = FPE_FLTOVF;
  684. /* Underflow */
  685. else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
  686. ret = FPE_FLTUND;
  687. /* Divide by zero */
  688. else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
  689. ret = FPE_FLTDIV;
  690. /* Inexact result */
  691. else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
  692. ret = FPE_FLTRES;
  693. return ret;
  694. }
  695. static void parse_fpe(struct pt_regs *regs)
  696. {
  697. int code = 0;
  698. flush_fp_to_thread(current);
  699. code = __parse_fpscr(current->thread.fpscr.val);
  700. _exception(SIGFPE, regs, code, regs->nip);
  701. }
  702. /*
  703. * Illegal instruction emulation support. Originally written to
  704. * provide the PVR to user applications using the mfspr rd, PVR.
  705. * Return non-zero if we can't emulate, or -EFAULT if the associated
  706. * memory access caused an access fault. Return zero on success.
  707. *
  708. * There are a couple of ways to do this, either "decode" the instruction
  709. * or directly match lots of bits. In this case, matching lots of
  710. * bits is faster and easier.
  711. *
  712. */
  713. static int emulate_string_inst(struct pt_regs *regs, u32 instword)
  714. {
  715. u8 rT = (instword >> 21) & 0x1f;
  716. u8 rA = (instword >> 16) & 0x1f;
  717. u8 NB_RB = (instword >> 11) & 0x1f;
  718. u32 num_bytes;
  719. unsigned long EA;
  720. int pos = 0;
  721. /* Early out if we are an invalid form of lswx */
  722. if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
  723. if ((rT == rA) || (rT == NB_RB))
  724. return -EINVAL;
  725. EA = (rA == 0) ? 0 : regs->gpr[rA];
  726. switch (instword & PPC_INST_STRING_MASK) {
  727. case PPC_INST_LSWX:
  728. case PPC_INST_STSWX:
  729. EA += NB_RB;
  730. num_bytes = regs->xer & 0x7f;
  731. break;
  732. case PPC_INST_LSWI:
  733. case PPC_INST_STSWI:
  734. num_bytes = (NB_RB == 0) ? 32 : NB_RB;
  735. break;
  736. default:
  737. return -EINVAL;
  738. }
  739. while (num_bytes != 0)
  740. {
  741. u8 val;
  742. u32 shift = 8 * (3 - (pos & 0x3));
  743. switch ((instword & PPC_INST_STRING_MASK)) {
  744. case PPC_INST_LSWX:
  745. case PPC_INST_LSWI:
  746. if (get_user(val, (u8 __user *)EA))
  747. return -EFAULT;
  748. /* first time updating this reg,
  749. * zero it out */
  750. if (pos == 0)
  751. regs->gpr[rT] = 0;
  752. regs->gpr[rT] |= val << shift;
  753. break;
  754. case PPC_INST_STSWI:
  755. case PPC_INST_STSWX:
  756. val = regs->gpr[rT] >> shift;
  757. if (put_user(val, (u8 __user *)EA))
  758. return -EFAULT;
  759. break;
  760. }
  761. /* move EA to next address */
  762. EA += 1;
  763. num_bytes--;
  764. /* manage our position within the register */
  765. if (++pos == 4) {
  766. pos = 0;
  767. if (++rT == 32)
  768. rT = 0;
  769. }
  770. }
  771. return 0;
  772. }
  773. static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
  774. {
  775. u32 ra,rs;
  776. unsigned long tmp;
  777. ra = (instword >> 16) & 0x1f;
  778. rs = (instword >> 21) & 0x1f;
  779. tmp = regs->gpr[rs];
  780. tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
  781. tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
  782. tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
  783. regs->gpr[ra] = tmp;
  784. return 0;
  785. }
  786. static int emulate_isel(struct pt_regs *regs, u32 instword)
  787. {
  788. u8 rT = (instword >> 21) & 0x1f;
  789. u8 rA = (instword >> 16) & 0x1f;
  790. u8 rB = (instword >> 11) & 0x1f;
  791. u8 BC = (instword >> 6) & 0x1f;
  792. u8 bit;
  793. unsigned long tmp;
  794. tmp = (rA == 0) ? 0 : regs->gpr[rA];
  795. bit = (regs->ccr >> (31 - BC)) & 0x1;
  796. regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
  797. return 0;
  798. }
  799. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  800. static inline bool tm_abort_check(struct pt_regs *regs, int cause)
  801. {
  802. /* If we're emulating a load/store in an active transaction, we cannot
  803. * emulate it as the kernel operates in transaction suspended context.
  804. * We need to abort the transaction. This creates a persistent TM
  805. * abort so tell the user what caused it with a new code.
  806. */
  807. if (MSR_TM_TRANSACTIONAL(regs->msr)) {
  808. tm_enable();
  809. tm_abort(cause);
  810. return true;
  811. }
  812. return false;
  813. }
  814. #else
  815. static inline bool tm_abort_check(struct pt_regs *regs, int reason)
  816. {
  817. return false;
  818. }
  819. #endif
  820. static int emulate_instruction(struct pt_regs *regs)
  821. {
  822. u32 instword;
  823. u32 rd;
  824. if (!user_mode(regs) || (regs->msr & MSR_LE))
  825. return -EINVAL;
  826. CHECK_FULL_REGS(regs);
  827. if (get_user(instword, (u32 __user *)(regs->nip)))
  828. return -EFAULT;
  829. /* Emulate the mfspr rD, PVR. */
  830. if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
  831. PPC_WARN_EMULATED(mfpvr, regs);
  832. rd = (instword >> 21) & 0x1f;
  833. regs->gpr[rd] = mfspr(SPRN_PVR);
  834. return 0;
  835. }
  836. /* Emulating the dcba insn is just a no-op. */
  837. if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
  838. PPC_WARN_EMULATED(dcba, regs);
  839. return 0;
  840. }
  841. /* Emulate the mcrxr insn. */
  842. if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
  843. int shift = (instword >> 21) & 0x1c;
  844. unsigned long msk = 0xf0000000UL >> shift;
  845. PPC_WARN_EMULATED(mcrxr, regs);
  846. regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
  847. regs->xer &= ~0xf0000000UL;
  848. return 0;
  849. }
  850. /* Emulate load/store string insn. */
  851. if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
  852. if (tm_abort_check(regs,
  853. TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
  854. return -EINVAL;
  855. PPC_WARN_EMULATED(string, regs);
  856. return emulate_string_inst(regs, instword);
  857. }
  858. /* Emulate the popcntb (Population Count Bytes) instruction. */
  859. if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
  860. PPC_WARN_EMULATED(popcntb, regs);
  861. return emulate_popcntb_inst(regs, instword);
  862. }
  863. /* Emulate isel (Integer Select) instruction */
  864. if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
  865. PPC_WARN_EMULATED(isel, regs);
  866. return emulate_isel(regs, instword);
  867. }
  868. #ifdef CONFIG_PPC64
  869. /* Emulate the mfspr rD, DSCR. */
  870. if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
  871. PPC_INST_MFSPR_DSCR_USER) ||
  872. ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
  873. PPC_INST_MFSPR_DSCR)) &&
  874. cpu_has_feature(CPU_FTR_DSCR)) {
  875. PPC_WARN_EMULATED(mfdscr, regs);
  876. rd = (instword >> 21) & 0x1f;
  877. regs->gpr[rd] = mfspr(SPRN_DSCR);
  878. return 0;
  879. }
  880. /* Emulate the mtspr DSCR, rD. */
  881. if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
  882. PPC_INST_MTSPR_DSCR_USER) ||
  883. ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
  884. PPC_INST_MTSPR_DSCR)) &&
  885. cpu_has_feature(CPU_FTR_DSCR)) {
  886. PPC_WARN_EMULATED(mtdscr, regs);
  887. rd = (instword >> 21) & 0x1f;
  888. current->thread.dscr = regs->gpr[rd];
  889. current->thread.dscr_inherit = 1;
  890. mtspr(SPRN_DSCR, current->thread.dscr);
  891. return 0;
  892. }
  893. #endif
  894. return -EINVAL;
  895. }
  896. int is_valid_bugaddr(unsigned long addr)
  897. {
  898. return is_kernel_addr(addr);
  899. }
  900. void __kprobes program_check_exception(struct pt_regs *regs)
  901. {
  902. enum ctx_state prev_state = exception_enter();
  903. unsigned int reason = get_reason(regs);
  904. extern int do_mathemu(struct pt_regs *regs);
  905. /* We can now get here via a FP Unavailable exception if the core
  906. * has no FPU, in that case the reason flags will be 0 */
  907. if (reason & REASON_FP) {
  908. /* IEEE FP exception */
  909. parse_fpe(regs);
  910. goto bail;
  911. }
  912. if (reason & REASON_TRAP) {
  913. /* Debugger is first in line to stop recursive faults in
  914. * rcu_lock, notify_die, or atomic_notifier_call_chain */
  915. if (debugger_bpt(regs))
  916. goto bail;
  917. /* trap exception */
  918. if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
  919. == NOTIFY_STOP)
  920. goto bail;
  921. if (!(regs->msr & MSR_PR) && /* not user-mode */
  922. report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
  923. regs->nip += 4;
  924. goto bail;
  925. }
  926. _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
  927. goto bail;
  928. }
  929. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  930. if (reason & REASON_TM) {
  931. /* This is a TM "Bad Thing Exception" program check.
  932. * This occurs when:
  933. * - An rfid/hrfid/mtmsrd attempts to cause an illegal
  934. * transition in TM states.
  935. * - A trechkpt is attempted when transactional.
  936. * - A treclaim is attempted when non transactional.
  937. * - A tend is illegally attempted.
  938. * - writing a TM SPR when transactional.
  939. */
  940. if (!user_mode(regs) &&
  941. report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
  942. regs->nip += 4;
  943. goto bail;
  944. }
  945. /* If usermode caused this, it's done something illegal and
  946. * gets a SIGILL slap on the wrist. We call it an illegal
  947. * operand to distinguish from the instruction just being bad
  948. * (e.g. executing a 'tend' on a CPU without TM!); it's an
  949. * illegal /placement/ of a valid instruction.
  950. */
  951. if (user_mode(regs)) {
  952. _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
  953. goto bail;
  954. } else {
  955. printk(KERN_EMERG "Unexpected TM Bad Thing exception "
  956. "at %lx (msr 0x%x)\n", regs->nip, reason);
  957. die("Unrecoverable exception", regs, SIGABRT);
  958. }
  959. }
  960. #endif
  961. /* We restore the interrupt state now */
  962. if (!arch_irq_disabled_regs(regs))
  963. local_irq_enable();
  964. #ifdef CONFIG_MATH_EMULATION
  965. /* (reason & REASON_ILLEGAL) would be the obvious thing here,
  966. * but there seems to be a hardware bug on the 405GP (RevD)
  967. * that means ESR is sometimes set incorrectly - either to
  968. * ESR_DST (!?) or 0. In the process of chasing this with the
  969. * hardware people - not sure if it can happen on any illegal
  970. * instruction or only on FP instructions, whether there is a
  971. * pattern to occurrences etc. -dgibson 31/Mar/2003
  972. */
  973. /*
  974. * If we support a HW FPU, we need to ensure the FP state
  975. * if flushed into the thread_struct before attempting
  976. * emulation
  977. */
  978. #ifdef CONFIG_PPC_FPU
  979. flush_fp_to_thread(current);
  980. #endif
  981. switch (do_mathemu(regs)) {
  982. case 0:
  983. emulate_single_step(regs);
  984. goto bail;
  985. case 1: {
  986. int code = 0;
  987. code = __parse_fpscr(current->thread.fpscr.val);
  988. _exception(SIGFPE, regs, code, regs->nip);
  989. goto bail;
  990. }
  991. case -EFAULT:
  992. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  993. goto bail;
  994. }
  995. /* fall through on any other errors */
  996. #endif /* CONFIG_MATH_EMULATION */
  997. /* Try to emulate it if we should. */
  998. if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
  999. switch (emulate_instruction(regs)) {
  1000. case 0:
  1001. regs->nip += 4;
  1002. emulate_single_step(regs);
  1003. goto bail;
  1004. case -EFAULT:
  1005. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  1006. goto bail;
  1007. }
  1008. }
  1009. if (reason & REASON_PRIVILEGED)
  1010. _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
  1011. else
  1012. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1013. bail:
  1014. exception_exit(prev_state);
  1015. }
  1016. void alignment_exception(struct pt_regs *regs)
  1017. {
  1018. enum ctx_state prev_state = exception_enter();
  1019. int sig, code, fixed = 0;
  1020. /* We restore the interrupt state now */
  1021. if (!arch_irq_disabled_regs(regs))
  1022. local_irq_enable();
  1023. if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
  1024. goto bail;
  1025. /* we don't implement logging of alignment exceptions */
  1026. if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
  1027. fixed = fix_alignment(regs);
  1028. if (fixed == 1) {
  1029. regs->nip += 4; /* skip over emulated instruction */
  1030. emulate_single_step(regs);
  1031. goto bail;
  1032. }
  1033. /* Operand address was bad */
  1034. if (fixed == -EFAULT) {
  1035. sig = SIGSEGV;
  1036. code = SEGV_ACCERR;
  1037. } else {
  1038. sig = SIGBUS;
  1039. code = BUS_ADRALN;
  1040. }
  1041. if (user_mode(regs))
  1042. _exception(sig, regs, code, regs->dar);
  1043. else
  1044. bad_page_fault(regs, regs->dar, sig);
  1045. bail:
  1046. exception_exit(prev_state);
  1047. }
  1048. void StackOverflow(struct pt_regs *regs)
  1049. {
  1050. printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
  1051. current, regs->gpr[1]);
  1052. debugger(regs);
  1053. show_regs(regs);
  1054. panic("kernel stack overflow");
  1055. }
  1056. void nonrecoverable_exception(struct pt_regs *regs)
  1057. {
  1058. printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
  1059. regs->nip, regs->msr);
  1060. debugger(regs);
  1061. die("nonrecoverable exception", regs, SIGKILL);
  1062. }
  1063. void trace_syscall(struct pt_regs *regs)
  1064. {
  1065. printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
  1066. current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
  1067. regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
  1068. }
  1069. void kernel_fp_unavailable_exception(struct pt_regs *regs)
  1070. {
  1071. enum ctx_state prev_state = exception_enter();
  1072. printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
  1073. "%lx at %lx\n", regs->trap, regs->nip);
  1074. die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
  1075. exception_exit(prev_state);
  1076. }
  1077. void altivec_unavailable_exception(struct pt_regs *regs)
  1078. {
  1079. enum ctx_state prev_state = exception_enter();
  1080. if (user_mode(regs)) {
  1081. /* A user program has executed an altivec instruction,
  1082. but this kernel doesn't support altivec. */
  1083. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1084. goto bail;
  1085. }
  1086. printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
  1087. "%lx at %lx\n", regs->trap, regs->nip);
  1088. die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
  1089. bail:
  1090. exception_exit(prev_state);
  1091. }
  1092. void vsx_unavailable_exception(struct pt_regs *regs)
  1093. {
  1094. if (user_mode(regs)) {
  1095. /* A user program has executed an vsx instruction,
  1096. but this kernel doesn't support vsx. */
  1097. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1098. return;
  1099. }
  1100. printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
  1101. "%lx at %lx\n", regs->trap, regs->nip);
  1102. die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
  1103. }
  1104. void tm_unavailable_exception(struct pt_regs *regs)
  1105. {
  1106. /* We restore the interrupt state now */
  1107. if (!arch_irq_disabled_regs(regs))
  1108. local_irq_enable();
  1109. /* Currently we never expect a TMU exception. Catch
  1110. * this and kill the process!
  1111. */
  1112. printk(KERN_EMERG "Unexpected TM unavailable exception at %lx "
  1113. "(msr %lx)\n",
  1114. regs->nip, regs->msr);
  1115. if (user_mode(regs)) {
  1116. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1117. return;
  1118. }
  1119. die("Unexpected TM unavailable exception", regs, SIGABRT);
  1120. }
  1121. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1122. extern void do_load_up_fpu(struct pt_regs *regs);
  1123. void fp_unavailable_tm(struct pt_regs *regs)
  1124. {
  1125. /* Note: This does not handle any kind of FP laziness. */
  1126. TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
  1127. regs->nip, regs->msr);
  1128. tm_enable();
  1129. /* We can only have got here if the task started using FP after
  1130. * beginning the transaction. So, the transactional regs are just a
  1131. * copy of the checkpointed ones. But, we still need to recheckpoint
  1132. * as we're enabling FP for the process; it will return, abort the
  1133. * transaction, and probably retry but now with FP enabled. So the
  1134. * checkpointed FP registers need to be loaded.
  1135. */
  1136. tm_reclaim(&current->thread, current->thread.regs->msr,
  1137. TM_CAUSE_FAC_UNAV);
  1138. /* Reclaim didn't save out any FPRs to transact_fprs. */
  1139. /* Enable FP for the task: */
  1140. regs->msr |= (MSR_FP | current->thread.fpexc_mode);
  1141. /* This loads and recheckpoints the FP registers from
  1142. * thread.fpr[]. They will remain in registers after the
  1143. * checkpoint so we don't need to reload them after.
  1144. */
  1145. tm_recheckpoint(&current->thread, regs->msr);
  1146. }
  1147. #ifdef CONFIG_ALTIVEC
  1148. extern void do_load_up_altivec(struct pt_regs *regs);
  1149. void altivec_unavailable_tm(struct pt_regs *regs)
  1150. {
  1151. /* See the comments in fp_unavailable_tm(). This function operates
  1152. * the same way.
  1153. */
  1154. TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
  1155. "MSR=%lx\n",
  1156. regs->nip, regs->msr);
  1157. tm_enable();
  1158. tm_reclaim(&current->thread, current->thread.regs->msr,
  1159. TM_CAUSE_FAC_UNAV);
  1160. regs->msr |= MSR_VEC;
  1161. tm_recheckpoint(&current->thread, regs->msr);
  1162. current->thread.used_vr = 1;
  1163. }
  1164. #endif
  1165. #ifdef CONFIG_VSX
  1166. void vsx_unavailable_tm(struct pt_regs *regs)
  1167. {
  1168. /* See the comments in fp_unavailable_tm(). This works similarly,
  1169. * though we're loading both FP and VEC registers in here.
  1170. *
  1171. * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
  1172. * regs. Either way, set MSR_VSX.
  1173. */
  1174. TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
  1175. "MSR=%lx\n",
  1176. regs->nip, regs->msr);
  1177. tm_enable();
  1178. /* This reclaims FP and/or VR regs if they're already enabled */
  1179. tm_reclaim(&current->thread, current->thread.regs->msr,
  1180. TM_CAUSE_FAC_UNAV);
  1181. regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
  1182. MSR_VSX;
  1183. /* This loads & recheckpoints FP and VRs. */
  1184. tm_recheckpoint(&current->thread, regs->msr);
  1185. current->thread.used_vsr = 1;
  1186. }
  1187. #endif
  1188. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  1189. void performance_monitor_exception(struct pt_regs *regs)
  1190. {
  1191. __get_cpu_var(irq_stat).pmu_irqs++;
  1192. perf_irq(regs);
  1193. }
  1194. #ifdef CONFIG_8xx
  1195. void SoftwareEmulation(struct pt_regs *regs)
  1196. {
  1197. extern int do_mathemu(struct pt_regs *);
  1198. #if defined(CONFIG_MATH_EMULATION)
  1199. int errcode;
  1200. #endif
  1201. CHECK_FULL_REGS(regs);
  1202. if (!user_mode(regs)) {
  1203. debugger(regs);
  1204. die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
  1205. }
  1206. #ifdef CONFIG_MATH_EMULATION
  1207. errcode = do_mathemu(regs);
  1208. if (errcode >= 0)
  1209. PPC_WARN_EMULATED(math, regs);
  1210. switch (errcode) {
  1211. case 0:
  1212. emulate_single_step(regs);
  1213. return;
  1214. case 1: {
  1215. int code = 0;
  1216. code = __parse_fpscr(current->thread.fpscr.val);
  1217. _exception(SIGFPE, regs, code, regs->nip);
  1218. return;
  1219. }
  1220. case -EFAULT:
  1221. _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
  1222. return;
  1223. default:
  1224. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1225. return;
  1226. }
  1227. #else
  1228. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1229. #endif
  1230. }
  1231. #endif /* CONFIG_8xx */
  1232. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  1233. static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
  1234. {
  1235. int changed = 0;
  1236. /*
  1237. * Determine the cause of the debug event, clear the
  1238. * event flags and send a trap to the handler. Torez
  1239. */
  1240. if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
  1241. dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
  1242. #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
  1243. current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
  1244. #endif
  1245. do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
  1246. 5);
  1247. changed |= 0x01;
  1248. } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
  1249. dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
  1250. do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
  1251. 6);
  1252. changed |= 0x01;
  1253. } else if (debug_status & DBSR_IAC1) {
  1254. current->thread.dbcr0 &= ~DBCR0_IAC1;
  1255. dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
  1256. do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
  1257. 1);
  1258. changed |= 0x01;
  1259. } else if (debug_status & DBSR_IAC2) {
  1260. current->thread.dbcr0 &= ~DBCR0_IAC2;
  1261. do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
  1262. 2);
  1263. changed |= 0x01;
  1264. } else if (debug_status & DBSR_IAC3) {
  1265. current->thread.dbcr0 &= ~DBCR0_IAC3;
  1266. dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
  1267. do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
  1268. 3);
  1269. changed |= 0x01;
  1270. } else if (debug_status & DBSR_IAC4) {
  1271. current->thread.dbcr0 &= ~DBCR0_IAC4;
  1272. do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
  1273. 4);
  1274. changed |= 0x01;
  1275. }
  1276. /*
  1277. * At the point this routine was called, the MSR(DE) was turned off.
  1278. * Check all other debug flags and see if that bit needs to be turned
  1279. * back on or not.
  1280. */
  1281. if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
  1282. regs->msr |= MSR_DE;
  1283. else
  1284. /* Make sure the IDM flag is off */
  1285. current->thread.dbcr0 &= ~DBCR0_IDM;
  1286. if (changed & 0x01)
  1287. mtspr(SPRN_DBCR0, current->thread.dbcr0);
  1288. }
  1289. void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
  1290. {
  1291. current->thread.dbsr = debug_status;
  1292. /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
  1293. * on server, it stops on the target of the branch. In order to simulate
  1294. * the server behaviour, we thus restart right away with a single step
  1295. * instead of stopping here when hitting a BT
  1296. */
  1297. if (debug_status & DBSR_BT) {
  1298. regs->msr &= ~MSR_DE;
  1299. /* Disable BT */
  1300. mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
  1301. /* Clear the BT event */
  1302. mtspr(SPRN_DBSR, DBSR_BT);
  1303. /* Do the single step trick only when coming from userspace */
  1304. if (user_mode(regs)) {
  1305. current->thread.dbcr0 &= ~DBCR0_BT;
  1306. current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
  1307. regs->msr |= MSR_DE;
  1308. return;
  1309. }
  1310. if (notify_die(DIE_SSTEP, "block_step", regs, 5,
  1311. 5, SIGTRAP) == NOTIFY_STOP) {
  1312. return;
  1313. }
  1314. if (debugger_sstep(regs))
  1315. return;
  1316. } else if (debug_status & DBSR_IC) { /* Instruction complete */
  1317. regs->msr &= ~MSR_DE;
  1318. /* Disable instruction completion */
  1319. mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
  1320. /* Clear the instruction completion event */
  1321. mtspr(SPRN_DBSR, DBSR_IC);
  1322. if (notify_die(DIE_SSTEP, "single_step", regs, 5,
  1323. 5, SIGTRAP) == NOTIFY_STOP) {
  1324. return;
  1325. }
  1326. if (debugger_sstep(regs))
  1327. return;
  1328. if (user_mode(regs)) {
  1329. current->thread.dbcr0 &= ~DBCR0_IC;
  1330. if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
  1331. current->thread.dbcr1))
  1332. regs->msr |= MSR_DE;
  1333. else
  1334. /* Make sure the IDM bit is off */
  1335. current->thread.dbcr0 &= ~DBCR0_IDM;
  1336. }
  1337. _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
  1338. } else
  1339. handle_debug(regs, debug_status);
  1340. }
  1341. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  1342. #if !defined(CONFIG_TAU_INT)
  1343. void TAUException(struct pt_regs *regs)
  1344. {
  1345. printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
  1346. regs->nip, regs->msr, regs->trap, print_tainted());
  1347. }
  1348. #endif /* CONFIG_INT_TAU */
  1349. #ifdef CONFIG_ALTIVEC
  1350. void altivec_assist_exception(struct pt_regs *regs)
  1351. {
  1352. int err;
  1353. if (!user_mode(regs)) {
  1354. printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
  1355. " at %lx\n", regs->nip);
  1356. die("Kernel VMX/Altivec assist exception", regs, SIGILL);
  1357. }
  1358. flush_altivec_to_thread(current);
  1359. PPC_WARN_EMULATED(altivec, regs);
  1360. err = emulate_altivec(regs);
  1361. if (err == 0) {
  1362. regs->nip += 4; /* skip emulated instruction */
  1363. emulate_single_step(regs);
  1364. return;
  1365. }
  1366. if (err == -EFAULT) {
  1367. /* got an error reading the instruction */
  1368. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1369. } else {
  1370. /* didn't recognize the instruction */
  1371. /* XXX quick hack for now: set the non-Java bit in the VSCR */
  1372. printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
  1373. "in %s at %lx\n", current->comm, regs->nip);
  1374. current->thread.vscr.u[3] |= 0x10000;
  1375. }
  1376. }
  1377. #endif /* CONFIG_ALTIVEC */
  1378. #ifdef CONFIG_VSX
  1379. void vsx_assist_exception(struct pt_regs *regs)
  1380. {
  1381. if (!user_mode(regs)) {
  1382. printk(KERN_EMERG "VSX assist exception in kernel mode"
  1383. " at %lx\n", regs->nip);
  1384. die("Kernel VSX assist exception", regs, SIGILL);
  1385. }
  1386. flush_vsx_to_thread(current);
  1387. printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
  1388. _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
  1389. }
  1390. #endif /* CONFIG_VSX */
  1391. #ifdef CONFIG_FSL_BOOKE
  1392. void CacheLockingException(struct pt_regs *regs, unsigned long address,
  1393. unsigned long error_code)
  1394. {
  1395. /* We treat cache locking instructions from the user
  1396. * as priv ops, in the future we could try to do
  1397. * something smarter
  1398. */
  1399. if (error_code & (ESR_DLK|ESR_ILK))
  1400. _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
  1401. return;
  1402. }
  1403. #endif /* CONFIG_FSL_BOOKE */
  1404. #ifdef CONFIG_SPE
  1405. void SPEFloatingPointException(struct pt_regs *regs)
  1406. {
  1407. extern int do_spe_mathemu(struct pt_regs *regs);
  1408. unsigned long spefscr;
  1409. int fpexc_mode;
  1410. int code = 0;
  1411. int err;
  1412. flush_spe_to_thread(current);
  1413. spefscr = current->thread.spefscr;
  1414. fpexc_mode = current->thread.fpexc_mode;
  1415. if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
  1416. code = FPE_FLTOVF;
  1417. }
  1418. else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
  1419. code = FPE_FLTUND;
  1420. }
  1421. else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
  1422. code = FPE_FLTDIV;
  1423. else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
  1424. code = FPE_FLTINV;
  1425. }
  1426. else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
  1427. code = FPE_FLTRES;
  1428. err = do_spe_mathemu(regs);
  1429. if (err == 0) {
  1430. regs->nip += 4; /* skip emulated instruction */
  1431. emulate_single_step(regs);
  1432. return;
  1433. }
  1434. if (err == -EFAULT) {
  1435. /* got an error reading the instruction */
  1436. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1437. } else if (err == -EINVAL) {
  1438. /* didn't recognize the instruction */
  1439. printk(KERN_ERR "unrecognized spe instruction "
  1440. "in %s at %lx\n", current->comm, regs->nip);
  1441. } else {
  1442. _exception(SIGFPE, regs, code, regs->nip);
  1443. }
  1444. return;
  1445. }
  1446. void SPEFloatingPointRoundException(struct pt_regs *regs)
  1447. {
  1448. extern int speround_handler(struct pt_regs *regs);
  1449. int err;
  1450. preempt_disable();
  1451. if (regs->msr & MSR_SPE)
  1452. giveup_spe(current);
  1453. preempt_enable();
  1454. regs->nip -= 4;
  1455. err = speround_handler(regs);
  1456. if (err == 0) {
  1457. regs->nip += 4; /* skip emulated instruction */
  1458. emulate_single_step(regs);
  1459. return;
  1460. }
  1461. if (err == -EFAULT) {
  1462. /* got an error reading the instruction */
  1463. _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
  1464. } else if (err == -EINVAL) {
  1465. /* didn't recognize the instruction */
  1466. printk(KERN_ERR "unrecognized spe instruction "
  1467. "in %s at %lx\n", current->comm, regs->nip);
  1468. } else {
  1469. _exception(SIGFPE, regs, 0, regs->nip);
  1470. return;
  1471. }
  1472. }
  1473. #endif
  1474. /*
  1475. * We enter here if we get an unrecoverable exception, that is, one
  1476. * that happened at a point where the RI (recoverable interrupt) bit
  1477. * in the MSR is 0. This indicates that SRR0/1 are live, and that
  1478. * we therefore lost state by taking this exception.
  1479. */
  1480. void unrecoverable_exception(struct pt_regs *regs)
  1481. {
  1482. printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
  1483. regs->trap, regs->nip);
  1484. die("Unrecoverable exception", regs, SIGABRT);
  1485. }
  1486. #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
  1487. /*
  1488. * Default handler for a Watchdog exception,
  1489. * spins until a reboot occurs
  1490. */
  1491. void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
  1492. {
  1493. /* Generic WatchdogHandler, implement your own */
  1494. mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
  1495. return;
  1496. }
  1497. void WatchdogException(struct pt_regs *regs)
  1498. {
  1499. printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
  1500. WatchdogHandler(regs);
  1501. }
  1502. #endif
  1503. /*
  1504. * We enter here if we discover during exception entry that we are
  1505. * running in supervisor mode with a userspace value in the stack pointer.
  1506. */
  1507. void kernel_bad_stack(struct pt_regs *regs)
  1508. {
  1509. printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
  1510. regs->gpr[1], regs->nip);
  1511. die("Bad kernel stack pointer", regs, SIGABRT);
  1512. }
  1513. void __init trap_init(void)
  1514. {
  1515. }
  1516. #ifdef CONFIG_PPC_EMULATED_STATS
  1517. #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
  1518. struct ppc_emulated ppc_emulated = {
  1519. #ifdef CONFIG_ALTIVEC
  1520. WARN_EMULATED_SETUP(altivec),
  1521. #endif
  1522. WARN_EMULATED_SETUP(dcba),
  1523. WARN_EMULATED_SETUP(dcbz),
  1524. WARN_EMULATED_SETUP(fp_pair),
  1525. WARN_EMULATED_SETUP(isel),
  1526. WARN_EMULATED_SETUP(mcrxr),
  1527. WARN_EMULATED_SETUP(mfpvr),
  1528. WARN_EMULATED_SETUP(multiple),
  1529. WARN_EMULATED_SETUP(popcntb),
  1530. WARN_EMULATED_SETUP(spe),
  1531. WARN_EMULATED_SETUP(string),
  1532. WARN_EMULATED_SETUP(unaligned),
  1533. #ifdef CONFIG_MATH_EMULATION
  1534. WARN_EMULATED_SETUP(math),
  1535. #endif
  1536. #ifdef CONFIG_VSX
  1537. WARN_EMULATED_SETUP(vsx),
  1538. #endif
  1539. #ifdef CONFIG_PPC64
  1540. WARN_EMULATED_SETUP(mfdscr),
  1541. WARN_EMULATED_SETUP(mtdscr),
  1542. #endif
  1543. };
  1544. u32 ppc_warn_emulated;
  1545. void ppc_warn_emulated_print(const char *type)
  1546. {
  1547. pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
  1548. type);
  1549. }
  1550. static int __init ppc_warn_emulated_init(void)
  1551. {
  1552. struct dentry *dir, *d;
  1553. unsigned int i;
  1554. struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
  1555. if (!powerpc_debugfs_root)
  1556. return -ENODEV;
  1557. dir = debugfs_create_dir("emulated_instructions",
  1558. powerpc_debugfs_root);
  1559. if (!dir)
  1560. return -ENOMEM;
  1561. d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
  1562. &ppc_warn_emulated);
  1563. if (!d)
  1564. goto fail;
  1565. for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
  1566. d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
  1567. (u32 *)&entries[i].val.counter);
  1568. if (!d)
  1569. goto fail;
  1570. }
  1571. return 0;
  1572. fail:
  1573. debugfs_remove_recursive(dir);
  1574. return -ENOMEM;
  1575. }
  1576. device_initcall(ppc_warn_emulated_init);
  1577. #endif /* CONFIG_PPC_EMULATED_STATS */