ice1712.c 82 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. NOTES:
  23. - spdif nonaudio consumer mode does not work (at least with my
  24. Sony STR-DB830)
  25. */
  26. /*
  27. * Changes:
  28. *
  29. * 2002.09.09 Takashi Iwai <tiwai@suse.de>
  30. * split the code to several files. each low-level routine
  31. * is stored in the local file and called from registration
  32. * function from card_info struct.
  33. *
  34. * 2002.11.26 James Stafford <jstafford@ampltd.com>
  35. * Added support for VT1724 (Envy24HT)
  36. * I have left out support for 176.4 and 192 KHz for the moment.
  37. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  38. *
  39. * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
  40. * Split vt1724 part to an independent driver.
  41. * The GPIO is accessed through the callback functions now.
  42. *
  43. * 2004.03.31 Doug McLain <nostar@comcast.net>
  44. * Added support for Event Electronics EZ8 card to hoontech.c.
  45. */
  46. #include <asm/io.h>
  47. #include <linux/delay.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/init.h>
  50. #include <linux/pci.h>
  51. #include <linux/dma-mapping.h>
  52. #include <linux/slab.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/mutex.h>
  55. #include <sound/core.h>
  56. #include <sound/cs8427.h>
  57. #include <sound/info.h>
  58. #include <sound/initval.h>
  59. #include <sound/tlv.h>
  60. #include <sound/asoundef.h>
  61. #include "ice1712.h"
  62. /* lowlevel routines */
  63. #include "delta.h"
  64. #include "ews.h"
  65. #include "hoontech.h"
  66. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  67. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  68. MODULE_LICENSE("GPL");
  69. MODULE_SUPPORTED_DEVICE("{"
  70. HOONTECH_DEVICE_DESC
  71. DELTA_DEVICE_DESC
  72. EWS_DEVICE_DESC
  73. "{ICEnsemble,Generic ICE1712},"
  74. "{ICEnsemble,Generic Envy24}}");
  75. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  76. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  77. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  78. static char *model[SNDRV_CARDS];
  79. static int omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  80. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transciever reset timeout value in msec */
  81. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  82. module_param_array(index, int, NULL, 0444);
  83. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  84. module_param_array(id, charp, NULL, 0444);
  85. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  86. module_param_array(enable, bool, NULL, 0444);
  87. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  88. module_param_array(omni, bool, NULL, 0444);
  89. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  90. module_param_array(cs8427_timeout, int, NULL, 0444);
  91. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  92. module_param_array(model, charp, NULL, 0444);
  93. MODULE_PARM_DESC(model, "Use the given board model.");
  94. module_param_array(dxr_enable, int, NULL, 0444);
  95. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  96. static const struct pci_device_id snd_ice1712_ids[] = {
  97. { PCI_VENDOR_ID_ICE, PCI_DEVICE_ID_ICE_1712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICE1712 */
  98. { 0, }
  99. };
  100. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  101. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  102. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  103. static int PRO_RATE_LOCKED;
  104. static int PRO_RATE_RESET = 1;
  105. static unsigned int PRO_RATE_DEFAULT = 44100;
  106. /*
  107. * Basic I/O
  108. */
  109. /* check whether the clock mode is spdif-in */
  110. static inline int is_spdif_master(struct snd_ice1712 *ice)
  111. {
  112. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  113. }
  114. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  115. {
  116. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  117. }
  118. static inline void snd_ice1712_ds_write(struct snd_ice1712 * ice, u8 channel, u8 addr, u32 data)
  119. {
  120. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  121. outl(data, ICEDS(ice, DATA));
  122. }
  123. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 * ice, u8 channel, u8 addr)
  124. {
  125. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  126. return inl(ICEDS(ice, DATA));
  127. }
  128. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  129. unsigned short reg,
  130. unsigned short val)
  131. {
  132. struct snd_ice1712 *ice = ac97->private_data;
  133. int tm;
  134. unsigned char old_cmd = 0;
  135. for (tm = 0; tm < 0x10000; tm++) {
  136. old_cmd = inb(ICEREG(ice, AC97_CMD));
  137. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  138. continue;
  139. if (!(old_cmd & ICE1712_AC97_READY))
  140. continue;
  141. break;
  142. }
  143. outb(reg, ICEREG(ice, AC97_INDEX));
  144. outw(val, ICEREG(ice, AC97_DATA));
  145. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  146. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  147. for (tm = 0; tm < 0x10000; tm++)
  148. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  149. break;
  150. }
  151. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  152. unsigned short reg)
  153. {
  154. struct snd_ice1712 *ice = ac97->private_data;
  155. int tm;
  156. unsigned char old_cmd = 0;
  157. for (tm = 0; tm < 0x10000; tm++) {
  158. old_cmd = inb(ICEREG(ice, AC97_CMD));
  159. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  160. continue;
  161. if (!(old_cmd & ICE1712_AC97_READY))
  162. continue;
  163. break;
  164. }
  165. outb(reg, ICEREG(ice, AC97_INDEX));
  166. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  167. for (tm = 0; tm < 0x10000; tm++)
  168. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  169. break;
  170. if (tm >= 0x10000) /* timeout */
  171. return ~0;
  172. return inw(ICEREG(ice, AC97_DATA));
  173. }
  174. /*
  175. * pro ac97 section
  176. */
  177. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  178. unsigned short reg,
  179. unsigned short val)
  180. {
  181. struct snd_ice1712 *ice = ac97->private_data;
  182. int tm;
  183. unsigned char old_cmd = 0;
  184. for (tm = 0; tm < 0x10000; tm++) {
  185. old_cmd = inb(ICEMT(ice, AC97_CMD));
  186. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  187. continue;
  188. if (!(old_cmd & ICE1712_AC97_READY))
  189. continue;
  190. break;
  191. }
  192. outb(reg, ICEMT(ice, AC97_INDEX));
  193. outw(val, ICEMT(ice, AC97_DATA));
  194. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  195. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  196. for (tm = 0; tm < 0x10000; tm++)
  197. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  198. break;
  199. }
  200. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  201. unsigned short reg)
  202. {
  203. struct snd_ice1712 *ice = ac97->private_data;
  204. int tm;
  205. unsigned char old_cmd = 0;
  206. for (tm = 0; tm < 0x10000; tm++) {
  207. old_cmd = inb(ICEMT(ice, AC97_CMD));
  208. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  209. continue;
  210. if (!(old_cmd & ICE1712_AC97_READY))
  211. continue;
  212. break;
  213. }
  214. outb(reg, ICEMT(ice, AC97_INDEX));
  215. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  216. for (tm = 0; tm < 0x10000; tm++)
  217. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  218. break;
  219. if (tm >= 0x10000) /* timeout */
  220. return ~0;
  221. return inw(ICEMT(ice, AC97_DATA));
  222. }
  223. /*
  224. * consumer ac97 digital mix
  225. */
  226. #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
  227. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  228. {
  229. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  230. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  231. return 0;
  232. }
  233. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  234. {
  235. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  236. unsigned char val, nval;
  237. spin_lock_irq(&ice->reg_lock);
  238. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  239. nval = val & ~ICE1712_ROUTE_AC97;
  240. if (ucontrol->value.integer.value[0]) nval |= ICE1712_ROUTE_AC97;
  241. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  242. spin_unlock_irq(&ice->reg_lock);
  243. return val != nval;
  244. }
  245. static struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 __devinitdata = {
  246. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  247. .name = "Digital Mixer To AC97",
  248. .info = snd_ice1712_digmix_route_ac97_info,
  249. .get = snd_ice1712_digmix_route_ac97_get,
  250. .put = snd_ice1712_digmix_route_ac97_put,
  251. };
  252. /*
  253. * gpio operations
  254. */
  255. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  256. {
  257. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  258. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  259. }
  260. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  261. {
  262. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  263. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  264. }
  265. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  266. {
  267. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  268. }
  269. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  270. {
  271. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  272. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  273. }
  274. /*
  275. *
  276. * CS8427 interface
  277. *
  278. */
  279. /*
  280. * change the input clock selection
  281. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  282. */
  283. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  284. {
  285. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  286. unsigned char val, nval;
  287. int res = 0;
  288. snd_i2c_lock(ice->i2c);
  289. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  290. snd_i2c_unlock(ice->i2c);
  291. return -EIO;
  292. }
  293. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  294. snd_i2c_unlock(ice->i2c);
  295. return -EIO;
  296. }
  297. nval = val & 0xf0;
  298. if (spdif_clock)
  299. nval |= 0x01;
  300. else
  301. nval |= 0x04;
  302. if (val != nval) {
  303. reg[1] = nval;
  304. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  305. res = -EIO;
  306. } else {
  307. res++;
  308. }
  309. }
  310. snd_i2c_unlock(ice->i2c);
  311. return res;
  312. }
  313. /*
  314. * spdif callbacks
  315. */
  316. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  317. {
  318. snd_cs8427_iec958_active(ice->cs8427, 1);
  319. }
  320. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  321. {
  322. snd_cs8427_iec958_active(ice->cs8427, 0);
  323. }
  324. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  325. {
  326. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  327. }
  328. /*
  329. * create and initialize callbacks for cs8427 interface
  330. */
  331. int __devinit snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  332. {
  333. int err;
  334. if ((err = snd_cs8427_create(ice->i2c, addr,
  335. (ice->cs8427_timeout * HZ) / 1000,
  336. &ice->cs8427)) < 0) {
  337. snd_printk(KERN_ERR "CS8427 initialization failed\n");
  338. return err;
  339. }
  340. ice->spdif.ops.open = open_cs8427;
  341. ice->spdif.ops.close = close_cs8427;
  342. ice->spdif.ops.setup_rate = setup_cs8427;
  343. return 0;
  344. }
  345. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  346. {
  347. /* change CS8427 clock source too */
  348. if (ice->cs8427)
  349. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  350. /* notify ak4524 chip as well */
  351. if (spdif_is_master) {
  352. unsigned int i;
  353. for (i = 0; i < ice->akm_codecs; i++) {
  354. if (ice->akm[i].ops.set_rate_val)
  355. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  356. }
  357. }
  358. }
  359. /*
  360. * Interrupt handler
  361. */
  362. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  363. {
  364. struct snd_ice1712 *ice = dev_id;
  365. unsigned char status;
  366. int handled = 0;
  367. while (1) {
  368. status = inb(ICEREG(ice, IRQSTAT));
  369. if (status == 0)
  370. break;
  371. handled = 1;
  372. if (status & ICE1712_IRQ_MPU1) {
  373. if (ice->rmidi[0])
  374. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  375. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  376. status &= ~ICE1712_IRQ_MPU1;
  377. }
  378. if (status & ICE1712_IRQ_TIMER)
  379. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  380. if (status & ICE1712_IRQ_MPU2) {
  381. if (ice->rmidi[1])
  382. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  383. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  384. status &= ~ICE1712_IRQ_MPU2;
  385. }
  386. if (status & ICE1712_IRQ_PROPCM) {
  387. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  388. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  389. if (ice->playback_pro_substream)
  390. snd_pcm_period_elapsed(ice->playback_pro_substream);
  391. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  392. }
  393. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  394. if (ice->capture_pro_substream)
  395. snd_pcm_period_elapsed(ice->capture_pro_substream);
  396. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  397. }
  398. }
  399. if (status & ICE1712_IRQ_FM)
  400. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  401. if (status & ICE1712_IRQ_PBKDS) {
  402. u32 idx;
  403. u16 pbkstatus;
  404. struct snd_pcm_substream *substream;
  405. pbkstatus = inw(ICEDS(ice, INTSTAT));
  406. //printk("pbkstatus = 0x%x\n", pbkstatus);
  407. for (idx = 0; idx < 6; idx++) {
  408. if ((pbkstatus & (3 << (idx * 2))) == 0)
  409. continue;
  410. if ((substream = ice->playback_con_substream_ds[idx]) != NULL)
  411. snd_pcm_period_elapsed(substream);
  412. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  413. }
  414. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  415. }
  416. if (status & ICE1712_IRQ_CONCAP) {
  417. if (ice->capture_con_substream)
  418. snd_pcm_period_elapsed(ice->capture_con_substream);
  419. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  420. }
  421. if (status & ICE1712_IRQ_CONPBK) {
  422. if (ice->playback_con_substream)
  423. snd_pcm_period_elapsed(ice->playback_con_substream);
  424. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  425. }
  426. }
  427. return IRQ_RETVAL(handled);
  428. }
  429. /*
  430. * PCM part - misc
  431. */
  432. static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
  433. struct snd_pcm_hw_params *hw_params)
  434. {
  435. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  436. }
  437. static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
  438. {
  439. return snd_pcm_lib_free_pages(substream);
  440. }
  441. /*
  442. * PCM part - consumer I/O
  443. */
  444. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  445. int cmd)
  446. {
  447. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  448. int result = 0;
  449. u32 tmp;
  450. spin_lock(&ice->reg_lock);
  451. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  452. if (cmd == SNDRV_PCM_TRIGGER_START) {
  453. tmp |= 1;
  454. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  455. tmp &= ~1;
  456. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  457. tmp |= 2;
  458. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  459. tmp &= ~2;
  460. } else {
  461. result = -EINVAL;
  462. }
  463. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  464. spin_unlock(&ice->reg_lock);
  465. return result;
  466. }
  467. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  468. int cmd)
  469. {
  470. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  471. int result = 0;
  472. u32 tmp;
  473. spin_lock(&ice->reg_lock);
  474. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  475. if (cmd == SNDRV_PCM_TRIGGER_START) {
  476. tmp |= 1;
  477. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  478. tmp &= ~1;
  479. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  480. tmp |= 2;
  481. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  482. tmp &= ~2;
  483. } else {
  484. result = -EINVAL;
  485. }
  486. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  487. spin_unlock(&ice->reg_lock);
  488. return result;
  489. }
  490. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  491. int cmd)
  492. {
  493. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  494. int result = 0;
  495. u8 tmp;
  496. spin_lock(&ice->reg_lock);
  497. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  498. if (cmd == SNDRV_PCM_TRIGGER_START) {
  499. tmp |= 1;
  500. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  501. tmp &= ~1;
  502. } else {
  503. result = -EINVAL;
  504. }
  505. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  506. spin_unlock(&ice->reg_lock);
  507. return result;
  508. }
  509. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  510. {
  511. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  512. struct snd_pcm_runtime *runtime = substream->runtime;
  513. u32 period_size, buf_size, rate, tmp;
  514. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  515. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  516. tmp = 0x0000;
  517. if (snd_pcm_format_width(runtime->format) == 16)
  518. tmp |= 0x10;
  519. if (runtime->channels == 2)
  520. tmp |= 0x08;
  521. rate = (runtime->rate * 8192) / 375;
  522. if (rate > 0x000fffff)
  523. rate = 0x000fffff;
  524. spin_lock_irq(&ice->reg_lock);
  525. outb(0, ice->ddma_port + 15);
  526. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  527. outl(runtime->dma_addr, ice->ddma_port + 0);
  528. outw(buf_size, ice->ddma_port + 4);
  529. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  530. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  531. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  532. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  533. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  534. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  535. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  536. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  537. spin_unlock_irq(&ice->reg_lock);
  538. return 0;
  539. }
  540. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  541. {
  542. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  543. struct snd_pcm_runtime *runtime = substream->runtime;
  544. u32 period_size, buf_size, rate, tmp, chn;
  545. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  546. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  547. tmp = 0x0064;
  548. if (snd_pcm_format_width(runtime->format) == 16)
  549. tmp &= ~0x04;
  550. if (runtime->channels == 2)
  551. tmp |= 0x08;
  552. rate = (runtime->rate * 8192) / 375;
  553. if (rate > 0x000fffff)
  554. rate = 0x000fffff;
  555. ice->playback_con_active_buf[substream->number] = 0;
  556. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  557. chn = substream->number * 2;
  558. spin_lock_irq(&ice->reg_lock);
  559. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  560. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  561. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  562. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  563. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  564. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  565. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  566. if (runtime->channels == 2) {
  567. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  568. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  569. }
  570. spin_unlock_irq(&ice->reg_lock);
  571. return 0;
  572. }
  573. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  574. {
  575. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  576. struct snd_pcm_runtime *runtime = substream->runtime;
  577. u32 period_size, buf_size;
  578. u8 tmp;
  579. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  580. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  581. tmp = 0x06;
  582. if (snd_pcm_format_width(runtime->format) == 16)
  583. tmp &= ~0x04;
  584. if (runtime->channels == 2)
  585. tmp &= ~0x02;
  586. spin_lock_irq(&ice->reg_lock);
  587. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  588. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  589. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  590. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  591. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  592. spin_unlock_irq(&ice->reg_lock);
  593. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  594. return 0;
  595. }
  596. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  597. {
  598. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  599. struct snd_pcm_runtime *runtime = substream->runtime;
  600. size_t ptr;
  601. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  602. return 0;
  603. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  604. if (ptr == runtime->buffer_size)
  605. ptr = 0;
  606. return bytes_to_frames(substream->runtime, ptr);
  607. }
  608. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  609. {
  610. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  611. u8 addr;
  612. size_t ptr;
  613. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  614. return 0;
  615. if (ice->playback_con_active_buf[substream->number])
  616. addr = ICE1712_DSC_ADDR1;
  617. else
  618. addr = ICE1712_DSC_ADDR0;
  619. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  620. ice->playback_con_virt_addr[substream->number];
  621. if (ptr == substream->runtime->buffer_size)
  622. ptr = 0;
  623. return bytes_to_frames(substream->runtime, ptr);
  624. }
  625. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  626. {
  627. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  628. size_t ptr;
  629. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  630. return 0;
  631. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  632. if (ptr == substream->runtime->buffer_size)
  633. ptr = 0;
  634. return bytes_to_frames(substream->runtime, ptr);
  635. }
  636. static const struct snd_pcm_hardware snd_ice1712_playback =
  637. {
  638. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  639. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  640. SNDRV_PCM_INFO_MMAP_VALID |
  641. SNDRV_PCM_INFO_PAUSE),
  642. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  643. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  644. .rate_min = 4000,
  645. .rate_max = 48000,
  646. .channels_min = 1,
  647. .channels_max = 2,
  648. .buffer_bytes_max = (64*1024),
  649. .period_bytes_min = 64,
  650. .period_bytes_max = (64*1024),
  651. .periods_min = 1,
  652. .periods_max = 1024,
  653. .fifo_size = 0,
  654. };
  655. static const struct snd_pcm_hardware snd_ice1712_playback_ds =
  656. {
  657. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  658. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  659. SNDRV_PCM_INFO_MMAP_VALID |
  660. SNDRV_PCM_INFO_PAUSE),
  661. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  662. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  663. .rate_min = 4000,
  664. .rate_max = 48000,
  665. .channels_min = 1,
  666. .channels_max = 2,
  667. .buffer_bytes_max = (128*1024),
  668. .period_bytes_min = 64,
  669. .period_bytes_max = (128*1024),
  670. .periods_min = 2,
  671. .periods_max = 2,
  672. .fifo_size = 0,
  673. };
  674. static const struct snd_pcm_hardware snd_ice1712_capture =
  675. {
  676. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  677. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  678. SNDRV_PCM_INFO_MMAP_VALID),
  679. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  680. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  681. .rate_min = 4000,
  682. .rate_max = 48000,
  683. .channels_min = 1,
  684. .channels_max = 2,
  685. .buffer_bytes_max = (64*1024),
  686. .period_bytes_min = 64,
  687. .period_bytes_max = (64*1024),
  688. .periods_min = 1,
  689. .periods_max = 1024,
  690. .fifo_size = 0,
  691. };
  692. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  693. {
  694. struct snd_pcm_runtime *runtime = substream->runtime;
  695. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  696. ice->playback_con_substream = substream;
  697. runtime->hw = snd_ice1712_playback;
  698. return 0;
  699. }
  700. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  701. {
  702. struct snd_pcm_runtime *runtime = substream->runtime;
  703. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  704. u32 tmp;
  705. ice->playback_con_substream_ds[substream->number] = substream;
  706. runtime->hw = snd_ice1712_playback_ds;
  707. spin_lock_irq(&ice->reg_lock);
  708. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  709. outw(tmp, ICEDS(ice, INTMASK));
  710. spin_unlock_irq(&ice->reg_lock);
  711. return 0;
  712. }
  713. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  714. {
  715. struct snd_pcm_runtime *runtime = substream->runtime;
  716. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  717. ice->capture_con_substream = substream;
  718. runtime->hw = snd_ice1712_capture;
  719. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  720. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  721. runtime->hw.rate_min = 48000;
  722. return 0;
  723. }
  724. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  725. {
  726. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  727. ice->playback_con_substream = NULL;
  728. return 0;
  729. }
  730. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  731. {
  732. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  733. u32 tmp;
  734. spin_lock_irq(&ice->reg_lock);
  735. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  736. outw(tmp, ICEDS(ice, INTMASK));
  737. spin_unlock_irq(&ice->reg_lock);
  738. ice->playback_con_substream_ds[substream->number] = NULL;
  739. return 0;
  740. }
  741. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  742. {
  743. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  744. ice->capture_con_substream = NULL;
  745. return 0;
  746. }
  747. static struct snd_pcm_ops snd_ice1712_playback_ops = {
  748. .open = snd_ice1712_playback_open,
  749. .close = snd_ice1712_playback_close,
  750. .ioctl = snd_pcm_lib_ioctl,
  751. .hw_params = snd_ice1712_hw_params,
  752. .hw_free = snd_ice1712_hw_free,
  753. .prepare = snd_ice1712_playback_prepare,
  754. .trigger = snd_ice1712_playback_trigger,
  755. .pointer = snd_ice1712_playback_pointer,
  756. };
  757. static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  758. .open = snd_ice1712_playback_ds_open,
  759. .close = snd_ice1712_playback_ds_close,
  760. .ioctl = snd_pcm_lib_ioctl,
  761. .hw_params = snd_ice1712_hw_params,
  762. .hw_free = snd_ice1712_hw_free,
  763. .prepare = snd_ice1712_playback_ds_prepare,
  764. .trigger = snd_ice1712_playback_ds_trigger,
  765. .pointer = snd_ice1712_playback_ds_pointer,
  766. };
  767. static struct snd_pcm_ops snd_ice1712_capture_ops = {
  768. .open = snd_ice1712_capture_open,
  769. .close = snd_ice1712_capture_close,
  770. .ioctl = snd_pcm_lib_ioctl,
  771. .hw_params = snd_ice1712_hw_params,
  772. .hw_free = snd_ice1712_hw_free,
  773. .prepare = snd_ice1712_capture_prepare,
  774. .trigger = snd_ice1712_capture_trigger,
  775. .pointer = snd_ice1712_capture_pointer,
  776. };
  777. static int __devinit snd_ice1712_pcm(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  778. {
  779. struct snd_pcm *pcm;
  780. int err;
  781. if (rpcm)
  782. *rpcm = NULL;
  783. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  784. if (err < 0)
  785. return err;
  786. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  787. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  788. pcm->private_data = ice;
  789. pcm->info_flags = 0;
  790. strcpy(pcm->name, "ICE1712 consumer");
  791. ice->pcm = pcm;
  792. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  793. snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
  794. if (rpcm)
  795. *rpcm = pcm;
  796. printk(KERN_WARNING "Consumer PCM code does not work well at the moment --jk\n");
  797. return 0;
  798. }
  799. static int __devinit snd_ice1712_pcm_ds(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  800. {
  801. struct snd_pcm *pcm;
  802. int err;
  803. if (rpcm)
  804. *rpcm = NULL;
  805. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  806. if (err < 0)
  807. return err;
  808. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  809. pcm->private_data = ice;
  810. pcm->info_flags = 0;
  811. strcpy(pcm->name, "ICE1712 consumer (DS)");
  812. ice->pcm_ds = pcm;
  813. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  814. snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
  815. if (rpcm)
  816. *rpcm = pcm;
  817. return 0;
  818. }
  819. /*
  820. * PCM code - professional part (multitrack)
  821. */
  822. static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  823. 32000, 44100, 48000, 64000, 88200, 96000 };
  824. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  825. .count = ARRAY_SIZE(rates),
  826. .list = rates,
  827. .mask = 0,
  828. };
  829. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  830. int cmd)
  831. {
  832. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  833. switch (cmd) {
  834. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  835. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  836. {
  837. unsigned int what;
  838. unsigned int old;
  839. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  840. return -EINVAL;
  841. what = ICE1712_PLAYBACK_PAUSE;
  842. snd_pcm_trigger_done(substream, substream);
  843. spin_lock(&ice->reg_lock);
  844. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  845. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  846. old |= what;
  847. else
  848. old &= ~what;
  849. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  850. spin_unlock(&ice->reg_lock);
  851. break;
  852. }
  853. case SNDRV_PCM_TRIGGER_START:
  854. case SNDRV_PCM_TRIGGER_STOP:
  855. {
  856. unsigned int what = 0;
  857. unsigned int old;
  858. struct snd_pcm_substream *s;
  859. snd_pcm_group_for_each_entry(s, substream) {
  860. if (s == ice->playback_pro_substream) {
  861. what |= ICE1712_PLAYBACK_START;
  862. snd_pcm_trigger_done(s, substream);
  863. } else if (s == ice->capture_pro_substream) {
  864. what |= ICE1712_CAPTURE_START_SHADOW;
  865. snd_pcm_trigger_done(s, substream);
  866. }
  867. }
  868. spin_lock(&ice->reg_lock);
  869. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  870. if (cmd == SNDRV_PCM_TRIGGER_START)
  871. old |= what;
  872. else
  873. old &= ~what;
  874. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  875. spin_unlock(&ice->reg_lock);
  876. break;
  877. }
  878. default:
  879. return -EINVAL;
  880. }
  881. return 0;
  882. }
  883. /*
  884. */
  885. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  886. {
  887. unsigned long flags;
  888. unsigned char val, old;
  889. unsigned int i;
  890. switch (rate) {
  891. case 8000: val = 6; break;
  892. case 9600: val = 3; break;
  893. case 11025: val = 10; break;
  894. case 12000: val = 2; break;
  895. case 16000: val = 5; break;
  896. case 22050: val = 9; break;
  897. case 24000: val = 1; break;
  898. case 32000: val = 4; break;
  899. case 44100: val = 8; break;
  900. case 48000: val = 0; break;
  901. case 64000: val = 15; break;
  902. case 88200: val = 11; break;
  903. case 96000: val = 7; break;
  904. default:
  905. snd_BUG();
  906. val = 0;
  907. rate = 48000;
  908. break;
  909. }
  910. spin_lock_irqsave(&ice->reg_lock, flags);
  911. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  912. ICE1712_PLAYBACK_PAUSE|
  913. ICE1712_PLAYBACK_START)) {
  914. __out:
  915. spin_unlock_irqrestore(&ice->reg_lock, flags);
  916. return;
  917. }
  918. if (!force && is_pro_rate_locked(ice))
  919. goto __out;
  920. old = inb(ICEMT(ice, RATE));
  921. if (!force && old == val)
  922. goto __out;
  923. outb(val, ICEMT(ice, RATE));
  924. spin_unlock_irqrestore(&ice->reg_lock, flags);
  925. if (ice->gpio.set_pro_rate)
  926. ice->gpio.set_pro_rate(ice, rate);
  927. for (i = 0; i < ice->akm_codecs; i++) {
  928. if (ice->akm[i].ops.set_rate_val)
  929. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  930. }
  931. if (ice->spdif.ops.setup_rate)
  932. ice->spdif.ops.setup_rate(ice, rate);
  933. }
  934. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  935. {
  936. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  937. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  938. spin_lock_irq(&ice->reg_lock);
  939. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  940. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  941. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  942. spin_unlock_irq(&ice->reg_lock);
  943. return 0;
  944. }
  945. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  946. struct snd_pcm_hw_params *hw_params)
  947. {
  948. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  949. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  950. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  951. }
  952. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  953. {
  954. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  955. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  956. spin_lock_irq(&ice->reg_lock);
  957. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  958. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  959. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  960. spin_unlock_irq(&ice->reg_lock);
  961. return 0;
  962. }
  963. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  964. struct snd_pcm_hw_params *hw_params)
  965. {
  966. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  967. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  968. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  969. }
  970. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  971. {
  972. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  973. size_t ptr;
  974. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  975. return 0;
  976. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  977. if (ptr == substream->runtime->buffer_size)
  978. ptr = 0;
  979. return bytes_to_frames(substream->runtime, ptr);
  980. }
  981. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  982. {
  983. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  984. size_t ptr;
  985. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  986. return 0;
  987. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  988. if (ptr == substream->runtime->buffer_size)
  989. ptr = 0;
  990. return bytes_to_frames(substream->runtime, ptr);
  991. }
  992. static const struct snd_pcm_hardware snd_ice1712_playback_pro =
  993. {
  994. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  995. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  996. SNDRV_PCM_INFO_MMAP_VALID |
  997. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  998. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  999. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1000. .rate_min = 4000,
  1001. .rate_max = 96000,
  1002. .channels_min = 10,
  1003. .channels_max = 10,
  1004. .buffer_bytes_max = (256*1024),
  1005. .period_bytes_min = 10 * 4 * 2,
  1006. .period_bytes_max = 131040,
  1007. .periods_min = 1,
  1008. .periods_max = 1024,
  1009. .fifo_size = 0,
  1010. };
  1011. static const struct snd_pcm_hardware snd_ice1712_capture_pro =
  1012. {
  1013. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1014. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1015. SNDRV_PCM_INFO_MMAP_VALID |
  1016. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1017. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1018. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1019. .rate_min = 4000,
  1020. .rate_max = 96000,
  1021. .channels_min = 12,
  1022. .channels_max = 12,
  1023. .buffer_bytes_max = (256*1024),
  1024. .period_bytes_min = 12 * 4 * 2,
  1025. .period_bytes_max = 131040,
  1026. .periods_min = 1,
  1027. .periods_max = 1024,
  1028. .fifo_size = 0,
  1029. };
  1030. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  1031. {
  1032. struct snd_pcm_runtime *runtime = substream->runtime;
  1033. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1034. ice->playback_pro_substream = substream;
  1035. runtime->hw = snd_ice1712_playback_pro;
  1036. snd_pcm_set_sync(substream);
  1037. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1038. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1039. if (ice->spdif.ops.open)
  1040. ice->spdif.ops.open(ice, substream);
  1041. return 0;
  1042. }
  1043. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1044. {
  1045. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1046. struct snd_pcm_runtime *runtime = substream->runtime;
  1047. ice->capture_pro_substream = substream;
  1048. runtime->hw = snd_ice1712_capture_pro;
  1049. snd_pcm_set_sync(substream);
  1050. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1051. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1052. return 0;
  1053. }
  1054. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1055. {
  1056. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1057. if (PRO_RATE_RESET)
  1058. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1059. ice->playback_pro_substream = NULL;
  1060. if (ice->spdif.ops.close)
  1061. ice->spdif.ops.close(ice, substream);
  1062. return 0;
  1063. }
  1064. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1065. {
  1066. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1067. if (PRO_RATE_RESET)
  1068. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1069. ice->capture_pro_substream = NULL;
  1070. return 0;
  1071. }
  1072. static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1073. .open = snd_ice1712_playback_pro_open,
  1074. .close = snd_ice1712_playback_pro_close,
  1075. .ioctl = snd_pcm_lib_ioctl,
  1076. .hw_params = snd_ice1712_playback_pro_hw_params,
  1077. .hw_free = snd_ice1712_hw_free,
  1078. .prepare = snd_ice1712_playback_pro_prepare,
  1079. .trigger = snd_ice1712_pro_trigger,
  1080. .pointer = snd_ice1712_playback_pro_pointer,
  1081. };
  1082. static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1083. .open = snd_ice1712_capture_pro_open,
  1084. .close = snd_ice1712_capture_pro_close,
  1085. .ioctl = snd_pcm_lib_ioctl,
  1086. .hw_params = snd_ice1712_capture_pro_hw_params,
  1087. .hw_free = snd_ice1712_hw_free,
  1088. .prepare = snd_ice1712_capture_pro_prepare,
  1089. .trigger = snd_ice1712_pro_trigger,
  1090. .pointer = snd_ice1712_capture_pro_pointer,
  1091. };
  1092. static int __devinit snd_ice1712_pcm_profi(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  1093. {
  1094. struct snd_pcm *pcm;
  1095. int err;
  1096. if (rpcm)
  1097. *rpcm = NULL;
  1098. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1099. if (err < 0)
  1100. return err;
  1101. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1102. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1103. pcm->private_data = ice;
  1104. pcm->info_flags = 0;
  1105. strcpy(pcm->name, "ICE1712 multi");
  1106. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1107. snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
  1108. ice->pcm_pro = pcm;
  1109. if (rpcm)
  1110. *rpcm = pcm;
  1111. if (ice->cs8427) {
  1112. /* assign channels to iec958 */
  1113. err = snd_cs8427_iec958_build(ice->cs8427,
  1114. pcm->streams[0].substream,
  1115. pcm->streams[1].substream);
  1116. if (err < 0)
  1117. return err;
  1118. }
  1119. if ((err = snd_ice1712_build_pro_mixer(ice)) < 0)
  1120. return err;
  1121. return 0;
  1122. }
  1123. /*
  1124. * Mixer section
  1125. */
  1126. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1127. {
  1128. unsigned int vol = ice->pro_volumes[index];
  1129. unsigned short val = 0;
  1130. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1131. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1132. outb(index, ICEMT(ice, MONITOR_INDEX));
  1133. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1134. }
  1135. #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
  1136. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1137. {
  1138. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1139. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1140. kcontrol->private_value;
  1141. spin_lock_irq(&ice->reg_lock);
  1142. ucontrol->value.integer.value[0] =
  1143. !((ice->pro_volumes[priv_idx] >> 15) & 1);
  1144. ucontrol->value.integer.value[1] =
  1145. !((ice->pro_volumes[priv_idx] >> 31) & 1);
  1146. spin_unlock_irq(&ice->reg_lock);
  1147. return 0;
  1148. }
  1149. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1150. {
  1151. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1152. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1153. kcontrol->private_value;
  1154. unsigned int nval, change;
  1155. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1156. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1157. spin_lock_irq(&ice->reg_lock);
  1158. nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
  1159. change = nval != ice->pro_volumes[priv_idx];
  1160. ice->pro_volumes[priv_idx] = nval;
  1161. snd_ice1712_update_volume(ice, priv_idx);
  1162. spin_unlock_irq(&ice->reg_lock);
  1163. return change;
  1164. }
  1165. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1166. {
  1167. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1168. uinfo->count = 2;
  1169. uinfo->value.integer.min = 0;
  1170. uinfo->value.integer.max = 96;
  1171. return 0;
  1172. }
  1173. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1174. {
  1175. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1176. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1177. kcontrol->private_value;
  1178. spin_lock_irq(&ice->reg_lock);
  1179. ucontrol->value.integer.value[0] =
  1180. (ice->pro_volumes[priv_idx] >> 0) & 127;
  1181. ucontrol->value.integer.value[1] =
  1182. (ice->pro_volumes[priv_idx] >> 16) & 127;
  1183. spin_unlock_irq(&ice->reg_lock);
  1184. return 0;
  1185. }
  1186. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1189. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1190. kcontrol->private_value;
  1191. unsigned int nval, change;
  1192. nval = (ucontrol->value.integer.value[0] & 127) |
  1193. ((ucontrol->value.integer.value[1] & 127) << 16);
  1194. spin_lock_irq(&ice->reg_lock);
  1195. nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
  1196. change = nval != ice->pro_volumes[priv_idx];
  1197. ice->pro_volumes[priv_idx] = nval;
  1198. snd_ice1712_update_volume(ice, priv_idx);
  1199. spin_unlock_irq(&ice->reg_lock);
  1200. return change;
  1201. }
  1202. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1203. static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] __devinitdata = {
  1204. {
  1205. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1206. .name = "Multi Playback Switch",
  1207. .info = snd_ice1712_pro_mixer_switch_info,
  1208. .get = snd_ice1712_pro_mixer_switch_get,
  1209. .put = snd_ice1712_pro_mixer_switch_put,
  1210. .private_value = 0,
  1211. .count = 10,
  1212. },
  1213. {
  1214. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1215. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1216. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1217. .name = "Multi Playback Volume",
  1218. .info = snd_ice1712_pro_mixer_volume_info,
  1219. .get = snd_ice1712_pro_mixer_volume_get,
  1220. .put = snd_ice1712_pro_mixer_volume_put,
  1221. .private_value = 0,
  1222. .count = 10,
  1223. .tlv = { .p = db_scale_playback }
  1224. },
  1225. };
  1226. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch __devinitdata = {
  1227. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1228. .name = "H/W Multi Capture Switch",
  1229. .info = snd_ice1712_pro_mixer_switch_info,
  1230. .get = snd_ice1712_pro_mixer_switch_get,
  1231. .put = snd_ice1712_pro_mixer_switch_put,
  1232. .private_value = 10,
  1233. };
  1234. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch __devinitdata = {
  1235. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1236. .name = SNDRV_CTL_NAME_IEC958("Multi ",CAPTURE,SWITCH),
  1237. .info = snd_ice1712_pro_mixer_switch_info,
  1238. .get = snd_ice1712_pro_mixer_switch_get,
  1239. .put = snd_ice1712_pro_mixer_switch_put,
  1240. .private_value = 18,
  1241. .count = 2,
  1242. };
  1243. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume __devinitdata = {
  1244. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1245. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1246. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1247. .name = "H/W Multi Capture Volume",
  1248. .info = snd_ice1712_pro_mixer_volume_info,
  1249. .get = snd_ice1712_pro_mixer_volume_get,
  1250. .put = snd_ice1712_pro_mixer_volume_put,
  1251. .private_value = 10,
  1252. .tlv = { .p = db_scale_playback }
  1253. };
  1254. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume __devinitdata = {
  1255. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1256. .name = SNDRV_CTL_NAME_IEC958("Multi ",CAPTURE,VOLUME),
  1257. .info = snd_ice1712_pro_mixer_volume_info,
  1258. .get = snd_ice1712_pro_mixer_volume_get,
  1259. .put = snd_ice1712_pro_mixer_volume_put,
  1260. .private_value = 18,
  1261. .count = 2,
  1262. };
  1263. static int __devinit snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1264. {
  1265. struct snd_card *card = ice->card;
  1266. unsigned int idx;
  1267. int err;
  1268. /* multi-channel mixer */
  1269. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1270. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1271. if (err < 0)
  1272. return err;
  1273. }
  1274. if (ice->num_total_adcs > 0) {
  1275. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1276. tmp.count = ice->num_total_adcs;
  1277. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1278. if (err < 0)
  1279. return err;
  1280. }
  1281. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1282. if (err < 0)
  1283. return err;
  1284. if (ice->num_total_adcs > 0) {
  1285. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1286. tmp.count = ice->num_total_adcs;
  1287. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1288. if (err < 0)
  1289. return err;
  1290. }
  1291. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1292. if (err < 0)
  1293. return err;
  1294. /* initialize volumes */
  1295. for (idx = 0; idx < 10; idx++) {
  1296. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1297. snd_ice1712_update_volume(ice, idx);
  1298. }
  1299. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1300. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1301. snd_ice1712_update_volume(ice, idx);
  1302. }
  1303. for (idx = 18; idx < 20; idx++) {
  1304. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1305. snd_ice1712_update_volume(ice, idx);
  1306. }
  1307. return 0;
  1308. }
  1309. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1310. {
  1311. struct snd_ice1712 *ice = ac97->private_data;
  1312. ice->ac97 = NULL;
  1313. }
  1314. static int __devinit snd_ice1712_ac97_mixer(struct snd_ice1712 * ice)
  1315. {
  1316. int err, bus_num = 0;
  1317. struct snd_ac97_template ac97;
  1318. struct snd_ac97_bus *pbus;
  1319. static struct snd_ac97_bus_ops con_ops = {
  1320. .write = snd_ice1712_ac97_write,
  1321. .read = snd_ice1712_ac97_read,
  1322. };
  1323. static struct snd_ac97_bus_ops pro_ops = {
  1324. .write = snd_ice1712_pro_ac97_write,
  1325. .read = snd_ice1712_pro_ac97_read,
  1326. };
  1327. if (ice_has_con_ac97(ice)) {
  1328. if ((err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus)) < 0)
  1329. return err;
  1330. memset(&ac97, 0, sizeof(ac97));
  1331. ac97.private_data = ice;
  1332. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1333. if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0)
  1334. printk(KERN_WARNING "ice1712: cannot initialize ac97 for consumer, skipped\n");
  1335. else {
  1336. if ((err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice))) < 0)
  1337. return err;
  1338. return 0;
  1339. }
  1340. }
  1341. if (! (ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1342. if ((err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus)) < 0)
  1343. return err;
  1344. memset(&ac97, 0, sizeof(ac97));
  1345. ac97.private_data = ice;
  1346. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1347. if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0)
  1348. printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n");
  1349. else
  1350. return 0;
  1351. }
  1352. /* I2S mixer only */
  1353. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1354. return 0;
  1355. }
  1356. /*
  1357. *
  1358. */
  1359. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1360. {
  1361. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1362. }
  1363. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1364. struct snd_info_buffer *buffer)
  1365. {
  1366. struct snd_ice1712 *ice = entry->private_data;
  1367. unsigned int idx;
  1368. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1369. snd_iprintf(buffer, "EEPROM:\n");
  1370. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1371. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1372. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1373. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1374. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1375. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1376. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1377. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1378. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1379. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1380. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1381. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1382. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1383. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1384. for (idx = 0; idx < 4; idx++)
  1385. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1386. for (idx = 0; idx < 4; idx++)
  1387. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1388. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1389. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1390. snd_iprintf(buffer, "\nRegisters:\n");
  1391. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1392. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1393. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1394. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1395. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1396. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1397. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1398. }
  1399. static void __devinit snd_ice1712_proc_init(struct snd_ice1712 * ice)
  1400. {
  1401. struct snd_info_entry *entry;
  1402. if (! snd_card_proc_new(ice->card, "ice1712", &entry))
  1403. snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
  1404. }
  1405. /*
  1406. *
  1407. */
  1408. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1409. struct snd_ctl_elem_info *uinfo)
  1410. {
  1411. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1412. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1413. return 0;
  1414. }
  1415. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1416. struct snd_ctl_elem_value *ucontrol)
  1417. {
  1418. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1419. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1420. return 0;
  1421. }
  1422. static struct snd_kcontrol_new snd_ice1712_eeprom __devinitdata = {
  1423. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1424. .name = "ICE1712 EEPROM",
  1425. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1426. .info = snd_ice1712_eeprom_info,
  1427. .get = snd_ice1712_eeprom_get
  1428. };
  1429. /*
  1430. */
  1431. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1432. struct snd_ctl_elem_info *uinfo)
  1433. {
  1434. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1435. uinfo->count = 1;
  1436. return 0;
  1437. }
  1438. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1439. struct snd_ctl_elem_value *ucontrol)
  1440. {
  1441. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1442. if (ice->spdif.ops.default_get)
  1443. ice->spdif.ops.default_get(ice, ucontrol);
  1444. return 0;
  1445. }
  1446. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1447. struct snd_ctl_elem_value *ucontrol)
  1448. {
  1449. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1450. if (ice->spdif.ops.default_put)
  1451. return ice->spdif.ops.default_put(ice, ucontrol);
  1452. return 0;
  1453. }
  1454. static struct snd_kcontrol_new snd_ice1712_spdif_default __devinitdata =
  1455. {
  1456. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1457. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1458. .info = snd_ice1712_spdif_info,
  1459. .get = snd_ice1712_spdif_default_get,
  1460. .put = snd_ice1712_spdif_default_put
  1461. };
  1462. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1463. struct snd_ctl_elem_value *ucontrol)
  1464. {
  1465. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1466. if (ice->spdif.ops.default_get) {
  1467. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1468. IEC958_AES0_PROFESSIONAL |
  1469. IEC958_AES0_CON_NOT_COPYRIGHT |
  1470. IEC958_AES0_CON_EMPHASIS;
  1471. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1472. IEC958_AES1_CON_CATEGORY;
  1473. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1474. } else {
  1475. ucontrol->value.iec958.status[0] = 0xff;
  1476. ucontrol->value.iec958.status[1] = 0xff;
  1477. ucontrol->value.iec958.status[2] = 0xff;
  1478. ucontrol->value.iec958.status[3] = 0xff;
  1479. ucontrol->value.iec958.status[4] = 0xff;
  1480. }
  1481. return 0;
  1482. }
  1483. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1484. struct snd_ctl_elem_value *ucontrol)
  1485. {
  1486. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1487. if (ice->spdif.ops.default_get) {
  1488. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1489. IEC958_AES0_PROFESSIONAL |
  1490. IEC958_AES0_PRO_FS |
  1491. IEC958_AES0_PRO_EMPHASIS;
  1492. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1493. } else {
  1494. ucontrol->value.iec958.status[0] = 0xff;
  1495. ucontrol->value.iec958.status[1] = 0xff;
  1496. ucontrol->value.iec958.status[2] = 0xff;
  1497. ucontrol->value.iec958.status[3] = 0xff;
  1498. ucontrol->value.iec958.status[4] = 0xff;
  1499. }
  1500. return 0;
  1501. }
  1502. static struct snd_kcontrol_new snd_ice1712_spdif_maskc __devinitdata =
  1503. {
  1504. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1505. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1506. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1507. .info = snd_ice1712_spdif_info,
  1508. .get = snd_ice1712_spdif_maskc_get,
  1509. };
  1510. static struct snd_kcontrol_new snd_ice1712_spdif_maskp __devinitdata =
  1511. {
  1512. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1513. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1514. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
  1515. .info = snd_ice1712_spdif_info,
  1516. .get = snd_ice1712_spdif_maskp_get,
  1517. };
  1518. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1519. struct snd_ctl_elem_value *ucontrol)
  1520. {
  1521. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1522. if (ice->spdif.ops.stream_get)
  1523. ice->spdif.ops.stream_get(ice, ucontrol);
  1524. return 0;
  1525. }
  1526. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1527. struct snd_ctl_elem_value *ucontrol)
  1528. {
  1529. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1530. if (ice->spdif.ops.stream_put)
  1531. return ice->spdif.ops.stream_put(ice, ucontrol);
  1532. return 0;
  1533. }
  1534. static struct snd_kcontrol_new snd_ice1712_spdif_stream __devinitdata =
  1535. {
  1536. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1537. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1538. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1539. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1540. .info = snd_ice1712_spdif_info,
  1541. .get = snd_ice1712_spdif_stream_get,
  1542. .put = snd_ice1712_spdif_stream_put
  1543. };
  1544. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1545. struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1548. unsigned char mask = kcontrol->private_value & 0xff;
  1549. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1550. snd_ice1712_save_gpio_status(ice);
  1551. ucontrol->value.integer.value[0] =
  1552. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1553. snd_ice1712_restore_gpio_status(ice);
  1554. return 0;
  1555. }
  1556. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1557. struct snd_ctl_elem_value *ucontrol)
  1558. {
  1559. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1560. unsigned char mask = kcontrol->private_value & 0xff;
  1561. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1562. unsigned int val, nval;
  1563. if (kcontrol->private_value & (1 << 31))
  1564. return -EPERM;
  1565. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1566. snd_ice1712_save_gpio_status(ice);
  1567. val = snd_ice1712_gpio_read(ice);
  1568. nval |= val & ~mask;
  1569. if (val != nval)
  1570. snd_ice1712_gpio_write(ice, nval);
  1571. snd_ice1712_restore_gpio_status(ice);
  1572. return val != nval;
  1573. }
  1574. /*
  1575. * rate
  1576. */
  1577. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1578. struct snd_ctl_elem_info *uinfo)
  1579. {
  1580. static const char * const texts[] = {
  1581. "8000", /* 0: 6 */
  1582. "9600", /* 1: 3 */
  1583. "11025", /* 2: 10 */
  1584. "12000", /* 3: 2 */
  1585. "16000", /* 4: 5 */
  1586. "22050", /* 5: 9 */
  1587. "24000", /* 6: 1 */
  1588. "32000", /* 7: 4 */
  1589. "44100", /* 8: 8 */
  1590. "48000", /* 9: 0 */
  1591. "64000", /* 10: 15 */
  1592. "88200", /* 11: 11 */
  1593. "96000", /* 12: 7 */
  1594. "IEC958 Input", /* 13: -- */
  1595. };
  1596. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1597. uinfo->count = 1;
  1598. uinfo->value.enumerated.items = 14;
  1599. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1600. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1601. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1602. return 0;
  1603. }
  1604. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1605. struct snd_ctl_elem_value *ucontrol)
  1606. {
  1607. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1608. static const unsigned char xlate[16] = {
  1609. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1610. };
  1611. unsigned char val;
  1612. spin_lock_irq(&ice->reg_lock);
  1613. if (is_spdif_master(ice)) {
  1614. ucontrol->value.enumerated.item[0] = 13;
  1615. } else {
  1616. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1617. if (val == 255) {
  1618. snd_BUG();
  1619. val = 0;
  1620. }
  1621. ucontrol->value.enumerated.item[0] = val;
  1622. }
  1623. spin_unlock_irq(&ice->reg_lock);
  1624. return 0;
  1625. }
  1626. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1627. struct snd_ctl_elem_value *ucontrol)
  1628. {
  1629. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1630. static const unsigned int xrate[13] = {
  1631. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1632. 32000, 44100, 48000, 64000, 88200, 96000
  1633. };
  1634. unsigned char oval;
  1635. int change = 0;
  1636. spin_lock_irq(&ice->reg_lock);
  1637. oval = inb(ICEMT(ice, RATE));
  1638. if (ucontrol->value.enumerated.item[0] == 13) {
  1639. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1640. } else {
  1641. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1642. spin_unlock_irq(&ice->reg_lock);
  1643. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1644. spin_lock_irq(&ice->reg_lock);
  1645. }
  1646. change = inb(ICEMT(ice, RATE)) != oval;
  1647. spin_unlock_irq(&ice->reg_lock);
  1648. if ((oval & ICE1712_SPDIF_MASTER) !=
  1649. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1650. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1651. return change;
  1652. }
  1653. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock __devinitdata = {
  1654. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1655. .name = "Multi Track Internal Clock",
  1656. .info = snd_ice1712_pro_internal_clock_info,
  1657. .get = snd_ice1712_pro_internal_clock_get,
  1658. .put = snd_ice1712_pro_internal_clock_put
  1659. };
  1660. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1661. struct snd_ctl_elem_info *uinfo)
  1662. {
  1663. static const char * const texts[] = {
  1664. "8000", /* 0: 6 */
  1665. "9600", /* 1: 3 */
  1666. "11025", /* 2: 10 */
  1667. "12000", /* 3: 2 */
  1668. "16000", /* 4: 5 */
  1669. "22050", /* 5: 9 */
  1670. "24000", /* 6: 1 */
  1671. "32000", /* 7: 4 */
  1672. "44100", /* 8: 8 */
  1673. "48000", /* 9: 0 */
  1674. "64000", /* 10: 15 */
  1675. "88200", /* 11: 11 */
  1676. "96000", /* 12: 7 */
  1677. // "IEC958 Input", /* 13: -- */
  1678. };
  1679. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1680. uinfo->count = 1;
  1681. uinfo->value.enumerated.items = 13;
  1682. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1683. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1684. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1685. return 0;
  1686. }
  1687. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1688. struct snd_ctl_elem_value *ucontrol)
  1689. {
  1690. int val;
  1691. static const unsigned int xrate[13] = {
  1692. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1693. 32000, 44100, 48000, 64000, 88200, 96000
  1694. };
  1695. for (val = 0; val < 13; val++) {
  1696. if (xrate[val] == PRO_RATE_DEFAULT)
  1697. break;
  1698. }
  1699. ucontrol->value.enumerated.item[0] = val;
  1700. return 0;
  1701. }
  1702. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1703. struct snd_ctl_elem_value *ucontrol)
  1704. {
  1705. static const unsigned int xrate[13] = {
  1706. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1707. 32000, 44100, 48000, 64000, 88200, 96000
  1708. };
  1709. unsigned char oval;
  1710. int change = 0;
  1711. oval = PRO_RATE_DEFAULT;
  1712. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1713. change = PRO_RATE_DEFAULT != oval;
  1714. return change;
  1715. }
  1716. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default __devinitdata = {
  1717. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1718. .name = "Multi Track Internal Clock Default",
  1719. .info = snd_ice1712_pro_internal_clock_default_info,
  1720. .get = snd_ice1712_pro_internal_clock_default_get,
  1721. .put = snd_ice1712_pro_internal_clock_default_put
  1722. };
  1723. #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
  1724. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1725. struct snd_ctl_elem_value *ucontrol)
  1726. {
  1727. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1728. return 0;
  1729. }
  1730. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1731. struct snd_ctl_elem_value *ucontrol)
  1732. {
  1733. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1734. int change = 0, nval;
  1735. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1736. spin_lock_irq(&ice->reg_lock);
  1737. change = PRO_RATE_LOCKED != nval;
  1738. PRO_RATE_LOCKED = nval;
  1739. spin_unlock_irq(&ice->reg_lock);
  1740. return change;
  1741. }
  1742. static struct snd_kcontrol_new snd_ice1712_pro_rate_locking __devinitdata = {
  1743. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1744. .name = "Multi Track Rate Locking",
  1745. .info = snd_ice1712_pro_rate_locking_info,
  1746. .get = snd_ice1712_pro_rate_locking_get,
  1747. .put = snd_ice1712_pro_rate_locking_put
  1748. };
  1749. #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
  1750. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1751. struct snd_ctl_elem_value *ucontrol)
  1752. {
  1753. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1754. return 0;
  1755. }
  1756. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1757. struct snd_ctl_elem_value *ucontrol)
  1758. {
  1759. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1760. int change = 0, nval;
  1761. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1762. spin_lock_irq(&ice->reg_lock);
  1763. change = PRO_RATE_RESET != nval;
  1764. PRO_RATE_RESET = nval;
  1765. spin_unlock_irq(&ice->reg_lock);
  1766. return change;
  1767. }
  1768. static struct snd_kcontrol_new snd_ice1712_pro_rate_reset __devinitdata = {
  1769. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1770. .name = "Multi Track Rate Reset",
  1771. .info = snd_ice1712_pro_rate_reset_info,
  1772. .get = snd_ice1712_pro_rate_reset_get,
  1773. .put = snd_ice1712_pro_rate_reset_put
  1774. };
  1775. /*
  1776. * routing
  1777. */
  1778. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1779. struct snd_ctl_elem_info *uinfo)
  1780. {
  1781. static const char * const texts[] = {
  1782. "PCM Out", /* 0 */
  1783. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1784. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1785. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1786. "Digital Mixer", /* 11 - optional */
  1787. };
  1788. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1789. uinfo->count = 1;
  1790. uinfo->value.enumerated.items =
  1791. snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1792. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1793. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1794. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1795. return 0;
  1796. }
  1797. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1798. struct snd_ctl_elem_value *ucontrol)
  1799. {
  1800. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1801. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1802. unsigned int val, cval;
  1803. spin_lock_irq(&ice->reg_lock);
  1804. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1805. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1806. spin_unlock_irq(&ice->reg_lock);
  1807. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1808. val &= 3;
  1809. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1810. if (val == 1 && idx < 2)
  1811. ucontrol->value.enumerated.item[0] = 11;
  1812. else if (val == 2)
  1813. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1814. else if (val == 3)
  1815. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1816. else
  1817. ucontrol->value.enumerated.item[0] = 0;
  1818. return 0;
  1819. }
  1820. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1821. struct snd_ctl_elem_value *ucontrol)
  1822. {
  1823. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1824. int change, shift;
  1825. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1826. unsigned int val, old_val, nval;
  1827. /* update PSDOUT */
  1828. if (ucontrol->value.enumerated.item[0] >= 11)
  1829. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1830. else if (ucontrol->value.enumerated.item[0] >= 9)
  1831. nval = 3; /* spdif in */
  1832. else if (ucontrol->value.enumerated.item[0] >= 1)
  1833. nval = 2; /* analog in */
  1834. else
  1835. nval = 0; /* pcm */
  1836. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1837. spin_lock_irq(&ice->reg_lock);
  1838. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1839. val &= ~(0x03 << shift);
  1840. val |= nval << shift;
  1841. change = val != old_val;
  1842. if (change)
  1843. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1844. spin_unlock_irq(&ice->reg_lock);
  1845. if (nval < 2) /* dig mixer of pcm */
  1846. return change;
  1847. /* update CAPTURE */
  1848. spin_lock_irq(&ice->reg_lock);
  1849. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1850. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1851. if (nval == 2) { /* analog in */
  1852. nval = ucontrol->value.enumerated.item[0] - 1;
  1853. val &= ~(0x07 << shift);
  1854. val |= nval << shift;
  1855. } else { /* spdif in */
  1856. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1857. val &= ~(0x08 << shift);
  1858. val |= nval << shift;
  1859. }
  1860. if (val != old_val) {
  1861. change = 1;
  1862. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1863. }
  1864. spin_unlock_irq(&ice->reg_lock);
  1865. return change;
  1866. }
  1867. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1868. struct snd_ctl_elem_value *ucontrol)
  1869. {
  1870. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1871. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1872. unsigned int val, cval;
  1873. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1874. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1875. val = (val >> (idx * 2)) & 0x03;
  1876. if (val == 1)
  1877. ucontrol->value.enumerated.item[0] = 11;
  1878. else if (val == 2)
  1879. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1880. else if (val == 3)
  1881. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1882. else
  1883. ucontrol->value.enumerated.item[0] = 0;
  1884. return 0;
  1885. }
  1886. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1887. struct snd_ctl_elem_value *ucontrol)
  1888. {
  1889. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1890. int change, shift;
  1891. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1892. unsigned int val, old_val, nval;
  1893. /* update SPDOUT */
  1894. spin_lock_irq(&ice->reg_lock);
  1895. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1896. if (ucontrol->value.enumerated.item[0] >= 11)
  1897. nval = 1;
  1898. else if (ucontrol->value.enumerated.item[0] >= 9)
  1899. nval = 3;
  1900. else if (ucontrol->value.enumerated.item[0] >= 1)
  1901. nval = 2;
  1902. else
  1903. nval = 0;
  1904. shift = idx * 2;
  1905. val &= ~(0x03 << shift);
  1906. val |= nval << shift;
  1907. shift = idx * 4 + 8;
  1908. if (nval == 2) {
  1909. nval = ucontrol->value.enumerated.item[0] - 1;
  1910. val &= ~(0x07 << shift);
  1911. val |= nval << shift;
  1912. } else if (nval == 3) {
  1913. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1914. val &= ~(0x08 << shift);
  1915. val |= nval << shift;
  1916. }
  1917. change = val != old_val;
  1918. if (change)
  1919. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1920. spin_unlock_irq(&ice->reg_lock);
  1921. return change;
  1922. }
  1923. static struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route __devinitdata = {
  1924. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1925. .name = "H/W Playback Route",
  1926. .info = snd_ice1712_pro_route_info,
  1927. .get = snd_ice1712_pro_route_analog_get,
  1928. .put = snd_ice1712_pro_route_analog_put,
  1929. };
  1930. static struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route __devinitdata = {
  1931. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1932. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Route",
  1933. .info = snd_ice1712_pro_route_info,
  1934. .get = snd_ice1712_pro_route_spdif_get,
  1935. .put = snd_ice1712_pro_route_spdif_put,
  1936. .count = 2,
  1937. };
  1938. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1939. struct snd_ctl_elem_info *uinfo)
  1940. {
  1941. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1942. uinfo->count = 1;
  1943. uinfo->value.integer.min = 0;
  1944. uinfo->value.integer.max = 255;
  1945. return 0;
  1946. }
  1947. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1948. struct snd_ctl_elem_value *ucontrol)
  1949. {
  1950. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1951. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1952. return 0;
  1953. }
  1954. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1955. struct snd_ctl_elem_value *ucontrol)
  1956. {
  1957. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1958. int change;
  1959. spin_lock_irq(&ice->reg_lock);
  1960. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1961. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1962. spin_unlock_irq(&ice->reg_lock);
  1963. return change;
  1964. }
  1965. static struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate __devinitdata = {
  1966. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1967. .name = "Multi Track Volume Rate",
  1968. .info = snd_ice1712_pro_volume_rate_info,
  1969. .get = snd_ice1712_pro_volume_rate_get,
  1970. .put = snd_ice1712_pro_volume_rate_put
  1971. };
  1972. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  1973. struct snd_ctl_elem_info *uinfo)
  1974. {
  1975. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1976. uinfo->count = 22;
  1977. uinfo->value.integer.min = 0;
  1978. uinfo->value.integer.max = 255;
  1979. return 0;
  1980. }
  1981. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  1982. struct snd_ctl_elem_value *ucontrol)
  1983. {
  1984. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1985. int idx;
  1986. spin_lock_irq(&ice->reg_lock);
  1987. for (idx = 0; idx < 22; idx++) {
  1988. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  1989. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  1990. }
  1991. spin_unlock_irq(&ice->reg_lock);
  1992. return 0;
  1993. }
  1994. static struct snd_kcontrol_new snd_ice1712_mixer_pro_peak __devinitdata = {
  1995. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1996. .name = "Multi Track Peak",
  1997. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1998. .info = snd_ice1712_pro_peak_info,
  1999. .get = snd_ice1712_pro_peak_get
  2000. };
  2001. /*
  2002. *
  2003. */
  2004. /*
  2005. * list of available boards
  2006. */
  2007. static struct snd_ice1712_card_info *card_tables[] __devinitdata = {
  2008. snd_ice1712_hoontech_cards,
  2009. snd_ice1712_delta_cards,
  2010. snd_ice1712_ews_cards,
  2011. NULL,
  2012. };
  2013. static unsigned char __devinit snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  2014. unsigned char dev,
  2015. unsigned char addr)
  2016. {
  2017. long t = 0x10000;
  2018. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  2019. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  2020. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  2021. return inb(ICEREG(ice, I2C_DATA));
  2022. }
  2023. static int __devinit snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  2024. const char *modelname)
  2025. {
  2026. int dev = 0xa0; /* EEPROM device address */
  2027. unsigned int i, size;
  2028. struct snd_ice1712_card_info * const *tbl, *c;
  2029. if (! modelname || ! *modelname) {
  2030. ice->eeprom.subvendor = 0;
  2031. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  2032. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  2033. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  2034. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  2035. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  2036. if (ice->eeprom.subvendor == 0 ||
  2037. ice->eeprom.subvendor == (unsigned int)-1) {
  2038. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  2039. u16 vendor, device;
  2040. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  2041. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2042. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2043. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  2044. printk(KERN_ERR "ice1712: No valid ID is found\n");
  2045. return -ENXIO;
  2046. }
  2047. }
  2048. }
  2049. for (tbl = card_tables; *tbl; tbl++) {
  2050. for (c = *tbl; c->subvendor; c++) {
  2051. if (modelname && c->model && ! strcmp(modelname, c->model)) {
  2052. printk(KERN_INFO "ice1712: Using board model %s\n", c->name);
  2053. ice->eeprom.subvendor = c->subvendor;
  2054. } else if (c->subvendor != ice->eeprom.subvendor)
  2055. continue;
  2056. if (! c->eeprom_size || ! c->eeprom_data)
  2057. goto found;
  2058. /* if the EEPROM is given by the driver, use it */
  2059. snd_printdd("using the defined eeprom..\n");
  2060. ice->eeprom.version = 1;
  2061. ice->eeprom.size = c->eeprom_size + 6;
  2062. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2063. goto read_skipped;
  2064. }
  2065. }
  2066. printk(KERN_WARNING "ice1712: No matching model found for ID 0x%x\n",
  2067. ice->eeprom.subvendor);
  2068. found:
  2069. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2070. if (ice->eeprom.size < 6)
  2071. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2072. else if (ice->eeprom.size > 32) {
  2073. snd_printk(KERN_ERR "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2074. return -EIO;
  2075. }
  2076. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2077. if (ice->eeprom.version != 1) {
  2078. snd_printk(KERN_ERR "invalid EEPROM version %i\n",
  2079. ice->eeprom.version);
  2080. /* return -EIO; */
  2081. }
  2082. size = ice->eeprom.size - 6;
  2083. for (i = 0; i < size; i++)
  2084. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2085. read_skipped:
  2086. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2087. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2088. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2089. return 0;
  2090. }
  2091. static int __devinit snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2092. {
  2093. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2094. udelay(200);
  2095. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2096. udelay(200);
  2097. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2098. !ice->dxr_enable)
  2099. /* Set eeprom value to limit active ADCs and DACs to 6;
  2100. * Also disable AC97 as no hardware in standard 6fire card/box
  2101. * Note: DXR extensions are not currently supported
  2102. */
  2103. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2104. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2105. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2106. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2107. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2108. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
  2109. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2110. ice->gpio.direction = ice->eeprom.gpiodir;
  2111. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2112. ice->eeprom.gpiomask);
  2113. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2114. ice->eeprom.gpiodir);
  2115. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2116. ice->eeprom.gpiostate);
  2117. } else {
  2118. ice->gpio.write_mask = 0xc0;
  2119. ice->gpio.direction = 0xff;
  2120. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2121. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2122. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2123. ICE1712_STDSP24_CLOCK_BIT);
  2124. }
  2125. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2126. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2127. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2128. udelay(100);
  2129. outb(0, ICEREG(ice, AC97_CMD));
  2130. udelay(200);
  2131. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2132. }
  2133. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2134. return 0;
  2135. }
  2136. int __devinit snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2137. {
  2138. int err;
  2139. struct snd_kcontrol *kctl;
  2140. snd_assert(ice->pcm_pro != NULL, return -EIO);
  2141. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
  2142. if (err < 0)
  2143. return err;
  2144. kctl->id.device = ice->pcm_pro->device;
  2145. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
  2146. if (err < 0)
  2147. return err;
  2148. kctl->id.device = ice->pcm_pro->device;
  2149. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
  2150. if (err < 0)
  2151. return err;
  2152. kctl->id.device = ice->pcm_pro->device;
  2153. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
  2154. if (err < 0)
  2155. return err;
  2156. kctl->id.device = ice->pcm_pro->device;
  2157. ice->spdif.stream_ctl = kctl;
  2158. return 0;
  2159. }
  2160. static int __devinit snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2161. {
  2162. int err;
  2163. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2164. if (err < 0)
  2165. return err;
  2166. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2167. if (err < 0)
  2168. return err;
  2169. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2170. if (err < 0)
  2171. return err;
  2172. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2173. if (err < 0)
  2174. return err;
  2175. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2176. if (err < 0)
  2177. return err;
  2178. if (ice->num_total_dacs > 0) {
  2179. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2180. tmp.count = ice->num_total_dacs;
  2181. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2182. if (err < 0)
  2183. return err;
  2184. }
  2185. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2186. if (err < 0)
  2187. return err;
  2188. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2189. if (err < 0)
  2190. return err;
  2191. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2192. if (err < 0)
  2193. return err;
  2194. return 0;
  2195. }
  2196. static int snd_ice1712_free(struct snd_ice1712 *ice)
  2197. {
  2198. if (! ice->port)
  2199. goto __hw_end;
  2200. /* mask all interrupts */
  2201. outb(0xc0, ICEMT(ice, IRQ));
  2202. outb(0xff, ICEREG(ice, IRQMASK));
  2203. /* --- */
  2204. __hw_end:
  2205. if (ice->irq >= 0)
  2206. free_irq(ice->irq, ice);
  2207. if (ice->port)
  2208. pci_release_regions(ice->pci);
  2209. snd_ice1712_akm4xxx_free(ice);
  2210. pci_disable_device(ice->pci);
  2211. kfree(ice->spec);
  2212. kfree(ice);
  2213. return 0;
  2214. }
  2215. static int snd_ice1712_dev_free(struct snd_device *device)
  2216. {
  2217. struct snd_ice1712 *ice = device->device_data;
  2218. return snd_ice1712_free(ice);
  2219. }
  2220. static int __devinit snd_ice1712_create(struct snd_card *card,
  2221. struct pci_dev *pci,
  2222. const char *modelname,
  2223. int omni,
  2224. int cs8427_timeout,
  2225. int dxr_enable,
  2226. struct snd_ice1712 ** r_ice1712)
  2227. {
  2228. struct snd_ice1712 *ice;
  2229. int err;
  2230. static struct snd_device_ops ops = {
  2231. .dev_free = snd_ice1712_dev_free,
  2232. };
  2233. *r_ice1712 = NULL;
  2234. /* enable PCI device */
  2235. if ((err = pci_enable_device(pci)) < 0)
  2236. return err;
  2237. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2238. if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
  2239. pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
  2240. snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
  2241. pci_disable_device(pci);
  2242. return -ENXIO;
  2243. }
  2244. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2245. if (ice == NULL) {
  2246. pci_disable_device(pci);
  2247. return -ENOMEM;
  2248. }
  2249. ice->omni = omni ? 1 : 0;
  2250. if (cs8427_timeout < 1)
  2251. cs8427_timeout = 1;
  2252. else if (cs8427_timeout > 1000)
  2253. cs8427_timeout = 1000;
  2254. ice->cs8427_timeout = cs8427_timeout;
  2255. ice->dxr_enable = dxr_enable;
  2256. spin_lock_init(&ice->reg_lock);
  2257. mutex_init(&ice->gpio_mutex);
  2258. mutex_init(&ice->i2c_mutex);
  2259. mutex_init(&ice->open_mutex);
  2260. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2261. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2262. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2263. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2264. ice->spdif.cs8403_bits =
  2265. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2266. 0x10 | /* no emphasis */
  2267. 0x20); /* PCM encoder/decoder */
  2268. ice->card = card;
  2269. ice->pci = pci;
  2270. ice->irq = -1;
  2271. pci_set_master(pci);
  2272. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2273. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2274. snd_ice1712_proc_init(ice);
  2275. synchronize_irq(pci->irq);
  2276. if ((err = pci_request_regions(pci, "ICE1712")) < 0) {
  2277. kfree(ice);
  2278. pci_disable_device(pci);
  2279. return err;
  2280. }
  2281. ice->port = pci_resource_start(pci, 0);
  2282. ice->ddma_port = pci_resource_start(pci, 1);
  2283. ice->dmapath_port = pci_resource_start(pci, 2);
  2284. ice->profi_port = pci_resource_start(pci, 3);
  2285. if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
  2286. "ICE1712", ice)) {
  2287. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2288. snd_ice1712_free(ice);
  2289. return -EIO;
  2290. }
  2291. ice->irq = pci->irq;
  2292. if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
  2293. snd_ice1712_free(ice);
  2294. return -EIO;
  2295. }
  2296. if (snd_ice1712_chip_init(ice) < 0) {
  2297. snd_ice1712_free(ice);
  2298. return -EIO;
  2299. }
  2300. /* unmask used interrupts */
  2301. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2302. ICE1712_IRQ_MPU2 : 0) |
  2303. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2304. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2305. ICEREG(ice, IRQMASK));
  2306. outb(0x00, ICEMT(ice, IRQ));
  2307. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops)) < 0) {
  2308. snd_ice1712_free(ice);
  2309. return err;
  2310. }
  2311. snd_card_set_dev(card, &pci->dev);
  2312. *r_ice1712 = ice;
  2313. return 0;
  2314. }
  2315. /*
  2316. *
  2317. * Registration
  2318. *
  2319. */
  2320. static struct snd_ice1712_card_info no_matched __devinitdata;
  2321. static int __devinit snd_ice1712_probe(struct pci_dev *pci,
  2322. const struct pci_device_id *pci_id)
  2323. {
  2324. static int dev;
  2325. struct snd_card *card;
  2326. struct snd_ice1712 *ice;
  2327. int pcm_dev = 0, err;
  2328. struct snd_ice1712_card_info * const *tbl, *c;
  2329. if (dev >= SNDRV_CARDS)
  2330. return -ENODEV;
  2331. if (!enable[dev]) {
  2332. dev++;
  2333. return -ENOENT;
  2334. }
  2335. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  2336. if (card == NULL)
  2337. return -ENOMEM;
  2338. strcpy(card->driver, "ICE1712");
  2339. strcpy(card->shortname, "ICEnsemble ICE1712");
  2340. if ((err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2341. cs8427_timeout[dev], dxr_enable[dev],
  2342. &ice)) < 0) {
  2343. snd_card_free(card);
  2344. return err;
  2345. }
  2346. for (tbl = card_tables; *tbl; tbl++) {
  2347. for (c = *tbl; c->subvendor; c++) {
  2348. if (c->subvendor == ice->eeprom.subvendor) {
  2349. strcpy(card->shortname, c->name);
  2350. if (c->driver) /* specific driver? */
  2351. strcpy(card->driver, c->driver);
  2352. if (c->chip_init) {
  2353. if ((err = c->chip_init(ice)) < 0) {
  2354. snd_card_free(card);
  2355. return err;
  2356. }
  2357. }
  2358. goto __found;
  2359. }
  2360. }
  2361. }
  2362. c = &no_matched;
  2363. __found:
  2364. if ((err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL)) < 0) {
  2365. snd_card_free(card);
  2366. return err;
  2367. }
  2368. if (ice_has_con_ac97(ice))
  2369. if ((err = snd_ice1712_pcm(ice, pcm_dev++, NULL)) < 0) {
  2370. snd_card_free(card);
  2371. return err;
  2372. }
  2373. if ((err = snd_ice1712_ac97_mixer(ice)) < 0) {
  2374. snd_card_free(card);
  2375. return err;
  2376. }
  2377. if ((err = snd_ice1712_build_controls(ice)) < 0) {
  2378. snd_card_free(card);
  2379. return err;
  2380. }
  2381. if (c->build_controls) {
  2382. if ((err = c->build_controls(ice)) < 0) {
  2383. snd_card_free(card);
  2384. return err;
  2385. }
  2386. }
  2387. if (ice_has_con_ac97(ice))
  2388. if ((err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL)) < 0) {
  2389. snd_card_free(card);
  2390. return err;
  2391. }
  2392. if (! c->no_mpu401) {
  2393. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2394. ICEREG(ice, MPU1_CTRL),
  2395. (c->mpu401_1_info_flags |
  2396. MPU401_INFO_INTEGRATED),
  2397. ice->irq, 0,
  2398. &ice->rmidi[0])) < 0) {
  2399. snd_card_free(card);
  2400. return err;
  2401. }
  2402. if (c->mpu401_1_name)
  2403. /* Prefered name available in card_info */
  2404. snprintf(ice->rmidi[0]->name,
  2405. sizeof(ice->rmidi[0]->name),
  2406. "%s %d", c->mpu401_1_name, card->number);
  2407. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2408. /* 2nd port used */
  2409. if ((err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2410. ICEREG(ice, MPU2_CTRL),
  2411. (c->mpu401_2_info_flags |
  2412. MPU401_INFO_INTEGRATED),
  2413. ice->irq, 0,
  2414. &ice->rmidi[1])) < 0) {
  2415. snd_card_free(card);
  2416. return err;
  2417. }
  2418. if (c->mpu401_2_name)
  2419. /* Prefered name available in card_info */
  2420. snprintf(ice->rmidi[1]->name,
  2421. sizeof(ice->rmidi[1]->name),
  2422. "%s %d", c->mpu401_2_name,
  2423. card->number);
  2424. }
  2425. }
  2426. snd_ice1712_set_input_clock_source(ice, 0);
  2427. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2428. card->shortname, ice->port, ice->irq);
  2429. if ((err = snd_card_register(card)) < 0) {
  2430. snd_card_free(card);
  2431. return err;
  2432. }
  2433. pci_set_drvdata(pci, card);
  2434. dev++;
  2435. return 0;
  2436. }
  2437. static void __devexit snd_ice1712_remove(struct pci_dev *pci)
  2438. {
  2439. snd_card_free(pci_get_drvdata(pci));
  2440. pci_set_drvdata(pci, NULL);
  2441. }
  2442. static struct pci_driver driver = {
  2443. .name = "ICE1712",
  2444. .id_table = snd_ice1712_ids,
  2445. .probe = snd_ice1712_probe,
  2446. .remove = __devexit_p(snd_ice1712_remove),
  2447. };
  2448. static int __init alsa_card_ice1712_init(void)
  2449. {
  2450. return pci_register_driver(&driver);
  2451. }
  2452. static void __exit alsa_card_ice1712_exit(void)
  2453. {
  2454. pci_unregister_driver(&driver);
  2455. }
  2456. module_init(alsa_card_ice1712_init)
  2457. module_exit(alsa_card_ice1712_exit)