cs4231_lib.c 61 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945
  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
  4. *
  5. * Bugs:
  6. * - sometimes record brokes playback with WSS portion of
  7. * Yamaha OPL3-SA3 chip
  8. * - CS4231 (GUS MAX) - still trouble with occasional noises
  9. * - broken initialization?
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/pm.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/slab.h>
  31. #include <linux/ioport.h>
  32. #include <sound/core.h>
  33. #include <sound/cs4231.h>
  34. #include <sound/pcm_params.h>
  35. #include <asm/io.h>
  36. #include <asm/dma.h>
  37. #include <asm/irq.h>
  38. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  39. MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
  40. MODULE_LICENSE("GPL");
  41. #if 0
  42. #define SNDRV_DEBUG_MCE
  43. #endif
  44. /*
  45. * Some variables
  46. */
  47. static unsigned char freq_bits[14] = {
  48. /* 5510 */ 0x00 | CS4231_XTAL2,
  49. /* 6620 */ 0x0E | CS4231_XTAL2,
  50. /* 8000 */ 0x00 | CS4231_XTAL1,
  51. /* 9600 */ 0x0E | CS4231_XTAL1,
  52. /* 11025 */ 0x02 | CS4231_XTAL2,
  53. /* 16000 */ 0x02 | CS4231_XTAL1,
  54. /* 18900 */ 0x04 | CS4231_XTAL2,
  55. /* 22050 */ 0x06 | CS4231_XTAL2,
  56. /* 27042 */ 0x04 | CS4231_XTAL1,
  57. /* 32000 */ 0x06 | CS4231_XTAL1,
  58. /* 33075 */ 0x0C | CS4231_XTAL2,
  59. /* 37800 */ 0x08 | CS4231_XTAL2,
  60. /* 44100 */ 0x0A | CS4231_XTAL2,
  61. /* 48000 */ 0x0C | CS4231_XTAL1
  62. };
  63. static unsigned int rates[14] = {
  64. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  65. 27042, 32000, 33075, 37800, 44100, 48000
  66. };
  67. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  68. .count = ARRAY_SIZE(rates),
  69. .list = rates,
  70. .mask = 0,
  71. };
  72. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  73. {
  74. return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  75. }
  76. static unsigned char snd_cs4231_original_image[32] =
  77. {
  78. 0x00, /* 00/00 - lic */
  79. 0x00, /* 01/01 - ric */
  80. 0x9f, /* 02/02 - la1ic */
  81. 0x9f, /* 03/03 - ra1ic */
  82. 0x9f, /* 04/04 - la2ic */
  83. 0x9f, /* 05/05 - ra2ic */
  84. 0xbf, /* 06/06 - loc */
  85. 0xbf, /* 07/07 - roc */
  86. 0x20, /* 08/08 - pdfr */
  87. CS4231_AUTOCALIB, /* 09/09 - ic */
  88. 0x00, /* 0a/10 - pc */
  89. 0x00, /* 0b/11 - ti */
  90. CS4231_MODE2, /* 0c/12 - mi */
  91. 0xfc, /* 0d/13 - lbc */
  92. 0x00, /* 0e/14 - pbru */
  93. 0x00, /* 0f/15 - pbrl */
  94. 0x80, /* 10/16 - afei */
  95. 0x01, /* 11/17 - afeii */
  96. 0x9f, /* 12/18 - llic */
  97. 0x9f, /* 13/19 - rlic */
  98. 0x00, /* 14/20 - tlb */
  99. 0x00, /* 15/21 - thb */
  100. 0x00, /* 16/22 - la3mic/reserved */
  101. 0x00, /* 17/23 - ra3mic/reserved */
  102. 0x00, /* 18/24 - afs */
  103. 0x00, /* 19/25 - lamoc/version */
  104. 0xcf, /* 1a/26 - mioc */
  105. 0x00, /* 1b/27 - ramoc/reserved */
  106. 0x20, /* 1c/28 - cdfr */
  107. 0x00, /* 1d/29 - res4 */
  108. 0x00, /* 1e/30 - cbru */
  109. 0x00, /* 1f/31 - cbrl */
  110. };
  111. static unsigned char snd_opti93x_original_image[32] =
  112. {
  113. 0x00, /* 00/00 - l_mixout_outctrl */
  114. 0x00, /* 01/01 - r_mixout_outctrl */
  115. 0x88, /* 02/02 - l_cd_inctrl */
  116. 0x88, /* 03/03 - r_cd_inctrl */
  117. 0x88, /* 04/04 - l_a1/fm_inctrl */
  118. 0x88, /* 05/05 - r_a1/fm_inctrl */
  119. 0x80, /* 06/06 - l_dac_inctrl */
  120. 0x80, /* 07/07 - r_dac_inctrl */
  121. 0x00, /* 08/08 - ply_dataform_reg */
  122. 0x00, /* 09/09 - if_conf */
  123. 0x00, /* 0a/10 - pin_ctrl */
  124. 0x00, /* 0b/11 - err_init_reg */
  125. 0x0a, /* 0c/12 - id_reg */
  126. 0x00, /* 0d/13 - reserved */
  127. 0x00, /* 0e/14 - ply_upcount_reg */
  128. 0x00, /* 0f/15 - ply_lowcount_reg */
  129. 0x88, /* 10/16 - reserved/l_a1_inctrl */
  130. 0x88, /* 11/17 - reserved/r_a1_inctrl */
  131. 0x88, /* 12/18 - l_line_inctrl */
  132. 0x88, /* 13/19 - r_line_inctrl */
  133. 0x88, /* 14/20 - l_mic_inctrl */
  134. 0x88, /* 15/21 - r_mic_inctrl */
  135. 0x80, /* 16/22 - l_out_outctrl */
  136. 0x80, /* 17/23 - r_out_outctrl */
  137. 0x00, /* 18/24 - reserved */
  138. 0x00, /* 19/25 - reserved */
  139. 0x00, /* 1a/26 - reserved */
  140. 0x00, /* 1b/27 - reserved */
  141. 0x00, /* 1c/28 - cap_dataform_reg */
  142. 0x00, /* 1d/29 - reserved */
  143. 0x00, /* 1e/30 - cap_upcount_reg */
  144. 0x00 /* 1f/31 - cap_lowcount_reg */
  145. };
  146. /*
  147. * Basic I/O functions
  148. */
  149. static inline void cs4231_outb(struct snd_cs4231 *chip, u8 offset, u8 val)
  150. {
  151. outb(val, chip->port + offset);
  152. }
  153. static inline u8 cs4231_inb(struct snd_cs4231 *chip, u8 offset)
  154. {
  155. return inb(chip->port + offset);
  156. }
  157. static void snd_cs4231_wait(struct snd_cs4231 *chip)
  158. {
  159. int timeout;
  160. for (timeout = 250;
  161. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  162. timeout--)
  163. udelay(100);
  164. }
  165. static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  166. unsigned char mask, unsigned char value)
  167. {
  168. unsigned char tmp = (chip->image[reg] & mask) | value;
  169. snd_cs4231_wait(chip);
  170. #ifdef CONFIG_SND_DEBUG
  171. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  172. snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  173. #endif
  174. chip->image[reg] = tmp;
  175. if (!chip->calibrate_mute) {
  176. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  177. wmb();
  178. cs4231_outb(chip, CS4231P(REG), tmp);
  179. mb();
  180. }
  181. }
  182. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  183. {
  184. int timeout;
  185. for (timeout = 250;
  186. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  187. timeout--)
  188. udelay(10);
  189. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  190. cs4231_outb(chip, CS4231P(REG), value);
  191. mb();
  192. }
  193. void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  194. {
  195. snd_cs4231_wait(chip);
  196. #ifdef CONFIG_SND_DEBUG
  197. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  198. snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  199. #endif
  200. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  201. cs4231_outb(chip, CS4231P(REG), value);
  202. chip->image[reg] = value;
  203. mb();
  204. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  205. chip->mce_bit | reg, value);
  206. }
  207. unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  208. {
  209. snd_cs4231_wait(chip);
  210. #ifdef CONFIG_SND_DEBUG
  211. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  212. snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
  213. #endif
  214. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  215. mb();
  216. return cs4231_inb(chip, CS4231P(REG));
  217. }
  218. void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val)
  219. {
  220. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  221. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  222. cs4231_outb(chip, CS4231P(REG), val);
  223. chip->eimage[CS4236_REG(reg)] = val;
  224. #if 0
  225. printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
  226. #endif
  227. }
  228. unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg)
  229. {
  230. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  231. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  232. #if 1
  233. return cs4231_inb(chip, CS4231P(REG));
  234. #else
  235. {
  236. unsigned char res;
  237. res = cs4231_inb(chip, CS4231P(REG));
  238. printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
  239. return res;
  240. }
  241. #endif
  242. }
  243. #if 0
  244. static void snd_cs4231_debug(struct snd_cs4231 *chip)
  245. {
  246. printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL)));
  247. printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS)));
  248. printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
  249. printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
  250. printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
  251. printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
  252. printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
  253. printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
  254. printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
  255. printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
  256. printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
  257. printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
  258. printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
  259. printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
  260. printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
  261. printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
  262. printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
  263. printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
  264. printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
  265. printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
  266. printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
  267. printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
  268. printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
  269. printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
  270. printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
  271. printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
  272. printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
  273. printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
  274. printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
  275. printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
  276. printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
  277. printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
  278. printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
  279. printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
  280. }
  281. #endif
  282. /*
  283. * CS4231 detection / MCE routines
  284. */
  285. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  286. {
  287. int timeout;
  288. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  289. for (timeout = 5; timeout > 0; timeout--)
  290. cs4231_inb(chip, CS4231P(REGSEL));
  291. /* end of cleanup sequence */
  292. for (timeout = 250;
  293. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  294. timeout--)
  295. udelay(10);
  296. }
  297. void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  298. {
  299. unsigned long flags;
  300. int timeout;
  301. snd_cs4231_wait(chip);
  302. #ifdef CONFIG_SND_DEBUG
  303. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  304. snd_printk("mce_up - auto calibration time out (0)\n");
  305. #endif
  306. spin_lock_irqsave(&chip->reg_lock, flags);
  307. chip->mce_bit |= CS4231_MCE;
  308. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  309. if (timeout == 0x80)
  310. snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  311. if (!(timeout & CS4231_MCE))
  312. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  313. spin_unlock_irqrestore(&chip->reg_lock, flags);
  314. }
  315. void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  316. {
  317. unsigned long flags;
  318. unsigned long end_time;
  319. int timeout;
  320. snd_cs4231_busy_wait(chip);
  321. #ifdef CONFIG_SND_DEBUG
  322. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  323. snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
  324. #endif
  325. spin_lock_irqsave(&chip->reg_lock, flags);
  326. chip->mce_bit &= ~CS4231_MCE;
  327. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  328. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  329. spin_unlock_irqrestore(&chip->reg_lock, flags);
  330. if (timeout == 0x80)
  331. snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  332. if ((timeout & CS4231_MCE) == 0 ||
  333. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  334. return;
  335. }
  336. /*
  337. * Wait for (possible -- during init auto-calibration may not be set)
  338. * calibration process to start. Needs upto 5 sample periods on AD1848
  339. * which at the slowest possible rate of 5.5125 kHz means 907 us.
  340. */
  341. msleep(1);
  342. snd_printdd("(1) jiffies = %lu\n", jiffies);
  343. /* check condition up to 250 ms */
  344. end_time = jiffies + msecs_to_jiffies(250);
  345. while (snd_cs4231_in(chip, CS4231_TEST_INIT) &
  346. CS4231_CALIB_IN_PROGRESS) {
  347. if (time_after(jiffies, end_time)) {
  348. snd_printk(KERN_ERR "mce_down - "
  349. "auto calibration time out (2)\n");
  350. return;
  351. }
  352. msleep(1);
  353. }
  354. snd_printdd("(2) jiffies = %lu\n", jiffies);
  355. /* check condition up to 100 ms */
  356. end_time = jiffies + msecs_to_jiffies(100);
  357. while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
  358. if (time_after(jiffies, end_time)) {
  359. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  360. return;
  361. }
  362. msleep(1);
  363. }
  364. snd_printdd("(3) jiffies = %lu\n", jiffies);
  365. snd_printd("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL)));
  366. }
  367. static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
  368. {
  369. switch (format & 0xe0) {
  370. case CS4231_LINEAR_16:
  371. case CS4231_LINEAR_16_BIG:
  372. size >>= 1;
  373. break;
  374. case CS4231_ADPCM_16:
  375. return size >> 2;
  376. }
  377. if (format & CS4231_STEREO)
  378. size >>= 1;
  379. return size;
  380. }
  381. static int snd_cs4231_trigger(struct snd_pcm_substream *substream,
  382. int cmd)
  383. {
  384. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  385. int result = 0;
  386. unsigned int what;
  387. struct snd_pcm_substream *s;
  388. int do_start;
  389. #if 0
  390. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS)));
  391. #endif
  392. switch (cmd) {
  393. case SNDRV_PCM_TRIGGER_START:
  394. case SNDRV_PCM_TRIGGER_RESUME:
  395. do_start = 1; break;
  396. case SNDRV_PCM_TRIGGER_STOP:
  397. case SNDRV_PCM_TRIGGER_SUSPEND:
  398. do_start = 0; break;
  399. default:
  400. return -EINVAL;
  401. }
  402. what = 0;
  403. snd_pcm_group_for_each_entry(s, substream) {
  404. if (s == chip->playback_substream) {
  405. what |= CS4231_PLAYBACK_ENABLE;
  406. snd_pcm_trigger_done(s, substream);
  407. } else if (s == chip->capture_substream) {
  408. what |= CS4231_RECORD_ENABLE;
  409. snd_pcm_trigger_done(s, substream);
  410. }
  411. }
  412. spin_lock(&chip->reg_lock);
  413. if (do_start) {
  414. chip->image[CS4231_IFACE_CTRL] |= what;
  415. if (chip->trigger)
  416. chip->trigger(chip, what, 1);
  417. } else {
  418. chip->image[CS4231_IFACE_CTRL] &= ~what;
  419. if (chip->trigger)
  420. chip->trigger(chip, what, 0);
  421. }
  422. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  423. spin_unlock(&chip->reg_lock);
  424. #if 0
  425. snd_cs4231_debug(chip);
  426. #endif
  427. return result;
  428. }
  429. /*
  430. * CODEC I/O
  431. */
  432. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  433. {
  434. int i;
  435. for (i = 0; i < ARRAY_SIZE(rates); i++)
  436. if (rate == rates[i])
  437. return freq_bits[i];
  438. // snd_BUG();
  439. return freq_bits[ARRAY_SIZE(rates) - 1];
  440. }
  441. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip,
  442. int format,
  443. int channels)
  444. {
  445. unsigned char rformat;
  446. rformat = CS4231_LINEAR_8;
  447. switch (format) {
  448. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  449. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  450. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  451. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  452. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  453. }
  454. if (channels > 1)
  455. rformat |= CS4231_STEREO;
  456. #if 0
  457. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  458. #endif
  459. return rformat;
  460. }
  461. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  462. {
  463. unsigned long flags;
  464. mute = mute ? 1 : 0;
  465. spin_lock_irqsave(&chip->reg_lock, flags);
  466. if (chip->calibrate_mute == mute) {
  467. spin_unlock_irqrestore(&chip->reg_lock, flags);
  468. return;
  469. }
  470. if (!mute) {
  471. snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]);
  472. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]);
  473. snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]);
  474. }
  475. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  476. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  477. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  478. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  479. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  480. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  481. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  482. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  483. snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  484. if (chip->hardware == CS4231_HW_INTERWAVE) {
  485. snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
  486. snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
  487. snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
  488. snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
  489. }
  490. chip->calibrate_mute = mute;
  491. spin_unlock_irqrestore(&chip->reg_lock, flags);
  492. }
  493. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  494. struct snd_pcm_hw_params *params,
  495. unsigned char pdfr)
  496. {
  497. unsigned long flags;
  498. int full_calib = 1;
  499. mutex_lock(&chip->mce_mutex);
  500. snd_cs4231_calibrate_mute(chip, 1);
  501. if (chip->hardware == CS4231_HW_CS4231A ||
  502. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  503. spin_lock_irqsave(&chip->reg_lock, flags);
  504. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
  505. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10);
  506. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  507. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
  508. udelay(100); /* Fixes audible clicks at least on GUS MAX */
  509. full_calib = 0;
  510. }
  511. spin_unlock_irqrestore(&chip->reg_lock, flags);
  512. }
  513. if (full_calib) {
  514. snd_cs4231_mce_up(chip);
  515. spin_lock_irqsave(&chip->reg_lock, flags);
  516. if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) {
  517. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  518. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  519. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  520. pdfr);
  521. } else {
  522. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  523. }
  524. spin_unlock_irqrestore(&chip->reg_lock, flags);
  525. if (chip->hardware == CS4231_HW_OPL3SA2)
  526. udelay(100); /* this seems to help */
  527. snd_cs4231_mce_down(chip);
  528. }
  529. snd_cs4231_calibrate_mute(chip, 0);
  530. mutex_unlock(&chip->mce_mutex);
  531. }
  532. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  533. struct snd_pcm_hw_params *params,
  534. unsigned char cdfr)
  535. {
  536. unsigned long flags;
  537. int full_calib = 1;
  538. mutex_lock(&chip->mce_mutex);
  539. snd_cs4231_calibrate_mute(chip, 1);
  540. if (chip->hardware == CS4231_HW_CS4231A ||
  541. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  542. spin_lock_irqsave(&chip->reg_lock, flags);
  543. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
  544. (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  545. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20);
  546. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr);
  547. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
  548. full_calib = 0;
  549. }
  550. spin_unlock_irqrestore(&chip->reg_lock, flags);
  551. }
  552. if (full_calib) {
  553. snd_cs4231_mce_up(chip);
  554. spin_lock_irqsave(&chip->reg_lock, flags);
  555. if (chip->hardware != CS4231_HW_INTERWAVE) {
  556. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  557. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  558. ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  559. (cdfr & 0x0f));
  560. spin_unlock_irqrestore(&chip->reg_lock, flags);
  561. snd_cs4231_mce_down(chip);
  562. snd_cs4231_mce_up(chip);
  563. spin_lock_irqsave(&chip->reg_lock, flags);
  564. }
  565. }
  566. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  567. spin_unlock_irqrestore(&chip->reg_lock, flags);
  568. snd_cs4231_mce_down(chip);
  569. }
  570. snd_cs4231_calibrate_mute(chip, 0);
  571. mutex_unlock(&chip->mce_mutex);
  572. }
  573. /*
  574. * Timer interface
  575. */
  576. static unsigned long snd_cs4231_timer_resolution(struct snd_timer * timer)
  577. {
  578. struct snd_cs4231 *chip = snd_timer_chip(timer);
  579. if (chip->hardware & CS4231_HW_CS4236B_MASK)
  580. return 14467;
  581. else
  582. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  583. }
  584. static int snd_cs4231_timer_start(struct snd_timer * timer)
  585. {
  586. unsigned long flags;
  587. unsigned int ticks;
  588. struct snd_cs4231 *chip = snd_timer_chip(timer);
  589. spin_lock_irqsave(&chip->reg_lock, flags);
  590. ticks = timer->sticks;
  591. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  592. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  593. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  594. snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8));
  595. snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks);
  596. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
  597. }
  598. spin_unlock_irqrestore(&chip->reg_lock, flags);
  599. return 0;
  600. }
  601. static int snd_cs4231_timer_stop(struct snd_timer * timer)
  602. {
  603. unsigned long flags;
  604. struct snd_cs4231 *chip = snd_timer_chip(timer);
  605. spin_lock_irqsave(&chip->reg_lock, flags);
  606. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
  607. spin_unlock_irqrestore(&chip->reg_lock, flags);
  608. return 0;
  609. }
  610. static void snd_cs4231_init(struct snd_cs4231 *chip)
  611. {
  612. unsigned long flags;
  613. snd_cs4231_mce_down(chip);
  614. #ifdef SNDRV_DEBUG_MCE
  615. snd_printk("init: (1)\n");
  616. #endif
  617. snd_cs4231_mce_up(chip);
  618. spin_lock_irqsave(&chip->reg_lock, flags);
  619. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  620. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
  621. CS4231_CALIB_MODE);
  622. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  623. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  624. spin_unlock_irqrestore(&chip->reg_lock, flags);
  625. snd_cs4231_mce_down(chip);
  626. #ifdef SNDRV_DEBUG_MCE
  627. snd_printk("init: (2)\n");
  628. #endif
  629. snd_cs4231_mce_up(chip);
  630. spin_lock_irqsave(&chip->reg_lock, flags);
  631. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  632. spin_unlock_irqrestore(&chip->reg_lock, flags);
  633. snd_cs4231_mce_down(chip);
  634. #ifdef SNDRV_DEBUG_MCE
  635. snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
  636. #endif
  637. spin_lock_irqsave(&chip->reg_lock, flags);
  638. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
  639. spin_unlock_irqrestore(&chip->reg_lock, flags);
  640. snd_cs4231_mce_up(chip);
  641. spin_lock_irqsave(&chip->reg_lock, flags);
  642. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
  643. spin_unlock_irqrestore(&chip->reg_lock, flags);
  644. snd_cs4231_mce_down(chip);
  645. #ifdef SNDRV_DEBUG_MCE
  646. snd_printk("init: (4)\n");
  647. #endif
  648. snd_cs4231_mce_up(chip);
  649. spin_lock_irqsave(&chip->reg_lock, flags);
  650. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  651. spin_unlock_irqrestore(&chip->reg_lock, flags);
  652. snd_cs4231_mce_down(chip);
  653. #ifdef SNDRV_DEBUG_MCE
  654. snd_printk("init: (5)\n");
  655. #endif
  656. }
  657. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  658. {
  659. unsigned long flags;
  660. mutex_lock(&chip->open_mutex);
  661. if ((chip->mode & mode) ||
  662. ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) {
  663. mutex_unlock(&chip->open_mutex);
  664. return -EAGAIN;
  665. }
  666. if (chip->mode & CS4231_MODE_OPEN) {
  667. chip->mode |= mode;
  668. mutex_unlock(&chip->open_mutex);
  669. return 0;
  670. }
  671. /* ok. now enable and ack CODEC IRQ */
  672. spin_lock_irqsave(&chip->reg_lock, flags);
  673. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  674. CS4231_RECORD_IRQ |
  675. CS4231_TIMER_IRQ);
  676. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  677. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  678. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  679. chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
  680. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  681. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  682. CS4231_RECORD_IRQ |
  683. CS4231_TIMER_IRQ);
  684. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  685. spin_unlock_irqrestore(&chip->reg_lock, flags);
  686. chip->mode = mode;
  687. mutex_unlock(&chip->open_mutex);
  688. return 0;
  689. }
  690. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  691. {
  692. unsigned long flags;
  693. mutex_lock(&chip->open_mutex);
  694. chip->mode &= ~mode;
  695. if (chip->mode & CS4231_MODE_OPEN) {
  696. mutex_unlock(&chip->open_mutex);
  697. return;
  698. }
  699. snd_cs4231_calibrate_mute(chip, 1);
  700. /* disable IRQ */
  701. spin_lock_irqsave(&chip->reg_lock, flags);
  702. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  703. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  704. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  705. chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
  706. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  707. /* now disable record & playback */
  708. if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  709. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  710. spin_unlock_irqrestore(&chip->reg_lock, flags);
  711. snd_cs4231_mce_up(chip);
  712. spin_lock_irqsave(&chip->reg_lock, flags);
  713. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  714. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  715. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  716. spin_unlock_irqrestore(&chip->reg_lock, flags);
  717. snd_cs4231_mce_down(chip);
  718. spin_lock_irqsave(&chip->reg_lock, flags);
  719. }
  720. /* clear IRQ again */
  721. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  722. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  723. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  724. spin_unlock_irqrestore(&chip->reg_lock, flags);
  725. snd_cs4231_calibrate_mute(chip, 0);
  726. chip->mode = 0;
  727. mutex_unlock(&chip->open_mutex);
  728. }
  729. /*
  730. * timer open/close
  731. */
  732. static int snd_cs4231_timer_open(struct snd_timer * timer)
  733. {
  734. struct snd_cs4231 *chip = snd_timer_chip(timer);
  735. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  736. return 0;
  737. }
  738. static int snd_cs4231_timer_close(struct snd_timer * timer)
  739. {
  740. struct snd_cs4231 *chip = snd_timer_chip(timer);
  741. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  742. return 0;
  743. }
  744. static struct snd_timer_hardware snd_cs4231_timer_table =
  745. {
  746. .flags = SNDRV_TIMER_HW_AUTO,
  747. .resolution = 9945,
  748. .ticks = 65535,
  749. .open = snd_cs4231_timer_open,
  750. .close = snd_cs4231_timer_close,
  751. .c_resolution = snd_cs4231_timer_resolution,
  752. .start = snd_cs4231_timer_start,
  753. .stop = snd_cs4231_timer_stop,
  754. };
  755. /*
  756. * ok.. exported functions..
  757. */
  758. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  759. struct snd_pcm_hw_params *hw_params)
  760. {
  761. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  762. unsigned char new_pdfr;
  763. int err;
  764. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  765. return err;
  766. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  767. snd_cs4231_get_rate(params_rate(hw_params));
  768. chip->set_playback_format(chip, hw_params, new_pdfr);
  769. return 0;
  770. }
  771. static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
  772. {
  773. return snd_pcm_lib_free_pages(substream);
  774. }
  775. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  776. {
  777. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  778. struct snd_pcm_runtime *runtime = substream->runtime;
  779. unsigned long flags;
  780. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  781. unsigned int count = snd_pcm_lib_period_bytes(substream);
  782. spin_lock_irqsave(&chip->reg_lock, flags);
  783. chip->p_dma_size = size;
  784. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
  785. snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  786. count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
  787. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  788. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  789. spin_unlock_irqrestore(&chip->reg_lock, flags);
  790. #if 0
  791. snd_cs4231_debug(chip);
  792. #endif
  793. return 0;
  794. }
  795. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  796. struct snd_pcm_hw_params *hw_params)
  797. {
  798. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  799. unsigned char new_cdfr;
  800. int err;
  801. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  802. return err;
  803. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  804. snd_cs4231_get_rate(params_rate(hw_params));
  805. chip->set_capture_format(chip, hw_params, new_cdfr);
  806. return 0;
  807. }
  808. static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
  809. {
  810. return snd_pcm_lib_free_pages(substream);
  811. }
  812. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  813. {
  814. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  815. struct snd_pcm_runtime *runtime = substream->runtime;
  816. unsigned long flags;
  817. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  818. unsigned int count = snd_pcm_lib_period_bytes(substream);
  819. spin_lock_irqsave(&chip->reg_lock, flags);
  820. chip->c_dma_size = size;
  821. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  822. snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  823. count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1;
  824. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  825. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  826. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  827. } else {
  828. snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
  829. snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8));
  830. }
  831. spin_unlock_irqrestore(&chip->reg_lock, flags);
  832. return 0;
  833. }
  834. void snd_cs4231_overrange(struct snd_cs4231 *chip)
  835. {
  836. unsigned long flags;
  837. unsigned char res;
  838. spin_lock_irqsave(&chip->reg_lock, flags);
  839. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  840. spin_unlock_irqrestore(&chip->reg_lock, flags);
  841. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  842. chip->capture_substream->runtime->overrange++;
  843. }
  844. irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id)
  845. {
  846. struct snd_cs4231 *chip = dev_id;
  847. unsigned char status;
  848. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  849. if (status & CS4231_TIMER_IRQ) {
  850. if (chip->timer)
  851. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  852. }
  853. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  854. if (status & CS4231_PLAYBACK_IRQ) {
  855. if (chip->mode & CS4231_MODE_PLAY) {
  856. if (chip->playback_substream)
  857. snd_pcm_period_elapsed(chip->playback_substream);
  858. }
  859. if (chip->mode & CS4231_MODE_RECORD) {
  860. if (chip->capture_substream) {
  861. snd_cs4231_overrange(chip);
  862. snd_pcm_period_elapsed(chip->capture_substream);
  863. }
  864. }
  865. }
  866. } else {
  867. if (status & CS4231_PLAYBACK_IRQ) {
  868. if (chip->playback_substream)
  869. snd_pcm_period_elapsed(chip->playback_substream);
  870. }
  871. if (status & CS4231_RECORD_IRQ) {
  872. if (chip->capture_substream) {
  873. snd_cs4231_overrange(chip);
  874. snd_pcm_period_elapsed(chip->capture_substream);
  875. }
  876. }
  877. }
  878. spin_lock(&chip->reg_lock);
  879. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  880. spin_unlock(&chip->reg_lock);
  881. return IRQ_HANDLED;
  882. }
  883. static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
  884. {
  885. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  886. size_t ptr;
  887. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  888. return 0;
  889. ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
  890. return bytes_to_frames(substream->runtime, ptr);
  891. }
  892. static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
  893. {
  894. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  895. size_t ptr;
  896. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  897. return 0;
  898. ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
  899. return bytes_to_frames(substream->runtime, ptr);
  900. }
  901. /*
  902. */
  903. static int snd_cs4231_probe(struct snd_cs4231 *chip)
  904. {
  905. unsigned long flags;
  906. int i, id, rev;
  907. unsigned char *ptr;
  908. unsigned int hw;
  909. #if 0
  910. snd_cs4231_debug(chip);
  911. #endif
  912. id = 0;
  913. for (i = 0; i < 50; i++) {
  914. mb();
  915. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  916. udelay(2000);
  917. else {
  918. spin_lock_irqsave(&chip->reg_lock, flags);
  919. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  920. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  921. spin_unlock_irqrestore(&chip->reg_lock, flags);
  922. if (id == 0x0a)
  923. break; /* this is valid value */
  924. }
  925. }
  926. snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
  927. if (id != 0x0a)
  928. return -ENODEV; /* no valid device found */
  929. if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  930. rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7;
  931. snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
  932. if (rev == 0x80) {
  933. unsigned char tmp = snd_cs4231_in(chip, 23);
  934. snd_cs4231_out(chip, 23, ~tmp);
  935. if (snd_cs4231_in(chip, 23) != tmp)
  936. chip->hardware = CS4231_HW_AD1845;
  937. else
  938. chip->hardware = CS4231_HW_CS4231;
  939. } else if (rev == 0xa0) {
  940. chip->hardware = CS4231_HW_CS4231A;
  941. } else if (rev == 0xa2) {
  942. chip->hardware = CS4231_HW_CS4232;
  943. } else if (rev == 0xb2) {
  944. chip->hardware = CS4231_HW_CS4232A;
  945. } else if (rev == 0x83) {
  946. chip->hardware = CS4231_HW_CS4236;
  947. } else if (rev == 0x03) {
  948. chip->hardware = CS4231_HW_CS4236B;
  949. } else {
  950. snd_printk("unknown CS chip with version 0x%x\n", rev);
  951. return -ENODEV; /* unknown CS4231 chip? */
  952. }
  953. }
  954. spin_lock_irqsave(&chip->reg_lock, flags);
  955. cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
  956. cs4231_outb(chip, CS4231P(STATUS), 0);
  957. mb();
  958. spin_unlock_irqrestore(&chip->reg_lock, flags);
  959. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  960. switch (chip->hardware) {
  961. case CS4231_HW_INTERWAVE:
  962. chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
  963. break;
  964. case CS4231_HW_CS4235:
  965. case CS4231_HW_CS4236B:
  966. case CS4231_HW_CS4237B:
  967. case CS4231_HW_CS4238B:
  968. case CS4231_HW_CS4239:
  969. if (hw == CS4231_HW_DETECT3)
  970. chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
  971. else
  972. chip->hardware = CS4231_HW_CS4236;
  973. break;
  974. }
  975. chip->image[CS4231_IFACE_CTRL] =
  976. (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
  977. (chip->single_dma ? CS4231_SINGLE_DMA : 0);
  978. if (chip->hardware != CS4231_HW_OPTI93X) {
  979. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  980. chip->image[CS4231_ALT_FEATURE_2] =
  981. chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01;
  982. }
  983. ptr = (unsigned char *) &chip->image;
  984. snd_cs4231_mce_down(chip);
  985. spin_lock_irqsave(&chip->reg_lock, flags);
  986. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  987. snd_cs4231_out(chip, i, *ptr++);
  988. spin_unlock_irqrestore(&chip->reg_lock, flags);
  989. snd_cs4231_mce_up(chip);
  990. snd_cs4231_mce_down(chip);
  991. mdelay(2);
  992. /* ok.. try check hardware version for CS4236+ chips */
  993. if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  994. if (chip->hardware == CS4231_HW_CS4236B) {
  995. rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
  996. snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
  997. id = snd_cs4236_ext_in(chip, CS4236_VERSION);
  998. snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
  999. snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
  1000. if ((id & 0x1f) == 0x1d) { /* CS4235 */
  1001. chip->hardware = CS4231_HW_CS4235;
  1002. switch (id >> 5) {
  1003. case 4:
  1004. case 5:
  1005. case 6:
  1006. break;
  1007. default:
  1008. snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
  1009. }
  1010. } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
  1011. switch (id >> 5) {
  1012. case 4:
  1013. case 5:
  1014. case 6:
  1015. case 7:
  1016. chip->hardware = CS4231_HW_CS4236B;
  1017. break;
  1018. default:
  1019. snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
  1020. }
  1021. } else if ((id & 0x1f) == 0x08) { /* CS4237B */
  1022. chip->hardware = CS4231_HW_CS4237B;
  1023. switch (id >> 5) {
  1024. case 4:
  1025. case 5:
  1026. case 6:
  1027. case 7:
  1028. break;
  1029. default:
  1030. snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
  1031. }
  1032. } else if ((id & 0x1f) == 0x09) { /* CS4238B */
  1033. chip->hardware = CS4231_HW_CS4238B;
  1034. switch (id >> 5) {
  1035. case 5:
  1036. case 6:
  1037. case 7:
  1038. break;
  1039. default:
  1040. snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
  1041. }
  1042. } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
  1043. chip->hardware = CS4231_HW_CS4239;
  1044. switch (id >> 5) {
  1045. case 4:
  1046. case 5:
  1047. case 6:
  1048. break;
  1049. default:
  1050. snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
  1051. }
  1052. } else {
  1053. snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
  1054. }
  1055. }
  1056. }
  1057. return 0; /* all things are ok.. */
  1058. }
  1059. /*
  1060. */
  1061. static struct snd_pcm_hardware snd_cs4231_playback =
  1062. {
  1063. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1064. SNDRV_PCM_INFO_MMAP_VALID |
  1065. SNDRV_PCM_INFO_RESUME |
  1066. SNDRV_PCM_INFO_SYNC_START),
  1067. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1068. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1069. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1070. .rate_min = 5510,
  1071. .rate_max = 48000,
  1072. .channels_min = 1,
  1073. .channels_max = 2,
  1074. .buffer_bytes_max = (128*1024),
  1075. .period_bytes_min = 64,
  1076. .period_bytes_max = (128*1024),
  1077. .periods_min = 1,
  1078. .periods_max = 1024,
  1079. .fifo_size = 0,
  1080. };
  1081. static struct snd_pcm_hardware snd_cs4231_capture =
  1082. {
  1083. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1084. SNDRV_PCM_INFO_MMAP_VALID |
  1085. SNDRV_PCM_INFO_RESUME |
  1086. SNDRV_PCM_INFO_SYNC_START),
  1087. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1088. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1089. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1090. .rate_min = 5510,
  1091. .rate_max = 48000,
  1092. .channels_min = 1,
  1093. .channels_max = 2,
  1094. .buffer_bytes_max = (128*1024),
  1095. .period_bytes_min = 64,
  1096. .period_bytes_max = (128*1024),
  1097. .periods_min = 1,
  1098. .periods_max = 1024,
  1099. .fifo_size = 0,
  1100. };
  1101. /*
  1102. */
  1103. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  1104. {
  1105. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1106. struct snd_pcm_runtime *runtime = substream->runtime;
  1107. int err;
  1108. runtime->hw = snd_cs4231_playback;
  1109. /* hardware bug in InterWave chipset */
  1110. if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3)
  1111. runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
  1112. /* hardware limitation of cheap chips */
  1113. if (chip->hardware == CS4231_HW_CS4235 ||
  1114. chip->hardware == CS4231_HW_CS4239)
  1115. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1116. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
  1117. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
  1118. if (chip->claim_dma) {
  1119. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
  1120. return err;
  1121. }
  1122. if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
  1123. if (chip->release_dma)
  1124. chip->release_dma(chip, chip->dma_private_data, chip->dma1);
  1125. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1126. return err;
  1127. }
  1128. chip->playback_substream = substream;
  1129. snd_pcm_set_sync(substream);
  1130. chip->rate_constraint(runtime);
  1131. return 0;
  1132. }
  1133. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  1134. {
  1135. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1136. struct snd_pcm_runtime *runtime = substream->runtime;
  1137. int err;
  1138. runtime->hw = snd_cs4231_capture;
  1139. /* hardware limitation of cheap chips */
  1140. if (chip->hardware == CS4231_HW_CS4235 ||
  1141. chip->hardware == CS4231_HW_CS4239)
  1142. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1143. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
  1144. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
  1145. if (chip->claim_dma) {
  1146. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
  1147. return err;
  1148. }
  1149. if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
  1150. if (chip->release_dma)
  1151. chip->release_dma(chip, chip->dma_private_data, chip->dma2);
  1152. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1153. return err;
  1154. }
  1155. chip->capture_substream = substream;
  1156. snd_pcm_set_sync(substream);
  1157. chip->rate_constraint(runtime);
  1158. return 0;
  1159. }
  1160. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1161. {
  1162. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1163. chip->playback_substream = NULL;
  1164. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1165. return 0;
  1166. }
  1167. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1168. {
  1169. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1170. chip->capture_substream = NULL;
  1171. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1172. return 0;
  1173. }
  1174. #ifdef CONFIG_PM
  1175. /* lowlevel suspend callback for CS4231 */
  1176. static void snd_cs4231_suspend(struct snd_cs4231 *chip)
  1177. {
  1178. int reg;
  1179. unsigned long flags;
  1180. snd_pcm_suspend_all(chip->pcm);
  1181. spin_lock_irqsave(&chip->reg_lock, flags);
  1182. for (reg = 0; reg < 32; reg++)
  1183. chip->image[reg] = snd_cs4231_in(chip, reg);
  1184. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1185. }
  1186. /* lowlevel resume callback for CS4231 */
  1187. static void snd_cs4231_resume(struct snd_cs4231 *chip)
  1188. {
  1189. int reg;
  1190. unsigned long flags;
  1191. /* int timeout; */
  1192. snd_cs4231_mce_up(chip);
  1193. spin_lock_irqsave(&chip->reg_lock, flags);
  1194. for (reg = 0; reg < 32; reg++) {
  1195. switch (reg) {
  1196. case CS4231_VERSION:
  1197. break;
  1198. default:
  1199. snd_cs4231_out(chip, reg, chip->image[reg]);
  1200. break;
  1201. }
  1202. }
  1203. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1204. #if 1
  1205. snd_cs4231_mce_down(chip);
  1206. #else
  1207. /* The following is a workaround to avoid freeze after resume on TP600E.
  1208. This is the first half of copy of snd_cs4231_mce_down(), but doesn't
  1209. include rescheduling. -- iwai
  1210. */
  1211. snd_cs4231_busy_wait(chip);
  1212. spin_lock_irqsave(&chip->reg_lock, flags);
  1213. chip->mce_bit &= ~CS4231_MCE;
  1214. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  1215. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  1216. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1217. if (timeout == 0x80)
  1218. snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  1219. if ((timeout & CS4231_MCE) == 0 ||
  1220. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  1221. return;
  1222. }
  1223. snd_cs4231_busy_wait(chip);
  1224. #endif
  1225. }
  1226. #endif /* CONFIG_PM */
  1227. static int snd_cs4231_free(struct snd_cs4231 *chip)
  1228. {
  1229. release_and_free_resource(chip->res_port);
  1230. release_and_free_resource(chip->res_cport);
  1231. if (chip->irq >= 0) {
  1232. disable_irq(chip->irq);
  1233. if (!(chip->hwshare & CS4231_HWSHARE_IRQ))
  1234. free_irq(chip->irq, (void *) chip);
  1235. }
  1236. if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) {
  1237. snd_dma_disable(chip->dma1);
  1238. free_dma(chip->dma1);
  1239. }
  1240. if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
  1241. snd_dma_disable(chip->dma2);
  1242. free_dma(chip->dma2);
  1243. }
  1244. if (chip->timer)
  1245. snd_device_free(chip->card, chip->timer);
  1246. kfree(chip);
  1247. return 0;
  1248. }
  1249. static int snd_cs4231_dev_free(struct snd_device *device)
  1250. {
  1251. struct snd_cs4231 *chip = device->device_data;
  1252. return snd_cs4231_free(chip);
  1253. }
  1254. const char *snd_cs4231_chip_id(struct snd_cs4231 *chip)
  1255. {
  1256. switch (chip->hardware) {
  1257. case CS4231_HW_CS4231: return "CS4231";
  1258. case CS4231_HW_CS4231A: return "CS4231A";
  1259. case CS4231_HW_CS4232: return "CS4232";
  1260. case CS4231_HW_CS4232A: return "CS4232A";
  1261. case CS4231_HW_CS4235: return "CS4235";
  1262. case CS4231_HW_CS4236: return "CS4236";
  1263. case CS4231_HW_CS4236B: return "CS4236B";
  1264. case CS4231_HW_CS4237B: return "CS4237B";
  1265. case CS4231_HW_CS4238B: return "CS4238B";
  1266. case CS4231_HW_CS4239: return "CS4239";
  1267. case CS4231_HW_INTERWAVE: return "AMD InterWave";
  1268. case CS4231_HW_OPL3SA2: return chip->card->shortname;
  1269. case CS4231_HW_AD1845: return "AD1845";
  1270. case CS4231_HW_OPTI93X: return "OPTi 93x";
  1271. default: return "???";
  1272. }
  1273. }
  1274. static int snd_cs4231_new(struct snd_card *card,
  1275. unsigned short hardware,
  1276. unsigned short hwshare,
  1277. struct snd_cs4231 ** rchip)
  1278. {
  1279. struct snd_cs4231 *chip;
  1280. *rchip = NULL;
  1281. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1282. if (chip == NULL)
  1283. return -ENOMEM;
  1284. chip->hardware = hardware;
  1285. chip->hwshare = hwshare;
  1286. spin_lock_init(&chip->reg_lock);
  1287. mutex_init(&chip->mce_mutex);
  1288. mutex_init(&chip->open_mutex);
  1289. chip->card = card;
  1290. chip->rate_constraint = snd_cs4231_xrate;
  1291. chip->set_playback_format = snd_cs4231_playback_format;
  1292. chip->set_capture_format = snd_cs4231_capture_format;
  1293. if (chip->hardware == CS4231_HW_OPTI93X)
  1294. memcpy(&chip->image, &snd_opti93x_original_image,
  1295. sizeof(snd_opti93x_original_image));
  1296. else
  1297. memcpy(&chip->image, &snd_cs4231_original_image,
  1298. sizeof(snd_cs4231_original_image));
  1299. *rchip = chip;
  1300. return 0;
  1301. }
  1302. int snd_cs4231_create(struct snd_card *card,
  1303. unsigned long port,
  1304. unsigned long cport,
  1305. int irq, int dma1, int dma2,
  1306. unsigned short hardware,
  1307. unsigned short hwshare,
  1308. struct snd_cs4231 ** rchip)
  1309. {
  1310. static struct snd_device_ops ops = {
  1311. .dev_free = snd_cs4231_dev_free,
  1312. };
  1313. struct snd_cs4231 *chip;
  1314. int err;
  1315. err = snd_cs4231_new(card, hardware, hwshare, &chip);
  1316. if (err < 0)
  1317. return err;
  1318. chip->irq = -1;
  1319. chip->dma1 = -1;
  1320. chip->dma2 = -1;
  1321. if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) {
  1322. snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port);
  1323. snd_cs4231_free(chip);
  1324. return -EBUSY;
  1325. }
  1326. chip->port = port;
  1327. if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) {
  1328. snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport);
  1329. snd_cs4231_free(chip);
  1330. return -ENODEV;
  1331. }
  1332. chip->cport = cport;
  1333. if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, IRQF_DISABLED, "CS4231", (void *) chip)) {
  1334. snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq);
  1335. snd_cs4231_free(chip);
  1336. return -EBUSY;
  1337. }
  1338. chip->irq = irq;
  1339. if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) {
  1340. snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1);
  1341. snd_cs4231_free(chip);
  1342. return -EBUSY;
  1343. }
  1344. chip->dma1 = dma1;
  1345. if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) {
  1346. snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2);
  1347. snd_cs4231_free(chip);
  1348. return -EBUSY;
  1349. }
  1350. if (dma1 == dma2 || dma2 < 0) {
  1351. chip->single_dma = 1;
  1352. chip->dma2 = chip->dma1;
  1353. } else
  1354. chip->dma2 = dma2;
  1355. /* global setup */
  1356. if (snd_cs4231_probe(chip) < 0) {
  1357. snd_cs4231_free(chip);
  1358. return -ENODEV;
  1359. }
  1360. snd_cs4231_init(chip);
  1361. #if 0
  1362. if (chip->hardware & CS4231_HW_CS4232_MASK) {
  1363. if (chip->res_cport == NULL)
  1364. snd_printk("CS4232 control port features are not accessible\n");
  1365. }
  1366. #endif
  1367. /* Register device */
  1368. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1369. snd_cs4231_free(chip);
  1370. return err;
  1371. }
  1372. #ifdef CONFIG_PM
  1373. /* Power Management */
  1374. chip->suspend = snd_cs4231_suspend;
  1375. chip->resume = snd_cs4231_resume;
  1376. #endif
  1377. *rchip = chip;
  1378. return 0;
  1379. }
  1380. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1381. .open = snd_cs4231_playback_open,
  1382. .close = snd_cs4231_playback_close,
  1383. .ioctl = snd_pcm_lib_ioctl,
  1384. .hw_params = snd_cs4231_playback_hw_params,
  1385. .hw_free = snd_cs4231_playback_hw_free,
  1386. .prepare = snd_cs4231_playback_prepare,
  1387. .trigger = snd_cs4231_trigger,
  1388. .pointer = snd_cs4231_playback_pointer,
  1389. };
  1390. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1391. .open = snd_cs4231_capture_open,
  1392. .close = snd_cs4231_capture_close,
  1393. .ioctl = snd_pcm_lib_ioctl,
  1394. .hw_params = snd_cs4231_capture_hw_params,
  1395. .hw_free = snd_cs4231_capture_hw_free,
  1396. .prepare = snd_cs4231_capture_prepare,
  1397. .trigger = snd_cs4231_trigger,
  1398. .pointer = snd_cs4231_capture_pointer,
  1399. };
  1400. int snd_cs4231_pcm(struct snd_cs4231 *chip, int device, struct snd_pcm **rpcm)
  1401. {
  1402. struct snd_pcm *pcm;
  1403. int err;
  1404. if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0)
  1405. return err;
  1406. spin_lock_init(&chip->reg_lock);
  1407. mutex_init(&chip->mce_mutex);
  1408. mutex_init(&chip->open_mutex);
  1409. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
  1410. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
  1411. /* global setup */
  1412. pcm->private_data = chip;
  1413. pcm->info_flags = 0;
  1414. if (chip->single_dma)
  1415. pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
  1416. if (chip->hardware != CS4231_HW_INTERWAVE)
  1417. pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
  1418. strcpy(pcm->name, snd_cs4231_chip_id(chip));
  1419. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1420. snd_dma_isa_data(),
  1421. 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
  1422. chip->pcm = pcm;
  1423. if (rpcm)
  1424. *rpcm = pcm;
  1425. return 0;
  1426. }
  1427. static void snd_cs4231_timer_free(struct snd_timer *timer)
  1428. {
  1429. struct snd_cs4231 *chip = timer->private_data;
  1430. chip->timer = NULL;
  1431. }
  1432. int snd_cs4231_timer(struct snd_cs4231 *chip, int device, struct snd_timer **rtimer)
  1433. {
  1434. struct snd_timer *timer;
  1435. struct snd_timer_id tid;
  1436. int err;
  1437. /* Timer initialization */
  1438. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1439. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1440. tid.card = chip->card->number;
  1441. tid.device = device;
  1442. tid.subdevice = 0;
  1443. if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
  1444. return err;
  1445. strcpy(timer->name, snd_cs4231_chip_id(chip));
  1446. timer->private_data = chip;
  1447. timer->private_free = snd_cs4231_timer_free;
  1448. timer->hw = snd_cs4231_timer_table;
  1449. chip->timer = timer;
  1450. if (rtimer)
  1451. *rtimer = timer;
  1452. return 0;
  1453. }
  1454. /*
  1455. * MIXER part
  1456. */
  1457. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1458. {
  1459. static char *texts[4] = {
  1460. "Line", "Aux", "Mic", "Mix"
  1461. };
  1462. static char *opl3sa_texts[4] = {
  1463. "Line", "CD", "Mic", "Mix"
  1464. };
  1465. static char *gusmax_texts[4] = {
  1466. "Line", "Synth", "Mic", "Mix"
  1467. };
  1468. char **ptexts = texts;
  1469. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1470. snd_assert(chip->card != NULL, return -EINVAL);
  1471. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1472. uinfo->count = 2;
  1473. uinfo->value.enumerated.items = 4;
  1474. if (uinfo->value.enumerated.item > 3)
  1475. uinfo->value.enumerated.item = 3;
  1476. if (!strcmp(chip->card->driver, "GUS MAX"))
  1477. ptexts = gusmax_texts;
  1478. switch (chip->hardware) {
  1479. case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break;
  1480. case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break;
  1481. }
  1482. strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
  1483. return 0;
  1484. }
  1485. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1486. {
  1487. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1488. unsigned long flags;
  1489. spin_lock_irqsave(&chip->reg_lock, flags);
  1490. ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1491. ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1492. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1493. return 0;
  1494. }
  1495. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1496. {
  1497. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1498. unsigned long flags;
  1499. unsigned short left, right;
  1500. int change;
  1501. if (ucontrol->value.enumerated.item[0] > 3 ||
  1502. ucontrol->value.enumerated.item[1] > 3)
  1503. return -EINVAL;
  1504. left = ucontrol->value.enumerated.item[0] << 6;
  1505. right = ucontrol->value.enumerated.item[1] << 6;
  1506. spin_lock_irqsave(&chip->reg_lock, flags);
  1507. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1508. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1509. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1510. right != chip->image[CS4231_RIGHT_INPUT];
  1511. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1512. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1513. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1514. return change;
  1515. }
  1516. int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1517. {
  1518. int mask = (kcontrol->private_value >> 16) & 0xff;
  1519. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1520. uinfo->count = 1;
  1521. uinfo->value.integer.min = 0;
  1522. uinfo->value.integer.max = mask;
  1523. return 0;
  1524. }
  1525. int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1526. {
  1527. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1528. unsigned long flags;
  1529. int reg = kcontrol->private_value & 0xff;
  1530. int shift = (kcontrol->private_value >> 8) & 0xff;
  1531. int mask = (kcontrol->private_value >> 16) & 0xff;
  1532. int invert = (kcontrol->private_value >> 24) & 0xff;
  1533. spin_lock_irqsave(&chip->reg_lock, flags);
  1534. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1535. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1536. if (invert)
  1537. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1538. return 0;
  1539. }
  1540. int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1541. {
  1542. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1543. unsigned long flags;
  1544. int reg = kcontrol->private_value & 0xff;
  1545. int shift = (kcontrol->private_value >> 8) & 0xff;
  1546. int mask = (kcontrol->private_value >> 16) & 0xff;
  1547. int invert = (kcontrol->private_value >> 24) & 0xff;
  1548. int change;
  1549. unsigned short val;
  1550. val = (ucontrol->value.integer.value[0] & mask);
  1551. if (invert)
  1552. val = mask - val;
  1553. val <<= shift;
  1554. spin_lock_irqsave(&chip->reg_lock, flags);
  1555. val = (chip->image[reg] & ~(mask << shift)) | val;
  1556. change = val != chip->image[reg];
  1557. snd_cs4231_out(chip, reg, val);
  1558. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1559. return change;
  1560. }
  1561. int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1562. {
  1563. int mask = (kcontrol->private_value >> 24) & 0xff;
  1564. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1565. uinfo->count = 2;
  1566. uinfo->value.integer.min = 0;
  1567. uinfo->value.integer.max = mask;
  1568. return 0;
  1569. }
  1570. int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1571. {
  1572. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1573. unsigned long flags;
  1574. int left_reg = kcontrol->private_value & 0xff;
  1575. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1576. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1577. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1578. int mask = (kcontrol->private_value >> 24) & 0xff;
  1579. int invert = (kcontrol->private_value >> 22) & 1;
  1580. spin_lock_irqsave(&chip->reg_lock, flags);
  1581. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1582. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1583. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1584. if (invert) {
  1585. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1586. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1587. }
  1588. return 0;
  1589. }
  1590. int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1591. {
  1592. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1593. unsigned long flags;
  1594. int left_reg = kcontrol->private_value & 0xff;
  1595. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1596. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1597. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1598. int mask = (kcontrol->private_value >> 24) & 0xff;
  1599. int invert = (kcontrol->private_value >> 22) & 1;
  1600. int change;
  1601. unsigned short val1, val2;
  1602. val1 = ucontrol->value.integer.value[0] & mask;
  1603. val2 = ucontrol->value.integer.value[1] & mask;
  1604. if (invert) {
  1605. val1 = mask - val1;
  1606. val2 = mask - val2;
  1607. }
  1608. val1 <<= shift_left;
  1609. val2 <<= shift_right;
  1610. spin_lock_irqsave(&chip->reg_lock, flags);
  1611. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1612. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1613. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1614. snd_cs4231_out(chip, left_reg, val1);
  1615. snd_cs4231_out(chip, right_reg, val2);
  1616. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1617. return change;
  1618. }
  1619. static struct snd_kcontrol_new snd_cs4231_controls[] = {
  1620. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1621. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1622. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1623. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1624. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1625. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1626. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1627. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1628. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1629. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1630. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1631. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1632. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1633. {
  1634. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1635. .name = "Capture Source",
  1636. .info = snd_cs4231_info_mux,
  1637. .get = snd_cs4231_get_mux,
  1638. .put = snd_cs4231_put_mux,
  1639. },
  1640. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1641. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1642. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1)
  1643. };
  1644. static struct snd_kcontrol_new snd_opti93x_controls[] = {
  1645. CS4231_DOUBLE("Master Playback Switch", 0,
  1646. OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
  1647. CS4231_DOUBLE("Master Playback Volume", 0,
  1648. OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
  1649. CS4231_DOUBLE("PCM Playback Switch", 0,
  1650. CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1651. CS4231_DOUBLE("PCM Playback Volume", 0,
  1652. CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
  1653. CS4231_DOUBLE("FM Playback Switch", 0,
  1654. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1655. CS4231_DOUBLE("FM Playback Volume", 0,
  1656. CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
  1657. CS4231_DOUBLE("Line Playback Switch", 0,
  1658. CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1659. CS4231_DOUBLE("Line Playback Volume", 0,
  1660. CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
  1661. CS4231_DOUBLE("Mic Playback Switch", 0,
  1662. OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
  1663. CS4231_DOUBLE("Mic Playback Volume", 0,
  1664. OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
  1665. CS4231_DOUBLE("Mic Boost", 0,
  1666. CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1667. CS4231_DOUBLE("CD Playback Switch", 0,
  1668. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1669. CS4231_DOUBLE("CD Playback Volume", 0,
  1670. CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
  1671. CS4231_DOUBLE("Aux Playback Switch", 0,
  1672. OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
  1673. CS4231_DOUBLE("Aux Playback Volume", 0,
  1674. OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
  1675. CS4231_DOUBLE("Capture Volume", 0,
  1676. CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1677. {
  1678. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1679. .name = "Capture Source",
  1680. .info = snd_cs4231_info_mux,
  1681. .get = snd_cs4231_get_mux,
  1682. .put = snd_cs4231_put_mux,
  1683. }
  1684. };
  1685. int snd_cs4231_mixer(struct snd_cs4231 *chip)
  1686. {
  1687. struct snd_card *card;
  1688. unsigned int idx;
  1689. int err;
  1690. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1691. card = chip->card;
  1692. strcpy(card->mixername, chip->pcm->name);
  1693. if (chip->hardware == CS4231_HW_OPTI93X)
  1694. for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
  1695. err = snd_ctl_add(card,
  1696. snd_ctl_new1(&snd_opti93x_controls[idx],
  1697. chip));
  1698. if (err < 0)
  1699. return err;
  1700. }
  1701. else
  1702. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1703. err = snd_ctl_add(card,
  1704. snd_ctl_new1(&snd_cs4231_controls[idx],
  1705. chip));
  1706. if (err < 0)
  1707. return err;
  1708. }
  1709. return 0;
  1710. }
  1711. EXPORT_SYMBOL(snd_cs4231_out);
  1712. EXPORT_SYMBOL(snd_cs4231_in);
  1713. EXPORT_SYMBOL(snd_cs4236_ext_out);
  1714. EXPORT_SYMBOL(snd_cs4236_ext_in);
  1715. EXPORT_SYMBOL(snd_cs4231_mce_up);
  1716. EXPORT_SYMBOL(snd_cs4231_mce_down);
  1717. EXPORT_SYMBOL(snd_cs4231_overrange);
  1718. EXPORT_SYMBOL(snd_cs4231_interrupt);
  1719. EXPORT_SYMBOL(snd_cs4231_chip_id);
  1720. EXPORT_SYMBOL(snd_cs4231_create);
  1721. EXPORT_SYMBOL(snd_cs4231_pcm);
  1722. EXPORT_SYMBOL(snd_cs4231_mixer);
  1723. EXPORT_SYMBOL(snd_cs4231_timer);
  1724. EXPORT_SYMBOL(snd_cs4231_info_single);
  1725. EXPORT_SYMBOL(snd_cs4231_get_single);
  1726. EXPORT_SYMBOL(snd_cs4231_put_single);
  1727. EXPORT_SYMBOL(snd_cs4231_info_double);
  1728. EXPORT_SYMBOL(snd_cs4231_get_double);
  1729. EXPORT_SYMBOL(snd_cs4231_put_double);
  1730. /*
  1731. * INIT part
  1732. */
  1733. static int __init alsa_cs4231_init(void)
  1734. {
  1735. return 0;
  1736. }
  1737. static void __exit alsa_cs4231_exit(void)
  1738. {
  1739. }
  1740. module_init(alsa_cs4231_init)
  1741. module_exit(alsa_cs4231_exit)