ad1848_lib.c 38 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of AD1848/AD1847/CS4248
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #define SNDRV_MAIN_OBJECT_FILE
  22. #include <linux/delay.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/slab.h>
  26. #include <linux/ioport.h>
  27. #include <sound/core.h>
  28. #include <sound/ad1848.h>
  29. #include <sound/control.h>
  30. #include <sound/tlv.h>
  31. #include <sound/pcm_params.h>
  32. #include <asm/io.h>
  33. #include <asm/dma.h>
  34. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  35. MODULE_DESCRIPTION("Routines for control of AD1848/AD1847/CS4248");
  36. MODULE_LICENSE("GPL");
  37. #if 0
  38. #define SNDRV_DEBUG_MCE
  39. #endif
  40. /*
  41. * Some variables
  42. */
  43. static unsigned char freq_bits[14] = {
  44. /* 5510 */ 0x00 | AD1848_XTAL2,
  45. /* 6620 */ 0x0E | AD1848_XTAL2,
  46. /* 8000 */ 0x00 | AD1848_XTAL1,
  47. /* 9600 */ 0x0E | AD1848_XTAL1,
  48. /* 11025 */ 0x02 | AD1848_XTAL2,
  49. /* 16000 */ 0x02 | AD1848_XTAL1,
  50. /* 18900 */ 0x04 | AD1848_XTAL2,
  51. /* 22050 */ 0x06 | AD1848_XTAL2,
  52. /* 27042 */ 0x04 | AD1848_XTAL1,
  53. /* 32000 */ 0x06 | AD1848_XTAL1,
  54. /* 33075 */ 0x0C | AD1848_XTAL2,
  55. /* 37800 */ 0x08 | AD1848_XTAL2,
  56. /* 44100 */ 0x0A | AD1848_XTAL2,
  57. /* 48000 */ 0x0C | AD1848_XTAL1
  58. };
  59. static unsigned int rates[14] = {
  60. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  61. 27042, 32000, 33075, 37800, 44100, 48000
  62. };
  63. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  64. .count = ARRAY_SIZE(rates),
  65. .list = rates,
  66. .mask = 0,
  67. };
  68. static unsigned char snd_ad1848_original_image[16] =
  69. {
  70. 0x00, /* 00 - lic */
  71. 0x00, /* 01 - ric */
  72. 0x9f, /* 02 - la1ic */
  73. 0x9f, /* 03 - ra1ic */
  74. 0x9f, /* 04 - la2ic */
  75. 0x9f, /* 05 - ra2ic */
  76. 0xbf, /* 06 - loc */
  77. 0xbf, /* 07 - roc */
  78. 0x20, /* 08 - dfr */
  79. AD1848_AUTOCALIB, /* 09 - ic */
  80. 0x00, /* 0a - pc */
  81. 0x00, /* 0b - ti */
  82. 0x00, /* 0c - mi */
  83. 0x00, /* 0d - lbc */
  84. 0x00, /* 0e - dru */
  85. 0x00, /* 0f - drl */
  86. };
  87. /*
  88. * Basic I/O functions
  89. */
  90. static void snd_ad1848_wait(struct snd_ad1848 *chip)
  91. {
  92. int timeout;
  93. for (timeout = 250; timeout > 0; timeout--) {
  94. if ((inb(AD1848P(chip, REGSEL)) & AD1848_INIT) == 0)
  95. break;
  96. udelay(100);
  97. }
  98. }
  99. void snd_ad1848_out(struct snd_ad1848 *chip,
  100. unsigned char reg,
  101. unsigned char value)
  102. {
  103. snd_ad1848_wait(chip);
  104. #ifdef CONFIG_SND_DEBUG
  105. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  106. snd_printk(KERN_WARNING "auto calibration time out - "
  107. "reg = 0x%x, value = 0x%x\n", reg, value);
  108. #endif
  109. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  110. outb(chip->image[reg] = value, AD1848P(chip, REG));
  111. mb();
  112. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  113. chip->mce_bit | reg, value);
  114. }
  115. EXPORT_SYMBOL(snd_ad1848_out);
  116. static void snd_ad1848_dout(struct snd_ad1848 *chip,
  117. unsigned char reg, unsigned char value)
  118. {
  119. snd_ad1848_wait(chip);
  120. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  121. outb(value, AD1848P(chip, REG));
  122. mb();
  123. }
  124. static unsigned char snd_ad1848_in(struct snd_ad1848 *chip, unsigned char reg)
  125. {
  126. snd_ad1848_wait(chip);
  127. #ifdef CONFIG_SND_DEBUG
  128. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  129. snd_printk(KERN_WARNING "auto calibration time out - "
  130. "reg = 0x%x\n", reg);
  131. #endif
  132. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  133. mb();
  134. return inb(AD1848P(chip, REG));
  135. }
  136. #if 0
  137. static void snd_ad1848_debug(struct snd_ad1848 *chip)
  138. {
  139. printk("AD1848 REGS: INDEX = 0x%02x ", inb(AD1848P(chip, REGSEL)));
  140. printk(" STATUS = 0x%02x\n", inb(AD1848P(chip, STATUS)));
  141. printk(" 0x00: left input = 0x%02x ", snd_ad1848_in(chip, 0x00));
  142. printk(" 0x08: playback format = 0x%02x\n", snd_ad1848_in(chip, 0x08));
  143. printk(" 0x01: right input = 0x%02x ", snd_ad1848_in(chip, 0x01));
  144. printk(" 0x09: iface (CFIG 1) = 0x%02x\n", snd_ad1848_in(chip, 0x09));
  145. printk(" 0x02: AUXA left = 0x%02x ", snd_ad1848_in(chip, 0x02));
  146. printk(" 0x0a: pin control = 0x%02x\n", snd_ad1848_in(chip, 0x0a));
  147. printk(" 0x03: AUXA right = 0x%02x ", snd_ad1848_in(chip, 0x03));
  148. printk(" 0x0b: init & status = 0x%02x\n", snd_ad1848_in(chip, 0x0b));
  149. printk(" 0x04: AUXB left = 0x%02x ", snd_ad1848_in(chip, 0x04));
  150. printk(" 0x0c: revision & mode = 0x%02x\n", snd_ad1848_in(chip, 0x0c));
  151. printk(" 0x05: AUXB right = 0x%02x ", snd_ad1848_in(chip, 0x05));
  152. printk(" 0x0d: loopback = 0x%02x\n", snd_ad1848_in(chip, 0x0d));
  153. printk(" 0x06: left output = 0x%02x ", snd_ad1848_in(chip, 0x06));
  154. printk(" 0x0e: data upr count = 0x%02x\n", snd_ad1848_in(chip, 0x0e));
  155. printk(" 0x07: right output = 0x%02x ", snd_ad1848_in(chip, 0x07));
  156. printk(" 0x0f: data lwr count = 0x%02x\n", snd_ad1848_in(chip, 0x0f));
  157. }
  158. #endif
  159. /*
  160. * AD1848 detection / MCE routines
  161. */
  162. static void snd_ad1848_mce_up(struct snd_ad1848 *chip)
  163. {
  164. unsigned long flags;
  165. int timeout;
  166. snd_ad1848_wait(chip);
  167. #ifdef CONFIG_SND_DEBUG
  168. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  169. snd_printk(KERN_WARNING "mce_up - auto calibration time out (0)\n");
  170. #endif
  171. spin_lock_irqsave(&chip->reg_lock, flags);
  172. chip->mce_bit |= AD1848_MCE;
  173. timeout = inb(AD1848P(chip, REGSEL));
  174. if (timeout == 0x80)
  175. snd_printk(KERN_WARNING "mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  176. if (!(timeout & AD1848_MCE))
  177. outb(chip->mce_bit | (timeout & 0x1f), AD1848P(chip, REGSEL));
  178. spin_unlock_irqrestore(&chip->reg_lock, flags);
  179. }
  180. static void snd_ad1848_mce_down(struct snd_ad1848 *chip)
  181. {
  182. unsigned long flags, timeout;
  183. int reg;
  184. spin_lock_irqsave(&chip->reg_lock, flags);
  185. for (timeout = 5; timeout > 0; timeout--)
  186. inb(AD1848P(chip, REGSEL));
  187. /* end of cleanup sequence */
  188. for (timeout = 12000; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  189. udelay(100);
  190. snd_printdd("(1) timeout = %ld\n", timeout);
  191. #ifdef CONFIG_SND_DEBUG
  192. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  193. snd_printk(KERN_WARNING "mce_down [0x%lx] - auto calibration time out (0)\n", AD1848P(chip, REGSEL));
  194. #endif
  195. chip->mce_bit &= ~AD1848_MCE;
  196. reg = inb(AD1848P(chip, REGSEL));
  197. outb(chip->mce_bit | (reg & 0x1f), AD1848P(chip, REGSEL));
  198. if (reg == 0x80)
  199. snd_printk(KERN_WARNING "mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  200. if ((reg & AD1848_MCE) == 0) {
  201. spin_unlock_irqrestore(&chip->reg_lock, flags);
  202. return;
  203. }
  204. /*
  205. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  206. * It may take up to 5 sample periods (at most 907 us @ 5.5125 kHz) for
  207. * the process to _start_, so it is important to wait at least that long
  208. * before checking. Otherwise we might think AC has finished when it
  209. * has in fact not begun. It could take 128 (no AC) or 384 (AC) cycles
  210. * for ACI to drop. This gives a wait of at most 70 ms with a more
  211. * typical value of 3-9 ms.
  212. */
  213. timeout = jiffies + msecs_to_jiffies(250);
  214. do {
  215. spin_unlock_irqrestore(&chip->reg_lock, flags);
  216. msleep(1);
  217. spin_lock_irqsave(&chip->reg_lock, flags);
  218. reg = snd_ad1848_in(chip, AD1848_TEST_INIT) &
  219. AD1848_CALIB_IN_PROGRESS;
  220. } while (reg && time_before(jiffies, timeout));
  221. spin_unlock_irqrestore(&chip->reg_lock, flags);
  222. if (reg)
  223. snd_printk(KERN_ERR
  224. "mce_down - auto calibration time out (2)\n");
  225. snd_printdd("(4) jiffies = %lu\n", jiffies);
  226. snd_printd("mce_down - exit = 0x%x\n", inb(AD1848P(chip, REGSEL)));
  227. }
  228. static unsigned int snd_ad1848_get_count(unsigned char format,
  229. unsigned int size)
  230. {
  231. switch (format & 0xe0) {
  232. case AD1848_LINEAR_16:
  233. size >>= 1;
  234. break;
  235. }
  236. if (format & AD1848_STEREO)
  237. size >>= 1;
  238. return size;
  239. }
  240. static int snd_ad1848_trigger(struct snd_ad1848 *chip, unsigned char what,
  241. int channel, int cmd)
  242. {
  243. int result = 0;
  244. #if 0
  245. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, inb(AD1848P(card, STATUS)));
  246. #endif
  247. spin_lock(&chip->reg_lock);
  248. if (cmd == SNDRV_PCM_TRIGGER_START) {
  249. if (chip->image[AD1848_IFACE_CTRL] & what) {
  250. spin_unlock(&chip->reg_lock);
  251. return 0;
  252. }
  253. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] |= what);
  254. chip->mode |= AD1848_MODE_RUNNING;
  255. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  256. if (!(chip->image[AD1848_IFACE_CTRL] & what)) {
  257. spin_unlock(&chip->reg_lock);
  258. return 0;
  259. }
  260. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] &= ~what);
  261. chip->mode &= ~AD1848_MODE_RUNNING;
  262. } else {
  263. result = -EINVAL;
  264. }
  265. spin_unlock(&chip->reg_lock);
  266. return result;
  267. }
  268. /*
  269. * CODEC I/O
  270. */
  271. static unsigned char snd_ad1848_get_rate(unsigned int rate)
  272. {
  273. int i;
  274. for (i = 0; i < ARRAY_SIZE(rates); i++)
  275. if (rate == rates[i])
  276. return freq_bits[i];
  277. snd_BUG();
  278. return freq_bits[ARRAY_SIZE(rates) - 1];
  279. }
  280. static int snd_ad1848_ioctl(struct snd_pcm_substream *substream,
  281. unsigned int cmd, void *arg)
  282. {
  283. return snd_pcm_lib_ioctl(substream, cmd, arg);
  284. }
  285. static unsigned char snd_ad1848_get_format(int format, int channels)
  286. {
  287. unsigned char rformat;
  288. rformat = AD1848_LINEAR_8;
  289. switch (format) {
  290. case SNDRV_PCM_FORMAT_A_LAW: rformat = AD1848_ALAW_8; break;
  291. case SNDRV_PCM_FORMAT_MU_LAW: rformat = AD1848_ULAW_8; break;
  292. case SNDRV_PCM_FORMAT_S16_LE: rformat = AD1848_LINEAR_16; break;
  293. }
  294. if (channels > 1)
  295. rformat |= AD1848_STEREO;
  296. #if 0
  297. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  298. #endif
  299. return rformat;
  300. }
  301. static void snd_ad1848_calibrate_mute(struct snd_ad1848 *chip, int mute)
  302. {
  303. unsigned long flags;
  304. mute = mute ? 1 : 0;
  305. spin_lock_irqsave(&chip->reg_lock, flags);
  306. if (chip->calibrate_mute == mute) {
  307. spin_unlock_irqrestore(&chip->reg_lock, flags);
  308. return;
  309. }
  310. if (!mute) {
  311. snd_ad1848_dout(chip, AD1848_LEFT_INPUT, chip->image[AD1848_LEFT_INPUT]);
  312. snd_ad1848_dout(chip, AD1848_RIGHT_INPUT, chip->image[AD1848_RIGHT_INPUT]);
  313. }
  314. snd_ad1848_dout(chip, AD1848_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_LEFT_INPUT]);
  315. snd_ad1848_dout(chip, AD1848_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_RIGHT_INPUT]);
  316. snd_ad1848_dout(chip, AD1848_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_LEFT_INPUT]);
  317. snd_ad1848_dout(chip, AD1848_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_RIGHT_INPUT]);
  318. snd_ad1848_dout(chip, AD1848_LEFT_OUTPUT, mute ? 0x80 : chip->image[AD1848_LEFT_OUTPUT]);
  319. snd_ad1848_dout(chip, AD1848_RIGHT_OUTPUT, mute ? 0x80 : chip->image[AD1848_RIGHT_OUTPUT]);
  320. chip->calibrate_mute = mute;
  321. spin_unlock_irqrestore(&chip->reg_lock, flags);
  322. }
  323. static void snd_ad1848_set_data_format(struct snd_ad1848 *chip, struct snd_pcm_hw_params *hw_params)
  324. {
  325. if (hw_params == NULL) {
  326. chip->image[AD1848_DATA_FORMAT] = 0x20;
  327. } else {
  328. chip->image[AD1848_DATA_FORMAT] =
  329. snd_ad1848_get_format(params_format(hw_params), params_channels(hw_params)) |
  330. snd_ad1848_get_rate(params_rate(hw_params));
  331. }
  332. // snd_printk(">>> pmode = 0x%x, dfr = 0x%x\n", pstr->mode, chip->image[AD1848_DATA_FORMAT]);
  333. }
  334. static int snd_ad1848_open(struct snd_ad1848 *chip, unsigned int mode)
  335. {
  336. unsigned long flags;
  337. if (chip->mode & AD1848_MODE_OPEN)
  338. return -EAGAIN;
  339. snd_ad1848_mce_down(chip);
  340. #ifdef SNDRV_DEBUG_MCE
  341. snd_printk("open: (1)\n");
  342. #endif
  343. snd_ad1848_mce_up(chip);
  344. spin_lock_irqsave(&chip->reg_lock, flags);
  345. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  346. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO |
  347. AD1848_CALIB_MODE);
  348. chip->image[AD1848_IFACE_CTRL] |= AD1848_AUTOCALIB;
  349. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  350. spin_unlock_irqrestore(&chip->reg_lock, flags);
  351. snd_ad1848_mce_down(chip);
  352. #ifdef SNDRV_DEBUG_MCE
  353. snd_printk("open: (2)\n");
  354. #endif
  355. snd_ad1848_set_data_format(chip, NULL);
  356. snd_ad1848_mce_up(chip);
  357. spin_lock_irqsave(&chip->reg_lock, flags);
  358. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  359. spin_unlock_irqrestore(&chip->reg_lock, flags);
  360. snd_ad1848_mce_down(chip);
  361. #ifdef SNDRV_DEBUG_MCE
  362. snd_printk("open: (3)\n");
  363. #endif
  364. /* ok. now enable and ack CODEC IRQ */
  365. spin_lock_irqsave(&chip->reg_lock, flags);
  366. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  367. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  368. chip->image[AD1848_PIN_CTRL] |= AD1848_IRQ_ENABLE;
  369. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  370. spin_unlock_irqrestore(&chip->reg_lock, flags);
  371. chip->mode = mode;
  372. return 0;
  373. }
  374. static void snd_ad1848_close(struct snd_ad1848 *chip)
  375. {
  376. unsigned long flags;
  377. if (!chip->mode)
  378. return;
  379. /* disable IRQ */
  380. spin_lock_irqsave(&chip->reg_lock, flags);
  381. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  382. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  383. chip->image[AD1848_PIN_CTRL] &= ~AD1848_IRQ_ENABLE;
  384. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  385. spin_unlock_irqrestore(&chip->reg_lock, flags);
  386. /* now disable capture & playback */
  387. snd_ad1848_mce_up(chip);
  388. spin_lock_irqsave(&chip->reg_lock, flags);
  389. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  390. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  391. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  392. spin_unlock_irqrestore(&chip->reg_lock, flags);
  393. snd_ad1848_mce_down(chip);
  394. /* clear IRQ again */
  395. spin_lock_irqsave(&chip->reg_lock, flags);
  396. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  397. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  398. spin_unlock_irqrestore(&chip->reg_lock, flags);
  399. chip->mode = 0;
  400. }
  401. /*
  402. * ok.. exported functions..
  403. */
  404. static int snd_ad1848_playback_trigger(struct snd_pcm_substream *substream,
  405. int cmd)
  406. {
  407. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  408. return snd_ad1848_trigger(chip, AD1848_PLAYBACK_ENABLE, SNDRV_PCM_STREAM_PLAYBACK, cmd);
  409. }
  410. static int snd_ad1848_capture_trigger(struct snd_pcm_substream *substream,
  411. int cmd)
  412. {
  413. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  414. return snd_ad1848_trigger(chip, AD1848_CAPTURE_ENABLE, SNDRV_PCM_STREAM_CAPTURE, cmd);
  415. }
  416. static int snd_ad1848_playback_hw_params(struct snd_pcm_substream *substream,
  417. struct snd_pcm_hw_params *hw_params)
  418. {
  419. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  420. unsigned long flags;
  421. int err;
  422. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  423. return err;
  424. snd_ad1848_calibrate_mute(chip, 1);
  425. snd_ad1848_set_data_format(chip, hw_params);
  426. snd_ad1848_mce_up(chip);
  427. spin_lock_irqsave(&chip->reg_lock, flags);
  428. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  429. spin_unlock_irqrestore(&chip->reg_lock, flags);
  430. snd_ad1848_mce_down(chip);
  431. snd_ad1848_calibrate_mute(chip, 0);
  432. return 0;
  433. }
  434. static int snd_ad1848_playback_hw_free(struct snd_pcm_substream *substream)
  435. {
  436. return snd_pcm_lib_free_pages(substream);
  437. }
  438. static int snd_ad1848_playback_prepare(struct snd_pcm_substream *substream)
  439. {
  440. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  441. struct snd_pcm_runtime *runtime = substream->runtime;
  442. unsigned long flags;
  443. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  444. unsigned int count = snd_pcm_lib_period_bytes(substream);
  445. chip->dma_size = size;
  446. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO);
  447. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  448. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  449. spin_lock_irqsave(&chip->reg_lock, flags);
  450. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  451. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  452. spin_unlock_irqrestore(&chip->reg_lock, flags);
  453. return 0;
  454. }
  455. static int snd_ad1848_capture_hw_params(struct snd_pcm_substream *substream,
  456. struct snd_pcm_hw_params *hw_params)
  457. {
  458. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  459. unsigned long flags;
  460. int err;
  461. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  462. return err;
  463. snd_ad1848_calibrate_mute(chip, 1);
  464. snd_ad1848_set_data_format(chip, hw_params);
  465. snd_ad1848_mce_up(chip);
  466. spin_lock_irqsave(&chip->reg_lock, flags);
  467. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  468. spin_unlock_irqrestore(&chip->reg_lock, flags);
  469. snd_ad1848_mce_down(chip);
  470. snd_ad1848_calibrate_mute(chip, 0);
  471. return 0;
  472. }
  473. static int snd_ad1848_capture_hw_free(struct snd_pcm_substream *substream)
  474. {
  475. return snd_pcm_lib_free_pages(substream);
  476. }
  477. static int snd_ad1848_capture_prepare(struct snd_pcm_substream *substream)
  478. {
  479. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  480. struct snd_pcm_runtime *runtime = substream->runtime;
  481. unsigned long flags;
  482. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  483. unsigned int count = snd_pcm_lib_period_bytes(substream);
  484. chip->dma_size = size;
  485. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  486. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  487. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  488. spin_lock_irqsave(&chip->reg_lock, flags);
  489. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  490. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  491. spin_unlock_irqrestore(&chip->reg_lock, flags);
  492. return 0;
  493. }
  494. static irqreturn_t snd_ad1848_interrupt(int irq, void *dev_id)
  495. {
  496. struct snd_ad1848 *chip = dev_id;
  497. if ((chip->mode & AD1848_MODE_PLAY) && chip->playback_substream &&
  498. (chip->mode & AD1848_MODE_RUNNING))
  499. snd_pcm_period_elapsed(chip->playback_substream);
  500. if ((chip->mode & AD1848_MODE_CAPTURE) && chip->capture_substream &&
  501. (chip->mode & AD1848_MODE_RUNNING))
  502. snd_pcm_period_elapsed(chip->capture_substream);
  503. outb(0, AD1848P(chip, STATUS)); /* clear global interrupt bit */
  504. return IRQ_HANDLED;
  505. }
  506. static snd_pcm_uframes_t snd_ad1848_playback_pointer(struct snd_pcm_substream *substream)
  507. {
  508. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  509. size_t ptr;
  510. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_PLAYBACK_ENABLE))
  511. return 0;
  512. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  513. return bytes_to_frames(substream->runtime, ptr);
  514. }
  515. static snd_pcm_uframes_t snd_ad1848_capture_pointer(struct snd_pcm_substream *substream)
  516. {
  517. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  518. size_t ptr;
  519. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_CAPTURE_ENABLE))
  520. return 0;
  521. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  522. return bytes_to_frames(substream->runtime, ptr);
  523. }
  524. /*
  525. */
  526. static void snd_ad1848_thinkpad_twiddle(struct snd_ad1848 *chip, int on) {
  527. int tmp;
  528. if (!chip->thinkpad_flag) return;
  529. outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
  530. tmp = inb(AD1848_THINKPAD_CTL_PORT2);
  531. if (on)
  532. /* turn it on */
  533. tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
  534. else
  535. /* turn it off */
  536. tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
  537. outb(tmp, AD1848_THINKPAD_CTL_PORT2);
  538. }
  539. #ifdef CONFIG_PM
  540. static void snd_ad1848_suspend(struct snd_ad1848 *chip)
  541. {
  542. snd_pcm_suspend_all(chip->pcm);
  543. if (chip->thinkpad_flag)
  544. snd_ad1848_thinkpad_twiddle(chip, 0);
  545. }
  546. static void snd_ad1848_resume(struct snd_ad1848 *chip)
  547. {
  548. int i;
  549. if (chip->thinkpad_flag)
  550. snd_ad1848_thinkpad_twiddle(chip, 1);
  551. /* clear any pendings IRQ */
  552. inb(AD1848P(chip, STATUS));
  553. outb(0, AD1848P(chip, STATUS));
  554. mb();
  555. snd_ad1848_mce_down(chip);
  556. for (i = 0; i < 16; i++)
  557. snd_ad1848_out(chip, i, chip->image[i]);
  558. snd_ad1848_mce_up(chip);
  559. snd_ad1848_mce_down(chip);
  560. }
  561. #endif /* CONFIG_PM */
  562. static int snd_ad1848_probe(struct snd_ad1848 * chip)
  563. {
  564. unsigned long flags;
  565. int i, id, rev, ad1847;
  566. unsigned char *ptr;
  567. #if 0
  568. snd_ad1848_debug(chip);
  569. #endif
  570. id = ad1847 = 0;
  571. for (i = 0; i < 1000; i++) {
  572. mb();
  573. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  574. udelay(500);
  575. else {
  576. spin_lock_irqsave(&chip->reg_lock, flags);
  577. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  578. snd_ad1848_out(chip, AD1848_LEFT_INPUT, 0xaa);
  579. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, 0x45);
  580. rev = snd_ad1848_in(chip, AD1848_RIGHT_INPUT);
  581. if (rev == 0x65) {
  582. spin_unlock_irqrestore(&chip->reg_lock, flags);
  583. id = 1;
  584. ad1847 = 1;
  585. break;
  586. }
  587. if (snd_ad1848_in(chip, AD1848_LEFT_INPUT) == 0xaa && rev == 0x45) {
  588. spin_unlock_irqrestore(&chip->reg_lock, flags);
  589. id = 1;
  590. break;
  591. }
  592. spin_unlock_irqrestore(&chip->reg_lock, flags);
  593. }
  594. }
  595. if (id != 1)
  596. return -ENODEV; /* no valid device found */
  597. if (chip->hardware == AD1848_HW_DETECT) {
  598. if (ad1847) {
  599. chip->hardware = AD1848_HW_AD1847;
  600. } else {
  601. chip->hardware = AD1848_HW_AD1848;
  602. rev = snd_ad1848_in(chip, AD1848_MISC_INFO);
  603. if (rev & 0x80) {
  604. chip->hardware = AD1848_HW_CS4248;
  605. } else if ((rev & 0x0f) == 0x0a) {
  606. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x40);
  607. for (i = 0; i < 16; ++i) {
  608. if (snd_ad1848_in(chip, i) != snd_ad1848_in(chip, i + 16)) {
  609. chip->hardware = AD1848_HW_CMI8330;
  610. break;
  611. }
  612. }
  613. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  614. }
  615. }
  616. }
  617. spin_lock_irqsave(&chip->reg_lock, flags);
  618. inb(AD1848P(chip, STATUS)); /* clear any pendings IRQ */
  619. outb(0, AD1848P(chip, STATUS));
  620. mb();
  621. spin_unlock_irqrestore(&chip->reg_lock, flags);
  622. chip->image[AD1848_MISC_INFO] = 0x00;
  623. chip->image[AD1848_IFACE_CTRL] =
  624. (chip->image[AD1848_IFACE_CTRL] & ~AD1848_SINGLE_DMA) | AD1848_SINGLE_DMA;
  625. ptr = (unsigned char *) &chip->image;
  626. snd_ad1848_mce_down(chip);
  627. spin_lock_irqsave(&chip->reg_lock, flags);
  628. for (i = 0; i < 16; i++) /* ok.. fill all AD1848 registers */
  629. snd_ad1848_out(chip, i, *ptr++);
  630. spin_unlock_irqrestore(&chip->reg_lock, flags);
  631. snd_ad1848_mce_up(chip);
  632. snd_ad1848_mce_down(chip);
  633. return 0; /* all things are ok.. */
  634. }
  635. /*
  636. */
  637. static struct snd_pcm_hardware snd_ad1848_playback =
  638. {
  639. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  640. SNDRV_PCM_INFO_MMAP_VALID),
  641. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  642. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  643. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  644. .rate_min = 5510,
  645. .rate_max = 48000,
  646. .channels_min = 1,
  647. .channels_max = 2,
  648. .buffer_bytes_max = (128*1024),
  649. .period_bytes_min = 64,
  650. .period_bytes_max = (128*1024),
  651. .periods_min = 1,
  652. .periods_max = 1024,
  653. .fifo_size = 0,
  654. };
  655. static struct snd_pcm_hardware snd_ad1848_capture =
  656. {
  657. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  658. SNDRV_PCM_INFO_MMAP_VALID),
  659. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  660. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  661. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  662. .rate_min = 5510,
  663. .rate_max = 48000,
  664. .channels_min = 1,
  665. .channels_max = 2,
  666. .buffer_bytes_max = (128*1024),
  667. .period_bytes_min = 64,
  668. .period_bytes_max = (128*1024),
  669. .periods_min = 1,
  670. .periods_max = 1024,
  671. .fifo_size = 0,
  672. };
  673. /*
  674. */
  675. static int snd_ad1848_playback_open(struct snd_pcm_substream *substream)
  676. {
  677. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  678. struct snd_pcm_runtime *runtime = substream->runtime;
  679. int err;
  680. if ((err = snd_ad1848_open(chip, AD1848_MODE_PLAY)) < 0)
  681. return err;
  682. chip->playback_substream = substream;
  683. runtime->hw = snd_ad1848_playback;
  684. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  685. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  686. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  687. return 0;
  688. }
  689. static int snd_ad1848_capture_open(struct snd_pcm_substream *substream)
  690. {
  691. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  692. struct snd_pcm_runtime *runtime = substream->runtime;
  693. int err;
  694. if ((err = snd_ad1848_open(chip, AD1848_MODE_CAPTURE)) < 0)
  695. return err;
  696. chip->capture_substream = substream;
  697. runtime->hw = snd_ad1848_capture;
  698. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  699. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  700. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  701. return 0;
  702. }
  703. static int snd_ad1848_playback_close(struct snd_pcm_substream *substream)
  704. {
  705. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  706. chip->mode &= ~AD1848_MODE_PLAY;
  707. chip->playback_substream = NULL;
  708. snd_ad1848_close(chip);
  709. return 0;
  710. }
  711. static int snd_ad1848_capture_close(struct snd_pcm_substream *substream)
  712. {
  713. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  714. chip->mode &= ~AD1848_MODE_CAPTURE;
  715. chip->capture_substream = NULL;
  716. snd_ad1848_close(chip);
  717. return 0;
  718. }
  719. static int snd_ad1848_free(struct snd_ad1848 *chip)
  720. {
  721. release_and_free_resource(chip->res_port);
  722. if (chip->irq >= 0)
  723. free_irq(chip->irq, (void *) chip);
  724. if (chip->dma >= 0) {
  725. snd_dma_disable(chip->dma);
  726. free_dma(chip->dma);
  727. }
  728. kfree(chip);
  729. return 0;
  730. }
  731. static int snd_ad1848_dev_free(struct snd_device *device)
  732. {
  733. struct snd_ad1848 *chip = device->device_data;
  734. return snd_ad1848_free(chip);
  735. }
  736. static const char *snd_ad1848_chip_id(struct snd_ad1848 *chip)
  737. {
  738. switch (chip->hardware) {
  739. case AD1848_HW_AD1847: return "AD1847";
  740. case AD1848_HW_AD1848: return "AD1848";
  741. case AD1848_HW_CS4248: return "CS4248";
  742. case AD1848_HW_CMI8330: return "CMI8330/C3D";
  743. default: return "???";
  744. }
  745. }
  746. int snd_ad1848_create(struct snd_card *card,
  747. unsigned long port,
  748. int irq, int dma,
  749. unsigned short hardware,
  750. struct snd_ad1848 ** rchip)
  751. {
  752. static struct snd_device_ops ops = {
  753. .dev_free = snd_ad1848_dev_free,
  754. };
  755. struct snd_ad1848 *chip;
  756. int err;
  757. *rchip = NULL;
  758. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  759. if (chip == NULL)
  760. return -ENOMEM;
  761. spin_lock_init(&chip->reg_lock);
  762. chip->card = card;
  763. chip->port = port;
  764. chip->irq = -1;
  765. chip->dma = -1;
  766. chip->hardware = hardware;
  767. memcpy(&chip->image, &snd_ad1848_original_image, sizeof(snd_ad1848_original_image));
  768. if ((chip->res_port = request_region(port, 4, "AD1848")) == NULL) {
  769. snd_printk(KERN_ERR "ad1848: can't grab port 0x%lx\n", port);
  770. snd_ad1848_free(chip);
  771. return -EBUSY;
  772. }
  773. if (request_irq(irq, snd_ad1848_interrupt, IRQF_DISABLED, "AD1848", (void *) chip)) {
  774. snd_printk(KERN_ERR "ad1848: can't grab IRQ %d\n", irq);
  775. snd_ad1848_free(chip);
  776. return -EBUSY;
  777. }
  778. chip->irq = irq;
  779. if (request_dma(dma, "AD1848")) {
  780. snd_printk(KERN_ERR "ad1848: can't grab DMA %d\n", dma);
  781. snd_ad1848_free(chip);
  782. return -EBUSY;
  783. }
  784. chip->dma = dma;
  785. if (hardware == AD1848_HW_THINKPAD) {
  786. chip->thinkpad_flag = 1;
  787. chip->hardware = AD1848_HW_DETECT; /* reset */
  788. snd_ad1848_thinkpad_twiddle(chip, 1);
  789. }
  790. if (snd_ad1848_probe(chip) < 0) {
  791. snd_ad1848_free(chip);
  792. return -ENODEV;
  793. }
  794. /* Register device */
  795. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  796. snd_ad1848_free(chip);
  797. return err;
  798. }
  799. #ifdef CONFIG_PM
  800. chip->suspend = snd_ad1848_suspend;
  801. chip->resume = snd_ad1848_resume;
  802. #endif
  803. *rchip = chip;
  804. return 0;
  805. }
  806. EXPORT_SYMBOL(snd_ad1848_create);
  807. static struct snd_pcm_ops snd_ad1848_playback_ops = {
  808. .open = snd_ad1848_playback_open,
  809. .close = snd_ad1848_playback_close,
  810. .ioctl = snd_ad1848_ioctl,
  811. .hw_params = snd_ad1848_playback_hw_params,
  812. .hw_free = snd_ad1848_playback_hw_free,
  813. .prepare = snd_ad1848_playback_prepare,
  814. .trigger = snd_ad1848_playback_trigger,
  815. .pointer = snd_ad1848_playback_pointer,
  816. };
  817. static struct snd_pcm_ops snd_ad1848_capture_ops = {
  818. .open = snd_ad1848_capture_open,
  819. .close = snd_ad1848_capture_close,
  820. .ioctl = snd_ad1848_ioctl,
  821. .hw_params = snd_ad1848_capture_hw_params,
  822. .hw_free = snd_ad1848_capture_hw_free,
  823. .prepare = snd_ad1848_capture_prepare,
  824. .trigger = snd_ad1848_capture_trigger,
  825. .pointer = snd_ad1848_capture_pointer,
  826. };
  827. int snd_ad1848_pcm(struct snd_ad1848 *chip, int device, struct snd_pcm **rpcm)
  828. {
  829. struct snd_pcm *pcm;
  830. int err;
  831. if ((err = snd_pcm_new(chip->card, "AD1848", device, 1, 1, &pcm)) < 0)
  832. return err;
  833. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ad1848_playback_ops);
  834. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ad1848_capture_ops);
  835. pcm->private_data = chip;
  836. pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  837. strcpy(pcm->name, snd_ad1848_chip_id(chip));
  838. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  839. snd_dma_isa_data(),
  840. 64*1024, chip->dma > 3 ? 128*1024 : 64*1024);
  841. chip->pcm = pcm;
  842. if (rpcm)
  843. *rpcm = pcm;
  844. return 0;
  845. }
  846. EXPORT_SYMBOL(snd_ad1848_pcm);
  847. const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction)
  848. {
  849. return direction == SNDRV_PCM_STREAM_PLAYBACK ?
  850. &snd_ad1848_playback_ops : &snd_ad1848_capture_ops;
  851. }
  852. EXPORT_SYMBOL(snd_ad1848_get_pcm_ops);
  853. /*
  854. * MIXER part
  855. */
  856. static int snd_ad1848_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  857. {
  858. static char *texts[4] = {
  859. "Line", "Aux", "Mic", "Mix"
  860. };
  861. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  862. uinfo->count = 2;
  863. uinfo->value.enumerated.items = 4;
  864. if (uinfo->value.enumerated.item > 3)
  865. uinfo->value.enumerated.item = 3;
  866. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  867. return 0;
  868. }
  869. static int snd_ad1848_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  870. {
  871. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  872. unsigned long flags;
  873. spin_lock_irqsave(&chip->reg_lock, flags);
  874. ucontrol->value.enumerated.item[0] = (chip->image[AD1848_LEFT_INPUT] & AD1848_MIXS_ALL) >> 6;
  875. ucontrol->value.enumerated.item[1] = (chip->image[AD1848_RIGHT_INPUT] & AD1848_MIXS_ALL) >> 6;
  876. spin_unlock_irqrestore(&chip->reg_lock, flags);
  877. return 0;
  878. }
  879. static int snd_ad1848_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  880. {
  881. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  882. unsigned long flags;
  883. unsigned short left, right;
  884. int change;
  885. if (ucontrol->value.enumerated.item[0] > 3 ||
  886. ucontrol->value.enumerated.item[1] > 3)
  887. return -EINVAL;
  888. left = ucontrol->value.enumerated.item[0] << 6;
  889. right = ucontrol->value.enumerated.item[1] << 6;
  890. spin_lock_irqsave(&chip->reg_lock, flags);
  891. left = (chip->image[AD1848_LEFT_INPUT] & ~AD1848_MIXS_ALL) | left;
  892. right = (chip->image[AD1848_RIGHT_INPUT] & ~AD1848_MIXS_ALL) | right;
  893. change = left != chip->image[AD1848_LEFT_INPUT] ||
  894. right != chip->image[AD1848_RIGHT_INPUT];
  895. snd_ad1848_out(chip, AD1848_LEFT_INPUT, left);
  896. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, right);
  897. spin_unlock_irqrestore(&chip->reg_lock, flags);
  898. return change;
  899. }
  900. static int snd_ad1848_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  901. {
  902. int mask = (kcontrol->private_value >> 16) & 0xff;
  903. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  904. uinfo->count = 1;
  905. uinfo->value.integer.min = 0;
  906. uinfo->value.integer.max = mask;
  907. return 0;
  908. }
  909. static int snd_ad1848_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  910. {
  911. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  912. unsigned long flags;
  913. int reg = kcontrol->private_value & 0xff;
  914. int shift = (kcontrol->private_value >> 8) & 0xff;
  915. int mask = (kcontrol->private_value >> 16) & 0xff;
  916. int invert = (kcontrol->private_value >> 24) & 0xff;
  917. spin_lock_irqsave(&chip->reg_lock, flags);
  918. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  919. spin_unlock_irqrestore(&chip->reg_lock, flags);
  920. if (invert)
  921. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  922. return 0;
  923. }
  924. static int snd_ad1848_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  925. {
  926. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  927. unsigned long flags;
  928. int reg = kcontrol->private_value & 0xff;
  929. int shift = (kcontrol->private_value >> 8) & 0xff;
  930. int mask = (kcontrol->private_value >> 16) & 0xff;
  931. int invert = (kcontrol->private_value >> 24) & 0xff;
  932. int change;
  933. unsigned short val;
  934. val = (ucontrol->value.integer.value[0] & mask);
  935. if (invert)
  936. val = mask - val;
  937. val <<= shift;
  938. spin_lock_irqsave(&chip->reg_lock, flags);
  939. val = (chip->image[reg] & ~(mask << shift)) | val;
  940. change = val != chip->image[reg];
  941. snd_ad1848_out(chip, reg, val);
  942. spin_unlock_irqrestore(&chip->reg_lock, flags);
  943. return change;
  944. }
  945. static int snd_ad1848_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  946. {
  947. int mask = (kcontrol->private_value >> 24) & 0xff;
  948. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  949. uinfo->count = 2;
  950. uinfo->value.integer.min = 0;
  951. uinfo->value.integer.max = mask;
  952. return 0;
  953. }
  954. static int snd_ad1848_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  955. {
  956. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  957. unsigned long flags;
  958. int left_reg = kcontrol->private_value & 0xff;
  959. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  960. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  961. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  962. int mask = (kcontrol->private_value >> 24) & 0xff;
  963. int invert = (kcontrol->private_value >> 22) & 1;
  964. spin_lock_irqsave(&chip->reg_lock, flags);
  965. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  966. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  967. spin_unlock_irqrestore(&chip->reg_lock, flags);
  968. if (invert) {
  969. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  970. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  971. }
  972. return 0;
  973. }
  974. static int snd_ad1848_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  975. {
  976. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  977. unsigned long flags;
  978. int left_reg = kcontrol->private_value & 0xff;
  979. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  980. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  981. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  982. int mask = (kcontrol->private_value >> 24) & 0xff;
  983. int invert = (kcontrol->private_value >> 22) & 1;
  984. int change;
  985. unsigned short val1, val2;
  986. val1 = ucontrol->value.integer.value[0] & mask;
  987. val2 = ucontrol->value.integer.value[1] & mask;
  988. if (invert) {
  989. val1 = mask - val1;
  990. val2 = mask - val2;
  991. }
  992. val1 <<= shift_left;
  993. val2 <<= shift_right;
  994. spin_lock_irqsave(&chip->reg_lock, flags);
  995. if (left_reg != right_reg) {
  996. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  997. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  998. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  999. snd_ad1848_out(chip, left_reg, val1);
  1000. snd_ad1848_out(chip, right_reg, val2);
  1001. } else {
  1002. val1 = (chip->image[left_reg] & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1003. change = val1 != chip->image[left_reg];
  1004. snd_ad1848_out(chip, left_reg, val1);
  1005. }
  1006. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1007. return change;
  1008. }
  1009. /*
  1010. */
  1011. int snd_ad1848_add_ctl_elem(struct snd_ad1848 *chip,
  1012. const struct ad1848_mix_elem *c)
  1013. {
  1014. static struct snd_kcontrol_new newctls[] = {
  1015. [AD1848_MIX_SINGLE] = {
  1016. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1017. .info = snd_ad1848_info_single,
  1018. .get = snd_ad1848_get_single,
  1019. .put = snd_ad1848_put_single,
  1020. },
  1021. [AD1848_MIX_DOUBLE] = {
  1022. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1023. .info = snd_ad1848_info_double,
  1024. .get = snd_ad1848_get_double,
  1025. .put = snd_ad1848_put_double,
  1026. },
  1027. [AD1848_MIX_CAPTURE] = {
  1028. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1029. .info = snd_ad1848_info_mux,
  1030. .get = snd_ad1848_get_mux,
  1031. .put = snd_ad1848_put_mux,
  1032. },
  1033. };
  1034. struct snd_kcontrol *ctl;
  1035. int err;
  1036. ctl = snd_ctl_new1(&newctls[c->type], chip);
  1037. if (! ctl)
  1038. return -ENOMEM;
  1039. strlcpy(ctl->id.name, c->name, sizeof(ctl->id.name));
  1040. ctl->id.index = c->index;
  1041. ctl->private_value = c->private_value;
  1042. if (c->tlv) {
  1043. ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  1044. ctl->tlv.p = c->tlv;
  1045. }
  1046. if ((err = snd_ctl_add(chip->card, ctl)) < 0)
  1047. return err;
  1048. return 0;
  1049. }
  1050. EXPORT_SYMBOL(snd_ad1848_add_ctl_elem);
  1051. static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
  1052. static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
  1053. static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
  1054. static struct ad1848_mix_elem snd_ad1848_controls[] = {
  1055. AD1848_DOUBLE("PCM Playback Switch", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 7, 7, 1, 1),
  1056. AD1848_DOUBLE_TLV("PCM Playback Volume", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 0, 0, 63, 1,
  1057. db_scale_6bit),
  1058. AD1848_DOUBLE("Aux Playback Switch", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1059. AD1848_DOUBLE_TLV("Aux Playback Volume", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
  1060. db_scale_5bit_12db_max),
  1061. AD1848_DOUBLE("Aux Playback Switch", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1062. AD1848_DOUBLE_TLV("Aux Playback Volume", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
  1063. db_scale_5bit_12db_max),
  1064. AD1848_DOUBLE_TLV("Capture Volume", 0, AD1848_LEFT_INPUT, AD1848_RIGHT_INPUT, 0, 0, 15, 0,
  1065. db_scale_rec_gain),
  1066. {
  1067. .name = "Capture Source",
  1068. .type = AD1848_MIX_CAPTURE,
  1069. },
  1070. AD1848_SINGLE("Loopback Capture Switch", 0, AD1848_LOOPBACK, 0, 1, 0),
  1071. AD1848_SINGLE_TLV("Loopback Capture Volume", 0, AD1848_LOOPBACK, 1, 63, 0,
  1072. db_scale_6bit),
  1073. };
  1074. int snd_ad1848_mixer(struct snd_ad1848 *chip)
  1075. {
  1076. struct snd_card *card;
  1077. struct snd_pcm *pcm;
  1078. unsigned int idx;
  1079. int err;
  1080. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1081. pcm = chip->pcm;
  1082. card = chip->card;
  1083. strcpy(card->mixername, pcm->name);
  1084. for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++)
  1085. if ((err = snd_ad1848_add_ctl_elem(chip, &snd_ad1848_controls[idx])) < 0)
  1086. return err;
  1087. return 0;
  1088. }
  1089. EXPORT_SYMBOL(snd_ad1848_mixer);
  1090. /*
  1091. * INIT part
  1092. */
  1093. static int __init alsa_ad1848_init(void)
  1094. {
  1095. return 0;
  1096. }
  1097. static void __exit alsa_ad1848_exit(void)
  1098. {
  1099. }
  1100. module_init(alsa_ad1848_init)
  1101. module_exit(alsa_ad1848_exit)