gart.h 1.7 KB

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  1. #ifndef _ASM_X8664_GART_H
  2. #define _ASM_X8664_GART_H 1
  3. #include <asm/e820.h>
  4. #include <asm/iommu.h>
  5. extern void set_up_gart_resume(u32, u32);
  6. extern int fallback_aper_order;
  7. extern int fallback_aper_force;
  8. extern int fix_aperture;
  9. /* PTE bits. */
  10. #define GPTE_VALID 1
  11. #define GPTE_COHERENT 2
  12. /* Aperture control register bits. */
  13. #define GARTEN (1<<0)
  14. #define DISGARTCPU (1<<4)
  15. #define DISGARTIO (1<<5)
  16. /* GART cache control register bits. */
  17. #define INVGART (1<<0)
  18. #define GARTPTEERR (1<<1)
  19. /* K8 On-cpu GART registers */
  20. #define AMD64_GARTAPERTURECTL 0x90
  21. #define AMD64_GARTAPERTUREBASE 0x94
  22. #define AMD64_GARTTABLEBASE 0x98
  23. #define AMD64_GARTCACHECTL 0x9c
  24. #define AMD64_GARTEN (1<<0)
  25. static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
  26. {
  27. u32 tmp, ctl;
  28. /* address of the mappings table */
  29. addr >>= 12;
  30. tmp = (u32) addr<<4;
  31. tmp &= ~0xf;
  32. pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
  33. /* Enable GART translation for this hammer. */
  34. pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
  35. ctl |= GARTEN;
  36. ctl &= ~(DISGARTCPU | DISGARTIO);
  37. pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
  38. }
  39. static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
  40. {
  41. if (!aper_base)
  42. return 0;
  43. if (aper_base + aper_size > 0x100000000ULL) {
  44. printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
  45. return 0;
  46. }
  47. if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
  48. printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
  49. return 0;
  50. }
  51. if (aper_size < min_size) {
  52. printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
  53. aper_size>>20, min_size>>20);
  54. return 0;
  55. }
  56. return 1;
  57. }
  58. #endif