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txx9
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txx927.h

txx927.h 3.8 KB
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  1. /*
    2. 

  2.  * Common definitions for TX3927/TX4927
    3. 

  3.  *
    4. 

  4.  * This file is subject to the terms and conditions of the GNU General Public
    5. 

  5.  * License.  See the file "COPYING" in the main directory of this archive
    6. 

  6.  * for more details.
    7. 

  7.  *
    8. 

  8.  * Copyright (C) 2000 Toshiba Corporation
    9. 

  9.  */
    10. 

  10. #ifndef __ASM_TXX9_TXX927_H
    11. 

  11. #define __ASM_TXX9_TXX927_H
    12. 

  12. 

  13. struct txx927_sio_reg {
    14. 

  14. 	volatile unsigned long lcr;
    15. 

  15. 	volatile unsigned long dicr;
    16. 

  16. 	volatile unsigned long disr;
    17. 

  17. 	volatile unsigned long cisr;
    18. 

  18. 	volatile unsigned long fcr;
    19. 

  19. 	volatile unsigned long flcr;
    20. 

  20. 	volatile unsigned long bgr;
    21. 

  21. 	volatile unsigned long tfifo;
    22. 

  22. 	volatile unsigned long rfifo;
    23. 

  23. };
    24. 

  24. 

  25. /*
    26. 

  26.  * SIO
    27. 

  27.  */
    28. 

  28. /* SILCR : Line Control */
    29. 

  29. #define TXx927_SILCR_SCS_MASK	0x00000060
    30. 

  30. #define TXx927_SILCR_SCS_IMCLK	0x00000000
    31. 

  31. #define TXx927_SILCR_SCS_IMCLK_BG	0x00000020
    32. 

  32. #define TXx927_SILCR_SCS_SCLK	0x00000040
    33. 

  33. #define TXx927_SILCR_SCS_SCLK_BG	0x00000060
    34. 

  34. #define TXx927_SILCR_UEPS	0x00000010
    35. 

  35. #define TXx927_SILCR_UPEN	0x00000008
    36. 

  36. #define TXx927_SILCR_USBL_MASK	0x00000004
    37. 

  37. #define TXx927_SILCR_USBL_1BIT	0x00000004
    38. 

  38. #define TXx927_SILCR_USBL_2BIT	0x00000000
    39. 

  39. #define TXx927_SILCR_UMODE_MASK	0x00000003
    40. 

  40. #define TXx927_SILCR_UMODE_8BIT	0x00000000
    41. 

  41. #define TXx927_SILCR_UMODE_7BIT	0x00000001
    42. 

  42. 

  43. /* SIDICR : DMA/Int. Control */
    44. 

  44. #define TXx927_SIDICR_TDE	0x00008000
    45. 

  45. #define TXx927_SIDICR_RDE	0x00004000
    46. 

  46. #define TXx927_SIDICR_TIE	0x00002000
    47. 

  47. #define TXx927_SIDICR_RIE	0x00001000
    48. 

  48. #define TXx927_SIDICR_SPIE	0x00000800
    49. 

  49. #define TXx927_SIDICR_CTSAC	0x00000600
    50. 

  50. #define TXx927_SIDICR_STIE_MASK	0x0000003f
    51. 

  51. #define TXx927_SIDICR_STIE_OERS		0x00000020
    52. 

  52. #define TXx927_SIDICR_STIE_CTSS		0x00000010
    53. 

  53. #define TXx927_SIDICR_STIE_RBRKD	0x00000008
    54. 

  54. #define TXx927_SIDICR_STIE_TRDY		0x00000004
    55. 

  55. #define TXx927_SIDICR_STIE_TXALS	0x00000002
    56. 

  56. #define TXx927_SIDICR_STIE_UBRKD	0x00000001
    57. 

  57. 

  58. /* SIDISR : DMA/Int. Status */
    59. 

  59. #define TXx927_SIDISR_UBRK	0x00008000
    60. 

  60. #define TXx927_SIDISR_UVALID	0x00004000
    61. 

  61. #define TXx927_SIDISR_UFER	0x00002000
    62. 

  62. #define TXx927_SIDISR_UPER	0x00001000
    63. 

  63. #define TXx927_SIDISR_UOER	0x00000800
    64. 

  64. #define TXx927_SIDISR_ERI	0x00000400
    65. 

  65. #define TXx927_SIDISR_TOUT	0x00000200
    66. 

  66. #define TXx927_SIDISR_TDIS	0x00000100
    67. 

  67. #define TXx927_SIDISR_RDIS	0x00000080
    68. 

  68. #define TXx927_SIDISR_STIS	0x00000040
    69. 

  69. #define TXx927_SIDISR_RFDN_MASK	0x0000001f
    70. 

  70. 

  71. /* SICISR : Change Int. Status */
    72. 

  72. #define TXx927_SICISR_OERS	0x00000020
    73. 

  73. #define TXx927_SICISR_CTSS	0x00000010
    74. 

  74. #define TXx927_SICISR_RBRKD	0x00000008
    75. 

  75. #define TXx927_SICISR_TRDY	0x00000004
    76. 

  76. #define TXx927_SICISR_TXALS	0x00000002
    77. 

  77. #define TXx927_SICISR_UBRKD	0x00000001
    78. 

  78. 

  79. /* SIFCR : FIFO Control */
    80. 

  80. #define TXx927_SIFCR_SWRST	0x00008000
    81. 

  81. #define TXx927_SIFCR_RDIL_MASK	0x00000180
    82. 

  82. #define TXx927_SIFCR_RDIL_1	0x00000000
    83. 

  83. #define TXx927_SIFCR_RDIL_4	0x00000080
    84. 

  84. #define TXx927_SIFCR_RDIL_8	0x00000100
    85. 

  85. #define TXx927_SIFCR_RDIL_12	0x00000180
    86. 

  86. #define TXx927_SIFCR_RDIL_MAX	0x00000180
    87. 

  87. #define TXx927_SIFCR_TDIL_MASK	0x00000018
    88. 

  88. #define TXx927_SIFCR_TDIL_MASK	0x00000018
    89. 

  89. #define TXx927_SIFCR_TDIL_1	0x00000000
    90. 

  90. #define TXx927_SIFCR_TDIL_4	0x00000001
    91. 

  91. #define TXx927_SIFCR_TDIL_8	0x00000010
    92. 

  92. #define TXx927_SIFCR_TDIL_MAX	0x00000010
    93. 

  93. #define TXx927_SIFCR_TFRST	0x00000004
    94. 

  94. #define TXx927_SIFCR_RFRST	0x00000002
    95. 

  95. #define TXx927_SIFCR_FRSTE	0x00000001
    96. 

  96. #define TXx927_SIO_TX_FIFO	8
    97. 

  97. #define TXx927_SIO_RX_FIFO	16
    98. 

  98. 

  99. /* SIFLCR : Flow Control */
    100. 

  100. #define TXx927_SIFLCR_RCS	0x00001000
    101. 

  101. #define TXx927_SIFLCR_TES	0x00000800
    102. 

  102. #define TXx927_SIFLCR_RTSSC	0x00000200
    103. 

  103. #define TXx927_SIFLCR_RSDE	0x00000100
    104. 

  104. #define TXx927_SIFLCR_TSDE	0x00000080
    105. 

  105. #define TXx927_SIFLCR_RTSTL_MASK	0x0000001e
    106. 

  106. #define TXx927_SIFLCR_RTSTL_MAX	0x0000001e
    107. 

  107. #define TXx927_SIFLCR_TBRK	0x00000001
    108. 

  108. 

  109. /* SIBGR : Baudrate Control */
    110. 

  110. #define TXx927_SIBGR_BCLK_MASK	0x00000300
    111. 

  111. #define TXx927_SIBGR_BCLK_T0	0x00000000
    112. 

  112. #define TXx927_SIBGR_BCLK_T2	0x00000100
    113. 

  113. #define TXx927_SIBGR_BCLK_T4	0x00000200
    114. 

  114. #define TXx927_SIBGR_BCLK_T6	0x00000300
    115. 

  115. #define TXx927_SIBGR_BRD_MASK	0x000000ff
    116. 

  116. 

  117. /*
    118. 

  118.  * PIO
    119. 

  119.  */
    120. 

  120. 

  121. #endif /* __ASM_TXX9_TXX927_H */
    122.