pxafb.c 48 KB

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  1. /*
  2. * linux/drivers/video/pxafb.c
  3. *
  4. * Copyright (C) 1999 Eric A. Thomas.
  5. * Copyright (C) 2004 Jean-Frederic Clere.
  6. * Copyright (C) 2004 Ian Campbell.
  7. * Copyright (C) 2004 Jeff Lackey.
  8. * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
  9. * which in turn is
  10. * Based on acornfb.c Copyright (C) Russell King.
  11. *
  12. * This file is subject to the terms and conditions of the GNU General Public
  13. * License. See the file COPYING in the main directory of this archive for
  14. * more details.
  15. *
  16. * Intel PXA250/210 LCD Controller Frame Buffer Driver
  17. *
  18. * Please direct your questions and comments on this driver to the following
  19. * email address:
  20. *
  21. * linux-arm-kernel@lists.arm.linux.org.uk
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/kernel.h>
  27. #include <linux/sched.h>
  28. #include <linux/errno.h>
  29. #include <linux/string.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/slab.h>
  32. #include <linux/fb.h>
  33. #include <linux/delay.h>
  34. #include <linux/init.h>
  35. #include <linux/ioport.h>
  36. #include <linux/cpufreq.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/clk.h>
  40. #include <linux/err.h>
  41. #include <linux/completion.h>
  42. #include <linux/kthread.h>
  43. #include <linux/freezer.h>
  44. #include <asm/hardware.h>
  45. #include <asm/io.h>
  46. #include <asm/irq.h>
  47. #include <asm/div64.h>
  48. #include <asm/arch/pxa-regs.h>
  49. #include <asm/arch/pxa2xx-gpio.h>
  50. #include <asm/arch/bitfield.h>
  51. #include <asm/arch/pxafb.h>
  52. /*
  53. * Complain if VAR is out of range.
  54. */
  55. #define DEBUG_VAR 1
  56. #include "pxafb.h"
  57. /* Bits which should not be set in machine configuration structures */
  58. #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
  59. LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
  60. LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
  61. #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
  62. LCCR3_PCD | LCCR3_BPP)
  63. static void (*pxafb_backlight_power)(int);
  64. static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
  65. static int pxafb_activate_var(struct fb_var_screeninfo *var,
  66. struct pxafb_info *);
  67. static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  68. static inline unsigned long
  69. lcd_readl(struct pxafb_info *fbi, unsigned int off)
  70. {
  71. return __raw_readl(fbi->mmio_base + off);
  72. }
  73. static inline void
  74. lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
  75. {
  76. __raw_writel(val, fbi->mmio_base + off);
  77. }
  78. static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
  79. {
  80. unsigned long flags;
  81. local_irq_save(flags);
  82. /*
  83. * We need to handle two requests being made at the same time.
  84. * There are two important cases:
  85. * 1. When we are changing VT (C_REENABLE) while unblanking
  86. * (C_ENABLE) We must perform the unblanking, which will
  87. * do our REENABLE for us.
  88. * 2. When we are blanking, but immediately unblank before
  89. * we have blanked. We do the "REENABLE" thing here as
  90. * well, just to be sure.
  91. */
  92. if (fbi->task_state == C_ENABLE && state == C_REENABLE)
  93. state = (u_int) -1;
  94. if (fbi->task_state == C_DISABLE && state == C_ENABLE)
  95. state = C_REENABLE;
  96. if (state != (u_int)-1) {
  97. fbi->task_state = state;
  98. schedule_work(&fbi->task);
  99. }
  100. local_irq_restore(flags);
  101. }
  102. static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  103. {
  104. chan &= 0xffff;
  105. chan >>= 16 - bf->length;
  106. return chan << bf->offset;
  107. }
  108. static int
  109. pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
  110. u_int trans, struct fb_info *info)
  111. {
  112. struct pxafb_info *fbi = (struct pxafb_info *)info;
  113. u_int val;
  114. if (regno >= fbi->palette_size)
  115. return 1;
  116. if (fbi->fb.var.grayscale) {
  117. fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
  118. return 0;
  119. }
  120. switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
  121. case LCCR4_PAL_FOR_0:
  122. val = ((red >> 0) & 0xf800);
  123. val |= ((green >> 5) & 0x07e0);
  124. val |= ((blue >> 11) & 0x001f);
  125. fbi->palette_cpu[regno] = val;
  126. break;
  127. case LCCR4_PAL_FOR_1:
  128. val = ((red << 8) & 0x00f80000);
  129. val |= ((green >> 0) & 0x0000fc00);
  130. val |= ((blue >> 8) & 0x000000f8);
  131. ((u32 *)(fbi->palette_cpu))[regno] = val;
  132. break;
  133. case LCCR4_PAL_FOR_2:
  134. val = ((red << 8) & 0x00fc0000);
  135. val |= ((green >> 0) & 0x0000fc00);
  136. val |= ((blue >> 8) & 0x000000fc);
  137. ((u32 *)(fbi->palette_cpu))[regno] = val;
  138. break;
  139. }
  140. return 0;
  141. }
  142. static int
  143. pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  144. u_int trans, struct fb_info *info)
  145. {
  146. struct pxafb_info *fbi = (struct pxafb_info *)info;
  147. unsigned int val;
  148. int ret = 1;
  149. /*
  150. * If inverse mode was selected, invert all the colours
  151. * rather than the register number. The register number
  152. * is what you poke into the framebuffer to produce the
  153. * colour you requested.
  154. */
  155. if (fbi->cmap_inverse) {
  156. red = 0xffff - red;
  157. green = 0xffff - green;
  158. blue = 0xffff - blue;
  159. }
  160. /*
  161. * If greyscale is true, then we convert the RGB value
  162. * to greyscale no matter what visual we are using.
  163. */
  164. if (fbi->fb.var.grayscale)
  165. red = green = blue = (19595 * red + 38470 * green +
  166. 7471 * blue) >> 16;
  167. switch (fbi->fb.fix.visual) {
  168. case FB_VISUAL_TRUECOLOR:
  169. /*
  170. * 16-bit True Colour. We encode the RGB value
  171. * according to the RGB bitfield information.
  172. */
  173. if (regno < 16) {
  174. u32 *pal = fbi->fb.pseudo_palette;
  175. val = chan_to_field(red, &fbi->fb.var.red);
  176. val |= chan_to_field(green, &fbi->fb.var.green);
  177. val |= chan_to_field(blue, &fbi->fb.var.blue);
  178. pal[regno] = val;
  179. ret = 0;
  180. }
  181. break;
  182. case FB_VISUAL_STATIC_PSEUDOCOLOR:
  183. case FB_VISUAL_PSEUDOCOLOR:
  184. ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
  185. break;
  186. }
  187. return ret;
  188. }
  189. /*
  190. * pxafb_bpp_to_lccr3():
  191. * Convert a bits per pixel value to the correct bit pattern for LCCR3
  192. */
  193. static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
  194. {
  195. int ret = 0;
  196. switch (var->bits_per_pixel) {
  197. case 1: ret = LCCR3_1BPP; break;
  198. case 2: ret = LCCR3_2BPP; break;
  199. case 4: ret = LCCR3_4BPP; break;
  200. case 8: ret = LCCR3_8BPP; break;
  201. case 16: ret = LCCR3_16BPP; break;
  202. }
  203. return ret;
  204. }
  205. #ifdef CONFIG_CPU_FREQ
  206. /*
  207. * pxafb_display_dma_period()
  208. * Calculate the minimum period (in picoseconds) between two DMA
  209. * requests for the LCD controller. If we hit this, it means we're
  210. * doing nothing but LCD DMA.
  211. */
  212. static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
  213. {
  214. /*
  215. * Period = pixclock * bits_per_byte * bytes_per_transfer
  216. * / memory_bits_per_pixel;
  217. */
  218. return var->pixclock * 8 * 16 / var->bits_per_pixel;
  219. }
  220. #endif
  221. /*
  222. * Select the smallest mode that allows the desired resolution to be
  223. * displayed. If desired parameters can be rounded up.
  224. */
  225. static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
  226. struct fb_var_screeninfo *var)
  227. {
  228. struct pxafb_mode_info *mode = NULL;
  229. struct pxafb_mode_info *modelist = mach->modes;
  230. unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
  231. unsigned int i;
  232. for (i = 0; i < mach->num_modes; i++) {
  233. if (modelist[i].xres >= var->xres &&
  234. modelist[i].yres >= var->yres &&
  235. modelist[i].xres < best_x &&
  236. modelist[i].yres < best_y &&
  237. modelist[i].bpp >= var->bits_per_pixel) {
  238. best_x = modelist[i].xres;
  239. best_y = modelist[i].yres;
  240. mode = &modelist[i];
  241. }
  242. }
  243. return mode;
  244. }
  245. static void pxafb_setmode(struct fb_var_screeninfo *var,
  246. struct pxafb_mode_info *mode)
  247. {
  248. var->xres = mode->xres;
  249. var->yres = mode->yres;
  250. var->bits_per_pixel = mode->bpp;
  251. var->pixclock = mode->pixclock;
  252. var->hsync_len = mode->hsync_len;
  253. var->left_margin = mode->left_margin;
  254. var->right_margin = mode->right_margin;
  255. var->vsync_len = mode->vsync_len;
  256. var->upper_margin = mode->upper_margin;
  257. var->lower_margin = mode->lower_margin;
  258. var->sync = mode->sync;
  259. var->grayscale = mode->cmap_greyscale;
  260. var->xres_virtual = var->xres;
  261. var->yres_virtual = var->yres;
  262. }
  263. /*
  264. * pxafb_check_var():
  265. * Get the video params out of 'var'. If a value doesn't fit, round it up,
  266. * if it's too big, return -EINVAL.
  267. *
  268. * Round up in the following order: bits_per_pixel, xres,
  269. * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
  270. * bitfields, horizontal timing, vertical timing.
  271. */
  272. static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  273. {
  274. struct pxafb_info *fbi = (struct pxafb_info *)info;
  275. struct pxafb_mach_info *inf = fbi->dev->platform_data;
  276. if (var->xres < MIN_XRES)
  277. var->xres = MIN_XRES;
  278. if (var->yres < MIN_YRES)
  279. var->yres = MIN_YRES;
  280. if (inf->fixed_modes) {
  281. struct pxafb_mode_info *mode;
  282. mode = pxafb_getmode(inf, var);
  283. if (!mode)
  284. return -EINVAL;
  285. pxafb_setmode(var, mode);
  286. } else {
  287. if (var->xres > inf->modes->xres)
  288. return -EINVAL;
  289. if (var->yres > inf->modes->yres)
  290. return -EINVAL;
  291. if (var->bits_per_pixel > inf->modes->bpp)
  292. return -EINVAL;
  293. }
  294. var->xres_virtual =
  295. max(var->xres_virtual, var->xres);
  296. var->yres_virtual =
  297. max(var->yres_virtual, var->yres);
  298. /*
  299. * Setup the RGB parameters for this display.
  300. *
  301. * The pixel packing format is described on page 7-11 of the
  302. * PXA2XX Developer's Manual.
  303. */
  304. if (var->bits_per_pixel == 16) {
  305. var->red.offset = 11; var->red.length = 5;
  306. var->green.offset = 5; var->green.length = 6;
  307. var->blue.offset = 0; var->blue.length = 5;
  308. var->transp.offset = var->transp.length = 0;
  309. } else {
  310. var->red.offset = var->green.offset = 0;
  311. var->blue.offset = var->transp.offset = 0;
  312. var->red.length = 8;
  313. var->green.length = 8;
  314. var->blue.length = 8;
  315. var->transp.length = 0;
  316. }
  317. #ifdef CONFIG_CPU_FREQ
  318. pr_debug("pxafb: dma period = %d ps\n",
  319. pxafb_display_dma_period(var));
  320. #endif
  321. return 0;
  322. }
  323. static inline void pxafb_set_truecolor(u_int is_true_color)
  324. {
  325. /* do your machine-specific setup if needed */
  326. }
  327. /*
  328. * pxafb_set_par():
  329. * Set the user defined part of the display for the specified console
  330. */
  331. static int pxafb_set_par(struct fb_info *info)
  332. {
  333. struct pxafb_info *fbi = (struct pxafb_info *)info;
  334. struct fb_var_screeninfo *var = &info->var;
  335. if (var->bits_per_pixel == 16)
  336. fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
  337. else if (!fbi->cmap_static)
  338. fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
  339. else {
  340. /*
  341. * Some people have weird ideas about wanting static
  342. * pseudocolor maps. I suspect their user space
  343. * applications are broken.
  344. */
  345. fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
  346. }
  347. fbi->fb.fix.line_length = var->xres_virtual *
  348. var->bits_per_pixel / 8;
  349. if (var->bits_per_pixel == 16)
  350. fbi->palette_size = 0;
  351. else
  352. fbi->palette_size = var->bits_per_pixel == 1 ?
  353. 4 : 1 << var->bits_per_pixel;
  354. fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
  355. /*
  356. * Set (any) board control register to handle new color depth
  357. */
  358. pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
  359. if (fbi->fb.var.bits_per_pixel == 16)
  360. fb_dealloc_cmap(&fbi->fb.cmap);
  361. else
  362. fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
  363. pxafb_activate_var(var, fbi);
  364. return 0;
  365. }
  366. /*
  367. * pxafb_blank():
  368. * Blank the display by setting all palette values to zero. Note, the
  369. * 16 bpp mode does not really use the palette, so this will not
  370. * blank the display in all modes.
  371. */
  372. static int pxafb_blank(int blank, struct fb_info *info)
  373. {
  374. struct pxafb_info *fbi = (struct pxafb_info *)info;
  375. int i;
  376. switch (blank) {
  377. case FB_BLANK_POWERDOWN:
  378. case FB_BLANK_VSYNC_SUSPEND:
  379. case FB_BLANK_HSYNC_SUSPEND:
  380. case FB_BLANK_NORMAL:
  381. if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
  382. fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
  383. for (i = 0; i < fbi->palette_size; i++)
  384. pxafb_setpalettereg(i, 0, 0, 0, 0, info);
  385. pxafb_schedule_work(fbi, C_DISABLE);
  386. /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
  387. break;
  388. case FB_BLANK_UNBLANK:
  389. /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
  390. if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
  391. fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
  392. fb_set_cmap(&fbi->fb.cmap, info);
  393. pxafb_schedule_work(fbi, C_ENABLE);
  394. }
  395. return 0;
  396. }
  397. static int pxafb_mmap(struct fb_info *info,
  398. struct vm_area_struct *vma)
  399. {
  400. struct pxafb_info *fbi = (struct pxafb_info *)info;
  401. unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
  402. if (off < info->fix.smem_len) {
  403. vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
  404. return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
  405. fbi->map_dma, fbi->map_size);
  406. }
  407. return -EINVAL;
  408. }
  409. static struct fb_ops pxafb_ops = {
  410. .owner = THIS_MODULE,
  411. .fb_check_var = pxafb_check_var,
  412. .fb_set_par = pxafb_set_par,
  413. .fb_setcolreg = pxafb_setcolreg,
  414. .fb_fillrect = cfb_fillrect,
  415. .fb_copyarea = cfb_copyarea,
  416. .fb_imageblit = cfb_imageblit,
  417. .fb_blank = pxafb_blank,
  418. .fb_mmap = pxafb_mmap,
  419. };
  420. /*
  421. * Calculate the PCD value from the clock rate (in picoseconds).
  422. * We take account of the PPCR clock setting.
  423. * From PXA Developer's Manual:
  424. *
  425. * PixelClock = LCLK
  426. * -------------
  427. * 2 ( PCD + 1 )
  428. *
  429. * PCD = LCLK
  430. * ------------- - 1
  431. * 2(PixelClock)
  432. *
  433. * Where:
  434. * LCLK = LCD/Memory Clock
  435. * PCD = LCCR3[7:0]
  436. *
  437. * PixelClock here is in Hz while the pixclock argument given is the
  438. * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
  439. *
  440. * The function get_lclk_frequency_10khz returns LCLK in units of
  441. * 10khz. Calling the result of this function lclk gives us the
  442. * following
  443. *
  444. * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
  445. * -------------------------------------- - 1
  446. * 2
  447. *
  448. * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
  449. */
  450. static inline unsigned int get_pcd(struct pxafb_info *fbi,
  451. unsigned int pixclock)
  452. {
  453. unsigned long long pcd;
  454. /* FIXME: Need to take into account Double Pixel Clock mode
  455. * (DPC) bit? or perhaps set it based on the various clock
  456. * speeds */
  457. pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
  458. pcd *= pixclock;
  459. do_div(pcd, 100000000 * 2);
  460. /* no need for this, since we should subtract 1 anyway. they cancel */
  461. /* pcd += 1; */ /* make up for integer math truncations */
  462. return (unsigned int)pcd;
  463. }
  464. /*
  465. * Some touchscreens need hsync information from the video driver to
  466. * function correctly. We export it here. Note that 'hsync_time' and
  467. * the value returned from pxafb_get_hsync_time() is the *reciprocal*
  468. * of the hsync period in seconds.
  469. */
  470. static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
  471. {
  472. unsigned long htime;
  473. if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
  474. fbi->hsync_time = 0;
  475. return;
  476. }
  477. htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
  478. fbi->hsync_time = htime;
  479. }
  480. unsigned long pxafb_get_hsync_time(struct device *dev)
  481. {
  482. struct pxafb_info *fbi = dev_get_drvdata(dev);
  483. /* If display is blanked/suspended, hsync isn't active */
  484. if (!fbi || (fbi->state != C_ENABLE))
  485. return 0;
  486. return fbi->hsync_time;
  487. }
  488. EXPORT_SYMBOL(pxafb_get_hsync_time);
  489. static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
  490. unsigned int offset, size_t size)
  491. {
  492. struct pxafb_dma_descriptor *dma_desc, *pal_desc;
  493. unsigned int dma_desc_off, pal_desc_off;
  494. if (dma < 0 || dma >= DMA_MAX)
  495. return -EINVAL;
  496. dma_desc = &fbi->dma_buff->dma_desc[dma];
  497. dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
  498. dma_desc->fsadr = fbi->screen_dma + offset;
  499. dma_desc->fidr = 0;
  500. dma_desc->ldcmd = size;
  501. if (pal < 0 || pal >= PAL_MAX) {
  502. dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
  503. fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
  504. } else {
  505. pal_desc = &fbi->dma_buff->pal_desc[pal];
  506. pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
  507. pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
  508. pal_desc->fidr = 0;
  509. if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
  510. pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
  511. else
  512. pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
  513. pal_desc->ldcmd |= LDCMD_PAL;
  514. /* flip back and forth between palette and frame buffer */
  515. pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
  516. dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
  517. fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
  518. }
  519. return 0;
  520. }
  521. #ifdef CONFIG_FB_PXA_SMARTPANEL
  522. static int setup_smart_dma(struct pxafb_info *fbi)
  523. {
  524. struct pxafb_dma_descriptor *dma_desc;
  525. unsigned long dma_desc_off, cmd_buff_off;
  526. dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
  527. dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
  528. cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
  529. dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
  530. dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
  531. dma_desc->fidr = 0;
  532. dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
  533. fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
  534. return 0;
  535. }
  536. int pxafb_smart_flush(struct fb_info *info)
  537. {
  538. struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
  539. uint32_t prsr;
  540. int ret = 0;
  541. /* disable controller until all registers are set up */
  542. lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
  543. /* 1. make it an even number of commands to align on 32-bit boundary
  544. * 2. add the interrupt command to the end of the chain so we can
  545. * keep track of the end of the transfer
  546. */
  547. while (fbi->n_smart_cmds & 1)
  548. fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
  549. fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
  550. fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
  551. setup_smart_dma(fbi);
  552. /* continue to execute next command */
  553. prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
  554. lcd_writel(fbi, PRSR, prsr);
  555. /* stop the processor in case it executed "wait for sync" cmd */
  556. lcd_writel(fbi, CMDCR, 0x0001);
  557. /* don't send interrupts for fifo underruns on channel 6 */
  558. lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
  559. lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
  560. lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
  561. lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
  562. lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
  563. lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
  564. /* begin sending */
  565. lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
  566. if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
  567. pr_warning("%s: timeout waiting for command done\n",
  568. __func__);
  569. ret = -ETIMEDOUT;
  570. }
  571. /* quick disable */
  572. prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
  573. lcd_writel(fbi, PRSR, prsr);
  574. lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
  575. lcd_writel(fbi, FDADR6, 0);
  576. fbi->n_smart_cmds = 0;
  577. return ret;
  578. }
  579. int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
  580. {
  581. int i;
  582. struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
  583. /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
  584. for (i = 0; i < n_cmds; i++) {
  585. if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
  586. pxafb_smart_flush(info);
  587. fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
  588. }
  589. return 0;
  590. }
  591. static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
  592. {
  593. unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
  594. return (t == 0) ? 1 : t;
  595. }
  596. static void setup_smart_timing(struct pxafb_info *fbi,
  597. struct fb_var_screeninfo *var)
  598. {
  599. struct pxafb_mach_info *inf = fbi->dev->platform_data;
  600. struct pxafb_mode_info *mode = &inf->modes[0];
  601. unsigned long lclk = clk_get_rate(fbi->clk);
  602. unsigned t1, t2, t3, t4;
  603. t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
  604. t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
  605. t3 = mode->op_hold_time;
  606. t4 = mode->cmd_inh_time;
  607. fbi->reg_lccr1 =
  608. LCCR1_DisWdth(var->xres) |
  609. LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
  610. LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
  611. LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
  612. fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
  613. fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
  614. /* FIXME: make this configurable */
  615. fbi->reg_cmdcr = 1;
  616. }
  617. static int pxafb_smart_thread(void *arg)
  618. {
  619. struct pxafb_info *fbi = arg;
  620. struct pxafb_mach_info *inf = fbi->dev->platform_data;
  621. if (!fbi || !inf->smart_update) {
  622. pr_err("%s: not properly initialized, thread terminated\n",
  623. __func__);
  624. return -EINVAL;
  625. }
  626. pr_debug("%s(): task starting\n", __func__);
  627. set_freezable();
  628. while (!kthread_should_stop()) {
  629. if (try_to_freeze())
  630. continue;
  631. if (fbi->state == C_ENABLE) {
  632. inf->smart_update(&fbi->fb);
  633. complete(&fbi->refresh_done);
  634. }
  635. set_current_state(TASK_INTERRUPTIBLE);
  636. schedule_timeout(30 * HZ / 1000);
  637. }
  638. pr_debug("%s(): task ending\n", __func__);
  639. return 0;
  640. }
  641. static int pxafb_smart_init(struct pxafb_info *fbi)
  642. {
  643. fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
  644. "lcd_refresh");
  645. if (IS_ERR(fbi->smart_thread)) {
  646. printk(KERN_ERR "%s: unable to create kernel thread\n",
  647. __func__);
  648. return PTR_ERR(fbi->smart_thread);
  649. }
  650. return 0;
  651. }
  652. #else
  653. int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
  654. {
  655. return 0;
  656. }
  657. int pxafb_smart_flush(struct fb_info *info)
  658. {
  659. return 0;
  660. }
  661. #endif /* CONFIG_FB_SMART_PANEL */
  662. static void setup_parallel_timing(struct pxafb_info *fbi,
  663. struct fb_var_screeninfo *var)
  664. {
  665. unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
  666. fbi->reg_lccr1 =
  667. LCCR1_DisWdth(var->xres) +
  668. LCCR1_HorSnchWdth(var->hsync_len) +
  669. LCCR1_BegLnDel(var->left_margin) +
  670. LCCR1_EndLnDel(var->right_margin);
  671. /*
  672. * If we have a dual scan LCD, we need to halve
  673. * the YRES parameter.
  674. */
  675. lines_per_panel = var->yres;
  676. if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
  677. lines_per_panel /= 2;
  678. fbi->reg_lccr2 =
  679. LCCR2_DisHght(lines_per_panel) +
  680. LCCR2_VrtSnchWdth(var->vsync_len) +
  681. LCCR2_BegFrmDel(var->upper_margin) +
  682. LCCR2_EndFrmDel(var->lower_margin);
  683. fbi->reg_lccr3 = fbi->lccr3 |
  684. (var->sync & FB_SYNC_HOR_HIGH_ACT ?
  685. LCCR3_HorSnchH : LCCR3_HorSnchL) |
  686. (var->sync & FB_SYNC_VERT_HIGH_ACT ?
  687. LCCR3_VrtSnchH : LCCR3_VrtSnchL);
  688. if (pcd) {
  689. fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
  690. set_hsync_time(fbi, pcd);
  691. }
  692. }
  693. /*
  694. * pxafb_activate_var():
  695. * Configures LCD Controller based on entries in var parameter.
  696. * Settings are only written to the controller if changes were made.
  697. */
  698. static int pxafb_activate_var(struct fb_var_screeninfo *var,
  699. struct pxafb_info *fbi)
  700. {
  701. u_long flags;
  702. size_t nbytes;
  703. #if DEBUG_VAR
  704. if (!(fbi->lccr0 & LCCR0_LCDT)) {
  705. if (var->xres < 16 || var->xres > 1024)
  706. printk(KERN_ERR "%s: invalid xres %d\n",
  707. fbi->fb.fix.id, var->xres);
  708. switch (var->bits_per_pixel) {
  709. case 1:
  710. case 2:
  711. case 4:
  712. case 8:
  713. case 16:
  714. break;
  715. default:
  716. printk(KERN_ERR "%s: invalid bit depth %d\n",
  717. fbi->fb.fix.id, var->bits_per_pixel);
  718. break;
  719. }
  720. if (var->hsync_len < 1 || var->hsync_len > 64)
  721. printk(KERN_ERR "%s: invalid hsync_len %d\n",
  722. fbi->fb.fix.id, var->hsync_len);
  723. if (var->left_margin < 1 || var->left_margin > 255)
  724. printk(KERN_ERR "%s: invalid left_margin %d\n",
  725. fbi->fb.fix.id, var->left_margin);
  726. if (var->right_margin < 1 || var->right_margin > 255)
  727. printk(KERN_ERR "%s: invalid right_margin %d\n",
  728. fbi->fb.fix.id, var->right_margin);
  729. if (var->yres < 1 || var->yres > 1024)
  730. printk(KERN_ERR "%s: invalid yres %d\n",
  731. fbi->fb.fix.id, var->yres);
  732. if (var->vsync_len < 1 || var->vsync_len > 64)
  733. printk(KERN_ERR "%s: invalid vsync_len %d\n",
  734. fbi->fb.fix.id, var->vsync_len);
  735. if (var->upper_margin < 0 || var->upper_margin > 255)
  736. printk(KERN_ERR "%s: invalid upper_margin %d\n",
  737. fbi->fb.fix.id, var->upper_margin);
  738. if (var->lower_margin < 0 || var->lower_margin > 255)
  739. printk(KERN_ERR "%s: invalid lower_margin %d\n",
  740. fbi->fb.fix.id, var->lower_margin);
  741. }
  742. #endif
  743. /* Update shadow copy atomically */
  744. local_irq_save(flags);
  745. #ifdef CONFIG_FB_PXA_SMARTPANEL
  746. if (fbi->lccr0 & LCCR0_LCDT)
  747. setup_smart_timing(fbi, var);
  748. else
  749. #endif
  750. setup_parallel_timing(fbi, var);
  751. fbi->reg_lccr0 = fbi->lccr0 |
  752. (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
  753. LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
  754. fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
  755. nbytes = var->yres * fbi->fb.fix.line_length;
  756. if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
  757. nbytes = nbytes / 2;
  758. setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
  759. }
  760. if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
  761. setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
  762. else
  763. setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
  764. fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
  765. fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
  766. local_irq_restore(flags);
  767. /*
  768. * Only update the registers if the controller is enabled
  769. * and something has changed.
  770. */
  771. if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
  772. (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
  773. (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
  774. (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
  775. (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
  776. (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
  777. pxafb_schedule_work(fbi, C_REENABLE);
  778. return 0;
  779. }
  780. /*
  781. * NOTE! The following functions are purely helpers for set_ctrlr_state.
  782. * Do not call them directly; set_ctrlr_state does the correct serialisation
  783. * to ensure that things happen in the right way 100% of time time.
  784. * -- rmk
  785. */
  786. static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
  787. {
  788. pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
  789. if (pxafb_backlight_power)
  790. pxafb_backlight_power(on);
  791. }
  792. static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
  793. {
  794. pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
  795. if (pxafb_lcd_power)
  796. pxafb_lcd_power(on, &fbi->fb.var);
  797. }
  798. static void pxafb_setup_gpio(struct pxafb_info *fbi)
  799. {
  800. int gpio, ldd_bits;
  801. unsigned int lccr0 = fbi->lccr0;
  802. /*
  803. * setup is based on type of panel supported
  804. */
  805. /* 4 bit interface */
  806. if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
  807. (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
  808. (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
  809. ldd_bits = 4;
  810. /* 8 bit interface */
  811. else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
  812. ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
  813. (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
  814. ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
  815. (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
  816. (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
  817. ldd_bits = 8;
  818. /* 16 bit interface */
  819. else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
  820. ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
  821. (lccr0 & LCCR0_PAS) == LCCR0_Act))
  822. ldd_bits = 16;
  823. else {
  824. printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
  825. "bits per pixel\n");
  826. return;
  827. }
  828. for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
  829. pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
  830. pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
  831. pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
  832. pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
  833. pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
  834. }
  835. static void pxafb_enable_controller(struct pxafb_info *fbi)
  836. {
  837. pr_debug("pxafb: Enabling LCD controller\n");
  838. pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
  839. pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
  840. pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
  841. pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
  842. pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
  843. pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
  844. /* enable LCD controller clock */
  845. clk_enable(fbi->clk);
  846. if (fbi->lccr0 & LCCR0_LCDT)
  847. return;
  848. /* Sequence from 11.7.10 */
  849. lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
  850. lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
  851. lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
  852. lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
  853. lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
  854. lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
  855. lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
  856. }
  857. static void pxafb_disable_controller(struct pxafb_info *fbi)
  858. {
  859. uint32_t lccr0;
  860. #ifdef CONFIG_FB_PXA_SMARTPANEL
  861. if (fbi->lccr0 & LCCR0_LCDT) {
  862. wait_for_completion_timeout(&fbi->refresh_done,
  863. 200 * HZ / 1000);
  864. return;
  865. }
  866. #endif
  867. /* Clear LCD Status Register */
  868. lcd_writel(fbi, LCSR, 0xffffffff);
  869. lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
  870. lcd_writel(fbi, LCCR0, lccr0);
  871. lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
  872. wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
  873. /* disable LCD controller clock */
  874. clk_disable(fbi->clk);
  875. }
  876. /*
  877. * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
  878. */
  879. static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
  880. {
  881. struct pxafb_info *fbi = dev_id;
  882. unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
  883. if (lcsr & LCSR_LDD) {
  884. lccr0 = lcd_readl(fbi, LCCR0);
  885. lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
  886. complete(&fbi->disable_done);
  887. }
  888. #ifdef CONFIG_FB_PXA_SMARTPANEL
  889. if (lcsr & LCSR_CMD_INT)
  890. complete(&fbi->command_done);
  891. #endif
  892. lcd_writel(fbi, LCSR, lcsr);
  893. return IRQ_HANDLED;
  894. }
  895. /*
  896. * This function must be called from task context only, since it will
  897. * sleep when disabling the LCD controller, or if we get two contending
  898. * processes trying to alter state.
  899. */
  900. static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
  901. {
  902. u_int old_state;
  903. down(&fbi->ctrlr_sem);
  904. old_state = fbi->state;
  905. /*
  906. * Hack around fbcon initialisation.
  907. */
  908. if (old_state == C_STARTUP && state == C_REENABLE)
  909. state = C_ENABLE;
  910. switch (state) {
  911. case C_DISABLE_CLKCHANGE:
  912. /*
  913. * Disable controller for clock change. If the
  914. * controller is already disabled, then do nothing.
  915. */
  916. if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
  917. fbi->state = state;
  918. /* TODO __pxafb_lcd_power(fbi, 0); */
  919. pxafb_disable_controller(fbi);
  920. }
  921. break;
  922. case C_DISABLE_PM:
  923. case C_DISABLE:
  924. /*
  925. * Disable controller
  926. */
  927. if (old_state != C_DISABLE) {
  928. fbi->state = state;
  929. __pxafb_backlight_power(fbi, 0);
  930. __pxafb_lcd_power(fbi, 0);
  931. if (old_state != C_DISABLE_CLKCHANGE)
  932. pxafb_disable_controller(fbi);
  933. }
  934. break;
  935. case C_ENABLE_CLKCHANGE:
  936. /*
  937. * Enable the controller after clock change. Only
  938. * do this if we were disabled for the clock change.
  939. */
  940. if (old_state == C_DISABLE_CLKCHANGE) {
  941. fbi->state = C_ENABLE;
  942. pxafb_enable_controller(fbi);
  943. /* TODO __pxafb_lcd_power(fbi, 1); */
  944. }
  945. break;
  946. case C_REENABLE:
  947. /*
  948. * Re-enable the controller only if it was already
  949. * enabled. This is so we reprogram the control
  950. * registers.
  951. */
  952. if (old_state == C_ENABLE) {
  953. __pxafb_lcd_power(fbi, 0);
  954. pxafb_disable_controller(fbi);
  955. pxafb_setup_gpio(fbi);
  956. pxafb_enable_controller(fbi);
  957. __pxafb_lcd_power(fbi, 1);
  958. }
  959. break;
  960. case C_ENABLE_PM:
  961. /*
  962. * Re-enable the controller after PM. This is not
  963. * perfect - think about the case where we were doing
  964. * a clock change, and we suspended half-way through.
  965. */
  966. if (old_state != C_DISABLE_PM)
  967. break;
  968. /* fall through */
  969. case C_ENABLE:
  970. /*
  971. * Power up the LCD screen, enable controller, and
  972. * turn on the backlight.
  973. */
  974. if (old_state != C_ENABLE) {
  975. fbi->state = C_ENABLE;
  976. pxafb_setup_gpio(fbi);
  977. pxafb_enable_controller(fbi);
  978. __pxafb_lcd_power(fbi, 1);
  979. __pxafb_backlight_power(fbi, 1);
  980. }
  981. break;
  982. }
  983. up(&fbi->ctrlr_sem);
  984. }
  985. /*
  986. * Our LCD controller task (which is called when we blank or unblank)
  987. * via keventd.
  988. */
  989. static void pxafb_task(struct work_struct *work)
  990. {
  991. struct pxafb_info *fbi =
  992. container_of(work, struct pxafb_info, task);
  993. u_int state = xchg(&fbi->task_state, -1);
  994. set_ctrlr_state(fbi, state);
  995. }
  996. #ifdef CONFIG_CPU_FREQ
  997. /*
  998. * CPU clock speed change handler. We need to adjust the LCD timing
  999. * parameters when the CPU clock is adjusted by the power management
  1000. * subsystem.
  1001. *
  1002. * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
  1003. */
  1004. static int
  1005. pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
  1006. {
  1007. struct pxafb_info *fbi = TO_INF(nb, freq_transition);
  1008. /* TODO struct cpufreq_freqs *f = data; */
  1009. u_int pcd;
  1010. switch (val) {
  1011. case CPUFREQ_PRECHANGE:
  1012. set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
  1013. break;
  1014. case CPUFREQ_POSTCHANGE:
  1015. pcd = get_pcd(fbi, fbi->fb.var.pixclock);
  1016. set_hsync_time(fbi, pcd);
  1017. fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
  1018. LCCR3_PixClkDiv(pcd);
  1019. set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
  1020. break;
  1021. }
  1022. return 0;
  1023. }
  1024. static int
  1025. pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
  1026. {
  1027. struct pxafb_info *fbi = TO_INF(nb, freq_policy);
  1028. struct fb_var_screeninfo *var = &fbi->fb.var;
  1029. struct cpufreq_policy *policy = data;
  1030. switch (val) {
  1031. case CPUFREQ_ADJUST:
  1032. case CPUFREQ_INCOMPATIBLE:
  1033. pr_debug("min dma period: %d ps, "
  1034. "new clock %d kHz\n", pxafb_display_dma_period(var),
  1035. policy->max);
  1036. /* TODO: fill in min/max values */
  1037. break;
  1038. }
  1039. return 0;
  1040. }
  1041. #endif
  1042. #ifdef CONFIG_PM
  1043. /*
  1044. * Power management hooks. Note that we won't be called from IRQ context,
  1045. * unlike the blank functions above, so we may sleep.
  1046. */
  1047. static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
  1048. {
  1049. struct pxafb_info *fbi = platform_get_drvdata(dev);
  1050. set_ctrlr_state(fbi, C_DISABLE_PM);
  1051. return 0;
  1052. }
  1053. static int pxafb_resume(struct platform_device *dev)
  1054. {
  1055. struct pxafb_info *fbi = platform_get_drvdata(dev);
  1056. set_ctrlr_state(fbi, C_ENABLE_PM);
  1057. return 0;
  1058. }
  1059. #else
  1060. #define pxafb_suspend NULL
  1061. #define pxafb_resume NULL
  1062. #endif
  1063. /*
  1064. * pxafb_map_video_memory():
  1065. * Allocates the DRAM memory for the frame buffer. This buffer is
  1066. * remapped into a non-cached, non-buffered, memory region to
  1067. * allow palette and pixel writes to occur without flushing the
  1068. * cache. Once this area is remapped, all virtual memory
  1069. * access to the video memory should occur at the new region.
  1070. */
  1071. static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
  1072. {
  1073. /*
  1074. * We reserve one page for the palette, plus the size
  1075. * of the framebuffer.
  1076. */
  1077. fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
  1078. fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
  1079. fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
  1080. &fbi->map_dma, GFP_KERNEL);
  1081. if (fbi->map_cpu) {
  1082. /* prevent initial garbage on screen */
  1083. memset(fbi->map_cpu, 0, fbi->map_size);
  1084. fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
  1085. fbi->screen_dma = fbi->map_dma + fbi->video_offset;
  1086. /*
  1087. * FIXME: this is actually the wrong thing to place in
  1088. * smem_start. But fbdev suffers from the problem that
  1089. * it needs an API which doesn't exist (in this case,
  1090. * dma_writecombine_mmap)
  1091. */
  1092. fbi->fb.fix.smem_start = fbi->screen_dma;
  1093. fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
  1094. fbi->dma_buff = (void *) fbi->map_cpu;
  1095. fbi->dma_buff_phys = fbi->map_dma;
  1096. fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
  1097. pr_debug("pxafb: palette_mem_size = 0x%08lx\n", fbi->palette_size*sizeof(u16));
  1098. #ifdef CONFIG_FB_PXA_SMARTPANEL
  1099. fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
  1100. fbi->n_smart_cmds = 0;
  1101. #endif
  1102. }
  1103. return fbi->map_cpu ? 0 : -ENOMEM;
  1104. }
  1105. static void pxafb_decode_mode_info(struct pxafb_info *fbi,
  1106. struct pxafb_mode_info *modes,
  1107. unsigned int num_modes)
  1108. {
  1109. unsigned int i, smemlen;
  1110. pxafb_setmode(&fbi->fb.var, &modes[0]);
  1111. for (i = 0; i < num_modes; i++) {
  1112. smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
  1113. if (smemlen > fbi->fb.fix.smem_len)
  1114. fbi->fb.fix.smem_len = smemlen;
  1115. }
  1116. }
  1117. static void pxafb_decode_mach_info(struct pxafb_info *fbi,
  1118. struct pxafb_mach_info *inf)
  1119. {
  1120. unsigned int lcd_conn = inf->lcd_conn;
  1121. fbi->cmap_inverse = inf->cmap_inverse;
  1122. fbi->cmap_static = inf->cmap_static;
  1123. switch (lcd_conn & 0xf) {
  1124. case LCD_TYPE_MONO_STN:
  1125. fbi->lccr0 = LCCR0_CMS;
  1126. break;
  1127. case LCD_TYPE_MONO_DSTN:
  1128. fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
  1129. break;
  1130. case LCD_TYPE_COLOR_STN:
  1131. fbi->lccr0 = 0;
  1132. break;
  1133. case LCD_TYPE_COLOR_DSTN:
  1134. fbi->lccr0 = LCCR0_SDS;
  1135. break;
  1136. case LCD_TYPE_COLOR_TFT:
  1137. fbi->lccr0 = LCCR0_PAS;
  1138. break;
  1139. case LCD_TYPE_SMART_PANEL:
  1140. fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
  1141. break;
  1142. default:
  1143. /* fall back to backward compatibility way */
  1144. fbi->lccr0 = inf->lccr0;
  1145. fbi->lccr3 = inf->lccr3;
  1146. fbi->lccr4 = inf->lccr4;
  1147. goto decode_mode;
  1148. }
  1149. if (lcd_conn == LCD_MONO_STN_8BPP)
  1150. fbi->lccr0 |= LCCR0_DPD;
  1151. fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
  1152. fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
  1153. fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
  1154. decode_mode:
  1155. pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
  1156. }
  1157. static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
  1158. {
  1159. struct pxafb_info *fbi;
  1160. void *addr;
  1161. struct pxafb_mach_info *inf = dev->platform_data;
  1162. /* Alloc the pxafb_info and pseudo_palette in one step */
  1163. fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
  1164. if (!fbi)
  1165. return NULL;
  1166. memset(fbi, 0, sizeof(struct pxafb_info));
  1167. fbi->dev = dev;
  1168. fbi->clk = clk_get(dev, "LCDCLK");
  1169. if (IS_ERR(fbi->clk)) {
  1170. kfree(fbi);
  1171. return NULL;
  1172. }
  1173. strcpy(fbi->fb.fix.id, PXA_NAME);
  1174. fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
  1175. fbi->fb.fix.type_aux = 0;
  1176. fbi->fb.fix.xpanstep = 0;
  1177. fbi->fb.fix.ypanstep = 0;
  1178. fbi->fb.fix.ywrapstep = 0;
  1179. fbi->fb.fix.accel = FB_ACCEL_NONE;
  1180. fbi->fb.var.nonstd = 0;
  1181. fbi->fb.var.activate = FB_ACTIVATE_NOW;
  1182. fbi->fb.var.height = -1;
  1183. fbi->fb.var.width = -1;
  1184. fbi->fb.var.accel_flags = 0;
  1185. fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
  1186. fbi->fb.fbops = &pxafb_ops;
  1187. fbi->fb.flags = FBINFO_DEFAULT;
  1188. fbi->fb.node = -1;
  1189. addr = fbi;
  1190. addr = addr + sizeof(struct pxafb_info);
  1191. fbi->fb.pseudo_palette = addr;
  1192. fbi->state = C_STARTUP;
  1193. fbi->task_state = (u_char)-1;
  1194. pxafb_decode_mach_info(fbi, inf);
  1195. init_waitqueue_head(&fbi->ctrlr_wait);
  1196. INIT_WORK(&fbi->task, pxafb_task);
  1197. init_MUTEX(&fbi->ctrlr_sem);
  1198. init_completion(&fbi->disable_done);
  1199. #ifdef CONFIG_FB_PXA_SMARTPANEL
  1200. init_completion(&fbi->command_done);
  1201. init_completion(&fbi->refresh_done);
  1202. #endif
  1203. return fbi;
  1204. }
  1205. #ifdef CONFIG_FB_PXA_PARAMETERS
  1206. static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
  1207. {
  1208. struct pxafb_mach_info *inf = dev->platform_data;
  1209. const char *name = this_opt+5;
  1210. unsigned int namelen = strlen(name);
  1211. int res_specified = 0, bpp_specified = 0;
  1212. unsigned int xres = 0, yres = 0, bpp = 0;
  1213. int yres_specified = 0;
  1214. int i;
  1215. for (i = namelen-1; i >= 0; i--) {
  1216. switch (name[i]) {
  1217. case '-':
  1218. namelen = i;
  1219. if (!bpp_specified && !yres_specified) {
  1220. bpp = simple_strtoul(&name[i+1], NULL, 0);
  1221. bpp_specified = 1;
  1222. } else
  1223. goto done;
  1224. break;
  1225. case 'x':
  1226. if (!yres_specified) {
  1227. yres = simple_strtoul(&name[i+1], NULL, 0);
  1228. yres_specified = 1;
  1229. } else
  1230. goto done;
  1231. break;
  1232. case '0' ... '9':
  1233. break;
  1234. default:
  1235. goto done;
  1236. }
  1237. }
  1238. if (i < 0 && yres_specified) {
  1239. xres = simple_strtoul(name, NULL, 0);
  1240. res_specified = 1;
  1241. }
  1242. done:
  1243. if (res_specified) {
  1244. dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
  1245. inf->modes[0].xres = xres; inf->modes[0].yres = yres;
  1246. }
  1247. if (bpp_specified)
  1248. switch (bpp) {
  1249. case 1:
  1250. case 2:
  1251. case 4:
  1252. case 8:
  1253. case 16:
  1254. inf->modes[0].bpp = bpp;
  1255. dev_info(dev, "overriding bit depth: %d\n", bpp);
  1256. break;
  1257. default:
  1258. dev_err(dev, "Depth %d is not valid\n", bpp);
  1259. return -EINVAL;
  1260. }
  1261. return 0;
  1262. }
  1263. static int __devinit parse_opt(struct device *dev, char *this_opt)
  1264. {
  1265. struct pxafb_mach_info *inf = dev->platform_data;
  1266. struct pxafb_mode_info *mode = &inf->modes[0];
  1267. char s[64];
  1268. s[0] = '\0';
  1269. if (!strncmp(this_opt, "mode:", 5)) {
  1270. return parse_opt_mode(dev, this_opt);
  1271. } else if (!strncmp(this_opt, "pixclock:", 9)) {
  1272. mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
  1273. sprintf(s, "pixclock: %ld\n", mode->pixclock);
  1274. } else if (!strncmp(this_opt, "left:", 5)) {
  1275. mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
  1276. sprintf(s, "left: %u\n", mode->left_margin);
  1277. } else if (!strncmp(this_opt, "right:", 6)) {
  1278. mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
  1279. sprintf(s, "right: %u\n", mode->right_margin);
  1280. } else if (!strncmp(this_opt, "upper:", 6)) {
  1281. mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
  1282. sprintf(s, "upper: %u\n", mode->upper_margin);
  1283. } else if (!strncmp(this_opt, "lower:", 6)) {
  1284. mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
  1285. sprintf(s, "lower: %u\n", mode->lower_margin);
  1286. } else if (!strncmp(this_opt, "hsynclen:", 9)) {
  1287. mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
  1288. sprintf(s, "hsynclen: %u\n", mode->hsync_len);
  1289. } else if (!strncmp(this_opt, "vsynclen:", 9)) {
  1290. mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
  1291. sprintf(s, "vsynclen: %u\n", mode->vsync_len);
  1292. } else if (!strncmp(this_opt, "hsync:", 6)) {
  1293. if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
  1294. sprintf(s, "hsync: Active Low\n");
  1295. mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
  1296. } else {
  1297. sprintf(s, "hsync: Active High\n");
  1298. mode->sync |= FB_SYNC_HOR_HIGH_ACT;
  1299. }
  1300. } else if (!strncmp(this_opt, "vsync:", 6)) {
  1301. if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
  1302. sprintf(s, "vsync: Active Low\n");
  1303. mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
  1304. } else {
  1305. sprintf(s, "vsync: Active High\n");
  1306. mode->sync |= FB_SYNC_VERT_HIGH_ACT;
  1307. }
  1308. } else if (!strncmp(this_opt, "dpc:", 4)) {
  1309. if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
  1310. sprintf(s, "double pixel clock: false\n");
  1311. inf->lccr3 &= ~LCCR3_DPC;
  1312. } else {
  1313. sprintf(s, "double pixel clock: true\n");
  1314. inf->lccr3 |= LCCR3_DPC;
  1315. }
  1316. } else if (!strncmp(this_opt, "outputen:", 9)) {
  1317. if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
  1318. sprintf(s, "output enable: active low\n");
  1319. inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
  1320. } else {
  1321. sprintf(s, "output enable: active high\n");
  1322. inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
  1323. }
  1324. } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
  1325. if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
  1326. sprintf(s, "pixel clock polarity: falling edge\n");
  1327. inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
  1328. } else {
  1329. sprintf(s, "pixel clock polarity: rising edge\n");
  1330. inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
  1331. }
  1332. } else if (!strncmp(this_opt, "color", 5)) {
  1333. inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
  1334. } else if (!strncmp(this_opt, "mono", 4)) {
  1335. inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
  1336. } else if (!strncmp(this_opt, "active", 6)) {
  1337. inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
  1338. } else if (!strncmp(this_opt, "passive", 7)) {
  1339. inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
  1340. } else if (!strncmp(this_opt, "single", 6)) {
  1341. inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
  1342. } else if (!strncmp(this_opt, "dual", 4)) {
  1343. inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
  1344. } else if (!strncmp(this_opt, "4pix", 4)) {
  1345. inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
  1346. } else if (!strncmp(this_opt, "8pix", 4)) {
  1347. inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
  1348. } else {
  1349. dev_err(dev, "unknown option: %s\n", this_opt);
  1350. return -EINVAL;
  1351. }
  1352. if (s[0] != '\0')
  1353. dev_info(dev, "override %s", s);
  1354. return 0;
  1355. }
  1356. static int __devinit pxafb_parse_options(struct device *dev, char *options)
  1357. {
  1358. char *this_opt;
  1359. int ret;
  1360. if (!options || !*options)
  1361. return 0;
  1362. dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
  1363. /* could be made table driven or similar?... */
  1364. while ((this_opt = strsep(&options, ",")) != NULL) {
  1365. ret = parse_opt(dev, this_opt);
  1366. if (ret)
  1367. return ret;
  1368. }
  1369. return 0;
  1370. }
  1371. static char g_options[256] __devinitdata = "";
  1372. #ifndef MODULE
  1373. static int __init pxafb_setup_options(void)
  1374. {
  1375. char *options = NULL;
  1376. if (fb_get_options("pxafb", &options))
  1377. return -ENODEV;
  1378. if (options)
  1379. strlcpy(g_options, options, sizeof(g_options));
  1380. return 0;
  1381. }
  1382. #else
  1383. #define pxafb_setup_options() (0)
  1384. module_param_string(options, g_options, sizeof(g_options), 0);
  1385. MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
  1386. #endif
  1387. #else
  1388. #define pxafb_parse_options(...) (0)
  1389. #define pxafb_setup_options() (0)
  1390. #endif
  1391. static int __devinit pxafb_probe(struct platform_device *dev)
  1392. {
  1393. struct pxafb_info *fbi;
  1394. struct pxafb_mach_info *inf;
  1395. struct resource *r;
  1396. int irq, ret;
  1397. dev_dbg(&dev->dev, "pxafb_probe\n");
  1398. inf = dev->dev.platform_data;
  1399. ret = -ENOMEM;
  1400. fbi = NULL;
  1401. if (!inf)
  1402. goto failed;
  1403. ret = pxafb_parse_options(&dev->dev, g_options);
  1404. if (ret < 0)
  1405. goto failed;
  1406. #ifdef DEBUG_VAR
  1407. /* Check for various illegal bit-combinations. Currently only
  1408. * a warning is given. */
  1409. if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
  1410. dev_warn(&dev->dev, "machine LCCR0 setting contains "
  1411. "illegal bits: %08x\n",
  1412. inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
  1413. if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
  1414. dev_warn(&dev->dev, "machine LCCR3 setting contains "
  1415. "illegal bits: %08x\n",
  1416. inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
  1417. if (inf->lccr0 & LCCR0_DPD &&
  1418. ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
  1419. (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
  1420. (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
  1421. dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
  1422. "only valid in passive mono"
  1423. " single panel mode\n");
  1424. if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
  1425. (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
  1426. dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
  1427. if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
  1428. (inf->modes->upper_margin || inf->modes->lower_margin))
  1429. dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
  1430. "passive mode\n");
  1431. #endif
  1432. dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
  1433. inf->modes->xres,
  1434. inf->modes->yres,
  1435. inf->modes->bpp);
  1436. if (inf->modes->xres == 0 ||
  1437. inf->modes->yres == 0 ||
  1438. inf->modes->bpp == 0) {
  1439. dev_err(&dev->dev, "Invalid resolution or bit depth\n");
  1440. ret = -EINVAL;
  1441. goto failed;
  1442. }
  1443. pxafb_backlight_power = inf->pxafb_backlight_power;
  1444. pxafb_lcd_power = inf->pxafb_lcd_power;
  1445. fbi = pxafb_init_fbinfo(&dev->dev);
  1446. if (!fbi) {
  1447. /* only reason for pxafb_init_fbinfo to fail is kmalloc */
  1448. dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
  1449. ret = -ENOMEM;
  1450. goto failed;
  1451. }
  1452. r = platform_get_resource(dev, IORESOURCE_MEM, 0);
  1453. if (r == NULL) {
  1454. dev_err(&dev->dev, "no I/O memory resource defined\n");
  1455. ret = -ENODEV;
  1456. goto failed_fbi;
  1457. }
  1458. r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
  1459. if (r == NULL) {
  1460. dev_err(&dev->dev, "failed to request I/O memory\n");
  1461. ret = -EBUSY;
  1462. goto failed_fbi;
  1463. }
  1464. fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
  1465. if (fbi->mmio_base == NULL) {
  1466. dev_err(&dev->dev, "failed to map I/O memory\n");
  1467. ret = -EBUSY;
  1468. goto failed_free_res;
  1469. }
  1470. /* Initialize video memory */
  1471. ret = pxafb_map_video_memory(fbi);
  1472. if (ret) {
  1473. dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
  1474. ret = -ENOMEM;
  1475. goto failed_free_io;
  1476. }
  1477. irq = platform_get_irq(dev, 0);
  1478. if (irq < 0) {
  1479. dev_err(&dev->dev, "no IRQ defined\n");
  1480. ret = -ENODEV;
  1481. goto failed_free_mem;
  1482. }
  1483. ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
  1484. if (ret) {
  1485. dev_err(&dev->dev, "request_irq failed: %d\n", ret);
  1486. ret = -EBUSY;
  1487. goto failed_free_mem;
  1488. }
  1489. #ifdef CONFIG_FB_PXA_SMARTPANEL
  1490. ret = pxafb_smart_init(fbi);
  1491. if (ret) {
  1492. dev_err(&dev->dev, "failed to initialize smartpanel\n");
  1493. goto failed_free_irq;
  1494. }
  1495. #endif
  1496. /*
  1497. * This makes sure that our colour bitfield
  1498. * descriptors are correctly initialised.
  1499. */
  1500. ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
  1501. if (ret) {
  1502. dev_err(&dev->dev, "failed to get suitable mode\n");
  1503. goto failed_free_irq;
  1504. }
  1505. ret = pxafb_set_par(&fbi->fb);
  1506. if (ret) {
  1507. dev_err(&dev->dev, "Failed to set parameters\n");
  1508. goto failed_free_irq;
  1509. }
  1510. platform_set_drvdata(dev, fbi);
  1511. ret = register_framebuffer(&fbi->fb);
  1512. if (ret < 0) {
  1513. dev_err(&dev->dev,
  1514. "Failed to register framebuffer device: %d\n", ret);
  1515. goto failed_free_cmap;
  1516. }
  1517. #ifdef CONFIG_CPU_FREQ
  1518. fbi->freq_transition.notifier_call = pxafb_freq_transition;
  1519. fbi->freq_policy.notifier_call = pxafb_freq_policy;
  1520. cpufreq_register_notifier(&fbi->freq_transition,
  1521. CPUFREQ_TRANSITION_NOTIFIER);
  1522. cpufreq_register_notifier(&fbi->freq_policy,
  1523. CPUFREQ_POLICY_NOTIFIER);
  1524. #endif
  1525. /*
  1526. * Ok, now enable the LCD controller
  1527. */
  1528. set_ctrlr_state(fbi, C_ENABLE);
  1529. return 0;
  1530. failed_free_cmap:
  1531. if (fbi->fb.cmap.len)
  1532. fb_dealloc_cmap(&fbi->fb.cmap);
  1533. failed_free_irq:
  1534. free_irq(irq, fbi);
  1535. failed_free_mem:
  1536. dma_free_writecombine(&dev->dev, fbi->map_size,
  1537. fbi->map_cpu, fbi->map_dma);
  1538. failed_free_io:
  1539. iounmap(fbi->mmio_base);
  1540. failed_free_res:
  1541. release_mem_region(r->start, r->end - r->start + 1);
  1542. failed_fbi:
  1543. clk_put(fbi->clk);
  1544. platform_set_drvdata(dev, NULL);
  1545. kfree(fbi);
  1546. failed:
  1547. return ret;
  1548. }
  1549. static int __devexit pxafb_remove(struct platform_device *dev)
  1550. {
  1551. struct pxafb_info *fbi = platform_get_drvdata(dev);
  1552. struct resource *r;
  1553. int irq;
  1554. struct fb_info *info;
  1555. if (!fbi)
  1556. return 0;
  1557. info = &fbi->fb;
  1558. unregister_framebuffer(info);
  1559. pxafb_disable_controller(fbi);
  1560. if (fbi->fb.cmap.len)
  1561. fb_dealloc_cmap(&fbi->fb.cmap);
  1562. irq = platform_get_irq(dev, 0);
  1563. free_irq(irq, fbi);
  1564. dma_free_writecombine(&dev->dev, fbi->map_size,
  1565. fbi->map_cpu, fbi->map_dma);
  1566. iounmap(fbi->mmio_base);
  1567. r = platform_get_resource(dev, IORESOURCE_MEM, 0);
  1568. release_mem_region(r->start, r->end - r->start + 1);
  1569. clk_put(fbi->clk);
  1570. kfree(fbi);
  1571. return 0;
  1572. }
  1573. static struct platform_driver pxafb_driver = {
  1574. .probe = pxafb_probe,
  1575. .remove = pxafb_remove,
  1576. .suspend = pxafb_suspend,
  1577. .resume = pxafb_resume,
  1578. .driver = {
  1579. .owner = THIS_MODULE,
  1580. .name = "pxa2xx-fb",
  1581. },
  1582. };
  1583. static int __init pxafb_init(void)
  1584. {
  1585. if (pxafb_setup_options())
  1586. return -EINVAL;
  1587. return platform_driver_register(&pxafb_driver);
  1588. }
  1589. static void __exit pxafb_exit(void)
  1590. {
  1591. platform_driver_unregister(&pxafb_driver);
  1592. }
  1593. module_init(pxafb_init);
  1594. module_exit(pxafb_exit);
  1595. MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
  1596. MODULE_LICENSE("GPL");