arkfb.c 31 KB

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  1. /*
  2. * linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
  3. * with ICS 5342 dac (it is easy to add support for different dacs).
  4. *
  5. * Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org>
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file COPYING in the main directory of this archive for
  9. * more details.
  10. *
  11. * Code is based on s3fb
  12. */
  13. #include <linux/version.h>
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/errno.h>
  17. #include <linux/string.h>
  18. #include <linux/mm.h>
  19. #include <linux/tty.h>
  20. #include <linux/slab.h>
  21. #include <linux/delay.h>
  22. #include <linux/fb.h>
  23. #include <linux/svga.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
  27. #include <video/vga.h>
  28. #ifdef CONFIG_MTRR
  29. #include <asm/mtrr.h>
  30. #endif
  31. struct arkfb_info {
  32. int mclk_freq;
  33. int mtrr_reg;
  34. struct dac_info *dac;
  35. struct vgastate state;
  36. struct mutex open_lock;
  37. unsigned int ref_count;
  38. u32 pseudo_palette[16];
  39. };
  40. /* ------------------------------------------------------------------------- */
  41. static const struct svga_fb_format arkfb_formats[] = {
  42. { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
  43. FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8},
  44. { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
  45. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  46. { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
  47. FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  48. { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
  49. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
  50. {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
  51. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
  52. {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
  53. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
  54. {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
  55. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8},
  56. {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
  57. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
  58. SVGA_FORMAT_END
  59. };
  60. /* CRT timing register sets */
  61. static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
  62. static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
  63. static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
  64. static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END};
  65. static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
  66. static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
  67. static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
  68. static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
  69. static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
  70. // const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END};
  71. static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
  72. static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
  73. static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
  74. static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
  75. static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
  76. static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
  77. static const struct svga_timing_regs ark_timing_regs = {
  78. ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
  79. ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
  80. ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
  81. ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
  82. };
  83. /* ------------------------------------------------------------------------- */
  84. /* Module parameters */
  85. static char *mode_option __devinitdata = "640x480-8@60";
  86. #ifdef CONFIG_MTRR
  87. static int mtrr = 1;
  88. #endif
  89. MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>");
  90. MODULE_LICENSE("GPL");
  91. MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
  92. module_param(mode_option, charp, 0444);
  93. MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
  94. module_param_named(mode, mode_option, charp, 0444);
  95. MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
  96. #ifdef CONFIG_MTRR
  97. module_param(mtrr, int, 0444);
  98. MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
  99. #endif
  100. static int threshold = 4;
  101. module_param(threshold, int, 0644);
  102. MODULE_PARM_DESC(threshold, "FIFO threshold");
  103. /* ------------------------------------------------------------------------- */
  104. static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
  105. {
  106. const u8 *font = map->data;
  107. u8 __iomem *fb = (u8 __iomem *)info->screen_base;
  108. int i, c;
  109. if ((map->width != 8) || (map->height != 16) ||
  110. (map->depth != 1) || (map->length != 256)) {
  111. printk(KERN_ERR "fb%d: unsupported font parameters: width %d, "
  112. "height %d, depth %d, length %d\n", info->node,
  113. map->width, map->height, map->depth, map->length);
  114. return;
  115. }
  116. fb += 2;
  117. for (c = 0; c < map->length; c++) {
  118. for (i = 0; i < map->height; i++) {
  119. fb_writeb(font[i], &fb[i * 4]);
  120. fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
  121. }
  122. fb += 128;
  123. if ((c % 8) == 7)
  124. fb += 128*8;
  125. font += map->height;
  126. }
  127. }
  128. static struct fb_tile_ops arkfb_tile_ops = {
  129. .fb_settile = arkfb_settile,
  130. .fb_tilecopy = svga_tilecopy,
  131. .fb_tilefill = svga_tilefill,
  132. .fb_tileblit = svga_tileblit,
  133. .fb_tilecursor = svga_tilecursor,
  134. .fb_get_tilemax = svga_get_tilemax,
  135. };
  136. /* ------------------------------------------------------------------------- */
  137. /* image data is MSB-first, fb structure is MSB-first too */
  138. static inline u32 expand_color(u32 c)
  139. {
  140. return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
  141. }
  142. /* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
  143. static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
  144. {
  145. u32 fg = expand_color(image->fg_color);
  146. u32 bg = expand_color(image->bg_color);
  147. const u8 *src1, *src;
  148. u8 __iomem *dst1;
  149. u32 __iomem *dst;
  150. u32 val;
  151. int x, y;
  152. src1 = image->data;
  153. dst1 = info->screen_base + (image->dy * info->fix.line_length)
  154. + ((image->dx / 8) * 4);
  155. for (y = 0; y < image->height; y++) {
  156. src = src1;
  157. dst = (u32 __iomem *) dst1;
  158. for (x = 0; x < image->width; x += 8) {
  159. val = *(src++) * 0x01010101;
  160. val = (val & fg) | (~val & bg);
  161. fb_writel(val, dst++);
  162. }
  163. src1 += image->width / 8;
  164. dst1 += info->fix.line_length;
  165. }
  166. }
  167. /* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
  168. static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  169. {
  170. u32 fg = expand_color(rect->color);
  171. u8 __iomem *dst1;
  172. u32 __iomem *dst;
  173. int x, y;
  174. dst1 = info->screen_base + (rect->dy * info->fix.line_length)
  175. + ((rect->dx / 8) * 4);
  176. for (y = 0; y < rect->height; y++) {
  177. dst = (u32 __iomem *) dst1;
  178. for (x = 0; x < rect->width; x += 8) {
  179. fb_writel(fg, dst++);
  180. }
  181. dst1 += info->fix.line_length;
  182. }
  183. }
  184. /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
  185. static inline u32 expand_pixel(u32 c)
  186. {
  187. return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
  188. ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
  189. }
  190. /* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
  191. static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
  192. {
  193. u32 fg = image->fg_color * 0x11111111;
  194. u32 bg = image->bg_color * 0x11111111;
  195. const u8 *src1, *src;
  196. u8 __iomem *dst1;
  197. u32 __iomem *dst;
  198. u32 val;
  199. int x, y;
  200. src1 = image->data;
  201. dst1 = info->screen_base + (image->dy * info->fix.line_length)
  202. + ((image->dx / 8) * 4);
  203. for (y = 0; y < image->height; y++) {
  204. src = src1;
  205. dst = (u32 __iomem *) dst1;
  206. for (x = 0; x < image->width; x += 8) {
  207. val = expand_pixel(*(src++));
  208. val = (val & fg) | (~val & bg);
  209. fb_writel(val, dst++);
  210. }
  211. src1 += image->width / 8;
  212. dst1 += info->fix.line_length;
  213. }
  214. }
  215. static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
  216. {
  217. if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
  218. && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
  219. if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
  220. arkfb_iplan_imageblit(info, image);
  221. else
  222. arkfb_cfb4_imageblit(info, image);
  223. } else
  224. cfb_imageblit(info, image);
  225. }
  226. static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  227. {
  228. if ((info->var.bits_per_pixel == 4)
  229. && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
  230. && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
  231. arkfb_iplan_fillrect(info, rect);
  232. else
  233. cfb_fillrect(info, rect);
  234. }
  235. /* ------------------------------------------------------------------------- */
  236. enum
  237. {
  238. DAC_PSEUDO8_8,
  239. DAC_RGB1555_8,
  240. DAC_RGB0565_8,
  241. DAC_RGB0888_8,
  242. DAC_RGB8888_8,
  243. DAC_PSEUDO8_16,
  244. DAC_RGB1555_16,
  245. DAC_RGB0565_16,
  246. DAC_RGB0888_16,
  247. DAC_RGB8888_16,
  248. DAC_MAX
  249. };
  250. struct dac_ops {
  251. int (*dac_get_mode)(struct dac_info *info);
  252. int (*dac_set_mode)(struct dac_info *info, int mode);
  253. int (*dac_get_freq)(struct dac_info *info, int channel);
  254. int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
  255. void (*dac_release)(struct dac_info *info);
  256. };
  257. typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
  258. typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
  259. struct dac_info
  260. {
  261. struct dac_ops *dacops;
  262. dac_read_regs_t dac_read_regs;
  263. dac_write_regs_t dac_write_regs;
  264. void *data;
  265. };
  266. static inline u8 dac_read_reg(struct dac_info *info, u8 reg)
  267. {
  268. u8 code[2] = {reg, 0};
  269. info->dac_read_regs(info->data, code, 1);
  270. return code[1];
  271. }
  272. static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
  273. {
  274. info->dac_read_regs(info->data, code, count);
  275. }
  276. static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
  277. {
  278. u8 code[2] = {reg, val};
  279. info->dac_write_regs(info->data, code, 1);
  280. }
  281. static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
  282. {
  283. info->dac_write_regs(info->data, code, count);
  284. }
  285. static inline int dac_set_mode(struct dac_info *info, int mode)
  286. {
  287. return info->dacops->dac_set_mode(info, mode);
  288. }
  289. static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
  290. {
  291. return info->dacops->dac_set_freq(info, channel, freq);
  292. }
  293. static inline void dac_release(struct dac_info *info)
  294. {
  295. info->dacops->dac_release(info);
  296. }
  297. /* ------------------------------------------------------------------------- */
  298. /* ICS5342 DAC */
  299. struct ics5342_info
  300. {
  301. struct dac_info dac;
  302. u8 mode;
  303. };
  304. #define DAC_PAR(info) ((struct ics5342_info *) info)
  305. /* LSB is set to distinguish unused slots */
  306. static const u8 ics5342_mode_table[DAC_MAX] = {
  307. [DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61,
  308. [DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
  309. [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
  310. };
  311. static int ics5342_set_mode(struct dac_info *info, int mode)
  312. {
  313. u8 code;
  314. if (mode >= DAC_MAX)
  315. return -EINVAL;
  316. code = ics5342_mode_table[mode];
  317. if (! code)
  318. return -EINVAL;
  319. dac_write_reg(info, 6, code & 0xF0);
  320. DAC_PAR(info)->mode = mode;
  321. return 0;
  322. }
  323. static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
  324. 60000, 250000, 14318};
  325. /* pd4 - allow only posdivider 4 (r=2) */
  326. static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
  327. 60000, 335000, 14318};
  328. /* 270 MHz should be upper bound for VCO clock according to specs,
  329. but that is too restrictive in pd4 case */
  330. static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
  331. {
  332. u16 m, n, r;
  333. /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
  334. int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
  335. ? &ics5342_pll_pd4 : &ics5342_pll,
  336. freq, &m, &n, &r, 0);
  337. if (rv < 0) {
  338. return -EINVAL;
  339. } else {
  340. u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
  341. dac_write_regs(info, code, 3);
  342. return 0;
  343. }
  344. }
  345. static void ics5342_release(struct dac_info *info)
  346. {
  347. ics5342_set_mode(info, DAC_PSEUDO8_8);
  348. kfree(info);
  349. }
  350. static struct dac_ops ics5342_ops = {
  351. .dac_set_mode = ics5342_set_mode,
  352. .dac_set_freq = ics5342_set_freq,
  353. .dac_release = ics5342_release
  354. };
  355. static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
  356. {
  357. struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
  358. if (! info)
  359. return NULL;
  360. info->dacops = &ics5342_ops;
  361. info->dac_read_regs = drr;
  362. info->dac_write_regs = dwr;
  363. info->data = data;
  364. DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
  365. return info;
  366. }
  367. /* ------------------------------------------------------------------------- */
  368. static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
  369. static void ark_dac_read_regs(void *data, u8 *code, int count)
  370. {
  371. u8 regval = vga_rseq(NULL, 0x1C);
  372. while (count != 0)
  373. {
  374. vga_wseq(NULL, 0x1C, regval | (code[0] & 4) ? 0x80 : 0);
  375. code[1] = vga_r(NULL, dac_regs[code[0] & 3]);
  376. count--;
  377. code += 2;
  378. }
  379. vga_wseq(NULL, 0x1C, regval);
  380. }
  381. static void ark_dac_write_regs(void *data, u8 *code, int count)
  382. {
  383. u8 regval = vga_rseq(NULL, 0x1C);
  384. while (count != 0)
  385. {
  386. vga_wseq(NULL, 0x1C, regval | (code[0] & 4) ? 0x80 : 0);
  387. vga_w(NULL, dac_regs[code[0] & 3], code[1]);
  388. count--;
  389. code += 2;
  390. }
  391. vga_wseq(NULL, 0x1C, regval);
  392. }
  393. static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
  394. {
  395. struct arkfb_info *par = info->par;
  396. u8 regval;
  397. int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
  398. if (rv < 0) {
  399. printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
  400. return;
  401. }
  402. /* Set VGA misc register */
  403. regval = vga_r(NULL, VGA_MIS_R);
  404. vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
  405. }
  406. /* Open framebuffer */
  407. static int arkfb_open(struct fb_info *info, int user)
  408. {
  409. struct arkfb_info *par = info->par;
  410. mutex_lock(&(par->open_lock));
  411. if (par->ref_count == 0) {
  412. memset(&(par->state), 0, sizeof(struct vgastate));
  413. par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
  414. par->state.num_crtc = 0x60;
  415. par->state.num_seq = 0x30;
  416. save_vga(&(par->state));
  417. }
  418. par->ref_count++;
  419. mutex_unlock(&(par->open_lock));
  420. return 0;
  421. }
  422. /* Close framebuffer */
  423. static int arkfb_release(struct fb_info *info, int user)
  424. {
  425. struct arkfb_info *par = info->par;
  426. mutex_lock(&(par->open_lock));
  427. if (par->ref_count == 0) {
  428. mutex_unlock(&(par->open_lock));
  429. return -EINVAL;
  430. }
  431. if (par->ref_count == 1) {
  432. restore_vga(&(par->state));
  433. dac_set_mode(par->dac, DAC_PSEUDO8_8);
  434. }
  435. par->ref_count--;
  436. mutex_unlock(&(par->open_lock));
  437. return 0;
  438. }
  439. /* Validate passed in var */
  440. static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  441. {
  442. int rv, mem, step;
  443. /* Find appropriate format */
  444. rv = svga_match_format (arkfb_formats, var, NULL);
  445. if (rv < 0)
  446. {
  447. printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
  448. return rv;
  449. }
  450. /* Do not allow to have real resoulution larger than virtual */
  451. if (var->xres > var->xres_virtual)
  452. var->xres_virtual = var->xres;
  453. if (var->yres > var->yres_virtual)
  454. var->yres_virtual = var->yres;
  455. /* Round up xres_virtual to have proper alignment of lines */
  456. step = arkfb_formats[rv].xresstep - 1;
  457. var->xres_virtual = (var->xres_virtual+step) & ~step;
  458. /* Check whether have enough memory */
  459. mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
  460. if (mem > info->screen_size)
  461. {
  462. printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
  463. return -EINVAL;
  464. }
  465. rv = svga_check_timings (&ark_timing_regs, var, info->node);
  466. if (rv < 0)
  467. {
  468. printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
  469. return rv;
  470. }
  471. /* Interlaced mode is broken */
  472. if (var->vmode & FB_VMODE_INTERLACED)
  473. return -EINVAL;
  474. return 0;
  475. }
  476. /* Set video mode from par */
  477. static int arkfb_set_par(struct fb_info *info)
  478. {
  479. struct arkfb_info *par = info->par;
  480. u32 value, mode, hmul, hdiv, offset_value, screen_size;
  481. u32 bpp = info->var.bits_per_pixel;
  482. u8 regval;
  483. if (bpp != 0) {
  484. info->fix.ypanstep = 1;
  485. info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
  486. info->flags &= ~FBINFO_MISC_TILEBLITTING;
  487. info->tileops = NULL;
  488. /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
  489. info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
  490. info->pixmap.blit_y = ~(u32)0;
  491. offset_value = (info->var.xres_virtual * bpp) / 64;
  492. screen_size = info->var.yres_virtual * info->fix.line_length;
  493. } else {
  494. info->fix.ypanstep = 16;
  495. info->fix.line_length = 0;
  496. info->flags |= FBINFO_MISC_TILEBLITTING;
  497. info->tileops = &arkfb_tile_ops;
  498. /* supports 8x16 tiles only */
  499. info->pixmap.blit_x = 1 << (8 - 1);
  500. info->pixmap.blit_y = 1 << (16 - 1);
  501. offset_value = info->var.xres_virtual / 16;
  502. screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
  503. }
  504. info->var.xoffset = 0;
  505. info->var.yoffset = 0;
  506. info->var.activate = FB_ACTIVATE_NOW;
  507. /* Unlock registers */
  508. svga_wcrt_mask(0x11, 0x00, 0x80);
  509. /* Blank screen and turn off sync */
  510. svga_wseq_mask(0x01, 0x20, 0x20);
  511. svga_wcrt_mask(0x17, 0x00, 0x80);
  512. /* Set default values */
  513. svga_set_default_gfx_regs();
  514. svga_set_default_atc_regs();
  515. svga_set_default_seq_regs();
  516. svga_set_default_crt_regs();
  517. svga_wcrt_multi(ark_line_compare_regs, 0xFFFFFFFF);
  518. svga_wcrt_multi(ark_start_address_regs, 0);
  519. /* ARK specific initialization */
  520. svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
  521. svga_wseq_mask(0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
  522. vga_wseq(NULL, 0x13, info->fix.smem_start >> 16);
  523. vga_wseq(NULL, 0x14, info->fix.smem_start >> 24);
  524. vga_wseq(NULL, 0x15, 0);
  525. vga_wseq(NULL, 0x16, 0);
  526. /* Set the FIFO threshold register */
  527. /* It is fascinating way to store 5-bit value in 8-bit register */
  528. regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
  529. vga_wseq(NULL, 0x18, regval);
  530. /* Set the offset register */
  531. pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
  532. svga_wcrt_multi(ark_offset_regs, offset_value);
  533. /* fix for hi-res textmode */
  534. svga_wcrt_mask(0x40, 0x08, 0x08);
  535. if (info->var.vmode & FB_VMODE_DOUBLE)
  536. svga_wcrt_mask(0x09, 0x80, 0x80);
  537. else
  538. svga_wcrt_mask(0x09, 0x00, 0x80);
  539. if (info->var.vmode & FB_VMODE_INTERLACED)
  540. svga_wcrt_mask(0x44, 0x04, 0x04);
  541. else
  542. svga_wcrt_mask(0x44, 0x00, 0x04);
  543. hmul = 1;
  544. hdiv = 1;
  545. mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
  546. /* Set mode-specific register values */
  547. switch (mode) {
  548. case 0:
  549. pr_debug("fb%d: text mode\n", info->node);
  550. svga_set_textmode_vga_regs();
  551. vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
  552. svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
  553. dac_set_mode(par->dac, DAC_PSEUDO8_8);
  554. break;
  555. case 1:
  556. pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
  557. vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
  558. vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
  559. svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
  560. dac_set_mode(par->dac, DAC_PSEUDO8_8);
  561. break;
  562. case 2:
  563. pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
  564. vga_wseq(NULL, 0x11, 0x10); /* basic VGA mode */
  565. svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
  566. dac_set_mode(par->dac, DAC_PSEUDO8_8);
  567. break;
  568. case 3:
  569. pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
  570. vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode */
  571. if (info->var.pixclock > 20000) {
  572. pr_debug("fb%d: not using multiplex\n", info->node);
  573. svga_wcrt_mask(0x46, 0x00, 0x04); /* 8bit pixel path */
  574. dac_set_mode(par->dac, DAC_PSEUDO8_8);
  575. } else {
  576. pr_debug("fb%d: using multiplex\n", info->node);
  577. svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
  578. dac_set_mode(par->dac, DAC_PSEUDO8_16);
  579. hdiv = 2;
  580. }
  581. break;
  582. case 4:
  583. pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
  584. vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
  585. svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
  586. dac_set_mode(par->dac, DAC_RGB1555_16);
  587. break;
  588. case 5:
  589. pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
  590. vga_wseq(NULL, 0x11, 0x1A); /* 16bpp accel mode */
  591. svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
  592. dac_set_mode(par->dac, DAC_RGB0565_16);
  593. break;
  594. case 6:
  595. pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
  596. vga_wseq(NULL, 0x11, 0x16); /* 8bpp accel mode ??? */
  597. svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
  598. dac_set_mode(par->dac, DAC_RGB0888_16);
  599. hmul = 3;
  600. hdiv = 2;
  601. break;
  602. case 7:
  603. pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
  604. vga_wseq(NULL, 0x11, 0x1E); /* 32bpp accel mode */
  605. svga_wcrt_mask(0x46, 0x04, 0x04); /* 16bit pixel path */
  606. dac_set_mode(par->dac, DAC_RGB8888_16);
  607. hmul = 2;
  608. break;
  609. default:
  610. printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
  611. return -EINVAL;
  612. }
  613. ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
  614. svga_set_timings(&ark_timing_regs, &(info->var), hmul, hdiv,
  615. (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
  616. (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
  617. hmul, info->node);
  618. /* Set interlaced mode start/end register */
  619. value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
  620. value = ((value * hmul / hdiv) / 8) - 5;
  621. vga_wcrt(NULL, 0x42, (value + 1) / 2);
  622. memset_io(info->screen_base, 0x00, screen_size);
  623. /* Device and screen back on */
  624. svga_wcrt_mask(0x17, 0x80, 0x80);
  625. svga_wseq_mask(0x01, 0x00, 0x20);
  626. return 0;
  627. }
  628. /* Set a colour register */
  629. static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  630. u_int transp, struct fb_info *fb)
  631. {
  632. switch (fb->var.bits_per_pixel) {
  633. case 0:
  634. case 4:
  635. if (regno >= 16)
  636. return -EINVAL;
  637. if ((fb->var.bits_per_pixel == 4) &&
  638. (fb->var.nonstd == 0)) {
  639. outb(0xF0, VGA_PEL_MSK);
  640. outb(regno*16, VGA_PEL_IW);
  641. } else {
  642. outb(0x0F, VGA_PEL_MSK);
  643. outb(regno, VGA_PEL_IW);
  644. }
  645. outb(red >> 10, VGA_PEL_D);
  646. outb(green >> 10, VGA_PEL_D);
  647. outb(blue >> 10, VGA_PEL_D);
  648. break;
  649. case 8:
  650. if (regno >= 256)
  651. return -EINVAL;
  652. outb(0xFF, VGA_PEL_MSK);
  653. outb(regno, VGA_PEL_IW);
  654. outb(red >> 10, VGA_PEL_D);
  655. outb(green >> 10, VGA_PEL_D);
  656. outb(blue >> 10, VGA_PEL_D);
  657. break;
  658. case 16:
  659. if (regno >= 16)
  660. return 0;
  661. if (fb->var.green.length == 5)
  662. ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
  663. ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
  664. else if (fb->var.green.length == 6)
  665. ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
  666. ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
  667. else
  668. return -EINVAL;
  669. break;
  670. case 24:
  671. case 32:
  672. if (regno >= 16)
  673. return 0;
  674. ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
  675. (green & 0xFF00) | ((blue & 0xFF00) >> 8);
  676. break;
  677. default:
  678. return -EINVAL;
  679. }
  680. return 0;
  681. }
  682. /* Set the display blanking state */
  683. static int arkfb_blank(int blank_mode, struct fb_info *info)
  684. {
  685. switch (blank_mode) {
  686. case FB_BLANK_UNBLANK:
  687. pr_debug("fb%d: unblank\n", info->node);
  688. svga_wseq_mask(0x01, 0x00, 0x20);
  689. svga_wcrt_mask(0x17, 0x80, 0x80);
  690. break;
  691. case FB_BLANK_NORMAL:
  692. pr_debug("fb%d: blank\n", info->node);
  693. svga_wseq_mask(0x01, 0x20, 0x20);
  694. svga_wcrt_mask(0x17, 0x80, 0x80);
  695. break;
  696. case FB_BLANK_POWERDOWN:
  697. case FB_BLANK_HSYNC_SUSPEND:
  698. case FB_BLANK_VSYNC_SUSPEND:
  699. pr_debug("fb%d: sync down\n", info->node);
  700. svga_wseq_mask(0x01, 0x20, 0x20);
  701. svga_wcrt_mask(0x17, 0x00, 0x80);
  702. break;
  703. }
  704. return 0;
  705. }
  706. /* Pan the display */
  707. static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  708. {
  709. unsigned int offset;
  710. /* Calculate the offset */
  711. if (var->bits_per_pixel == 0) {
  712. offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
  713. offset = offset >> 2;
  714. } else {
  715. offset = (var->yoffset * info->fix.line_length) +
  716. (var->xoffset * var->bits_per_pixel / 8);
  717. offset = offset >> ((var->bits_per_pixel == 4) ? 2 : 3);
  718. }
  719. /* Set the offset */
  720. svga_wcrt_multi(ark_start_address_regs, offset);
  721. return 0;
  722. }
  723. /* ------------------------------------------------------------------------- */
  724. /* Frame buffer operations */
  725. static struct fb_ops arkfb_ops = {
  726. .owner = THIS_MODULE,
  727. .fb_open = arkfb_open,
  728. .fb_release = arkfb_release,
  729. .fb_check_var = arkfb_check_var,
  730. .fb_set_par = arkfb_set_par,
  731. .fb_setcolreg = arkfb_setcolreg,
  732. .fb_blank = arkfb_blank,
  733. .fb_pan_display = arkfb_pan_display,
  734. .fb_fillrect = arkfb_fillrect,
  735. .fb_copyarea = cfb_copyarea,
  736. .fb_imageblit = arkfb_imageblit,
  737. .fb_get_caps = svga_get_caps,
  738. };
  739. /* ------------------------------------------------------------------------- */
  740. /* PCI probe */
  741. static int __devinit ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  742. {
  743. struct fb_info *info;
  744. struct arkfb_info *par;
  745. int rc;
  746. u8 regval;
  747. /* Ignore secondary VGA device because there is no VGA arbitration */
  748. if (! svga_primary_device(dev)) {
  749. dev_info(&(dev->dev), "ignoring secondary device\n");
  750. return -ENODEV;
  751. }
  752. /* Allocate and fill driver data structure */
  753. info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
  754. if (! info) {
  755. dev_err(&(dev->dev), "cannot allocate memory\n");
  756. return -ENOMEM;
  757. }
  758. par = info->par;
  759. mutex_init(&par->open_lock);
  760. info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
  761. info->fbops = &arkfb_ops;
  762. /* Prepare PCI device */
  763. rc = pci_enable_device(dev);
  764. if (rc < 0) {
  765. dev_err(info->dev, "cannot enable PCI device\n");
  766. goto err_enable_device;
  767. }
  768. rc = pci_request_regions(dev, "arkfb");
  769. if (rc < 0) {
  770. dev_err(info->dev, "cannot reserve framebuffer region\n");
  771. goto err_request_regions;
  772. }
  773. par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
  774. if (! par->dac) {
  775. rc = -ENOMEM;
  776. dev_err(info->dev, "RAMDAC initialization failed\n");
  777. goto err_dac;
  778. }
  779. info->fix.smem_start = pci_resource_start(dev, 0);
  780. info->fix.smem_len = pci_resource_len(dev, 0);
  781. /* Map physical IO memory address into kernel space */
  782. info->screen_base = pci_iomap(dev, 0, 0);
  783. if (! info->screen_base) {
  784. rc = -ENOMEM;
  785. dev_err(info->dev, "iomap for framebuffer failed\n");
  786. goto err_iomap;
  787. }
  788. /* FIXME get memsize */
  789. regval = vga_rseq(NULL, 0x10);
  790. info->screen_size = (1 << (regval >> 6)) << 20;
  791. info->fix.smem_len = info->screen_size;
  792. strcpy(info->fix.id, "ARK 2000PV");
  793. info->fix.mmio_start = 0;
  794. info->fix.mmio_len = 0;
  795. info->fix.type = FB_TYPE_PACKED_PIXELS;
  796. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  797. info->fix.ypanstep = 0;
  798. info->fix.accel = FB_ACCEL_NONE;
  799. info->pseudo_palette = (void*) (par->pseudo_palette);
  800. /* Prepare startup mode */
  801. rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
  802. if (! ((rc == 1) || (rc == 2))) {
  803. rc = -EINVAL;
  804. dev_err(info->dev, "mode %s not found\n", mode_option);
  805. goto err_find_mode;
  806. }
  807. rc = fb_alloc_cmap(&info->cmap, 256, 0);
  808. if (rc < 0) {
  809. dev_err(info->dev, "cannot allocate colormap\n");
  810. goto err_alloc_cmap;
  811. }
  812. rc = register_framebuffer(info);
  813. if (rc < 0) {
  814. dev_err(info->dev, "cannot register framebugger\n");
  815. goto err_reg_fb;
  816. }
  817. printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id,
  818. pci_name(dev), info->fix.smem_len >> 20);
  819. /* Record a reference to the driver data */
  820. pci_set_drvdata(dev, info);
  821. #ifdef CONFIG_MTRR
  822. if (mtrr) {
  823. par->mtrr_reg = -1;
  824. par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
  825. }
  826. #endif
  827. return 0;
  828. /* Error handling */
  829. err_reg_fb:
  830. fb_dealloc_cmap(&info->cmap);
  831. err_alloc_cmap:
  832. err_find_mode:
  833. pci_iounmap(dev, info->screen_base);
  834. err_iomap:
  835. dac_release(par->dac);
  836. err_dac:
  837. pci_release_regions(dev);
  838. err_request_regions:
  839. /* pci_disable_device(dev); */
  840. err_enable_device:
  841. framebuffer_release(info);
  842. return rc;
  843. }
  844. /* PCI remove */
  845. static void __devexit ark_pci_remove(struct pci_dev *dev)
  846. {
  847. struct fb_info *info = pci_get_drvdata(dev);
  848. if (info) {
  849. struct arkfb_info *par = info->par;
  850. #ifdef CONFIG_MTRR
  851. if (par->mtrr_reg >= 0) {
  852. mtrr_del(par->mtrr_reg, 0, 0);
  853. par->mtrr_reg = -1;
  854. }
  855. #endif
  856. dac_release(par->dac);
  857. unregister_framebuffer(info);
  858. fb_dealloc_cmap(&info->cmap);
  859. pci_iounmap(dev, info->screen_base);
  860. pci_release_regions(dev);
  861. /* pci_disable_device(dev); */
  862. pci_set_drvdata(dev, NULL);
  863. framebuffer_release(info);
  864. }
  865. }
  866. #ifdef CONFIG_PM
  867. /* PCI suspend */
  868. static int ark_pci_suspend (struct pci_dev* dev, pm_message_t state)
  869. {
  870. struct fb_info *info = pci_get_drvdata(dev);
  871. struct arkfb_info *par = info->par;
  872. dev_info(info->dev, "suspend\n");
  873. acquire_console_sem();
  874. mutex_lock(&(par->open_lock));
  875. if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
  876. mutex_unlock(&(par->open_lock));
  877. release_console_sem();
  878. return 0;
  879. }
  880. fb_set_suspend(info, 1);
  881. pci_save_state(dev);
  882. pci_disable_device(dev);
  883. pci_set_power_state(dev, pci_choose_state(dev, state));
  884. mutex_unlock(&(par->open_lock));
  885. release_console_sem();
  886. return 0;
  887. }
  888. /* PCI resume */
  889. static int ark_pci_resume (struct pci_dev* dev)
  890. {
  891. struct fb_info *info = pci_get_drvdata(dev);
  892. struct arkfb_info *par = info->par;
  893. dev_info(info->dev, "resume\n");
  894. acquire_console_sem();
  895. mutex_lock(&(par->open_lock));
  896. if (par->ref_count == 0) {
  897. mutex_unlock(&(par->open_lock));
  898. release_console_sem();
  899. return 0;
  900. }
  901. pci_set_power_state(dev, PCI_D0);
  902. pci_restore_state(dev);
  903. if (pci_enable_device(dev))
  904. goto fail;
  905. pci_set_master(dev);
  906. arkfb_set_par(info);
  907. fb_set_suspend(info, 0);
  908. mutex_unlock(&(par->open_lock));
  909. fail:
  910. release_console_sem();
  911. return 0;
  912. }
  913. #else
  914. #define ark_pci_suspend NULL
  915. #define ark_pci_resume NULL
  916. #endif /* CONFIG_PM */
  917. /* List of boards that we are trying to support */
  918. static struct pci_device_id ark_devices[] __devinitdata = {
  919. {PCI_DEVICE(0xEDD8, 0xA099)},
  920. {0, 0, 0, 0, 0, 0, 0}
  921. };
  922. MODULE_DEVICE_TABLE(pci, ark_devices);
  923. static struct pci_driver arkfb_pci_driver = {
  924. .name = "arkfb",
  925. .id_table = ark_devices,
  926. .probe = ark_pci_probe,
  927. .remove = __devexit_p(ark_pci_remove),
  928. .suspend = ark_pci_suspend,
  929. .resume = ark_pci_resume,
  930. };
  931. /* Cleanup */
  932. static void __exit arkfb_cleanup(void)
  933. {
  934. pr_debug("arkfb: cleaning up\n");
  935. pci_unregister_driver(&arkfb_pci_driver);
  936. }
  937. /* Driver Initialisation */
  938. static int __init arkfb_init(void)
  939. {
  940. #ifndef MODULE
  941. char *option = NULL;
  942. if (fb_get_options("arkfb", &option))
  943. return -ENODEV;
  944. if (option && *option)
  945. mode_option = option;
  946. #endif
  947. pr_debug("arkfb: initializing\n");
  948. return pci_register_driver(&arkfb_pci_driver);
  949. }
  950. module_init(arkfb_init);
  951. module_exit(arkfb_cleanup);