qeth_core_main.c 122 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477
  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm-s390/ebcdic.h>
  21. #include <asm-s390/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_TRACE] = {"qeth_trace",
  33. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_MSG] = {"qeth_msg",
  35. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  36. [QETH_DBF_SENSE] = {"qeth_sense",
  37. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_MISC] = {"qeth_misc",
  39. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_CTRL] = {"qeth_control",
  41. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  42. };
  43. EXPORT_SYMBOL_GPL(qeth_dbf);
  44. struct qeth_card_list_struct qeth_core_card_list;
  45. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  46. static struct device *qeth_core_root_dev;
  47. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  48. static struct lock_class_key qdio_out_skb_queue_key;
  49. static void qeth_send_control_data_cb(struct qeth_channel *,
  50. struct qeth_cmd_buffer *);
  51. static int qeth_issue_next_read(struct qeth_card *);
  52. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  53. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  54. static void qeth_free_buffer_pool(struct qeth_card *);
  55. static int qeth_qdio_establish(struct qeth_card *);
  56. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  57. struct qdio_buffer *buffer, int is_tso,
  58. int *next_element_to_fill)
  59. {
  60. struct skb_frag_struct *frag;
  61. int fragno;
  62. unsigned long addr;
  63. int element, cnt, dlen;
  64. fragno = skb_shinfo(skb)->nr_frags;
  65. element = *next_element_to_fill;
  66. dlen = 0;
  67. if (is_tso)
  68. buffer->element[element].flags =
  69. SBAL_FLAGS_MIDDLE_FRAG;
  70. else
  71. buffer->element[element].flags =
  72. SBAL_FLAGS_FIRST_FRAG;
  73. dlen = skb->len - skb->data_len;
  74. if (dlen) {
  75. buffer->element[element].addr = skb->data;
  76. buffer->element[element].length = dlen;
  77. element++;
  78. }
  79. for (cnt = 0; cnt < fragno; cnt++) {
  80. frag = &skb_shinfo(skb)->frags[cnt];
  81. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  82. frag->page_offset;
  83. buffer->element[element].addr = (char *)addr;
  84. buffer->element[element].length = frag->size;
  85. if (cnt < (fragno - 1))
  86. buffer->element[element].flags =
  87. SBAL_FLAGS_MIDDLE_FRAG;
  88. else
  89. buffer->element[element].flags =
  90. SBAL_FLAGS_LAST_FRAG;
  91. element++;
  92. }
  93. *next_element_to_fill = element;
  94. }
  95. static inline const char *qeth_get_cardname(struct qeth_card *card)
  96. {
  97. if (card->info.guestlan) {
  98. switch (card->info.type) {
  99. case QETH_CARD_TYPE_OSAE:
  100. return " Guest LAN QDIO";
  101. case QETH_CARD_TYPE_IQD:
  102. return " Guest LAN Hiper";
  103. default:
  104. return " unknown";
  105. }
  106. } else {
  107. switch (card->info.type) {
  108. case QETH_CARD_TYPE_OSAE:
  109. return " OSD Express";
  110. case QETH_CARD_TYPE_IQD:
  111. return " HiperSockets";
  112. case QETH_CARD_TYPE_OSN:
  113. return " OSN QDIO";
  114. default:
  115. return " unknown";
  116. }
  117. }
  118. return " n/a";
  119. }
  120. /* max length to be returned: 14 */
  121. const char *qeth_get_cardname_short(struct qeth_card *card)
  122. {
  123. if (card->info.guestlan) {
  124. switch (card->info.type) {
  125. case QETH_CARD_TYPE_OSAE:
  126. return "GuestLAN QDIO";
  127. case QETH_CARD_TYPE_IQD:
  128. return "GuestLAN Hiper";
  129. default:
  130. return "unknown";
  131. }
  132. } else {
  133. switch (card->info.type) {
  134. case QETH_CARD_TYPE_OSAE:
  135. switch (card->info.link_type) {
  136. case QETH_LINK_TYPE_FAST_ETH:
  137. return "OSD_100";
  138. case QETH_LINK_TYPE_HSTR:
  139. return "HSTR";
  140. case QETH_LINK_TYPE_GBIT_ETH:
  141. return "OSD_1000";
  142. case QETH_LINK_TYPE_10GBIT_ETH:
  143. return "OSD_10GIG";
  144. case QETH_LINK_TYPE_LANE_ETH100:
  145. return "OSD_FE_LANE";
  146. case QETH_LINK_TYPE_LANE_TR:
  147. return "OSD_TR_LANE";
  148. case QETH_LINK_TYPE_LANE_ETH1000:
  149. return "OSD_GbE_LANE";
  150. case QETH_LINK_TYPE_LANE:
  151. return "OSD_ATM_LANE";
  152. default:
  153. return "OSD_Express";
  154. }
  155. case QETH_CARD_TYPE_IQD:
  156. return "HiperSockets";
  157. case QETH_CARD_TYPE_OSN:
  158. return "OSN";
  159. default:
  160. return "unknown";
  161. }
  162. }
  163. return "n/a";
  164. }
  165. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  166. int clear_start_mask)
  167. {
  168. unsigned long flags;
  169. spin_lock_irqsave(&card->thread_mask_lock, flags);
  170. card->thread_allowed_mask = threads;
  171. if (clear_start_mask)
  172. card->thread_start_mask &= threads;
  173. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  174. wake_up(&card->wait_q);
  175. }
  176. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  177. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  178. {
  179. unsigned long flags;
  180. int rc = 0;
  181. spin_lock_irqsave(&card->thread_mask_lock, flags);
  182. rc = (card->thread_running_mask & threads);
  183. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  184. return rc;
  185. }
  186. EXPORT_SYMBOL_GPL(qeth_threads_running);
  187. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  188. {
  189. return wait_event_interruptible(card->wait_q,
  190. qeth_threads_running(card, threads) == 0);
  191. }
  192. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  193. void qeth_clear_working_pool_list(struct qeth_card *card)
  194. {
  195. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  196. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  197. list_for_each_entry_safe(pool_entry, tmp,
  198. &card->qdio.in_buf_pool.entry_list, list){
  199. list_del(&pool_entry->list);
  200. }
  201. }
  202. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  203. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  204. {
  205. struct qeth_buffer_pool_entry *pool_entry;
  206. void *ptr;
  207. int i, j;
  208. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  209. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  210. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  211. if (!pool_entry) {
  212. qeth_free_buffer_pool(card);
  213. return -ENOMEM;
  214. }
  215. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  216. ptr = (void *) __get_free_page(GFP_KERNEL);
  217. if (!ptr) {
  218. while (j > 0)
  219. free_page((unsigned long)
  220. pool_entry->elements[--j]);
  221. kfree(pool_entry);
  222. qeth_free_buffer_pool(card);
  223. return -ENOMEM;
  224. }
  225. pool_entry->elements[j] = ptr;
  226. }
  227. list_add(&pool_entry->init_list,
  228. &card->qdio.init_pool.entry_list);
  229. }
  230. return 0;
  231. }
  232. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  233. {
  234. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  235. if ((card->state != CARD_STATE_DOWN) &&
  236. (card->state != CARD_STATE_RECOVER))
  237. return -EPERM;
  238. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  239. qeth_clear_working_pool_list(card);
  240. qeth_free_buffer_pool(card);
  241. card->qdio.in_buf_pool.buf_count = bufcnt;
  242. card->qdio.init_pool.buf_count = bufcnt;
  243. return qeth_alloc_buffer_pool(card);
  244. }
  245. int qeth_set_large_send(struct qeth_card *card,
  246. enum qeth_large_send_types type)
  247. {
  248. int rc = 0;
  249. if (card->dev == NULL) {
  250. card->options.large_send = type;
  251. return 0;
  252. }
  253. if (card->state == CARD_STATE_UP)
  254. netif_tx_disable(card->dev);
  255. card->options.large_send = type;
  256. switch (card->options.large_send) {
  257. case QETH_LARGE_SEND_EDDP:
  258. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  259. NETIF_F_HW_CSUM;
  260. break;
  261. case QETH_LARGE_SEND_TSO:
  262. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  263. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  264. NETIF_F_HW_CSUM;
  265. } else {
  266. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  267. NETIF_F_HW_CSUM);
  268. card->options.large_send = QETH_LARGE_SEND_NO;
  269. rc = -EOPNOTSUPP;
  270. }
  271. break;
  272. default: /* includes QETH_LARGE_SEND_NO */
  273. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  274. NETIF_F_HW_CSUM);
  275. break;
  276. }
  277. if (card->state == CARD_STATE_UP)
  278. netif_wake_queue(card->dev);
  279. return rc;
  280. }
  281. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  282. static int qeth_issue_next_read(struct qeth_card *card)
  283. {
  284. int rc;
  285. struct qeth_cmd_buffer *iob;
  286. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  287. if (card->read.state != CH_STATE_UP)
  288. return -EIO;
  289. iob = qeth_get_buffer(&card->read);
  290. if (!iob) {
  291. PRINT_WARN("issue_next_read failed: no iob available!\n");
  292. return -ENOMEM;
  293. }
  294. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  295. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  296. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  297. (addr_t) iob, 0, 0);
  298. if (rc) {
  299. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  300. atomic_set(&card->read.irq_pending, 0);
  301. qeth_schedule_recovery(card);
  302. wake_up(&card->wait_q);
  303. }
  304. return rc;
  305. }
  306. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  307. {
  308. struct qeth_reply *reply;
  309. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  310. if (reply) {
  311. atomic_set(&reply->refcnt, 1);
  312. atomic_set(&reply->received, 0);
  313. reply->card = card;
  314. };
  315. return reply;
  316. }
  317. static void qeth_get_reply(struct qeth_reply *reply)
  318. {
  319. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  320. atomic_inc(&reply->refcnt);
  321. }
  322. static void qeth_put_reply(struct qeth_reply *reply)
  323. {
  324. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  325. if (atomic_dec_and_test(&reply->refcnt))
  326. kfree(reply);
  327. }
  328. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  329. struct qeth_card *card)
  330. {
  331. char *ipa_name;
  332. int com = cmd->hdr.command;
  333. ipa_name = qeth_get_ipa_cmd_name(com);
  334. if (rc)
  335. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  336. ipa_name, com, QETH_CARD_IFNAME(card),
  337. rc, qeth_get_ipa_msg(rc));
  338. else
  339. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  340. ipa_name, com, QETH_CARD_IFNAME(card));
  341. }
  342. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  343. struct qeth_cmd_buffer *iob)
  344. {
  345. struct qeth_ipa_cmd *cmd = NULL;
  346. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  347. if (IS_IPA(iob->data)) {
  348. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  349. if (IS_IPA_REPLY(cmd)) {
  350. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  351. cmd->hdr.command > IPA_CMD_MODCCID)
  352. qeth_issue_ipa_msg(cmd,
  353. cmd->hdr.return_code, card);
  354. return cmd;
  355. } else {
  356. switch (cmd->hdr.command) {
  357. case IPA_CMD_STOPLAN:
  358. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  359. "there is a network problem or "
  360. "someone pulled the cable or "
  361. "disabled the port.\n",
  362. QETH_CARD_IFNAME(card),
  363. card->info.chpid);
  364. card->lan_online = 0;
  365. if (card->dev && netif_carrier_ok(card->dev))
  366. netif_carrier_off(card->dev);
  367. return NULL;
  368. case IPA_CMD_STARTLAN:
  369. PRINT_INFO("Link reestablished on %s "
  370. "(CHPID 0x%X). Scheduling "
  371. "IP address reset.\n",
  372. QETH_CARD_IFNAME(card),
  373. card->info.chpid);
  374. netif_carrier_on(card->dev);
  375. card->lan_online = 1;
  376. qeth_schedule_recovery(card);
  377. return NULL;
  378. case IPA_CMD_MODCCID:
  379. return cmd;
  380. case IPA_CMD_REGISTER_LOCAL_ADDR:
  381. QETH_DBF_TEXT(TRACE, 3, "irla");
  382. break;
  383. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  384. QETH_DBF_TEXT(TRACE, 3, "urla");
  385. break;
  386. default:
  387. QETH_DBF_MESSAGE(2, "Received data is IPA "
  388. "but not a reply!\n");
  389. break;
  390. }
  391. }
  392. }
  393. return cmd;
  394. }
  395. void qeth_clear_ipacmd_list(struct qeth_card *card)
  396. {
  397. struct qeth_reply *reply, *r;
  398. unsigned long flags;
  399. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  400. spin_lock_irqsave(&card->lock, flags);
  401. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  402. qeth_get_reply(reply);
  403. reply->rc = -EIO;
  404. atomic_inc(&reply->received);
  405. list_del_init(&reply->list);
  406. wake_up(&reply->wait_q);
  407. qeth_put_reply(reply);
  408. }
  409. spin_unlock_irqrestore(&card->lock, flags);
  410. }
  411. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  412. static int qeth_check_idx_response(unsigned char *buffer)
  413. {
  414. if (!buffer)
  415. return 0;
  416. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  417. if ((buffer[2] & 0xc0) == 0xc0) {
  418. PRINT_WARN("received an IDX TERMINATE "
  419. "with cause code 0x%02x%s\n",
  420. buffer[4],
  421. ((buffer[4] == 0x22) ?
  422. " -- try another portname" : ""));
  423. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  424. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  425. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  426. return -EIO;
  427. }
  428. return 0;
  429. }
  430. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  431. __u32 len)
  432. {
  433. struct qeth_card *card;
  434. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  435. card = CARD_FROM_CDEV(channel->ccwdev);
  436. if (channel == &card->read)
  437. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  438. else
  439. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  440. channel->ccw.count = len;
  441. channel->ccw.cda = (__u32) __pa(iob);
  442. }
  443. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  444. {
  445. __u8 index;
  446. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  447. index = channel->io_buf_no;
  448. do {
  449. if (channel->iob[index].state == BUF_STATE_FREE) {
  450. channel->iob[index].state = BUF_STATE_LOCKED;
  451. channel->io_buf_no = (channel->io_buf_no + 1) %
  452. QETH_CMD_BUFFER_NO;
  453. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  454. return channel->iob + index;
  455. }
  456. index = (index + 1) % QETH_CMD_BUFFER_NO;
  457. } while (index != channel->io_buf_no);
  458. return NULL;
  459. }
  460. void qeth_release_buffer(struct qeth_channel *channel,
  461. struct qeth_cmd_buffer *iob)
  462. {
  463. unsigned long flags;
  464. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  465. spin_lock_irqsave(&channel->iob_lock, flags);
  466. memset(iob->data, 0, QETH_BUFSIZE);
  467. iob->state = BUF_STATE_FREE;
  468. iob->callback = qeth_send_control_data_cb;
  469. iob->rc = 0;
  470. spin_unlock_irqrestore(&channel->iob_lock, flags);
  471. }
  472. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  473. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  474. {
  475. struct qeth_cmd_buffer *buffer = NULL;
  476. unsigned long flags;
  477. spin_lock_irqsave(&channel->iob_lock, flags);
  478. buffer = __qeth_get_buffer(channel);
  479. spin_unlock_irqrestore(&channel->iob_lock, flags);
  480. return buffer;
  481. }
  482. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  483. {
  484. struct qeth_cmd_buffer *buffer;
  485. wait_event(channel->wait_q,
  486. ((buffer = qeth_get_buffer(channel)) != NULL));
  487. return buffer;
  488. }
  489. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  490. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  491. {
  492. int cnt;
  493. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  494. qeth_release_buffer(channel, &channel->iob[cnt]);
  495. channel->buf_no = 0;
  496. channel->io_buf_no = 0;
  497. }
  498. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  499. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  500. struct qeth_cmd_buffer *iob)
  501. {
  502. struct qeth_card *card;
  503. struct qeth_reply *reply, *r;
  504. struct qeth_ipa_cmd *cmd;
  505. unsigned long flags;
  506. int keep_reply;
  507. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  508. card = CARD_FROM_CDEV(channel->ccwdev);
  509. if (qeth_check_idx_response(iob->data)) {
  510. qeth_clear_ipacmd_list(card);
  511. qeth_schedule_recovery(card);
  512. goto out;
  513. }
  514. cmd = qeth_check_ipa_data(card, iob);
  515. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  516. goto out;
  517. /*in case of OSN : check if cmd is set */
  518. if (card->info.type == QETH_CARD_TYPE_OSN &&
  519. cmd &&
  520. cmd->hdr.command != IPA_CMD_STARTLAN &&
  521. card->osn_info.assist_cb != NULL) {
  522. card->osn_info.assist_cb(card->dev, cmd);
  523. goto out;
  524. }
  525. spin_lock_irqsave(&card->lock, flags);
  526. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  527. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  528. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  529. qeth_get_reply(reply);
  530. list_del_init(&reply->list);
  531. spin_unlock_irqrestore(&card->lock, flags);
  532. keep_reply = 0;
  533. if (reply->callback != NULL) {
  534. if (cmd) {
  535. reply->offset = (__u16)((char *)cmd -
  536. (char *)iob->data);
  537. keep_reply = reply->callback(card,
  538. reply,
  539. (unsigned long)cmd);
  540. } else
  541. keep_reply = reply->callback(card,
  542. reply,
  543. (unsigned long)iob);
  544. }
  545. if (cmd)
  546. reply->rc = (u16) cmd->hdr.return_code;
  547. else if (iob->rc)
  548. reply->rc = iob->rc;
  549. if (keep_reply) {
  550. spin_lock_irqsave(&card->lock, flags);
  551. list_add_tail(&reply->list,
  552. &card->cmd_waiter_list);
  553. spin_unlock_irqrestore(&card->lock, flags);
  554. } else {
  555. atomic_inc(&reply->received);
  556. wake_up(&reply->wait_q);
  557. }
  558. qeth_put_reply(reply);
  559. goto out;
  560. }
  561. }
  562. spin_unlock_irqrestore(&card->lock, flags);
  563. out:
  564. memcpy(&card->seqno.pdu_hdr_ack,
  565. QETH_PDU_HEADER_SEQ_NO(iob->data),
  566. QETH_SEQ_NO_LENGTH);
  567. qeth_release_buffer(channel, iob);
  568. }
  569. static int qeth_setup_channel(struct qeth_channel *channel)
  570. {
  571. int cnt;
  572. QETH_DBF_TEXT(SETUP, 2, "setupch");
  573. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  574. channel->iob[cnt].data = (char *)
  575. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  576. if (channel->iob[cnt].data == NULL)
  577. break;
  578. channel->iob[cnt].state = BUF_STATE_FREE;
  579. channel->iob[cnt].channel = channel;
  580. channel->iob[cnt].callback = qeth_send_control_data_cb;
  581. channel->iob[cnt].rc = 0;
  582. }
  583. if (cnt < QETH_CMD_BUFFER_NO) {
  584. while (cnt-- > 0)
  585. kfree(channel->iob[cnt].data);
  586. return -ENOMEM;
  587. }
  588. channel->buf_no = 0;
  589. channel->io_buf_no = 0;
  590. atomic_set(&channel->irq_pending, 0);
  591. spin_lock_init(&channel->iob_lock);
  592. init_waitqueue_head(&channel->wait_q);
  593. return 0;
  594. }
  595. static int qeth_set_thread_start_bit(struct qeth_card *card,
  596. unsigned long thread)
  597. {
  598. unsigned long flags;
  599. spin_lock_irqsave(&card->thread_mask_lock, flags);
  600. if (!(card->thread_allowed_mask & thread) ||
  601. (card->thread_start_mask & thread)) {
  602. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  603. return -EPERM;
  604. }
  605. card->thread_start_mask |= thread;
  606. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  607. return 0;
  608. }
  609. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  610. {
  611. unsigned long flags;
  612. spin_lock_irqsave(&card->thread_mask_lock, flags);
  613. card->thread_start_mask &= ~thread;
  614. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  615. wake_up(&card->wait_q);
  616. }
  617. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  618. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  619. {
  620. unsigned long flags;
  621. spin_lock_irqsave(&card->thread_mask_lock, flags);
  622. card->thread_running_mask &= ~thread;
  623. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  624. wake_up(&card->wait_q);
  625. }
  626. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  627. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  628. {
  629. unsigned long flags;
  630. int rc = 0;
  631. spin_lock_irqsave(&card->thread_mask_lock, flags);
  632. if (card->thread_start_mask & thread) {
  633. if ((card->thread_allowed_mask & thread) &&
  634. !(card->thread_running_mask & thread)) {
  635. rc = 1;
  636. card->thread_start_mask &= ~thread;
  637. card->thread_running_mask |= thread;
  638. } else
  639. rc = -EPERM;
  640. }
  641. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  642. return rc;
  643. }
  644. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  645. {
  646. int rc = 0;
  647. wait_event(card->wait_q,
  648. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  649. return rc;
  650. }
  651. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  652. void qeth_schedule_recovery(struct qeth_card *card)
  653. {
  654. QETH_DBF_TEXT(TRACE, 2, "startrec");
  655. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  656. schedule_work(&card->kernel_thread_starter);
  657. }
  658. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  659. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  660. {
  661. int dstat, cstat;
  662. char *sense;
  663. sense = (char *) irb->ecw;
  664. cstat = irb->scsw.cmd.cstat;
  665. dstat = irb->scsw.cmd.dstat;
  666. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  667. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  668. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  669. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  670. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  671. cdev->dev.bus_id, dstat, cstat);
  672. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  673. 16, 1, irb, 64, 1);
  674. return 1;
  675. }
  676. if (dstat & DEV_STAT_UNIT_CHECK) {
  677. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  678. SENSE_RESETTING_EVENT_FLAG) {
  679. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  680. return 1;
  681. }
  682. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  683. SENSE_COMMAND_REJECT_FLAG) {
  684. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  685. return 0;
  686. }
  687. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  688. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  689. return 1;
  690. }
  691. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  692. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  693. return 0;
  694. }
  695. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  696. return 1;
  697. }
  698. return 0;
  699. }
  700. static long __qeth_check_irb_error(struct ccw_device *cdev,
  701. unsigned long intparm, struct irb *irb)
  702. {
  703. if (!IS_ERR(irb))
  704. return 0;
  705. switch (PTR_ERR(irb)) {
  706. case -EIO:
  707. PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
  708. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  709. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  710. break;
  711. case -ETIMEDOUT:
  712. PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
  713. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  714. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  715. if (intparm == QETH_RCD_PARM) {
  716. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  717. if (card && (card->data.ccwdev == cdev)) {
  718. card->data.state = CH_STATE_DOWN;
  719. wake_up(&card->wait_q);
  720. }
  721. }
  722. break;
  723. default:
  724. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  725. cdev->dev.bus_id);
  726. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  727. QETH_DBF_TEXT(TRACE, 2, " rc???");
  728. }
  729. return PTR_ERR(irb);
  730. }
  731. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  732. struct irb *irb)
  733. {
  734. int rc;
  735. int cstat, dstat;
  736. struct qeth_cmd_buffer *buffer;
  737. struct qeth_channel *channel;
  738. struct qeth_card *card;
  739. struct qeth_cmd_buffer *iob;
  740. __u8 index;
  741. QETH_DBF_TEXT(TRACE, 5, "irq");
  742. if (__qeth_check_irb_error(cdev, intparm, irb))
  743. return;
  744. cstat = irb->scsw.cmd.cstat;
  745. dstat = irb->scsw.cmd.dstat;
  746. card = CARD_FROM_CDEV(cdev);
  747. if (!card)
  748. return;
  749. if (card->read.ccwdev == cdev) {
  750. channel = &card->read;
  751. QETH_DBF_TEXT(TRACE, 5, "read");
  752. } else if (card->write.ccwdev == cdev) {
  753. channel = &card->write;
  754. QETH_DBF_TEXT(TRACE, 5, "write");
  755. } else {
  756. channel = &card->data;
  757. QETH_DBF_TEXT(TRACE, 5, "data");
  758. }
  759. atomic_set(&channel->irq_pending, 0);
  760. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  761. channel->state = CH_STATE_STOPPED;
  762. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  763. channel->state = CH_STATE_HALTED;
  764. /*let's wake up immediately on data channel*/
  765. if ((channel == &card->data) && (intparm != 0) &&
  766. (intparm != QETH_RCD_PARM))
  767. goto out;
  768. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  769. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  770. /* we don't have to handle this further */
  771. intparm = 0;
  772. }
  773. if (intparm == QETH_HALT_CHANNEL_PARM) {
  774. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  775. /* we don't have to handle this further */
  776. intparm = 0;
  777. }
  778. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  779. (dstat & DEV_STAT_UNIT_CHECK) ||
  780. (cstat)) {
  781. if (irb->esw.esw0.erw.cons) {
  782. /* TODO: we should make this s390dbf */
  783. PRINT_WARN("sense data available on channel %s.\n",
  784. CHANNEL_ID(channel));
  785. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  786. print_hex_dump(KERN_WARNING, "qeth: irb ",
  787. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  788. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  789. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  790. }
  791. if (intparm == QETH_RCD_PARM) {
  792. channel->state = CH_STATE_DOWN;
  793. goto out;
  794. }
  795. rc = qeth_get_problem(cdev, irb);
  796. if (rc) {
  797. qeth_schedule_recovery(card);
  798. goto out;
  799. }
  800. }
  801. if (intparm == QETH_RCD_PARM) {
  802. channel->state = CH_STATE_RCD_DONE;
  803. goto out;
  804. }
  805. if (intparm) {
  806. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  807. buffer->state = BUF_STATE_PROCESSED;
  808. }
  809. if (channel == &card->data)
  810. return;
  811. if (channel == &card->read &&
  812. channel->state == CH_STATE_UP)
  813. qeth_issue_next_read(card);
  814. iob = channel->iob;
  815. index = channel->buf_no;
  816. while (iob[index].state == BUF_STATE_PROCESSED) {
  817. if (iob[index].callback != NULL)
  818. iob[index].callback(channel, iob + index);
  819. index = (index + 1) % QETH_CMD_BUFFER_NO;
  820. }
  821. channel->buf_no = index;
  822. out:
  823. wake_up(&card->wait_q);
  824. return;
  825. }
  826. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  827. struct qeth_qdio_out_buffer *buf)
  828. {
  829. int i;
  830. struct sk_buff *skb;
  831. /* is PCI flag set on buffer? */
  832. if (buf->buffer->element[0].flags & 0x40)
  833. atomic_dec(&queue->set_pci_flags_count);
  834. skb = skb_dequeue(&buf->skb_list);
  835. while (skb) {
  836. atomic_dec(&skb->users);
  837. dev_kfree_skb_any(skb);
  838. skb = skb_dequeue(&buf->skb_list);
  839. }
  840. qeth_eddp_buf_release_contexts(buf);
  841. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  842. buf->buffer->element[i].length = 0;
  843. buf->buffer->element[i].addr = NULL;
  844. buf->buffer->element[i].flags = 0;
  845. }
  846. buf->next_element_to_fill = 0;
  847. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  848. }
  849. void qeth_clear_qdio_buffers(struct qeth_card *card)
  850. {
  851. int i, j;
  852. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  853. /* clear outbound buffers to free skbs */
  854. for (i = 0; i < card->qdio.no_out_queues; ++i)
  855. if (card->qdio.out_qs[i]) {
  856. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  857. qeth_clear_output_buffer(card->qdio.out_qs[i],
  858. &card->qdio.out_qs[i]->bufs[j]);
  859. }
  860. }
  861. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  862. static void qeth_free_buffer_pool(struct qeth_card *card)
  863. {
  864. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  865. int i = 0;
  866. QETH_DBF_TEXT(TRACE, 5, "freepool");
  867. list_for_each_entry_safe(pool_entry, tmp,
  868. &card->qdio.init_pool.entry_list, init_list){
  869. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  870. free_page((unsigned long)pool_entry->elements[i]);
  871. list_del(&pool_entry->init_list);
  872. kfree(pool_entry);
  873. }
  874. }
  875. static void qeth_free_qdio_buffers(struct qeth_card *card)
  876. {
  877. int i, j;
  878. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  879. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  880. QETH_QDIO_UNINITIALIZED)
  881. return;
  882. kfree(card->qdio.in_q);
  883. card->qdio.in_q = NULL;
  884. /* inbound buffer pool */
  885. qeth_free_buffer_pool(card);
  886. /* free outbound qdio_qs */
  887. if (card->qdio.out_qs) {
  888. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  889. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  890. qeth_clear_output_buffer(card->qdio.out_qs[i],
  891. &card->qdio.out_qs[i]->bufs[j]);
  892. kfree(card->qdio.out_qs[i]);
  893. }
  894. kfree(card->qdio.out_qs);
  895. card->qdio.out_qs = NULL;
  896. }
  897. }
  898. static void qeth_clean_channel(struct qeth_channel *channel)
  899. {
  900. int cnt;
  901. QETH_DBF_TEXT(SETUP, 2, "freech");
  902. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  903. kfree(channel->iob[cnt].data);
  904. }
  905. static int qeth_is_1920_device(struct qeth_card *card)
  906. {
  907. int single_queue = 0;
  908. struct ccw_device *ccwdev;
  909. struct channelPath_dsc {
  910. u8 flags;
  911. u8 lsn;
  912. u8 desc;
  913. u8 chpid;
  914. u8 swla;
  915. u8 zeroes;
  916. u8 chla;
  917. u8 chpp;
  918. } *chp_dsc;
  919. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  920. ccwdev = card->data.ccwdev;
  921. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  922. if (chp_dsc != NULL) {
  923. /* CHPP field bit 6 == 1 -> single queue */
  924. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  925. kfree(chp_dsc);
  926. }
  927. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  928. return single_queue;
  929. }
  930. static void qeth_init_qdio_info(struct qeth_card *card)
  931. {
  932. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  933. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  934. /* inbound */
  935. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  936. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  937. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  938. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  939. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  940. }
  941. static void qeth_set_intial_options(struct qeth_card *card)
  942. {
  943. card->options.route4.type = NO_ROUTER;
  944. card->options.route6.type = NO_ROUTER;
  945. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  946. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  947. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  948. card->options.fake_broadcast = 0;
  949. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  950. card->options.fake_ll = 0;
  951. card->options.performance_stats = 0;
  952. card->options.rx_sg_cb = QETH_RX_SG_CB;
  953. }
  954. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  955. {
  956. unsigned long flags;
  957. int rc = 0;
  958. spin_lock_irqsave(&card->thread_mask_lock, flags);
  959. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  960. (u8) card->thread_start_mask,
  961. (u8) card->thread_allowed_mask,
  962. (u8) card->thread_running_mask);
  963. rc = (card->thread_start_mask & thread);
  964. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  965. return rc;
  966. }
  967. static void qeth_start_kernel_thread(struct work_struct *work)
  968. {
  969. struct qeth_card *card = container_of(work, struct qeth_card,
  970. kernel_thread_starter);
  971. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  972. if (card->read.state != CH_STATE_UP &&
  973. card->write.state != CH_STATE_UP)
  974. return;
  975. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  976. kthread_run(card->discipline.recover, (void *) card,
  977. "qeth_recover");
  978. }
  979. static int qeth_setup_card(struct qeth_card *card)
  980. {
  981. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  982. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  983. card->read.state = CH_STATE_DOWN;
  984. card->write.state = CH_STATE_DOWN;
  985. card->data.state = CH_STATE_DOWN;
  986. card->state = CARD_STATE_DOWN;
  987. card->lan_online = 0;
  988. card->use_hard_stop = 0;
  989. card->dev = NULL;
  990. spin_lock_init(&card->vlanlock);
  991. spin_lock_init(&card->mclock);
  992. card->vlangrp = NULL;
  993. spin_lock_init(&card->lock);
  994. spin_lock_init(&card->ip_lock);
  995. spin_lock_init(&card->thread_mask_lock);
  996. card->thread_start_mask = 0;
  997. card->thread_allowed_mask = 0;
  998. card->thread_running_mask = 0;
  999. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1000. INIT_LIST_HEAD(&card->ip_list);
  1001. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1002. if (!card->ip_tbd_list) {
  1003. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1004. return -ENOMEM;
  1005. }
  1006. INIT_LIST_HEAD(card->ip_tbd_list);
  1007. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1008. init_waitqueue_head(&card->wait_q);
  1009. /* intial options */
  1010. qeth_set_intial_options(card);
  1011. /* IP address takeover */
  1012. INIT_LIST_HEAD(&card->ipato.entries);
  1013. card->ipato.enabled = 0;
  1014. card->ipato.invert4 = 0;
  1015. card->ipato.invert6 = 0;
  1016. /* init QDIO stuff */
  1017. qeth_init_qdio_info(card);
  1018. return 0;
  1019. }
  1020. static struct qeth_card *qeth_alloc_card(void)
  1021. {
  1022. struct qeth_card *card;
  1023. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1024. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1025. if (!card)
  1026. return NULL;
  1027. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1028. if (qeth_setup_channel(&card->read)) {
  1029. kfree(card);
  1030. return NULL;
  1031. }
  1032. if (qeth_setup_channel(&card->write)) {
  1033. qeth_clean_channel(&card->read);
  1034. kfree(card);
  1035. return NULL;
  1036. }
  1037. card->options.layer2 = -1;
  1038. return card;
  1039. }
  1040. static int qeth_determine_card_type(struct qeth_card *card)
  1041. {
  1042. int i = 0;
  1043. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1044. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1045. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1046. while (known_devices[i][4]) {
  1047. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1048. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1049. card->info.type = known_devices[i][4];
  1050. card->qdio.no_out_queues = known_devices[i][8];
  1051. card->info.is_multicast_different = known_devices[i][9];
  1052. if (qeth_is_1920_device(card)) {
  1053. PRINT_INFO("Priority Queueing not able "
  1054. "due to hardware limitations!\n");
  1055. card->qdio.no_out_queues = 1;
  1056. card->qdio.default_out_queue = 0;
  1057. }
  1058. return 0;
  1059. }
  1060. i++;
  1061. }
  1062. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1063. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1064. return -ENOENT;
  1065. }
  1066. static int qeth_clear_channel(struct qeth_channel *channel)
  1067. {
  1068. unsigned long flags;
  1069. struct qeth_card *card;
  1070. int rc;
  1071. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1072. card = CARD_FROM_CDEV(channel->ccwdev);
  1073. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1074. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1075. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1076. if (rc)
  1077. return rc;
  1078. rc = wait_event_interruptible_timeout(card->wait_q,
  1079. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1080. if (rc == -ERESTARTSYS)
  1081. return rc;
  1082. if (channel->state != CH_STATE_STOPPED)
  1083. return -ETIME;
  1084. channel->state = CH_STATE_DOWN;
  1085. return 0;
  1086. }
  1087. static int qeth_halt_channel(struct qeth_channel *channel)
  1088. {
  1089. unsigned long flags;
  1090. struct qeth_card *card;
  1091. int rc;
  1092. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1093. card = CARD_FROM_CDEV(channel->ccwdev);
  1094. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1095. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1096. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1097. if (rc)
  1098. return rc;
  1099. rc = wait_event_interruptible_timeout(card->wait_q,
  1100. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1101. if (rc == -ERESTARTSYS)
  1102. return rc;
  1103. if (channel->state != CH_STATE_HALTED)
  1104. return -ETIME;
  1105. return 0;
  1106. }
  1107. static int qeth_halt_channels(struct qeth_card *card)
  1108. {
  1109. int rc1 = 0, rc2 = 0, rc3 = 0;
  1110. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1111. rc1 = qeth_halt_channel(&card->read);
  1112. rc2 = qeth_halt_channel(&card->write);
  1113. rc3 = qeth_halt_channel(&card->data);
  1114. if (rc1)
  1115. return rc1;
  1116. if (rc2)
  1117. return rc2;
  1118. return rc3;
  1119. }
  1120. static int qeth_clear_channels(struct qeth_card *card)
  1121. {
  1122. int rc1 = 0, rc2 = 0, rc3 = 0;
  1123. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1124. rc1 = qeth_clear_channel(&card->read);
  1125. rc2 = qeth_clear_channel(&card->write);
  1126. rc3 = qeth_clear_channel(&card->data);
  1127. if (rc1)
  1128. return rc1;
  1129. if (rc2)
  1130. return rc2;
  1131. return rc3;
  1132. }
  1133. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1134. {
  1135. int rc = 0;
  1136. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1137. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1138. if (halt)
  1139. rc = qeth_halt_channels(card);
  1140. if (rc)
  1141. return rc;
  1142. return qeth_clear_channels(card);
  1143. }
  1144. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1145. {
  1146. int rc = 0;
  1147. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1148. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1149. QETH_QDIO_CLEANING)) {
  1150. case QETH_QDIO_ESTABLISHED:
  1151. if (card->info.type == QETH_CARD_TYPE_IQD)
  1152. rc = qdio_cleanup(CARD_DDEV(card),
  1153. QDIO_FLAG_CLEANUP_USING_HALT);
  1154. else
  1155. rc = qdio_cleanup(CARD_DDEV(card),
  1156. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1157. if (rc)
  1158. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1159. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1160. break;
  1161. case QETH_QDIO_CLEANING:
  1162. return rc;
  1163. default:
  1164. break;
  1165. }
  1166. rc = qeth_clear_halt_card(card, use_halt);
  1167. if (rc)
  1168. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1169. card->state = CARD_STATE_DOWN;
  1170. return rc;
  1171. }
  1172. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1173. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1174. int *length)
  1175. {
  1176. struct ciw *ciw;
  1177. char *rcd_buf;
  1178. int ret;
  1179. struct qeth_channel *channel = &card->data;
  1180. unsigned long flags;
  1181. /*
  1182. * scan for RCD command in extended SenseID data
  1183. */
  1184. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1185. if (!ciw || ciw->cmd == 0)
  1186. return -EOPNOTSUPP;
  1187. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1188. if (!rcd_buf)
  1189. return -ENOMEM;
  1190. channel->ccw.cmd_code = ciw->cmd;
  1191. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1192. channel->ccw.count = ciw->count;
  1193. channel->ccw.flags = CCW_FLAG_SLI;
  1194. channel->state = CH_STATE_RCD;
  1195. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1196. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1197. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1198. QETH_RCD_TIMEOUT);
  1199. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1200. if (!ret)
  1201. wait_event(card->wait_q,
  1202. (channel->state == CH_STATE_RCD_DONE ||
  1203. channel->state == CH_STATE_DOWN));
  1204. if (channel->state == CH_STATE_DOWN)
  1205. ret = -EIO;
  1206. else
  1207. channel->state = CH_STATE_DOWN;
  1208. if (ret) {
  1209. kfree(rcd_buf);
  1210. *buffer = NULL;
  1211. *length = 0;
  1212. } else {
  1213. *length = ciw->count;
  1214. *buffer = rcd_buf;
  1215. }
  1216. return ret;
  1217. }
  1218. static int qeth_get_unitaddr(struct qeth_card *card)
  1219. {
  1220. int length;
  1221. char *prcd;
  1222. int rc;
  1223. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1224. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1225. if (rc) {
  1226. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1227. CARD_DDEV_ID(card), rc);
  1228. return rc;
  1229. }
  1230. card->info.chpid = prcd[30];
  1231. card->info.unit_addr2 = prcd[31];
  1232. card->info.cula = prcd[63];
  1233. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1234. (prcd[0x11] == _ascebc['M']));
  1235. kfree(prcd);
  1236. return 0;
  1237. }
  1238. static void qeth_init_tokens(struct qeth_card *card)
  1239. {
  1240. card->token.issuer_rm_w = 0x00010103UL;
  1241. card->token.cm_filter_w = 0x00010108UL;
  1242. card->token.cm_connection_w = 0x0001010aUL;
  1243. card->token.ulp_filter_w = 0x0001010bUL;
  1244. card->token.ulp_connection_w = 0x0001010dUL;
  1245. }
  1246. static void qeth_init_func_level(struct qeth_card *card)
  1247. {
  1248. if (card->ipato.enabled) {
  1249. if (card->info.type == QETH_CARD_TYPE_IQD)
  1250. card->info.func_level =
  1251. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1252. else
  1253. card->info.func_level =
  1254. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1255. } else {
  1256. if (card->info.type == QETH_CARD_TYPE_IQD)
  1257. /*FIXME:why do we have same values for dis and ena for
  1258. osae??? */
  1259. card->info.func_level =
  1260. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1261. else
  1262. card->info.func_level =
  1263. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1264. }
  1265. }
  1266. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1267. void (*idx_reply_cb)(struct qeth_channel *,
  1268. struct qeth_cmd_buffer *))
  1269. {
  1270. struct qeth_cmd_buffer *iob;
  1271. unsigned long flags;
  1272. int rc;
  1273. struct qeth_card *card;
  1274. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1275. card = CARD_FROM_CDEV(channel->ccwdev);
  1276. iob = qeth_get_buffer(channel);
  1277. iob->callback = idx_reply_cb;
  1278. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1279. channel->ccw.count = QETH_BUFSIZE;
  1280. channel->ccw.cda = (__u32) __pa(iob->data);
  1281. wait_event(card->wait_q,
  1282. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1283. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1284. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1285. rc = ccw_device_start(channel->ccwdev,
  1286. &channel->ccw, (addr_t) iob, 0, 0);
  1287. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1288. if (rc) {
  1289. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1290. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1291. atomic_set(&channel->irq_pending, 0);
  1292. wake_up(&card->wait_q);
  1293. return rc;
  1294. }
  1295. rc = wait_event_interruptible_timeout(card->wait_q,
  1296. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1297. if (rc == -ERESTARTSYS)
  1298. return rc;
  1299. if (channel->state != CH_STATE_UP) {
  1300. rc = -ETIME;
  1301. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1302. qeth_clear_cmd_buffers(channel);
  1303. } else
  1304. rc = 0;
  1305. return rc;
  1306. }
  1307. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1308. void (*idx_reply_cb)(struct qeth_channel *,
  1309. struct qeth_cmd_buffer *))
  1310. {
  1311. struct qeth_card *card;
  1312. struct qeth_cmd_buffer *iob;
  1313. unsigned long flags;
  1314. __u16 temp;
  1315. __u8 tmp;
  1316. int rc;
  1317. struct ccw_dev_id temp_devid;
  1318. card = CARD_FROM_CDEV(channel->ccwdev);
  1319. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1320. iob = qeth_get_buffer(channel);
  1321. iob->callback = idx_reply_cb;
  1322. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1323. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1324. channel->ccw.cda = (__u32) __pa(iob->data);
  1325. if (channel == &card->write) {
  1326. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1327. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1328. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1329. card->seqno.trans_hdr++;
  1330. } else {
  1331. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1332. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1333. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1334. }
  1335. tmp = ((__u8)card->info.portno) | 0x80;
  1336. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1337. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1338. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1339. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1340. &card->info.func_level, sizeof(__u16));
  1341. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1342. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1343. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1344. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1345. wait_event(card->wait_q,
  1346. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1347. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1348. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1349. rc = ccw_device_start(channel->ccwdev,
  1350. &channel->ccw, (addr_t) iob, 0, 0);
  1351. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1352. if (rc) {
  1353. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1354. rc);
  1355. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1356. atomic_set(&channel->irq_pending, 0);
  1357. wake_up(&card->wait_q);
  1358. return rc;
  1359. }
  1360. rc = wait_event_interruptible_timeout(card->wait_q,
  1361. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1362. if (rc == -ERESTARTSYS)
  1363. return rc;
  1364. if (channel->state != CH_STATE_ACTIVATING) {
  1365. PRINT_WARN("IDX activate timed out!\n");
  1366. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1367. qeth_clear_cmd_buffers(channel);
  1368. return -ETIME;
  1369. }
  1370. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1371. }
  1372. static int qeth_peer_func_level(int level)
  1373. {
  1374. if ((level & 0xff) == 8)
  1375. return (level & 0xff) + 0x400;
  1376. if (((level >> 8) & 3) == 1)
  1377. return (level & 0xff) + 0x200;
  1378. return level;
  1379. }
  1380. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1381. struct qeth_cmd_buffer *iob)
  1382. {
  1383. struct qeth_card *card;
  1384. __u16 temp;
  1385. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1386. if (channel->state == CH_STATE_DOWN) {
  1387. channel->state = CH_STATE_ACTIVATING;
  1388. goto out;
  1389. }
  1390. card = CARD_FROM_CDEV(channel->ccwdev);
  1391. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1392. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1393. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1394. "adapter exclusively used by another host\n",
  1395. CARD_WDEV_ID(card));
  1396. else
  1397. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1398. "negative reply\n", CARD_WDEV_ID(card));
  1399. goto out;
  1400. }
  1401. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1402. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1403. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1404. "function level mismatch "
  1405. "(sent: 0x%x, received: 0x%x)\n",
  1406. CARD_WDEV_ID(card), card->info.func_level, temp);
  1407. goto out;
  1408. }
  1409. channel->state = CH_STATE_UP;
  1410. out:
  1411. qeth_release_buffer(channel, iob);
  1412. }
  1413. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1414. struct qeth_cmd_buffer *iob)
  1415. {
  1416. struct qeth_card *card;
  1417. __u16 temp;
  1418. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1419. if (channel->state == CH_STATE_DOWN) {
  1420. channel->state = CH_STATE_ACTIVATING;
  1421. goto out;
  1422. }
  1423. card = CARD_FROM_CDEV(channel->ccwdev);
  1424. if (qeth_check_idx_response(iob->data))
  1425. goto out;
  1426. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1427. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1428. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1429. "adapter exclusively used by another host\n",
  1430. CARD_RDEV_ID(card));
  1431. else
  1432. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1433. "negative reply\n", CARD_RDEV_ID(card));
  1434. goto out;
  1435. }
  1436. /**
  1437. * temporary fix for microcode bug
  1438. * to revert it,replace OR by AND
  1439. */
  1440. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1441. (card->info.type == QETH_CARD_TYPE_OSAE))
  1442. card->info.portname_required = 1;
  1443. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1444. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1445. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1446. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1447. CARD_RDEV_ID(card), card->info.func_level, temp);
  1448. goto out;
  1449. }
  1450. memcpy(&card->token.issuer_rm_r,
  1451. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1452. QETH_MPC_TOKEN_LENGTH);
  1453. memcpy(&card->info.mcl_level[0],
  1454. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1455. channel->state = CH_STATE_UP;
  1456. out:
  1457. qeth_release_buffer(channel, iob);
  1458. }
  1459. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1460. struct qeth_cmd_buffer *iob)
  1461. {
  1462. qeth_setup_ccw(&card->write, iob->data, len);
  1463. iob->callback = qeth_release_buffer;
  1464. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1465. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1466. card->seqno.trans_hdr++;
  1467. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1468. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1469. card->seqno.pdu_hdr++;
  1470. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1471. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1472. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1473. }
  1474. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1475. int qeth_send_control_data(struct qeth_card *card, int len,
  1476. struct qeth_cmd_buffer *iob,
  1477. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1478. unsigned long),
  1479. void *reply_param)
  1480. {
  1481. int rc;
  1482. unsigned long flags;
  1483. struct qeth_reply *reply = NULL;
  1484. unsigned long timeout;
  1485. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1486. reply = qeth_alloc_reply(card);
  1487. if (!reply) {
  1488. return -ENOMEM;
  1489. }
  1490. reply->callback = reply_cb;
  1491. reply->param = reply_param;
  1492. if (card->state == CARD_STATE_DOWN)
  1493. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1494. else
  1495. reply->seqno = card->seqno.ipa++;
  1496. init_waitqueue_head(&reply->wait_q);
  1497. spin_lock_irqsave(&card->lock, flags);
  1498. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1499. spin_unlock_irqrestore(&card->lock, flags);
  1500. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1501. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1502. qeth_prepare_control_data(card, len, iob);
  1503. if (IS_IPA(iob->data))
  1504. timeout = jiffies + QETH_IPA_TIMEOUT;
  1505. else
  1506. timeout = jiffies + QETH_TIMEOUT;
  1507. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1508. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1509. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1510. (addr_t) iob, 0, 0);
  1511. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1512. if (rc) {
  1513. PRINT_WARN("qeth_send_control_data: "
  1514. "ccw_device_start rc = %i\n", rc);
  1515. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1516. spin_lock_irqsave(&card->lock, flags);
  1517. list_del_init(&reply->list);
  1518. qeth_put_reply(reply);
  1519. spin_unlock_irqrestore(&card->lock, flags);
  1520. qeth_release_buffer(iob->channel, iob);
  1521. atomic_set(&card->write.irq_pending, 0);
  1522. wake_up(&card->wait_q);
  1523. return rc;
  1524. }
  1525. while (!atomic_read(&reply->received)) {
  1526. if (time_after(jiffies, timeout)) {
  1527. spin_lock_irqsave(&reply->card->lock, flags);
  1528. list_del_init(&reply->list);
  1529. spin_unlock_irqrestore(&reply->card->lock, flags);
  1530. reply->rc = -ETIME;
  1531. atomic_inc(&reply->received);
  1532. wake_up(&reply->wait_q);
  1533. }
  1534. cpu_relax();
  1535. };
  1536. rc = reply->rc;
  1537. qeth_put_reply(reply);
  1538. return rc;
  1539. }
  1540. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1541. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1542. unsigned long data)
  1543. {
  1544. struct qeth_cmd_buffer *iob;
  1545. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1546. iob = (struct qeth_cmd_buffer *) data;
  1547. memcpy(&card->token.cm_filter_r,
  1548. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1549. QETH_MPC_TOKEN_LENGTH);
  1550. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1551. return 0;
  1552. }
  1553. static int qeth_cm_enable(struct qeth_card *card)
  1554. {
  1555. int rc;
  1556. struct qeth_cmd_buffer *iob;
  1557. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1558. iob = qeth_wait_for_buffer(&card->write);
  1559. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1560. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1561. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1562. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1563. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1564. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1565. qeth_cm_enable_cb, NULL);
  1566. return rc;
  1567. }
  1568. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1569. unsigned long data)
  1570. {
  1571. struct qeth_cmd_buffer *iob;
  1572. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1573. iob = (struct qeth_cmd_buffer *) data;
  1574. memcpy(&card->token.cm_connection_r,
  1575. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1576. QETH_MPC_TOKEN_LENGTH);
  1577. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1578. return 0;
  1579. }
  1580. static int qeth_cm_setup(struct qeth_card *card)
  1581. {
  1582. int rc;
  1583. struct qeth_cmd_buffer *iob;
  1584. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1585. iob = qeth_wait_for_buffer(&card->write);
  1586. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1587. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1588. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1589. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1590. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1591. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1592. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1593. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1594. qeth_cm_setup_cb, NULL);
  1595. return rc;
  1596. }
  1597. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1598. {
  1599. switch (card->info.type) {
  1600. case QETH_CARD_TYPE_UNKNOWN:
  1601. return 1500;
  1602. case QETH_CARD_TYPE_IQD:
  1603. return card->info.max_mtu;
  1604. case QETH_CARD_TYPE_OSAE:
  1605. switch (card->info.link_type) {
  1606. case QETH_LINK_TYPE_HSTR:
  1607. case QETH_LINK_TYPE_LANE_TR:
  1608. return 2000;
  1609. default:
  1610. return 1492;
  1611. }
  1612. default:
  1613. return 1500;
  1614. }
  1615. }
  1616. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1617. {
  1618. switch (cardtype) {
  1619. case QETH_CARD_TYPE_UNKNOWN:
  1620. case QETH_CARD_TYPE_OSAE:
  1621. case QETH_CARD_TYPE_OSN:
  1622. return 61440;
  1623. case QETH_CARD_TYPE_IQD:
  1624. return 57344;
  1625. default:
  1626. return 1500;
  1627. }
  1628. }
  1629. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1630. {
  1631. switch (cardtype) {
  1632. case QETH_CARD_TYPE_IQD:
  1633. return 1;
  1634. default:
  1635. return 0;
  1636. }
  1637. }
  1638. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1639. {
  1640. switch (framesize) {
  1641. case 0x4000:
  1642. return 8192;
  1643. case 0x6000:
  1644. return 16384;
  1645. case 0xa000:
  1646. return 32768;
  1647. case 0xffff:
  1648. return 57344;
  1649. default:
  1650. return 0;
  1651. }
  1652. }
  1653. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1654. {
  1655. switch (card->info.type) {
  1656. case QETH_CARD_TYPE_OSAE:
  1657. return ((mtu >= 576) && (mtu <= 61440));
  1658. case QETH_CARD_TYPE_IQD:
  1659. return ((mtu >= 576) &&
  1660. (mtu <= card->info.max_mtu + 4096 - 32));
  1661. case QETH_CARD_TYPE_OSN:
  1662. case QETH_CARD_TYPE_UNKNOWN:
  1663. default:
  1664. return 1;
  1665. }
  1666. }
  1667. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1668. unsigned long data)
  1669. {
  1670. __u16 mtu, framesize;
  1671. __u16 len;
  1672. __u8 link_type;
  1673. struct qeth_cmd_buffer *iob;
  1674. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1675. iob = (struct qeth_cmd_buffer *) data;
  1676. memcpy(&card->token.ulp_filter_r,
  1677. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1678. QETH_MPC_TOKEN_LENGTH);
  1679. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1680. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1681. mtu = qeth_get_mtu_outof_framesize(framesize);
  1682. if (!mtu) {
  1683. iob->rc = -EINVAL;
  1684. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1685. return 0;
  1686. }
  1687. card->info.max_mtu = mtu;
  1688. card->info.initial_mtu = mtu;
  1689. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1690. } else {
  1691. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1692. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1693. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1694. }
  1695. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1696. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1697. memcpy(&link_type,
  1698. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1699. card->info.link_type = link_type;
  1700. } else
  1701. card->info.link_type = 0;
  1702. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1703. return 0;
  1704. }
  1705. static int qeth_ulp_enable(struct qeth_card *card)
  1706. {
  1707. int rc;
  1708. char prot_type;
  1709. struct qeth_cmd_buffer *iob;
  1710. /*FIXME: trace view callbacks*/
  1711. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1712. iob = qeth_wait_for_buffer(&card->write);
  1713. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1714. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1715. (__u8) card->info.portno;
  1716. if (card->options.layer2)
  1717. if (card->info.type == QETH_CARD_TYPE_OSN)
  1718. prot_type = QETH_PROT_OSN2;
  1719. else
  1720. prot_type = QETH_PROT_LAYER2;
  1721. else
  1722. prot_type = QETH_PROT_TCPIP;
  1723. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1724. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1725. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1726. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1727. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1728. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1729. card->info.portname, 9);
  1730. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1731. qeth_ulp_enable_cb, NULL);
  1732. return rc;
  1733. }
  1734. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1735. unsigned long data)
  1736. {
  1737. struct qeth_cmd_buffer *iob;
  1738. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1739. iob = (struct qeth_cmd_buffer *) data;
  1740. memcpy(&card->token.ulp_connection_r,
  1741. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1742. QETH_MPC_TOKEN_LENGTH);
  1743. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1744. return 0;
  1745. }
  1746. static int qeth_ulp_setup(struct qeth_card *card)
  1747. {
  1748. int rc;
  1749. __u16 temp;
  1750. struct qeth_cmd_buffer *iob;
  1751. struct ccw_dev_id dev_id;
  1752. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1753. iob = qeth_wait_for_buffer(&card->write);
  1754. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1755. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1756. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1757. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1758. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1759. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1760. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1761. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1762. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1763. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1764. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1765. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1766. qeth_ulp_setup_cb, NULL);
  1767. return rc;
  1768. }
  1769. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1770. {
  1771. int i, j;
  1772. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1773. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1774. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1775. return 0;
  1776. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1777. GFP_KERNEL);
  1778. if (!card->qdio.in_q)
  1779. goto out_nomem;
  1780. QETH_DBF_TEXT(SETUP, 2, "inq");
  1781. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1782. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1783. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1784. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1785. card->qdio.in_q->bufs[i].buffer =
  1786. &card->qdio.in_q->qdio_bufs[i];
  1787. /* inbound buffer pool */
  1788. if (qeth_alloc_buffer_pool(card))
  1789. goto out_freeinq;
  1790. /* outbound */
  1791. card->qdio.out_qs =
  1792. kmalloc(card->qdio.no_out_queues *
  1793. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1794. if (!card->qdio.out_qs)
  1795. goto out_freepool;
  1796. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1797. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1798. GFP_KERNEL);
  1799. if (!card->qdio.out_qs[i])
  1800. goto out_freeoutq;
  1801. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1802. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1803. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1804. card->qdio.out_qs[i]->queue_no = i;
  1805. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1806. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1807. card->qdio.out_qs[i]->bufs[j].buffer =
  1808. &card->qdio.out_qs[i]->qdio_bufs[j];
  1809. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1810. skb_list);
  1811. lockdep_set_class(
  1812. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1813. &qdio_out_skb_queue_key);
  1814. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1815. }
  1816. }
  1817. return 0;
  1818. out_freeoutq:
  1819. while (i > 0)
  1820. kfree(card->qdio.out_qs[--i]);
  1821. kfree(card->qdio.out_qs);
  1822. card->qdio.out_qs = NULL;
  1823. out_freepool:
  1824. qeth_free_buffer_pool(card);
  1825. out_freeinq:
  1826. kfree(card->qdio.in_q);
  1827. card->qdio.in_q = NULL;
  1828. out_nomem:
  1829. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1830. return -ENOMEM;
  1831. }
  1832. static void qeth_create_qib_param_field(struct qeth_card *card,
  1833. char *param_field)
  1834. {
  1835. param_field[0] = _ascebc['P'];
  1836. param_field[1] = _ascebc['C'];
  1837. param_field[2] = _ascebc['I'];
  1838. param_field[3] = _ascebc['T'];
  1839. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1840. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1841. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1842. }
  1843. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1844. char *param_field)
  1845. {
  1846. param_field[16] = _ascebc['B'];
  1847. param_field[17] = _ascebc['L'];
  1848. param_field[18] = _ascebc['K'];
  1849. param_field[19] = _ascebc['T'];
  1850. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1851. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1852. *((unsigned int *) (&param_field[28])) =
  1853. card->info.blkt.inter_packet_jumbo;
  1854. }
  1855. static int qeth_qdio_activate(struct qeth_card *card)
  1856. {
  1857. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1858. return qdio_activate(CARD_DDEV(card));
  1859. }
  1860. static int qeth_dm_act(struct qeth_card *card)
  1861. {
  1862. int rc;
  1863. struct qeth_cmd_buffer *iob;
  1864. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1865. iob = qeth_wait_for_buffer(&card->write);
  1866. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1867. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1868. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1869. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1870. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1871. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1872. return rc;
  1873. }
  1874. static int qeth_mpc_initialize(struct qeth_card *card)
  1875. {
  1876. int rc;
  1877. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1878. rc = qeth_issue_next_read(card);
  1879. if (rc) {
  1880. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1881. return rc;
  1882. }
  1883. rc = qeth_cm_enable(card);
  1884. if (rc) {
  1885. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1886. goto out_qdio;
  1887. }
  1888. rc = qeth_cm_setup(card);
  1889. if (rc) {
  1890. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1891. goto out_qdio;
  1892. }
  1893. rc = qeth_ulp_enable(card);
  1894. if (rc) {
  1895. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1896. goto out_qdio;
  1897. }
  1898. rc = qeth_ulp_setup(card);
  1899. if (rc) {
  1900. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1901. goto out_qdio;
  1902. }
  1903. rc = qeth_alloc_qdio_buffers(card);
  1904. if (rc) {
  1905. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1906. goto out_qdio;
  1907. }
  1908. rc = qeth_qdio_establish(card);
  1909. if (rc) {
  1910. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1911. qeth_free_qdio_buffers(card);
  1912. goto out_qdio;
  1913. }
  1914. rc = qeth_qdio_activate(card);
  1915. if (rc) {
  1916. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1917. goto out_qdio;
  1918. }
  1919. rc = qeth_dm_act(card);
  1920. if (rc) {
  1921. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1922. goto out_qdio;
  1923. }
  1924. return 0;
  1925. out_qdio:
  1926. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1927. return rc;
  1928. }
  1929. static void qeth_print_status_with_portname(struct qeth_card *card)
  1930. {
  1931. char dbf_text[15];
  1932. int i;
  1933. sprintf(dbf_text, "%s", card->info.portname + 1);
  1934. for (i = 0; i < 8; i++)
  1935. dbf_text[i] =
  1936. (char) _ebcasc[(__u8) dbf_text[i]];
  1937. dbf_text[8] = 0;
  1938. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1939. "with link type %s (portname: %s)\n",
  1940. CARD_RDEV_ID(card),
  1941. CARD_WDEV_ID(card),
  1942. CARD_DDEV_ID(card),
  1943. qeth_get_cardname(card),
  1944. (card->info.mcl_level[0]) ? " (level: " : "",
  1945. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1946. (card->info.mcl_level[0]) ? ")" : "",
  1947. qeth_get_cardname_short(card),
  1948. dbf_text);
  1949. }
  1950. static void qeth_print_status_no_portname(struct qeth_card *card)
  1951. {
  1952. if (card->info.portname[0])
  1953. PRINT_INFO("Device %s/%s/%s is a%s "
  1954. "card%s%s%s\nwith link type %s "
  1955. "(no portname needed by interface).\n",
  1956. CARD_RDEV_ID(card),
  1957. CARD_WDEV_ID(card),
  1958. CARD_DDEV_ID(card),
  1959. qeth_get_cardname(card),
  1960. (card->info.mcl_level[0]) ? " (level: " : "",
  1961. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1962. (card->info.mcl_level[0]) ? ")" : "",
  1963. qeth_get_cardname_short(card));
  1964. else
  1965. PRINT_INFO("Device %s/%s/%s is a%s "
  1966. "card%s%s%s\nwith link type %s.\n",
  1967. CARD_RDEV_ID(card),
  1968. CARD_WDEV_ID(card),
  1969. CARD_DDEV_ID(card),
  1970. qeth_get_cardname(card),
  1971. (card->info.mcl_level[0]) ? " (level: " : "",
  1972. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1973. (card->info.mcl_level[0]) ? ")" : "",
  1974. qeth_get_cardname_short(card));
  1975. }
  1976. void qeth_print_status_message(struct qeth_card *card)
  1977. {
  1978. switch (card->info.type) {
  1979. case QETH_CARD_TYPE_OSAE:
  1980. /* VM will use a non-zero first character
  1981. * to indicate a HiperSockets like reporting
  1982. * of the level OSA sets the first character to zero
  1983. * */
  1984. if (!card->info.mcl_level[0]) {
  1985. sprintf(card->info.mcl_level, "%02x%02x",
  1986. card->info.mcl_level[2],
  1987. card->info.mcl_level[3]);
  1988. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  1989. break;
  1990. }
  1991. /* fallthrough */
  1992. case QETH_CARD_TYPE_IQD:
  1993. if (card->info.guestlan) {
  1994. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  1995. card->info.mcl_level[0]];
  1996. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  1997. card->info.mcl_level[1]];
  1998. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  1999. card->info.mcl_level[2]];
  2000. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2001. card->info.mcl_level[3]];
  2002. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2003. }
  2004. break;
  2005. default:
  2006. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2007. }
  2008. if (card->info.portname_required)
  2009. qeth_print_status_with_portname(card);
  2010. else
  2011. qeth_print_status_no_portname(card);
  2012. }
  2013. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2014. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2015. {
  2016. struct qeth_buffer_pool_entry *entry;
  2017. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2018. list_for_each_entry(entry,
  2019. &card->qdio.init_pool.entry_list, init_list) {
  2020. qeth_put_buffer_pool_entry(card, entry);
  2021. }
  2022. }
  2023. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2024. struct qeth_card *card)
  2025. {
  2026. struct list_head *plh;
  2027. struct qeth_buffer_pool_entry *entry;
  2028. int i, free;
  2029. struct page *page;
  2030. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2031. return NULL;
  2032. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2033. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2034. free = 1;
  2035. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2036. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2037. free = 0;
  2038. break;
  2039. }
  2040. }
  2041. if (free) {
  2042. list_del_init(&entry->list);
  2043. return entry;
  2044. }
  2045. }
  2046. /* no free buffer in pool so take first one and swap pages */
  2047. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2048. struct qeth_buffer_pool_entry, list);
  2049. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2050. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2051. page = alloc_page(GFP_ATOMIC);
  2052. if (!page) {
  2053. return NULL;
  2054. } else {
  2055. free_page((unsigned long)entry->elements[i]);
  2056. entry->elements[i] = page_address(page);
  2057. if (card->options.performance_stats)
  2058. card->perf_stats.sg_alloc_page_rx++;
  2059. }
  2060. }
  2061. }
  2062. list_del_init(&entry->list);
  2063. return entry;
  2064. }
  2065. static int qeth_init_input_buffer(struct qeth_card *card,
  2066. struct qeth_qdio_buffer *buf)
  2067. {
  2068. struct qeth_buffer_pool_entry *pool_entry;
  2069. int i;
  2070. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2071. if (!pool_entry)
  2072. return 1;
  2073. /*
  2074. * since the buffer is accessed only from the input_tasklet
  2075. * there shouldn't be a need to synchronize; also, since we use
  2076. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2077. * buffers
  2078. */
  2079. BUG_ON(!pool_entry);
  2080. buf->pool_entry = pool_entry;
  2081. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2082. buf->buffer->element[i].length = PAGE_SIZE;
  2083. buf->buffer->element[i].addr = pool_entry->elements[i];
  2084. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2085. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2086. else
  2087. buf->buffer->element[i].flags = 0;
  2088. }
  2089. return 0;
  2090. }
  2091. int qeth_init_qdio_queues(struct qeth_card *card)
  2092. {
  2093. int i, j;
  2094. int rc;
  2095. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2096. /* inbound queue */
  2097. memset(card->qdio.in_q->qdio_bufs, 0,
  2098. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2099. qeth_initialize_working_pool_list(card);
  2100. /*give only as many buffers to hardware as we have buffer pool entries*/
  2101. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2102. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2103. card->qdio.in_q->next_buf_to_init =
  2104. card->qdio.in_buf_pool.buf_count - 1;
  2105. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2106. card->qdio.in_buf_pool.buf_count - 1);
  2107. if (rc) {
  2108. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2109. return rc;
  2110. }
  2111. /* outbound queue */
  2112. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2113. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2114. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2115. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2116. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2117. &card->qdio.out_qs[i]->bufs[j]);
  2118. }
  2119. card->qdio.out_qs[i]->card = card;
  2120. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2121. card->qdio.out_qs[i]->do_pack = 0;
  2122. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2123. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2124. atomic_set(&card->qdio.out_qs[i]->state,
  2125. QETH_OUT_Q_UNLOCKED);
  2126. }
  2127. return 0;
  2128. }
  2129. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2130. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2131. {
  2132. switch (link_type) {
  2133. case QETH_LINK_TYPE_HSTR:
  2134. return 2;
  2135. default:
  2136. return 1;
  2137. }
  2138. }
  2139. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2140. struct qeth_ipa_cmd *cmd, __u8 command,
  2141. enum qeth_prot_versions prot)
  2142. {
  2143. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2144. cmd->hdr.command = command;
  2145. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2146. cmd->hdr.seqno = card->seqno.ipa;
  2147. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2148. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2149. if (card->options.layer2)
  2150. cmd->hdr.prim_version_no = 2;
  2151. else
  2152. cmd->hdr.prim_version_no = 1;
  2153. cmd->hdr.param_count = 1;
  2154. cmd->hdr.prot_version = prot;
  2155. cmd->hdr.ipa_supported = 0;
  2156. cmd->hdr.ipa_enabled = 0;
  2157. }
  2158. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2159. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2160. {
  2161. struct qeth_cmd_buffer *iob;
  2162. struct qeth_ipa_cmd *cmd;
  2163. iob = qeth_wait_for_buffer(&card->write);
  2164. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2165. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2166. return iob;
  2167. }
  2168. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2169. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2170. char prot_type)
  2171. {
  2172. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2173. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2174. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2175. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2176. }
  2177. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2178. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2179. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2180. unsigned long),
  2181. void *reply_param)
  2182. {
  2183. int rc;
  2184. char prot_type;
  2185. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2186. if (card->options.layer2)
  2187. if (card->info.type == QETH_CARD_TYPE_OSN)
  2188. prot_type = QETH_PROT_OSN2;
  2189. else
  2190. prot_type = QETH_PROT_LAYER2;
  2191. else
  2192. prot_type = QETH_PROT_TCPIP;
  2193. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2194. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2195. iob, reply_cb, reply_param);
  2196. return rc;
  2197. }
  2198. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2199. static int qeth_send_startstoplan(struct qeth_card *card,
  2200. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2201. {
  2202. int rc;
  2203. struct qeth_cmd_buffer *iob;
  2204. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2205. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2206. return rc;
  2207. }
  2208. int qeth_send_startlan(struct qeth_card *card)
  2209. {
  2210. int rc;
  2211. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2212. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2213. return rc;
  2214. }
  2215. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2216. int qeth_send_stoplan(struct qeth_card *card)
  2217. {
  2218. int rc = 0;
  2219. /*
  2220. * TODO: according to the IPA format document page 14,
  2221. * TCP/IP (we!) never issue a STOPLAN
  2222. * is this right ?!?
  2223. */
  2224. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2225. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2226. return rc;
  2227. }
  2228. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2229. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2230. struct qeth_reply *reply, unsigned long data)
  2231. {
  2232. struct qeth_ipa_cmd *cmd;
  2233. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2234. cmd = (struct qeth_ipa_cmd *) data;
  2235. if (cmd->hdr.return_code == 0)
  2236. cmd->hdr.return_code =
  2237. cmd->data.setadapterparms.hdr.return_code;
  2238. return 0;
  2239. }
  2240. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2241. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2242. struct qeth_reply *reply, unsigned long data)
  2243. {
  2244. struct qeth_ipa_cmd *cmd;
  2245. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2246. cmd = (struct qeth_ipa_cmd *) data;
  2247. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2248. card->info.link_type =
  2249. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2250. card->options.adp.supported_funcs =
  2251. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2252. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2253. }
  2254. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2255. __u32 command, __u32 cmdlen)
  2256. {
  2257. struct qeth_cmd_buffer *iob;
  2258. struct qeth_ipa_cmd *cmd;
  2259. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2260. QETH_PROT_IPV4);
  2261. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2262. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2263. cmd->data.setadapterparms.hdr.command_code = command;
  2264. cmd->data.setadapterparms.hdr.used_total = 1;
  2265. cmd->data.setadapterparms.hdr.seq_no = 1;
  2266. return iob;
  2267. }
  2268. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2269. int qeth_query_setadapterparms(struct qeth_card *card)
  2270. {
  2271. int rc;
  2272. struct qeth_cmd_buffer *iob;
  2273. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2274. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2275. sizeof(struct qeth_ipacmd_setadpparms));
  2276. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2277. return rc;
  2278. }
  2279. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2280. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2281. const char *dbftext)
  2282. {
  2283. if (qdio_error) {
  2284. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2285. QETH_DBF_TEXT(QERR, 2, dbftext);
  2286. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2287. buf->element[15].flags & 0xff);
  2288. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2289. buf->element[14].flags & 0xff);
  2290. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2291. return 1;
  2292. }
  2293. return 0;
  2294. }
  2295. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2296. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2297. {
  2298. struct qeth_qdio_q *queue = card->qdio.in_q;
  2299. int count;
  2300. int i;
  2301. int rc;
  2302. int newcount = 0;
  2303. count = (index < queue->next_buf_to_init)?
  2304. card->qdio.in_buf_pool.buf_count -
  2305. (queue->next_buf_to_init - index) :
  2306. card->qdio.in_buf_pool.buf_count -
  2307. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2308. /* only requeue at a certain threshold to avoid SIGAs */
  2309. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2310. for (i = queue->next_buf_to_init;
  2311. i < queue->next_buf_to_init + count; ++i) {
  2312. if (qeth_init_input_buffer(card,
  2313. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2314. break;
  2315. } else {
  2316. newcount++;
  2317. }
  2318. }
  2319. if (newcount < count) {
  2320. /* we are in memory shortage so we switch back to
  2321. traditional skb allocation and drop packages */
  2322. atomic_set(&card->force_alloc_skb, 3);
  2323. count = newcount;
  2324. } else {
  2325. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2326. }
  2327. /*
  2328. * according to old code it should be avoided to requeue all
  2329. * 128 buffers in order to benefit from PCI avoidance.
  2330. * this function keeps at least one buffer (the buffer at
  2331. * 'index') un-requeued -> this buffer is the first buffer that
  2332. * will be requeued the next time
  2333. */
  2334. if (card->options.performance_stats) {
  2335. card->perf_stats.inbound_do_qdio_cnt++;
  2336. card->perf_stats.inbound_do_qdio_start_time =
  2337. qeth_get_micros();
  2338. }
  2339. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2340. queue->next_buf_to_init, count);
  2341. if (card->options.performance_stats)
  2342. card->perf_stats.inbound_do_qdio_time +=
  2343. qeth_get_micros() -
  2344. card->perf_stats.inbound_do_qdio_start_time;
  2345. if (rc) {
  2346. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2347. "return %i (device %s).\n",
  2348. rc, CARD_DDEV_ID(card));
  2349. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2350. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2351. }
  2352. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2353. QDIO_MAX_BUFFERS_PER_Q;
  2354. }
  2355. }
  2356. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2357. static int qeth_handle_send_error(struct qeth_card *card,
  2358. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2359. {
  2360. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2361. int cc = qdio_err & 3;
  2362. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2363. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2364. switch (cc) {
  2365. case 0:
  2366. if (qdio_err) {
  2367. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2368. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2369. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2370. (u16)qdio_err, (u8)sbalf15);
  2371. return QETH_SEND_ERROR_LINK_FAILURE;
  2372. }
  2373. return QETH_SEND_ERROR_NONE;
  2374. case 2:
  2375. if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
  2376. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2377. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2378. return QETH_SEND_ERROR_KICK_IT;
  2379. }
  2380. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2381. return QETH_SEND_ERROR_RETRY;
  2382. return QETH_SEND_ERROR_LINK_FAILURE;
  2383. /* look at qdio_error and sbalf 15 */
  2384. case 1:
  2385. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2386. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2387. return QETH_SEND_ERROR_LINK_FAILURE;
  2388. case 3:
  2389. default:
  2390. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2391. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2392. return QETH_SEND_ERROR_KICK_IT;
  2393. }
  2394. }
  2395. /*
  2396. * Switched to packing state if the number of used buffers on a queue
  2397. * reaches a certain limit.
  2398. */
  2399. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2400. {
  2401. if (!queue->do_pack) {
  2402. if (atomic_read(&queue->used_buffers)
  2403. >= QETH_HIGH_WATERMARK_PACK){
  2404. /* switch non-PACKING -> PACKING */
  2405. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2406. if (queue->card->options.performance_stats)
  2407. queue->card->perf_stats.sc_dp_p++;
  2408. queue->do_pack = 1;
  2409. }
  2410. }
  2411. }
  2412. /*
  2413. * Switches from packing to non-packing mode. If there is a packing
  2414. * buffer on the queue this buffer will be prepared to be flushed.
  2415. * In that case 1 is returned to inform the caller. If no buffer
  2416. * has to be flushed, zero is returned.
  2417. */
  2418. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2419. {
  2420. struct qeth_qdio_out_buffer *buffer;
  2421. int flush_count = 0;
  2422. if (queue->do_pack) {
  2423. if (atomic_read(&queue->used_buffers)
  2424. <= QETH_LOW_WATERMARK_PACK) {
  2425. /* switch PACKING -> non-PACKING */
  2426. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2427. if (queue->card->options.performance_stats)
  2428. queue->card->perf_stats.sc_p_dp++;
  2429. queue->do_pack = 0;
  2430. /* flush packing buffers */
  2431. buffer = &queue->bufs[queue->next_buf_to_fill];
  2432. if ((atomic_read(&buffer->state) ==
  2433. QETH_QDIO_BUF_EMPTY) &&
  2434. (buffer->next_element_to_fill > 0)) {
  2435. atomic_set(&buffer->state,
  2436. QETH_QDIO_BUF_PRIMED);
  2437. flush_count++;
  2438. queue->next_buf_to_fill =
  2439. (queue->next_buf_to_fill + 1) %
  2440. QDIO_MAX_BUFFERS_PER_Q;
  2441. }
  2442. }
  2443. }
  2444. return flush_count;
  2445. }
  2446. /*
  2447. * Called to flush a packing buffer if no more pci flags are on the queue.
  2448. * Checks if there is a packing buffer and prepares it to be flushed.
  2449. * In that case returns 1, otherwise zero.
  2450. */
  2451. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2452. {
  2453. struct qeth_qdio_out_buffer *buffer;
  2454. buffer = &queue->bufs[queue->next_buf_to_fill];
  2455. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2456. (buffer->next_element_to_fill > 0)) {
  2457. /* it's a packing buffer */
  2458. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2459. queue->next_buf_to_fill =
  2460. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2461. return 1;
  2462. }
  2463. return 0;
  2464. }
  2465. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2466. int count)
  2467. {
  2468. struct qeth_qdio_out_buffer *buf;
  2469. int rc;
  2470. int i;
  2471. unsigned int qdio_flags;
  2472. for (i = index; i < index + count; ++i) {
  2473. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2474. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2475. SBAL_FLAGS_LAST_ENTRY;
  2476. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2477. continue;
  2478. if (!queue->do_pack) {
  2479. if ((atomic_read(&queue->used_buffers) >=
  2480. (QETH_HIGH_WATERMARK_PACK -
  2481. QETH_WATERMARK_PACK_FUZZ)) &&
  2482. !atomic_read(&queue->set_pci_flags_count)) {
  2483. /* it's likely that we'll go to packing
  2484. * mode soon */
  2485. atomic_inc(&queue->set_pci_flags_count);
  2486. buf->buffer->element[0].flags |= 0x40;
  2487. }
  2488. } else {
  2489. if (!atomic_read(&queue->set_pci_flags_count)) {
  2490. /*
  2491. * there's no outstanding PCI any more, so we
  2492. * have to request a PCI to be sure the the PCI
  2493. * will wake at some time in the future then we
  2494. * can flush packed buffers that might still be
  2495. * hanging around, which can happen if no
  2496. * further send was requested by the stack
  2497. */
  2498. atomic_inc(&queue->set_pci_flags_count);
  2499. buf->buffer->element[0].flags |= 0x40;
  2500. }
  2501. }
  2502. }
  2503. queue->card->dev->trans_start = jiffies;
  2504. if (queue->card->options.performance_stats) {
  2505. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2506. queue->card->perf_stats.outbound_do_qdio_start_time =
  2507. qeth_get_micros();
  2508. }
  2509. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2510. if (atomic_read(&queue->set_pci_flags_count))
  2511. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2512. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2513. queue->queue_no, index, count);
  2514. if (queue->card->options.performance_stats)
  2515. queue->card->perf_stats.outbound_do_qdio_time +=
  2516. qeth_get_micros() -
  2517. queue->card->perf_stats.outbound_do_qdio_start_time;
  2518. if (rc) {
  2519. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2520. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2521. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2522. queue->card->stats.tx_errors += count;
  2523. /* this must not happen under normal circumstances. if it
  2524. * happens something is really wrong -> recover */
  2525. qeth_schedule_recovery(queue->card);
  2526. return;
  2527. }
  2528. atomic_add(count, &queue->used_buffers);
  2529. if (queue->card->options.performance_stats)
  2530. queue->card->perf_stats.bufs_sent += count;
  2531. }
  2532. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2533. {
  2534. int index;
  2535. int flush_cnt = 0;
  2536. int q_was_packing = 0;
  2537. /*
  2538. * check if weed have to switch to non-packing mode or if
  2539. * we have to get a pci flag out on the queue
  2540. */
  2541. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2542. !atomic_read(&queue->set_pci_flags_count)) {
  2543. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2544. QETH_OUT_Q_UNLOCKED) {
  2545. /*
  2546. * If we get in here, there was no action in
  2547. * do_send_packet. So, we check if there is a
  2548. * packing buffer to be flushed here.
  2549. */
  2550. netif_stop_queue(queue->card->dev);
  2551. index = queue->next_buf_to_fill;
  2552. q_was_packing = queue->do_pack;
  2553. /* queue->do_pack may change */
  2554. barrier();
  2555. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2556. if (!flush_cnt &&
  2557. !atomic_read(&queue->set_pci_flags_count))
  2558. flush_cnt +=
  2559. qeth_flush_buffers_on_no_pci(queue);
  2560. if (queue->card->options.performance_stats &&
  2561. q_was_packing)
  2562. queue->card->perf_stats.bufs_sent_pack +=
  2563. flush_cnt;
  2564. if (flush_cnt)
  2565. qeth_flush_buffers(queue, index, flush_cnt);
  2566. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2567. }
  2568. }
  2569. }
  2570. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2571. unsigned int qdio_error, int __queue, int first_element,
  2572. int count, unsigned long card_ptr)
  2573. {
  2574. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2575. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2576. struct qeth_qdio_out_buffer *buffer;
  2577. int i;
  2578. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2579. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2580. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2581. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2582. netif_stop_queue(card->dev);
  2583. qeth_schedule_recovery(card);
  2584. return;
  2585. }
  2586. if (card->options.performance_stats) {
  2587. card->perf_stats.outbound_handler_cnt++;
  2588. card->perf_stats.outbound_handler_start_time =
  2589. qeth_get_micros();
  2590. }
  2591. for (i = first_element; i < (first_element + count); ++i) {
  2592. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2593. /*we only handle the KICK_IT error by doing a recovery */
  2594. if (qeth_handle_send_error(card, buffer, qdio_error)
  2595. == QETH_SEND_ERROR_KICK_IT){
  2596. netif_stop_queue(card->dev);
  2597. qeth_schedule_recovery(card);
  2598. return;
  2599. }
  2600. qeth_clear_output_buffer(queue, buffer);
  2601. }
  2602. atomic_sub(count, &queue->used_buffers);
  2603. /* check if we need to do something on this outbound queue */
  2604. if (card->info.type != QETH_CARD_TYPE_IQD)
  2605. qeth_check_outbound_queue(queue);
  2606. netif_wake_queue(queue->card->dev);
  2607. if (card->options.performance_stats)
  2608. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2609. card->perf_stats.outbound_handler_start_time;
  2610. }
  2611. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2612. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2613. {
  2614. int cast_type = RTN_UNSPEC;
  2615. if (card->info.type == QETH_CARD_TYPE_OSN)
  2616. return cast_type;
  2617. if (skb->dst && skb->dst->neighbour) {
  2618. cast_type = skb->dst->neighbour->type;
  2619. if ((cast_type == RTN_BROADCAST) ||
  2620. (cast_type == RTN_MULTICAST) ||
  2621. (cast_type == RTN_ANYCAST))
  2622. return cast_type;
  2623. else
  2624. return RTN_UNSPEC;
  2625. }
  2626. /* try something else */
  2627. if (skb->protocol == ETH_P_IPV6)
  2628. return (skb_network_header(skb)[24] == 0xff) ?
  2629. RTN_MULTICAST : 0;
  2630. else if (skb->protocol == ETH_P_IP)
  2631. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2632. RTN_MULTICAST : 0;
  2633. /* ... */
  2634. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2635. return RTN_BROADCAST;
  2636. else {
  2637. u16 hdr_mac;
  2638. hdr_mac = *((u16 *)skb->data);
  2639. /* tr multicast? */
  2640. switch (card->info.link_type) {
  2641. case QETH_LINK_TYPE_HSTR:
  2642. case QETH_LINK_TYPE_LANE_TR:
  2643. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2644. (hdr_mac == QETH_TR_MAC_C))
  2645. return RTN_MULTICAST;
  2646. break;
  2647. /* eth or so multicast? */
  2648. default:
  2649. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2650. (hdr_mac == QETH_ETH_MAC_V6))
  2651. return RTN_MULTICAST;
  2652. }
  2653. }
  2654. return cast_type;
  2655. }
  2656. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2657. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2658. int ipv, int cast_type)
  2659. {
  2660. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2661. return card->qdio.default_out_queue;
  2662. switch (card->qdio.no_out_queues) {
  2663. case 4:
  2664. if (cast_type && card->info.is_multicast_different)
  2665. return card->info.is_multicast_different &
  2666. (card->qdio.no_out_queues - 1);
  2667. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2668. const u8 tos = ip_hdr(skb)->tos;
  2669. if (card->qdio.do_prio_queueing ==
  2670. QETH_PRIO_Q_ING_TOS) {
  2671. if (tos & IP_TOS_NOTIMPORTANT)
  2672. return 3;
  2673. if (tos & IP_TOS_HIGHRELIABILITY)
  2674. return 2;
  2675. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2676. return 1;
  2677. if (tos & IP_TOS_LOWDELAY)
  2678. return 0;
  2679. }
  2680. if (card->qdio.do_prio_queueing ==
  2681. QETH_PRIO_Q_ING_PREC)
  2682. return 3 - (tos >> 6);
  2683. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2684. /* TODO: IPv6!!! */
  2685. }
  2686. return card->qdio.default_out_queue;
  2687. case 1: /* fallthrough for single-out-queue 1920-device */
  2688. default:
  2689. return card->qdio.default_out_queue;
  2690. }
  2691. }
  2692. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2693. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2694. struct sk_buff *skb, int elems)
  2695. {
  2696. int elements_needed = 0;
  2697. if (skb_shinfo(skb)->nr_frags > 0)
  2698. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2699. if (elements_needed == 0)
  2700. elements_needed = 1 + (((((unsigned long) hdr) % PAGE_SIZE)
  2701. + skb->len) >> PAGE_SHIFT);
  2702. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2703. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2704. "(Number=%d / Length=%d). Discarded.\n",
  2705. (elements_needed+elems), skb->len);
  2706. return 0;
  2707. }
  2708. return elements_needed;
  2709. }
  2710. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2711. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2712. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill)
  2713. {
  2714. int length = skb->len;
  2715. int length_here;
  2716. int element;
  2717. char *data;
  2718. int first_lap ;
  2719. element = *next_element_to_fill;
  2720. data = skb->data;
  2721. first_lap = (is_tso == 0 ? 1 : 0);
  2722. while (length > 0) {
  2723. /* length_here is the remaining amount of data in this page */
  2724. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2725. if (length < length_here)
  2726. length_here = length;
  2727. buffer->element[element].addr = data;
  2728. buffer->element[element].length = length_here;
  2729. length -= length_here;
  2730. if (!length) {
  2731. if (first_lap)
  2732. buffer->element[element].flags = 0;
  2733. else
  2734. buffer->element[element].flags =
  2735. SBAL_FLAGS_LAST_FRAG;
  2736. } else {
  2737. if (first_lap)
  2738. buffer->element[element].flags =
  2739. SBAL_FLAGS_FIRST_FRAG;
  2740. else
  2741. buffer->element[element].flags =
  2742. SBAL_FLAGS_MIDDLE_FRAG;
  2743. }
  2744. data += length_here;
  2745. element++;
  2746. first_lap = 0;
  2747. }
  2748. *next_element_to_fill = element;
  2749. }
  2750. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2751. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb)
  2752. {
  2753. struct qdio_buffer *buffer;
  2754. struct qeth_hdr_tso *hdr;
  2755. int flush_cnt = 0, hdr_len, large_send = 0;
  2756. buffer = buf->buffer;
  2757. atomic_inc(&skb->users);
  2758. skb_queue_tail(&buf->skb_list, skb);
  2759. hdr = (struct qeth_hdr_tso *) skb->data;
  2760. /*check first on TSO ....*/
  2761. if (hdr->hdr.hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2762. int element = buf->next_element_to_fill;
  2763. hdr_len = sizeof(struct qeth_hdr_tso) + hdr->ext.dg_hdr_len;
  2764. /*fill first buffer entry only with header information */
  2765. buffer->element[element].addr = skb->data;
  2766. buffer->element[element].length = hdr_len;
  2767. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2768. buf->next_element_to_fill++;
  2769. skb->data += hdr_len;
  2770. skb->len -= hdr_len;
  2771. large_send = 1;
  2772. }
  2773. if (skb_shinfo(skb)->nr_frags == 0)
  2774. __qeth_fill_buffer(skb, buffer, large_send,
  2775. (int *)&buf->next_element_to_fill);
  2776. else
  2777. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2778. (int *)&buf->next_element_to_fill);
  2779. if (!queue->do_pack) {
  2780. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2781. /* set state to PRIMED -> will be flushed */
  2782. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2783. flush_cnt = 1;
  2784. } else {
  2785. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2786. if (queue->card->options.performance_stats)
  2787. queue->card->perf_stats.skbs_sent_pack++;
  2788. if (buf->next_element_to_fill >=
  2789. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2790. /*
  2791. * packed buffer if full -> set state PRIMED
  2792. * -> will be flushed
  2793. */
  2794. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2795. flush_cnt = 1;
  2796. }
  2797. }
  2798. return flush_cnt;
  2799. }
  2800. int qeth_do_send_packet_fast(struct qeth_card *card,
  2801. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2802. struct qeth_hdr *hdr, int elements_needed,
  2803. struct qeth_eddp_context *ctx)
  2804. {
  2805. struct qeth_qdio_out_buffer *buffer;
  2806. int buffers_needed = 0;
  2807. int flush_cnt = 0;
  2808. int index;
  2809. /* spin until we get the queue ... */
  2810. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2811. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2812. /* ... now we've got the queue */
  2813. index = queue->next_buf_to_fill;
  2814. buffer = &queue->bufs[queue->next_buf_to_fill];
  2815. /*
  2816. * check if buffer is empty to make sure that we do not 'overtake'
  2817. * ourselves and try to fill a buffer that is already primed
  2818. */
  2819. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2820. goto out;
  2821. if (ctx == NULL)
  2822. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2823. QDIO_MAX_BUFFERS_PER_Q;
  2824. else {
  2825. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2826. ctx);
  2827. if (buffers_needed < 0)
  2828. goto out;
  2829. queue->next_buf_to_fill =
  2830. (queue->next_buf_to_fill + buffers_needed) %
  2831. QDIO_MAX_BUFFERS_PER_Q;
  2832. }
  2833. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2834. if (ctx == NULL) {
  2835. qeth_fill_buffer(queue, buffer, skb);
  2836. qeth_flush_buffers(queue, index, 1);
  2837. } else {
  2838. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2839. WARN_ON(buffers_needed != flush_cnt);
  2840. qeth_flush_buffers(queue, index, flush_cnt);
  2841. }
  2842. return 0;
  2843. out:
  2844. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2845. return -EBUSY;
  2846. }
  2847. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2848. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2849. struct sk_buff *skb, struct qeth_hdr *hdr,
  2850. int elements_needed, struct qeth_eddp_context *ctx)
  2851. {
  2852. struct qeth_qdio_out_buffer *buffer;
  2853. int start_index;
  2854. int flush_count = 0;
  2855. int do_pack = 0;
  2856. int tmp;
  2857. int rc = 0;
  2858. /* spin until we get the queue ... */
  2859. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2860. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2861. start_index = queue->next_buf_to_fill;
  2862. buffer = &queue->bufs[queue->next_buf_to_fill];
  2863. /*
  2864. * check if buffer is empty to make sure that we do not 'overtake'
  2865. * ourselves and try to fill a buffer that is already primed
  2866. */
  2867. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2868. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2869. return -EBUSY;
  2870. }
  2871. /* check if we need to switch packing state of this queue */
  2872. qeth_switch_to_packing_if_needed(queue);
  2873. if (queue->do_pack) {
  2874. do_pack = 1;
  2875. if (ctx == NULL) {
  2876. /* does packet fit in current buffer? */
  2877. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2878. buffer->next_element_to_fill) < elements_needed) {
  2879. /* ... no -> set state PRIMED */
  2880. atomic_set(&buffer->state,
  2881. QETH_QDIO_BUF_PRIMED);
  2882. flush_count++;
  2883. queue->next_buf_to_fill =
  2884. (queue->next_buf_to_fill + 1) %
  2885. QDIO_MAX_BUFFERS_PER_Q;
  2886. buffer = &queue->bufs[queue->next_buf_to_fill];
  2887. /* we did a step forward, so check buffer state
  2888. * again */
  2889. if (atomic_read(&buffer->state) !=
  2890. QETH_QDIO_BUF_EMPTY){
  2891. qeth_flush_buffers(queue, start_index,
  2892. flush_count);
  2893. atomic_set(&queue->state,
  2894. QETH_OUT_Q_UNLOCKED);
  2895. return -EBUSY;
  2896. }
  2897. }
  2898. } else {
  2899. /* check if we have enough elements (including following
  2900. * free buffers) to handle eddp context */
  2901. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2902. < 0) {
  2903. rc = -EBUSY;
  2904. goto out;
  2905. }
  2906. }
  2907. }
  2908. if (ctx == NULL)
  2909. tmp = qeth_fill_buffer(queue, buffer, skb);
  2910. else {
  2911. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2912. queue->next_buf_to_fill);
  2913. if (tmp < 0) {
  2914. rc = -EBUSY;
  2915. goto out;
  2916. }
  2917. }
  2918. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2919. QDIO_MAX_BUFFERS_PER_Q;
  2920. flush_count += tmp;
  2921. out:
  2922. if (flush_count)
  2923. qeth_flush_buffers(queue, start_index, flush_count);
  2924. else if (!atomic_read(&queue->set_pci_flags_count))
  2925. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2926. /*
  2927. * queue->state will go from LOCKED -> UNLOCKED or from
  2928. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2929. * (switch packing state or flush buffer to get another pci flag out).
  2930. * In that case we will enter this loop
  2931. */
  2932. while (atomic_dec_return(&queue->state)) {
  2933. flush_count = 0;
  2934. start_index = queue->next_buf_to_fill;
  2935. /* check if we can go back to non-packing state */
  2936. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2937. /*
  2938. * check if we need to flush a packing buffer to get a pci
  2939. * flag out on the queue
  2940. */
  2941. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2942. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2943. if (flush_count)
  2944. qeth_flush_buffers(queue, start_index, flush_count);
  2945. }
  2946. /* at this point the queue is UNLOCKED again */
  2947. if (queue->card->options.performance_stats && do_pack)
  2948. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2949. return rc;
  2950. }
  2951. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2952. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2953. struct qeth_reply *reply, unsigned long data)
  2954. {
  2955. struct qeth_ipa_cmd *cmd;
  2956. struct qeth_ipacmd_setadpparms *setparms;
  2957. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2958. cmd = (struct qeth_ipa_cmd *) data;
  2959. setparms = &(cmd->data.setadapterparms);
  2960. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2961. if (cmd->hdr.return_code) {
  2962. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2963. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2964. }
  2965. card->info.promisc_mode = setparms->data.mode;
  2966. return 0;
  2967. }
  2968. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2969. {
  2970. enum qeth_ipa_promisc_modes mode;
  2971. struct net_device *dev = card->dev;
  2972. struct qeth_cmd_buffer *iob;
  2973. struct qeth_ipa_cmd *cmd;
  2974. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2975. if (((dev->flags & IFF_PROMISC) &&
  2976. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2977. (!(dev->flags & IFF_PROMISC) &&
  2978. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2979. return;
  2980. mode = SET_PROMISC_MODE_OFF;
  2981. if (dev->flags & IFF_PROMISC)
  2982. mode = SET_PROMISC_MODE_ON;
  2983. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2984. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2985. sizeof(struct qeth_ipacmd_setadpparms));
  2986. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2987. cmd->data.setadapterparms.data.mode = mode;
  2988. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2989. }
  2990. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2991. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2992. {
  2993. struct qeth_card *card;
  2994. char dbf_text[15];
  2995. card = netdev_priv(dev);
  2996. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2997. sprintf(dbf_text, "%8x", new_mtu);
  2998. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2999. if (new_mtu < 64)
  3000. return -EINVAL;
  3001. if (new_mtu > 65535)
  3002. return -EINVAL;
  3003. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3004. (!qeth_mtu_is_valid(card, new_mtu)))
  3005. return -EINVAL;
  3006. dev->mtu = new_mtu;
  3007. return 0;
  3008. }
  3009. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3010. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3011. {
  3012. struct qeth_card *card;
  3013. card = netdev_priv(dev);
  3014. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3015. return &card->stats;
  3016. }
  3017. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3018. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3019. struct qeth_reply *reply, unsigned long data)
  3020. {
  3021. struct qeth_ipa_cmd *cmd;
  3022. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3023. cmd = (struct qeth_ipa_cmd *) data;
  3024. if (!card->options.layer2 ||
  3025. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3026. memcpy(card->dev->dev_addr,
  3027. &cmd->data.setadapterparms.data.change_addr.addr,
  3028. OSA_ADDR_LEN);
  3029. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3030. }
  3031. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3032. return 0;
  3033. }
  3034. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3035. {
  3036. int rc;
  3037. struct qeth_cmd_buffer *iob;
  3038. struct qeth_ipa_cmd *cmd;
  3039. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3040. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3041. sizeof(struct qeth_ipacmd_setadpparms));
  3042. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3043. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3044. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3045. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3046. card->dev->dev_addr, OSA_ADDR_LEN);
  3047. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3048. NULL);
  3049. return rc;
  3050. }
  3051. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3052. void qeth_tx_timeout(struct net_device *dev)
  3053. {
  3054. struct qeth_card *card;
  3055. card = netdev_priv(dev);
  3056. card->stats.tx_errors++;
  3057. qeth_schedule_recovery(card);
  3058. }
  3059. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3060. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3061. {
  3062. struct qeth_card *card = netdev_priv(dev);
  3063. int rc = 0;
  3064. switch (regnum) {
  3065. case MII_BMCR: /* Basic mode control register */
  3066. rc = BMCR_FULLDPLX;
  3067. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3068. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3069. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3070. rc |= BMCR_SPEED100;
  3071. break;
  3072. case MII_BMSR: /* Basic mode status register */
  3073. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3074. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3075. BMSR_100BASE4;
  3076. break;
  3077. case MII_PHYSID1: /* PHYS ID 1 */
  3078. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3079. dev->dev_addr[2];
  3080. rc = (rc >> 5) & 0xFFFF;
  3081. break;
  3082. case MII_PHYSID2: /* PHYS ID 2 */
  3083. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3084. break;
  3085. case MII_ADVERTISE: /* Advertisement control reg */
  3086. rc = ADVERTISE_ALL;
  3087. break;
  3088. case MII_LPA: /* Link partner ability reg */
  3089. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3090. LPA_100BASE4 | LPA_LPACK;
  3091. break;
  3092. case MII_EXPANSION: /* Expansion register */
  3093. break;
  3094. case MII_DCOUNTER: /* disconnect counter */
  3095. break;
  3096. case MII_FCSCOUNTER: /* false carrier counter */
  3097. break;
  3098. case MII_NWAYTEST: /* N-way auto-neg test register */
  3099. break;
  3100. case MII_RERRCOUNTER: /* rx error counter */
  3101. rc = card->stats.rx_errors;
  3102. break;
  3103. case MII_SREVISION: /* silicon revision */
  3104. break;
  3105. case MII_RESV1: /* reserved 1 */
  3106. break;
  3107. case MII_LBRERROR: /* loopback, rx, bypass error */
  3108. break;
  3109. case MII_PHYADDR: /* physical address */
  3110. break;
  3111. case MII_RESV2: /* reserved 2 */
  3112. break;
  3113. case MII_TPISTATUS: /* TPI status for 10mbps */
  3114. break;
  3115. case MII_NCONFIG: /* network interface config */
  3116. break;
  3117. default:
  3118. break;
  3119. }
  3120. return rc;
  3121. }
  3122. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3123. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3124. struct qeth_cmd_buffer *iob, int len,
  3125. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3126. unsigned long),
  3127. void *reply_param)
  3128. {
  3129. u16 s1, s2;
  3130. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3131. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3132. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3133. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3134. /* adjust PDU length fields in IPA_PDU_HEADER */
  3135. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3136. s2 = (u32) len;
  3137. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3138. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3139. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3140. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3141. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3142. reply_cb, reply_param);
  3143. }
  3144. static int qeth_snmp_command_cb(struct qeth_card *card,
  3145. struct qeth_reply *reply, unsigned long sdata)
  3146. {
  3147. struct qeth_ipa_cmd *cmd;
  3148. struct qeth_arp_query_info *qinfo;
  3149. struct qeth_snmp_cmd *snmp;
  3150. unsigned char *data;
  3151. __u16 data_len;
  3152. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3153. cmd = (struct qeth_ipa_cmd *) sdata;
  3154. data = (unsigned char *)((char *)cmd - reply->offset);
  3155. qinfo = (struct qeth_arp_query_info *) reply->param;
  3156. snmp = &cmd->data.setadapterparms.data.snmp;
  3157. if (cmd->hdr.return_code) {
  3158. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3159. return 0;
  3160. }
  3161. if (cmd->data.setadapterparms.hdr.return_code) {
  3162. cmd->hdr.return_code =
  3163. cmd->data.setadapterparms.hdr.return_code;
  3164. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3165. return 0;
  3166. }
  3167. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3168. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3169. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3170. else
  3171. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3172. /* check if there is enough room in userspace */
  3173. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3174. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3175. cmd->hdr.return_code = -ENOMEM;
  3176. return 0;
  3177. }
  3178. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3179. cmd->data.setadapterparms.hdr.used_total);
  3180. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3181. cmd->data.setadapterparms.hdr.seq_no);
  3182. /*copy entries to user buffer*/
  3183. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3184. memcpy(qinfo->udata + qinfo->udata_offset,
  3185. (char *)snmp,
  3186. data_len + offsetof(struct qeth_snmp_cmd, data));
  3187. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3188. } else {
  3189. memcpy(qinfo->udata + qinfo->udata_offset,
  3190. (char *)&snmp->request, data_len);
  3191. }
  3192. qinfo->udata_offset += data_len;
  3193. /* check if all replies received ... */
  3194. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3195. cmd->data.setadapterparms.hdr.used_total);
  3196. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3197. cmd->data.setadapterparms.hdr.seq_no);
  3198. if (cmd->data.setadapterparms.hdr.seq_no <
  3199. cmd->data.setadapterparms.hdr.used_total)
  3200. return 1;
  3201. return 0;
  3202. }
  3203. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3204. {
  3205. struct qeth_cmd_buffer *iob;
  3206. struct qeth_ipa_cmd *cmd;
  3207. struct qeth_snmp_ureq *ureq;
  3208. int req_len;
  3209. struct qeth_arp_query_info qinfo = {0, };
  3210. int rc = 0;
  3211. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3212. if (card->info.guestlan)
  3213. return -EOPNOTSUPP;
  3214. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3215. (!card->options.layer2)) {
  3216. return -EOPNOTSUPP;
  3217. }
  3218. /* skip 4 bytes (data_len struct member) to get req_len */
  3219. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3220. return -EFAULT;
  3221. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3222. if (!ureq) {
  3223. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3224. return -ENOMEM;
  3225. }
  3226. if (copy_from_user(ureq, udata,
  3227. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3228. kfree(ureq);
  3229. return -EFAULT;
  3230. }
  3231. qinfo.udata_len = ureq->hdr.data_len;
  3232. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3233. if (!qinfo.udata) {
  3234. kfree(ureq);
  3235. return -ENOMEM;
  3236. }
  3237. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3238. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3239. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3240. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3241. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3242. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3243. qeth_snmp_command_cb, (void *)&qinfo);
  3244. if (rc)
  3245. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3246. QETH_CARD_IFNAME(card), rc);
  3247. else {
  3248. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3249. rc = -EFAULT;
  3250. }
  3251. kfree(ureq);
  3252. kfree(qinfo.udata);
  3253. return rc;
  3254. }
  3255. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3256. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3257. {
  3258. switch (card->info.type) {
  3259. case QETH_CARD_TYPE_IQD:
  3260. return 2;
  3261. default:
  3262. return 0;
  3263. }
  3264. }
  3265. static int qeth_qdio_establish(struct qeth_card *card)
  3266. {
  3267. struct qdio_initialize init_data;
  3268. char *qib_param_field;
  3269. struct qdio_buffer **in_sbal_ptrs;
  3270. struct qdio_buffer **out_sbal_ptrs;
  3271. int i, j, k;
  3272. int rc = 0;
  3273. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3274. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3275. GFP_KERNEL);
  3276. if (!qib_param_field)
  3277. return -ENOMEM;
  3278. qeth_create_qib_param_field(card, qib_param_field);
  3279. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3280. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3281. GFP_KERNEL);
  3282. if (!in_sbal_ptrs) {
  3283. kfree(qib_param_field);
  3284. return -ENOMEM;
  3285. }
  3286. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3287. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3288. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3289. out_sbal_ptrs =
  3290. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3291. sizeof(void *), GFP_KERNEL);
  3292. if (!out_sbal_ptrs) {
  3293. kfree(in_sbal_ptrs);
  3294. kfree(qib_param_field);
  3295. return -ENOMEM;
  3296. }
  3297. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3298. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3299. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3300. card->qdio.out_qs[i]->bufs[j].buffer);
  3301. }
  3302. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3303. init_data.cdev = CARD_DDEV(card);
  3304. init_data.q_format = qeth_get_qdio_q_format(card);
  3305. init_data.qib_param_field_format = 0;
  3306. init_data.qib_param_field = qib_param_field;
  3307. init_data.no_input_qs = 1;
  3308. init_data.no_output_qs = card->qdio.no_out_queues;
  3309. init_data.input_handler = card->discipline.input_handler;
  3310. init_data.output_handler = card->discipline.output_handler;
  3311. init_data.int_parm = (unsigned long) card;
  3312. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3313. QDIO_OUTBOUND_0COPY_SBALS |
  3314. QDIO_USE_OUTBOUND_PCIS;
  3315. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3316. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3317. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3318. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3319. rc = qdio_initialize(&init_data);
  3320. if (rc)
  3321. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3322. }
  3323. kfree(out_sbal_ptrs);
  3324. kfree(in_sbal_ptrs);
  3325. kfree(qib_param_field);
  3326. return rc;
  3327. }
  3328. static void qeth_core_free_card(struct qeth_card *card)
  3329. {
  3330. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3331. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3332. qeth_clean_channel(&card->read);
  3333. qeth_clean_channel(&card->write);
  3334. if (card->dev)
  3335. free_netdev(card->dev);
  3336. kfree(card->ip_tbd_list);
  3337. qeth_free_qdio_buffers(card);
  3338. kfree(card);
  3339. }
  3340. static struct ccw_device_id qeth_ids[] = {
  3341. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3342. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3343. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3344. {},
  3345. };
  3346. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3347. static struct ccw_driver qeth_ccw_driver = {
  3348. .name = "qeth",
  3349. .ids = qeth_ids,
  3350. .probe = ccwgroup_probe_ccwdev,
  3351. .remove = ccwgroup_remove_ccwdev,
  3352. };
  3353. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3354. unsigned long driver_id)
  3355. {
  3356. return ccwgroup_create_from_string(root_dev, driver_id,
  3357. &qeth_ccw_driver, 3, buf);
  3358. }
  3359. int qeth_core_hardsetup_card(struct qeth_card *card)
  3360. {
  3361. struct qdio_ssqd_desc *qdio_ssqd;
  3362. int retries = 3;
  3363. int mpno = 0;
  3364. int rc;
  3365. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3366. atomic_set(&card->force_alloc_skb, 0);
  3367. retry:
  3368. if (retries < 3) {
  3369. PRINT_WARN("Retrying to do IDX activates.\n");
  3370. ccw_device_set_offline(CARD_DDEV(card));
  3371. ccw_device_set_offline(CARD_WDEV(card));
  3372. ccw_device_set_offline(CARD_RDEV(card));
  3373. ccw_device_set_online(CARD_RDEV(card));
  3374. ccw_device_set_online(CARD_WDEV(card));
  3375. ccw_device_set_online(CARD_DDEV(card));
  3376. }
  3377. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3378. if (rc == -ERESTARTSYS) {
  3379. QETH_DBF_TEXT(SETUP, 2, "break1");
  3380. return rc;
  3381. } else if (rc) {
  3382. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3383. if (--retries < 0)
  3384. goto out;
  3385. else
  3386. goto retry;
  3387. }
  3388. rc = qeth_get_unitaddr(card);
  3389. if (rc) {
  3390. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3391. return rc;
  3392. }
  3393. qdio_ssqd = qdio_get_ssqd_desc(CARD_DDEV(card));
  3394. if (qdio_ssqd)
  3395. mpno = qdio_ssqd->pcnt;
  3396. if (mpno)
  3397. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3398. if (card->info.portno > mpno) {
  3399. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3400. "\n.", CARD_BUS_ID(card), card->info.portno);
  3401. rc = -ENODEV;
  3402. goto out;
  3403. }
  3404. qeth_init_tokens(card);
  3405. qeth_init_func_level(card);
  3406. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3407. if (rc == -ERESTARTSYS) {
  3408. QETH_DBF_TEXT(SETUP, 2, "break2");
  3409. return rc;
  3410. } else if (rc) {
  3411. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3412. if (--retries < 0)
  3413. goto out;
  3414. else
  3415. goto retry;
  3416. }
  3417. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3418. if (rc == -ERESTARTSYS) {
  3419. QETH_DBF_TEXT(SETUP, 2, "break3");
  3420. return rc;
  3421. } else if (rc) {
  3422. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3423. if (--retries < 0)
  3424. goto out;
  3425. else
  3426. goto retry;
  3427. }
  3428. rc = qeth_mpc_initialize(card);
  3429. if (rc) {
  3430. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3431. goto out;
  3432. }
  3433. return 0;
  3434. out:
  3435. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3436. return rc;
  3437. }
  3438. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3439. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3440. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3441. {
  3442. struct page *page = virt_to_page(element->addr);
  3443. if (*pskb == NULL) {
  3444. /* the upper protocol layers assume that there is data in the
  3445. * skb itself. Copy a small amount (64 bytes) to make them
  3446. * happy. */
  3447. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3448. if (!(*pskb))
  3449. return -ENOMEM;
  3450. skb_reserve(*pskb, ETH_HLEN);
  3451. if (data_len <= 64) {
  3452. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3453. data_len);
  3454. } else {
  3455. get_page(page);
  3456. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3457. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3458. data_len - 64);
  3459. (*pskb)->data_len += data_len - 64;
  3460. (*pskb)->len += data_len - 64;
  3461. (*pskb)->truesize += data_len - 64;
  3462. (*pfrag)++;
  3463. }
  3464. } else {
  3465. get_page(page);
  3466. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3467. (*pskb)->data_len += data_len;
  3468. (*pskb)->len += data_len;
  3469. (*pskb)->truesize += data_len;
  3470. (*pfrag)++;
  3471. }
  3472. return 0;
  3473. }
  3474. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3475. struct qdio_buffer *buffer,
  3476. struct qdio_buffer_element **__element, int *__offset,
  3477. struct qeth_hdr **hdr)
  3478. {
  3479. struct qdio_buffer_element *element = *__element;
  3480. int offset = *__offset;
  3481. struct sk_buff *skb = NULL;
  3482. int skb_len;
  3483. void *data_ptr;
  3484. int data_len;
  3485. int headroom = 0;
  3486. int use_rx_sg = 0;
  3487. int frag = 0;
  3488. /* qeth_hdr must not cross element boundaries */
  3489. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3490. if (qeth_is_last_sbale(element))
  3491. return NULL;
  3492. element++;
  3493. offset = 0;
  3494. if (element->length < sizeof(struct qeth_hdr))
  3495. return NULL;
  3496. }
  3497. *hdr = element->addr + offset;
  3498. offset += sizeof(struct qeth_hdr);
  3499. if (card->options.layer2) {
  3500. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3501. skb_len = (*hdr)->hdr.osn.pdu_length;
  3502. headroom = sizeof(struct qeth_hdr);
  3503. } else {
  3504. skb_len = (*hdr)->hdr.l2.pkt_length;
  3505. }
  3506. } else {
  3507. skb_len = (*hdr)->hdr.l3.length;
  3508. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3509. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3510. headroom = TR_HLEN;
  3511. else
  3512. headroom = ETH_HLEN;
  3513. }
  3514. if (!skb_len)
  3515. return NULL;
  3516. if ((skb_len >= card->options.rx_sg_cb) &&
  3517. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3518. (!atomic_read(&card->force_alloc_skb))) {
  3519. use_rx_sg = 1;
  3520. } else {
  3521. skb = dev_alloc_skb(skb_len + headroom);
  3522. if (!skb)
  3523. goto no_mem;
  3524. if (headroom)
  3525. skb_reserve(skb, headroom);
  3526. }
  3527. data_ptr = element->addr + offset;
  3528. while (skb_len) {
  3529. data_len = min(skb_len, (int)(element->length - offset));
  3530. if (data_len) {
  3531. if (use_rx_sg) {
  3532. if (qeth_create_skb_frag(element, &skb, offset,
  3533. &frag, data_len))
  3534. goto no_mem;
  3535. } else {
  3536. memcpy(skb_put(skb, data_len), data_ptr,
  3537. data_len);
  3538. }
  3539. }
  3540. skb_len -= data_len;
  3541. if (skb_len) {
  3542. if (qeth_is_last_sbale(element)) {
  3543. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3544. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3545. CARD_BUS_ID(card));
  3546. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3547. QETH_DBF_TEXT_(QERR, 2, "%s",
  3548. CARD_BUS_ID(card));
  3549. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3550. dev_kfree_skb_any(skb);
  3551. card->stats.rx_errors++;
  3552. return NULL;
  3553. }
  3554. element++;
  3555. offset = 0;
  3556. data_ptr = element->addr;
  3557. } else {
  3558. offset += data_len;
  3559. }
  3560. }
  3561. *__element = element;
  3562. *__offset = offset;
  3563. if (use_rx_sg && card->options.performance_stats) {
  3564. card->perf_stats.sg_skbs_rx++;
  3565. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3566. }
  3567. return skb;
  3568. no_mem:
  3569. if (net_ratelimit()) {
  3570. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3571. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3572. }
  3573. card->stats.rx_dropped++;
  3574. return NULL;
  3575. }
  3576. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3577. static void qeth_unregister_dbf_views(void)
  3578. {
  3579. int x;
  3580. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3581. debug_unregister(qeth_dbf[x].id);
  3582. qeth_dbf[x].id = NULL;
  3583. }
  3584. }
  3585. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3586. {
  3587. char dbf_txt_buf[32];
  3588. va_list args;
  3589. if (level > (qeth_dbf[dbf_nix].id)->level)
  3590. return;
  3591. va_start(args, fmt);
  3592. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3593. va_end(args);
  3594. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3595. }
  3596. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3597. static int qeth_register_dbf_views(void)
  3598. {
  3599. int ret;
  3600. int x;
  3601. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3602. /* register the areas */
  3603. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3604. qeth_dbf[x].pages,
  3605. qeth_dbf[x].areas,
  3606. qeth_dbf[x].len);
  3607. if (qeth_dbf[x].id == NULL) {
  3608. qeth_unregister_dbf_views();
  3609. return -ENOMEM;
  3610. }
  3611. /* register a view */
  3612. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3613. if (ret) {
  3614. qeth_unregister_dbf_views();
  3615. return ret;
  3616. }
  3617. /* set a passing level */
  3618. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3619. }
  3620. return 0;
  3621. }
  3622. int qeth_core_load_discipline(struct qeth_card *card,
  3623. enum qeth_discipline_id discipline)
  3624. {
  3625. int rc = 0;
  3626. switch (discipline) {
  3627. case QETH_DISCIPLINE_LAYER3:
  3628. card->discipline.ccwgdriver = try_then_request_module(
  3629. symbol_get(qeth_l3_ccwgroup_driver),
  3630. "qeth_l3");
  3631. break;
  3632. case QETH_DISCIPLINE_LAYER2:
  3633. card->discipline.ccwgdriver = try_then_request_module(
  3634. symbol_get(qeth_l2_ccwgroup_driver),
  3635. "qeth_l2");
  3636. break;
  3637. }
  3638. if (!card->discipline.ccwgdriver) {
  3639. PRINT_ERR("Support for discipline %d not present\n",
  3640. discipline);
  3641. rc = -EINVAL;
  3642. }
  3643. return rc;
  3644. }
  3645. void qeth_core_free_discipline(struct qeth_card *card)
  3646. {
  3647. if (card->options.layer2)
  3648. symbol_put(qeth_l2_ccwgroup_driver);
  3649. else
  3650. symbol_put(qeth_l3_ccwgroup_driver);
  3651. card->discipline.ccwgdriver = NULL;
  3652. }
  3653. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3654. {
  3655. struct qeth_card *card;
  3656. struct device *dev;
  3657. int rc;
  3658. unsigned long flags;
  3659. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3660. dev = &gdev->dev;
  3661. if (!get_device(dev))
  3662. return -ENODEV;
  3663. QETH_DBF_TEXT_(SETUP, 2, "%s", gdev->dev.bus_id);
  3664. card = qeth_alloc_card();
  3665. if (!card) {
  3666. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3667. rc = -ENOMEM;
  3668. goto err_dev;
  3669. }
  3670. card->read.ccwdev = gdev->cdev[0];
  3671. card->write.ccwdev = gdev->cdev[1];
  3672. card->data.ccwdev = gdev->cdev[2];
  3673. dev_set_drvdata(&gdev->dev, card);
  3674. card->gdev = gdev;
  3675. gdev->cdev[0]->handler = qeth_irq;
  3676. gdev->cdev[1]->handler = qeth_irq;
  3677. gdev->cdev[2]->handler = qeth_irq;
  3678. rc = qeth_determine_card_type(card);
  3679. if (rc) {
  3680. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3681. goto err_card;
  3682. }
  3683. rc = qeth_setup_card(card);
  3684. if (rc) {
  3685. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3686. goto err_card;
  3687. }
  3688. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3689. rc = qeth_core_create_osn_attributes(dev);
  3690. if (rc)
  3691. goto err_card;
  3692. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3693. if (rc) {
  3694. qeth_core_remove_osn_attributes(dev);
  3695. goto err_card;
  3696. }
  3697. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3698. if (rc) {
  3699. qeth_core_free_discipline(card);
  3700. qeth_core_remove_osn_attributes(dev);
  3701. goto err_card;
  3702. }
  3703. } else {
  3704. rc = qeth_core_create_device_attributes(dev);
  3705. if (rc)
  3706. goto err_card;
  3707. }
  3708. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3709. list_add_tail(&card->list, &qeth_core_card_list.list);
  3710. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3711. return 0;
  3712. err_card:
  3713. qeth_core_free_card(card);
  3714. err_dev:
  3715. put_device(dev);
  3716. return rc;
  3717. }
  3718. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3719. {
  3720. unsigned long flags;
  3721. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3722. if (card->discipline.ccwgdriver) {
  3723. card->discipline.ccwgdriver->remove(gdev);
  3724. qeth_core_free_discipline(card);
  3725. }
  3726. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3727. qeth_core_remove_osn_attributes(&gdev->dev);
  3728. } else {
  3729. qeth_core_remove_device_attributes(&gdev->dev);
  3730. }
  3731. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3732. list_del(&card->list);
  3733. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3734. qeth_core_free_card(card);
  3735. dev_set_drvdata(&gdev->dev, NULL);
  3736. put_device(&gdev->dev);
  3737. return;
  3738. }
  3739. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3740. {
  3741. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3742. int rc = 0;
  3743. int def_discipline;
  3744. if (!card->discipline.ccwgdriver) {
  3745. if (card->info.type == QETH_CARD_TYPE_IQD)
  3746. def_discipline = QETH_DISCIPLINE_LAYER3;
  3747. else
  3748. def_discipline = QETH_DISCIPLINE_LAYER2;
  3749. rc = qeth_core_load_discipline(card, def_discipline);
  3750. if (rc)
  3751. goto err;
  3752. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3753. if (rc)
  3754. goto err;
  3755. }
  3756. rc = card->discipline.ccwgdriver->set_online(gdev);
  3757. err:
  3758. return rc;
  3759. }
  3760. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3761. {
  3762. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3763. return card->discipline.ccwgdriver->set_offline(gdev);
  3764. }
  3765. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3766. {
  3767. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3768. if (card->discipline.ccwgdriver &&
  3769. card->discipline.ccwgdriver->shutdown)
  3770. card->discipline.ccwgdriver->shutdown(gdev);
  3771. }
  3772. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3773. .owner = THIS_MODULE,
  3774. .name = "qeth",
  3775. .driver_id = 0xD8C5E3C8,
  3776. .probe = qeth_core_probe_device,
  3777. .remove = qeth_core_remove_device,
  3778. .set_online = qeth_core_set_online,
  3779. .set_offline = qeth_core_set_offline,
  3780. .shutdown = qeth_core_shutdown,
  3781. };
  3782. static ssize_t
  3783. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3784. size_t count)
  3785. {
  3786. int err;
  3787. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3788. qeth_core_ccwgroup_driver.driver_id);
  3789. if (err)
  3790. return err;
  3791. else
  3792. return count;
  3793. }
  3794. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3795. static struct {
  3796. const char str[ETH_GSTRING_LEN];
  3797. } qeth_ethtool_stats_keys[] = {
  3798. /* 0 */{"rx skbs"},
  3799. {"rx buffers"},
  3800. {"tx skbs"},
  3801. {"tx buffers"},
  3802. {"tx skbs no packing"},
  3803. {"tx buffers no packing"},
  3804. {"tx skbs packing"},
  3805. {"tx buffers packing"},
  3806. {"tx sg skbs"},
  3807. {"tx sg frags"},
  3808. /* 10 */{"rx sg skbs"},
  3809. {"rx sg frags"},
  3810. {"rx sg page allocs"},
  3811. {"tx large kbytes"},
  3812. {"tx large count"},
  3813. {"tx pk state ch n->p"},
  3814. {"tx pk state ch p->n"},
  3815. {"tx pk watermark low"},
  3816. {"tx pk watermark high"},
  3817. {"queue 0 buffer usage"},
  3818. /* 20 */{"queue 1 buffer usage"},
  3819. {"queue 2 buffer usage"},
  3820. {"queue 3 buffer usage"},
  3821. {"rx handler time"},
  3822. {"rx handler count"},
  3823. {"rx do_QDIO time"},
  3824. {"rx do_QDIO count"},
  3825. {"tx handler time"},
  3826. {"tx handler count"},
  3827. {"tx time"},
  3828. /* 30 */{"tx count"},
  3829. {"tx do_QDIO time"},
  3830. {"tx do_QDIO count"},
  3831. };
  3832. int qeth_core_get_stats_count(struct net_device *dev)
  3833. {
  3834. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3835. }
  3836. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3837. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3838. struct ethtool_stats *stats, u64 *data)
  3839. {
  3840. struct qeth_card *card = netdev_priv(dev);
  3841. data[0] = card->stats.rx_packets -
  3842. card->perf_stats.initial_rx_packets;
  3843. data[1] = card->perf_stats.bufs_rec;
  3844. data[2] = card->stats.tx_packets -
  3845. card->perf_stats.initial_tx_packets;
  3846. data[3] = card->perf_stats.bufs_sent;
  3847. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3848. - card->perf_stats.skbs_sent_pack;
  3849. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3850. data[6] = card->perf_stats.skbs_sent_pack;
  3851. data[7] = card->perf_stats.bufs_sent_pack;
  3852. data[8] = card->perf_stats.sg_skbs_sent;
  3853. data[9] = card->perf_stats.sg_frags_sent;
  3854. data[10] = card->perf_stats.sg_skbs_rx;
  3855. data[11] = card->perf_stats.sg_frags_rx;
  3856. data[12] = card->perf_stats.sg_alloc_page_rx;
  3857. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3858. data[14] = card->perf_stats.large_send_cnt;
  3859. data[15] = card->perf_stats.sc_dp_p;
  3860. data[16] = card->perf_stats.sc_p_dp;
  3861. data[17] = QETH_LOW_WATERMARK_PACK;
  3862. data[18] = QETH_HIGH_WATERMARK_PACK;
  3863. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3864. data[20] = (card->qdio.no_out_queues > 1) ?
  3865. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3866. data[21] = (card->qdio.no_out_queues > 2) ?
  3867. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3868. data[22] = (card->qdio.no_out_queues > 3) ?
  3869. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3870. data[23] = card->perf_stats.inbound_time;
  3871. data[24] = card->perf_stats.inbound_cnt;
  3872. data[25] = card->perf_stats.inbound_do_qdio_time;
  3873. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3874. data[27] = card->perf_stats.outbound_handler_time;
  3875. data[28] = card->perf_stats.outbound_handler_cnt;
  3876. data[29] = card->perf_stats.outbound_time;
  3877. data[30] = card->perf_stats.outbound_cnt;
  3878. data[31] = card->perf_stats.outbound_do_qdio_time;
  3879. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3880. }
  3881. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3882. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3883. {
  3884. switch (stringset) {
  3885. case ETH_SS_STATS:
  3886. memcpy(data, &qeth_ethtool_stats_keys,
  3887. sizeof(qeth_ethtool_stats_keys));
  3888. break;
  3889. default:
  3890. WARN_ON(1);
  3891. break;
  3892. }
  3893. }
  3894. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3895. void qeth_core_get_drvinfo(struct net_device *dev,
  3896. struct ethtool_drvinfo *info)
  3897. {
  3898. struct qeth_card *card = netdev_priv(dev);
  3899. if (card->options.layer2)
  3900. strcpy(info->driver, "qeth_l2");
  3901. else
  3902. strcpy(info->driver, "qeth_l3");
  3903. strcpy(info->version, "1.0");
  3904. strcpy(info->fw_version, card->info.mcl_level);
  3905. sprintf(info->bus_info, "%s/%s/%s",
  3906. CARD_RDEV_ID(card),
  3907. CARD_WDEV_ID(card),
  3908. CARD_DDEV_ID(card));
  3909. }
  3910. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3911. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3912. struct ethtool_cmd *ecmd)
  3913. {
  3914. struct qeth_card *card = netdev_priv(netdev);
  3915. enum qeth_link_types link_type;
  3916. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3917. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3918. else
  3919. link_type = card->info.link_type;
  3920. ecmd->transceiver = XCVR_INTERNAL;
  3921. ecmd->supported = SUPPORTED_Autoneg;
  3922. ecmd->advertising = ADVERTISED_Autoneg;
  3923. ecmd->duplex = DUPLEX_FULL;
  3924. ecmd->autoneg = AUTONEG_ENABLE;
  3925. switch (link_type) {
  3926. case QETH_LINK_TYPE_FAST_ETH:
  3927. case QETH_LINK_TYPE_LANE_ETH100:
  3928. ecmd->supported |= SUPPORTED_10baseT_Half |
  3929. SUPPORTED_10baseT_Full |
  3930. SUPPORTED_100baseT_Half |
  3931. SUPPORTED_100baseT_Full |
  3932. SUPPORTED_TP;
  3933. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3934. ADVERTISED_10baseT_Full |
  3935. ADVERTISED_100baseT_Half |
  3936. ADVERTISED_100baseT_Full |
  3937. ADVERTISED_TP;
  3938. ecmd->speed = SPEED_100;
  3939. ecmd->port = PORT_TP;
  3940. break;
  3941. case QETH_LINK_TYPE_GBIT_ETH:
  3942. case QETH_LINK_TYPE_LANE_ETH1000:
  3943. ecmd->supported |= SUPPORTED_10baseT_Half |
  3944. SUPPORTED_10baseT_Full |
  3945. SUPPORTED_100baseT_Half |
  3946. SUPPORTED_100baseT_Full |
  3947. SUPPORTED_1000baseT_Half |
  3948. SUPPORTED_1000baseT_Full |
  3949. SUPPORTED_FIBRE;
  3950. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3951. ADVERTISED_10baseT_Full |
  3952. ADVERTISED_100baseT_Half |
  3953. ADVERTISED_100baseT_Full |
  3954. ADVERTISED_1000baseT_Half |
  3955. ADVERTISED_1000baseT_Full |
  3956. ADVERTISED_FIBRE;
  3957. ecmd->speed = SPEED_1000;
  3958. ecmd->port = PORT_FIBRE;
  3959. break;
  3960. case QETH_LINK_TYPE_10GBIT_ETH:
  3961. ecmd->supported |= SUPPORTED_10baseT_Half |
  3962. SUPPORTED_10baseT_Full |
  3963. SUPPORTED_100baseT_Half |
  3964. SUPPORTED_100baseT_Full |
  3965. SUPPORTED_1000baseT_Half |
  3966. SUPPORTED_1000baseT_Full |
  3967. SUPPORTED_10000baseT_Full |
  3968. SUPPORTED_FIBRE;
  3969. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3970. ADVERTISED_10baseT_Full |
  3971. ADVERTISED_100baseT_Half |
  3972. ADVERTISED_100baseT_Full |
  3973. ADVERTISED_1000baseT_Half |
  3974. ADVERTISED_1000baseT_Full |
  3975. ADVERTISED_10000baseT_Full |
  3976. ADVERTISED_FIBRE;
  3977. ecmd->speed = SPEED_10000;
  3978. ecmd->port = PORT_FIBRE;
  3979. break;
  3980. default:
  3981. ecmd->supported |= SUPPORTED_10baseT_Half |
  3982. SUPPORTED_10baseT_Full |
  3983. SUPPORTED_TP;
  3984. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3985. ADVERTISED_10baseT_Full |
  3986. ADVERTISED_TP;
  3987. ecmd->speed = SPEED_10;
  3988. ecmd->port = PORT_TP;
  3989. }
  3990. return 0;
  3991. }
  3992. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  3993. static int __init qeth_core_init(void)
  3994. {
  3995. int rc;
  3996. PRINT_INFO("loading core functions\n");
  3997. INIT_LIST_HEAD(&qeth_core_card_list.list);
  3998. rwlock_init(&qeth_core_card_list.rwlock);
  3999. rc = qeth_register_dbf_views();
  4000. if (rc)
  4001. goto out_err;
  4002. rc = ccw_driver_register(&qeth_ccw_driver);
  4003. if (rc)
  4004. goto ccw_err;
  4005. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4006. if (rc)
  4007. goto ccwgroup_err;
  4008. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4009. &driver_attr_group);
  4010. if (rc)
  4011. goto driver_err;
  4012. qeth_core_root_dev = s390_root_dev_register("qeth");
  4013. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4014. if (rc)
  4015. goto register_err;
  4016. return 0;
  4017. register_err:
  4018. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4019. &driver_attr_group);
  4020. driver_err:
  4021. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4022. ccwgroup_err:
  4023. ccw_driver_unregister(&qeth_ccw_driver);
  4024. ccw_err:
  4025. qeth_unregister_dbf_views();
  4026. out_err:
  4027. PRINT_ERR("Initialization failed with code %d\n", rc);
  4028. return rc;
  4029. }
  4030. static void __exit qeth_core_exit(void)
  4031. {
  4032. s390_root_dev_unregister(qeth_core_root_dev);
  4033. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4034. &driver_attr_group);
  4035. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4036. ccw_driver_unregister(&qeth_ccw_driver);
  4037. qeth_unregister_dbf_views();
  4038. PRINT_INFO("core functions removed\n");
  4039. }
  4040. module_init(qeth_core_init);
  4041. module_exit(qeth_core_exit);
  4042. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4043. MODULE_DESCRIPTION("qeth core functions");
  4044. MODULE_LICENSE("GPL");