i82443bxgx_edac.c 13 KB

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  1. /*
  2. * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
  3. * module (C) 2006 Tim Small
  4. *
  5. * This file may be distributed under the terms of the GNU General
  6. * Public License.
  7. *
  8. * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
  9. * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
  10. * others.
  11. *
  12. * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
  13. *
  14. * Written with reference to 82443BX Host Bridge Datasheet:
  15. * http://www.intel.com/design/chipsets/440/documentation.htm
  16. * references to this document given in [].
  17. *
  18. * This module doesn't support the 440LX, but it may be possible to
  19. * make it do so (the 440LX's register definitions are different, but
  20. * not completely so - I haven't studied them in enough detail to know
  21. * how easy this would be).
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/pci_ids.h>
  27. #include <linux/slab.h>
  28. #include <linux/edac.h>
  29. #include "edac_core.h"
  30. #define I82443_REVISION "0.1"
  31. #define EDAC_MOD_STR "i82443bxgx_edac"
  32. /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
  33. * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
  34. * rows" "The 82443BX supports multiple-bit error detection and
  35. * single-bit error correction when ECC mode is enabled and
  36. * single/multi-bit error detection when correction is disabled.
  37. * During writes to the DRAM, the 82443BX generates ECC for the data
  38. * on a QWord basis. Partial QWord writes require a read-modify-write
  39. * cycle when ECC is enabled."
  40. */
  41. /* "Additionally, the 82443BX ensures that the data is corrected in
  42. * main memory so that accumulation of errors is prevented. Another
  43. * error within the same QWord would result in a double-bit error
  44. * which is unrecoverable. This is known as hardware scrubbing since
  45. * it requires no software intervention to correct the data in memory."
  46. */
  47. /* [Also see page 100 (section 4.3), "DRAM Interface"]
  48. * [Also see page 112 (section 4.6.1.4), ECC]
  49. */
  50. #define I82443BXGX_NR_CSROWS 8
  51. #define I82443BXGX_NR_CHANS 1
  52. #define I82443BXGX_NR_DIMMS 4
  53. /* 82443 PCI Device 0 */
  54. #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
  55. * config space offset */
  56. #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
  57. * row is non-ECC */
  58. #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
  59. #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
  60. #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
  61. #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
  62. #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
  63. #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
  64. #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
  65. /* 82443 PCI Device 0 */
  66. #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
  67. * config space offset, Error Address
  68. * Pointer Register */
  69. #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
  70. #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
  71. #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
  72. #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
  73. * config space offset. */
  74. #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
  75. #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
  76. #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
  77. * config space offset. */
  78. #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
  79. #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
  80. #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
  81. #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
  82. #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
  83. * config space offset. */
  84. #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
  85. #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
  86. #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
  87. #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
  88. #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
  89. * config space offset. */
  90. /* FIXME - don't poll when ECC disabled? */
  91. struct i82443bxgx_edacmc_error_info {
  92. u32 eap;
  93. };
  94. static struct edac_pci_ctl_info *i82443bxgx_pci;
  95. static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
  96. struct i82443bxgx_edacmc_error_info
  97. *info)
  98. {
  99. struct pci_dev *pdev;
  100. pdev = to_pci_dev(mci->dev);
  101. pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
  102. if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
  103. /* Clear error to allow next error to be reported [p.61] */
  104. pci_write_bits32(pdev, I82443BXGX_EAP,
  105. I82443BXGX_EAP_OFFSET_SBE,
  106. I82443BXGX_EAP_OFFSET_SBE);
  107. if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
  108. /* Clear error to allow next error to be reported [p.61] */
  109. pci_write_bits32(pdev, I82443BXGX_EAP,
  110. I82443BXGX_EAP_OFFSET_MBE,
  111. I82443BXGX_EAP_OFFSET_MBE);
  112. }
  113. static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
  114. struct
  115. i82443bxgx_edacmc_error_info
  116. *info, int handle_errors)
  117. {
  118. int error_found = 0;
  119. u32 eapaddr, page, pageoffset;
  120. /* bits 30:12 hold the 4kb block in which the error occurred
  121. * [p.61] */
  122. eapaddr = (info->eap & 0xfffff000);
  123. page = eapaddr >> PAGE_SHIFT;
  124. pageoffset = eapaddr - (page << PAGE_SHIFT);
  125. if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
  126. error_found = 1;
  127. if (handle_errors)
  128. edac_mc_handle_ce(mci, page, pageoffset,
  129. /* 440BX/GX don't make syndrome information
  130. * available */
  131. 0, edac_mc_find_csrow_by_page(mci, page), 0,
  132. mci->ctl_name);
  133. }
  134. if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
  135. error_found = 1;
  136. if (handle_errors)
  137. edac_mc_handle_ue(mci, page, pageoffset,
  138. edac_mc_find_csrow_by_page(mci, page),
  139. mci->ctl_name);
  140. }
  141. return error_found;
  142. }
  143. static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
  144. {
  145. struct i82443bxgx_edacmc_error_info info;
  146. debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
  147. i82443bxgx_edacmc_get_error_info(mci, &info);
  148. i82443bxgx_edacmc_process_error_info(mci, &info, 1);
  149. }
  150. static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
  151. struct pci_dev *pdev,
  152. enum edac_type edac_mode,
  153. enum mem_type mtype)
  154. {
  155. struct csrow_info *csrow;
  156. int index;
  157. u8 drbar, dramc;
  158. u32 row_base, row_high_limit, row_high_limit_last;
  159. pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
  160. row_high_limit_last = 0;
  161. for (index = 0; index < mci->nr_csrows; index++) {
  162. csrow = &mci->csrows[index];
  163. pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
  164. debugf1("MC%d: " __FILE__ ": %s() Row=%d DRB = %#0x\n",
  165. mci->mc_idx, __func__, index, drbar);
  166. row_high_limit = ((u32) drbar << 23);
  167. /* find the DRAM Chip Select Base address and mask */
  168. debugf1("MC%d: " __FILE__ ": %s() Row=%d, "
  169. "Boundry Address=%#0x, Last = %#0x \n",
  170. mci->mc_idx, __func__, index, row_high_limit,
  171. row_high_limit_last);
  172. /* 440GX goes to 2GB, represented with a DRB of 0. */
  173. if (row_high_limit_last && !row_high_limit)
  174. row_high_limit = 1UL << 31;
  175. /* This row is empty [p.49] */
  176. if (row_high_limit == row_high_limit_last)
  177. continue;
  178. row_base = row_high_limit_last;
  179. csrow->first_page = row_base >> PAGE_SHIFT;
  180. csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
  181. csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
  182. /* EAP reports in 4kilobyte granularity [61] */
  183. csrow->grain = 1 << 12;
  184. csrow->mtype = mtype;
  185. /* I don't think 440BX can tell you device type? FIXME? */
  186. csrow->dtype = DEV_UNKNOWN;
  187. /* Mode is global to all rows on 440BX */
  188. csrow->edac_mode = edac_mode;
  189. row_high_limit_last = row_high_limit;
  190. }
  191. }
  192. static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
  193. {
  194. struct mem_ctl_info *mci;
  195. u8 dramc;
  196. u32 nbxcfg, ecc_mode;
  197. enum mem_type mtype;
  198. enum edac_type edac_mode;
  199. debugf0("MC: " __FILE__ ": %s()\n", __func__);
  200. /* Something is really hosed if PCI config space reads from
  201. * the MC aren't working.
  202. */
  203. if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
  204. return -EIO;
  205. mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0);
  206. if (mci == NULL)
  207. return -ENOMEM;
  208. debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
  209. mci->dev = &pdev->dev;
  210. mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
  211. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  212. pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
  213. switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
  214. case I82443BXGX_DRAMC_DRAM_IS_EDO:
  215. mtype = MEM_EDO;
  216. break;
  217. case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
  218. mtype = MEM_SDR;
  219. break;
  220. case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
  221. mtype = MEM_RDR;
  222. break;
  223. default:
  224. debugf0("Unknown/reserved DRAM type value "
  225. "in DRAMC register!\n");
  226. mtype = -MEM_UNKNOWN;
  227. }
  228. if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
  229. mci->edac_cap = mci->edac_ctl_cap;
  230. else
  231. mci->edac_cap = EDAC_FLAG_NONE;
  232. mci->scrub_cap = SCRUB_FLAG_HW_SRC;
  233. pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
  234. ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
  235. (BIT(0) | BIT(1)));
  236. mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
  237. ? SCRUB_HW_SRC : SCRUB_NONE;
  238. switch (ecc_mode) {
  239. case I82443BXGX_NBXCFG_INTEGRITY_NONE:
  240. edac_mode = EDAC_NONE;
  241. break;
  242. case I82443BXGX_NBXCFG_INTEGRITY_EC:
  243. edac_mode = EDAC_EC;
  244. break;
  245. case I82443BXGX_NBXCFG_INTEGRITY_ECC:
  246. case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
  247. edac_mode = EDAC_SECDED;
  248. break;
  249. default:
  250. debugf0("%s(): Unknown/reserved ECC state "
  251. "in NBXCFG register!\n", __func__);
  252. edac_mode = EDAC_UNKNOWN;
  253. break;
  254. }
  255. i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
  256. /* Many BIOSes don't clear error flags on boot, so do this
  257. * here, or we get "phantom" errors occuring at module-load
  258. * time. */
  259. pci_write_bits32(pdev, I82443BXGX_EAP,
  260. (I82443BXGX_EAP_OFFSET_SBE |
  261. I82443BXGX_EAP_OFFSET_MBE),
  262. (I82443BXGX_EAP_OFFSET_SBE |
  263. I82443BXGX_EAP_OFFSET_MBE));
  264. mci->mod_name = EDAC_MOD_STR;
  265. mci->mod_ver = I82443_REVISION;
  266. mci->ctl_name = "I82443BXGX";
  267. mci->dev_name = pci_name(pdev);
  268. mci->edac_check = i82443bxgx_edacmc_check;
  269. mci->ctl_page_to_phys = NULL;
  270. if (edac_mc_add_mc(mci)) {
  271. debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
  272. goto fail;
  273. }
  274. /* allocating generic PCI control info */
  275. i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  276. if (!i82443bxgx_pci) {
  277. printk(KERN_WARNING
  278. "%s(): Unable to create PCI control\n",
  279. __func__);
  280. printk(KERN_WARNING
  281. "%s(): PCI error report via EDAC not setup\n",
  282. __func__);
  283. }
  284. debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
  285. return 0;
  286. fail:
  287. edac_mc_free(mci);
  288. return -ENODEV;
  289. }
  290. EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
  291. /* returns count (>= 0), or negative on error */
  292. static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
  293. const struct pci_device_id *ent)
  294. {
  295. debugf0("MC: " __FILE__ ": %s()\n", __func__);
  296. /* don't need to call pci_device_enable() */
  297. return i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
  298. }
  299. static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
  300. {
  301. struct mem_ctl_info *mci;
  302. debugf0(__FILE__ ": %s()\n", __func__);
  303. if (i82443bxgx_pci)
  304. edac_pci_release_generic_ctl(i82443bxgx_pci);
  305. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  306. return;
  307. edac_mc_free(mci);
  308. }
  309. EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
  310. static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
  311. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
  312. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
  313. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
  314. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
  315. {0,} /* 0 terminated list. */
  316. };
  317. MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
  318. static struct pci_driver i82443bxgx_edacmc_driver = {
  319. .name = EDAC_MOD_STR,
  320. .probe = i82443bxgx_edacmc_init_one,
  321. .remove = __devexit_p(i82443bxgx_edacmc_remove_one),
  322. .id_table = i82443bxgx_pci_tbl,
  323. };
  324. static int __init i82443bxgx_edacmc_init(void)
  325. {
  326. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  327. opstate_init();
  328. return pci_register_driver(&i82443bxgx_edacmc_driver);
  329. }
  330. static void __exit i82443bxgx_edacmc_exit(void)
  331. {
  332. pci_unregister_driver(&i82443bxgx_edacmc_driver);
  333. }
  334. module_init(i82443bxgx_edacmc_init);
  335. module_exit(i82443bxgx_edacmc_exit);
  336. MODULE_LICENSE("GPL");
  337. MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
  338. MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
  339. module_param(edac_op_state, int, 0444);
  340. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");