ahci.c 73 KB

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  1. /*
  2. * ahci.c - AHCI SATA support
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2004-2005 Red Hat, Inc.
  9. *
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. *
  26. * libata documentation is available via 'make {ps|pdf}docs',
  27. * as Documentation/DocBook/libata.*
  28. *
  29. * AHCI hardware documentation:
  30. * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31. * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32. *
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/pci.h>
  37. #include <linux/init.h>
  38. #include <linux/blkdev.h>
  39. #include <linux/delay.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/device.h>
  43. #include <linux/dmi.h>
  44. #include <scsi/scsi_host.h>
  45. #include <scsi/scsi_cmnd.h>
  46. #include <linux/libata.h>
  47. #define DRV_NAME "ahci"
  48. #define DRV_VERSION "3.0"
  49. static int ahci_skip_host_reset;
  50. module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
  51. MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
  52. static int ahci_enable_alpm(struct ata_port *ap,
  53. enum link_pm policy);
  54. static void ahci_disable_alpm(struct ata_port *ap);
  55. static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
  56. static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
  57. size_t size);
  58. static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
  59. ssize_t size);
  60. #define MAX_SLOTS 8
  61. enum {
  62. AHCI_PCI_BAR = 5,
  63. AHCI_MAX_PORTS = 32,
  64. AHCI_MAX_SG = 168, /* hardware max is 64K */
  65. AHCI_DMA_BOUNDARY = 0xffffffff,
  66. AHCI_MAX_CMDS = 32,
  67. AHCI_CMD_SZ = 32,
  68. AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
  69. AHCI_RX_FIS_SZ = 256,
  70. AHCI_CMD_TBL_CDB = 0x40,
  71. AHCI_CMD_TBL_HDR_SZ = 0x80,
  72. AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
  73. AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
  74. AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
  75. AHCI_RX_FIS_SZ,
  76. AHCI_IRQ_ON_SG = (1 << 31),
  77. AHCI_CMD_ATAPI = (1 << 5),
  78. AHCI_CMD_WRITE = (1 << 6),
  79. AHCI_CMD_PREFETCH = (1 << 7),
  80. AHCI_CMD_RESET = (1 << 8),
  81. AHCI_CMD_CLR_BUSY = (1 << 10),
  82. RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
  83. RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
  84. RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
  85. board_ahci = 0,
  86. board_ahci_vt8251 = 1,
  87. board_ahci_ign_iferr = 2,
  88. board_ahci_sb600 = 3,
  89. board_ahci_mv = 4,
  90. board_ahci_sb700 = 5,
  91. board_ahci_mcp65 = 6,
  92. board_ahci_nopmp = 7,
  93. /* global controller registers */
  94. HOST_CAP = 0x00, /* host capabilities */
  95. HOST_CTL = 0x04, /* global host control */
  96. HOST_IRQ_STAT = 0x08, /* interrupt status */
  97. HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
  98. HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
  99. HOST_EM_LOC = 0x1c, /* Enclosure Management location */
  100. HOST_EM_CTL = 0x20, /* Enclosure Management Control */
  101. /* HOST_CTL bits */
  102. HOST_RESET = (1 << 0), /* reset controller; self-clear */
  103. HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
  104. HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
  105. /* HOST_CAP bits */
  106. HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
  107. HOST_CAP_SSC = (1 << 14), /* Slumber capable */
  108. HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
  109. HOST_CAP_CLO = (1 << 24), /* Command List Override support */
  110. HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
  111. HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
  112. HOST_CAP_SNTF = (1 << 29), /* SNotification register */
  113. HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
  114. HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
  115. /* registers for each SATA port */
  116. PORT_LST_ADDR = 0x00, /* command list DMA addr */
  117. PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
  118. PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
  119. PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
  120. PORT_IRQ_STAT = 0x10, /* interrupt status */
  121. PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
  122. PORT_CMD = 0x18, /* port command */
  123. PORT_TFDATA = 0x20, /* taskfile data */
  124. PORT_SIG = 0x24, /* device TF signature */
  125. PORT_CMD_ISSUE = 0x38, /* command issue */
  126. PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
  127. PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
  128. PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
  129. PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
  130. PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
  131. /* PORT_IRQ_{STAT,MASK} bits */
  132. PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
  133. PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
  134. PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
  135. PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
  136. PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
  137. PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
  138. PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
  139. PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
  140. PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
  141. PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
  142. PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
  143. PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
  144. PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
  145. PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
  146. PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
  147. PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
  148. PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
  149. PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
  150. PORT_IRQ_IF_ERR |
  151. PORT_IRQ_CONNECT |
  152. PORT_IRQ_PHYRDY |
  153. PORT_IRQ_UNK_FIS |
  154. PORT_IRQ_BAD_PMP,
  155. PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
  156. PORT_IRQ_TF_ERR |
  157. PORT_IRQ_HBUS_DATA_ERR,
  158. DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
  159. PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
  160. PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
  161. /* PORT_CMD bits */
  162. PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
  163. PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
  164. PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
  165. PORT_CMD_PMP = (1 << 17), /* PMP attached */
  166. PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
  167. PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
  168. PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
  169. PORT_CMD_CLO = (1 << 3), /* Command list override */
  170. PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
  171. PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
  172. PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
  173. PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
  174. PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
  175. PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
  176. PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
  177. /* hpriv->flags bits */
  178. AHCI_HFLAG_NO_NCQ = (1 << 0),
  179. AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
  180. AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
  181. AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
  182. AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
  183. AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
  184. AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
  185. AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
  186. AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
  187. AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
  188. /* ap->flags bits */
  189. AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  190. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
  191. ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
  192. ATA_FLAG_IPM,
  193. ICH_MAP = 0x90, /* ICH MAP register */
  194. /* em_ctl bits */
  195. EM_CTL_RST = (1 << 9), /* Reset */
  196. EM_CTL_TM = (1 << 8), /* Transmit Message */
  197. EM_CTL_ALHD = (1 << 26), /* Activity LED */
  198. };
  199. struct ahci_cmd_hdr {
  200. __le32 opts;
  201. __le32 status;
  202. __le32 tbl_addr;
  203. __le32 tbl_addr_hi;
  204. __le32 reserved[4];
  205. };
  206. struct ahci_sg {
  207. __le32 addr;
  208. __le32 addr_hi;
  209. __le32 reserved;
  210. __le32 flags_size;
  211. };
  212. struct ahci_em_priv {
  213. enum sw_activity blink_policy;
  214. struct timer_list timer;
  215. unsigned long saved_activity;
  216. unsigned long activity;
  217. unsigned long led_state;
  218. };
  219. struct ahci_host_priv {
  220. unsigned int flags; /* AHCI_HFLAG_* */
  221. u32 cap; /* cap to use */
  222. u32 port_map; /* port map to use */
  223. u32 saved_cap; /* saved initial cap */
  224. u32 saved_port_map; /* saved initial port_map */
  225. u32 em_loc; /* enclosure management location */
  226. };
  227. struct ahci_port_priv {
  228. struct ata_link *active_link;
  229. struct ahci_cmd_hdr *cmd_slot;
  230. dma_addr_t cmd_slot_dma;
  231. void *cmd_tbl;
  232. dma_addr_t cmd_tbl_dma;
  233. void *rx_fis;
  234. dma_addr_t rx_fis_dma;
  235. /* for NCQ spurious interrupt analysis */
  236. unsigned int ncq_saw_d2h:1;
  237. unsigned int ncq_saw_dmas:1;
  238. unsigned int ncq_saw_sdb:1;
  239. u32 intr_mask; /* interrupts to enable */
  240. struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
  241. * per PM slot */
  242. };
  243. static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
  244. static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
  245. static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  246. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
  247. static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
  248. static int ahci_port_start(struct ata_port *ap);
  249. static void ahci_port_stop(struct ata_port *ap);
  250. static void ahci_qc_prep(struct ata_queued_cmd *qc);
  251. static void ahci_freeze(struct ata_port *ap);
  252. static void ahci_thaw(struct ata_port *ap);
  253. static void ahci_pmp_attach(struct ata_port *ap);
  254. static void ahci_pmp_detach(struct ata_port *ap);
  255. static int ahci_softreset(struct ata_link *link, unsigned int *class,
  256. unsigned long deadline);
  257. static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
  258. unsigned long deadline);
  259. static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  260. unsigned long deadline);
  261. static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  262. unsigned long deadline);
  263. static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  264. unsigned long deadline);
  265. static void ahci_postreset(struct ata_link *link, unsigned int *class);
  266. static void ahci_error_handler(struct ata_port *ap);
  267. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
  268. static int ahci_port_resume(struct ata_port *ap);
  269. static void ahci_dev_config(struct ata_device *dev);
  270. static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
  271. static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
  272. u32 opts);
  273. #ifdef CONFIG_PM
  274. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
  275. static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  276. static int ahci_pci_device_resume(struct pci_dev *pdev);
  277. #endif
  278. static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
  279. static ssize_t ahci_activity_store(struct ata_device *dev,
  280. enum sw_activity val);
  281. static void ahci_init_sw_activity(struct ata_link *link);
  282. static struct device_attribute *ahci_shost_attrs[] = {
  283. &dev_attr_link_power_management_policy,
  284. &dev_attr_em_message_type,
  285. &dev_attr_em_message,
  286. NULL
  287. };
  288. static struct device_attribute *ahci_sdev_attrs[] = {
  289. &dev_attr_sw_activity,
  290. NULL
  291. };
  292. static struct scsi_host_template ahci_sht = {
  293. ATA_NCQ_SHT(DRV_NAME),
  294. .can_queue = AHCI_MAX_CMDS - 1,
  295. .sg_tablesize = AHCI_MAX_SG,
  296. .dma_boundary = AHCI_DMA_BOUNDARY,
  297. .shost_attrs = ahci_shost_attrs,
  298. .sdev_attrs = ahci_sdev_attrs,
  299. };
  300. static struct ata_port_operations ahci_ops = {
  301. .inherits = &sata_pmp_port_ops,
  302. .qc_defer = sata_pmp_qc_defer_cmd_switch,
  303. .qc_prep = ahci_qc_prep,
  304. .qc_issue = ahci_qc_issue,
  305. .qc_fill_rtf = ahci_qc_fill_rtf,
  306. .freeze = ahci_freeze,
  307. .thaw = ahci_thaw,
  308. .softreset = ahci_softreset,
  309. .hardreset = ahci_hardreset,
  310. .postreset = ahci_postreset,
  311. .pmp_softreset = ahci_softreset,
  312. .error_handler = ahci_error_handler,
  313. .post_internal_cmd = ahci_post_internal_cmd,
  314. .dev_config = ahci_dev_config,
  315. .scr_read = ahci_scr_read,
  316. .scr_write = ahci_scr_write,
  317. .pmp_attach = ahci_pmp_attach,
  318. .pmp_detach = ahci_pmp_detach,
  319. .enable_pm = ahci_enable_alpm,
  320. .disable_pm = ahci_disable_alpm,
  321. .em_show = ahci_led_show,
  322. .em_store = ahci_led_store,
  323. .sw_activity_show = ahci_activity_show,
  324. .sw_activity_store = ahci_activity_store,
  325. #ifdef CONFIG_PM
  326. .port_suspend = ahci_port_suspend,
  327. .port_resume = ahci_port_resume,
  328. #endif
  329. .port_start = ahci_port_start,
  330. .port_stop = ahci_port_stop,
  331. };
  332. static struct ata_port_operations ahci_vt8251_ops = {
  333. .inherits = &ahci_ops,
  334. .hardreset = ahci_vt8251_hardreset,
  335. };
  336. static struct ata_port_operations ahci_p5wdh_ops = {
  337. .inherits = &ahci_ops,
  338. .hardreset = ahci_p5wdh_hardreset,
  339. };
  340. static struct ata_port_operations ahci_sb600_ops = {
  341. .inherits = &ahci_ops,
  342. .softreset = ahci_sb600_softreset,
  343. .pmp_softreset = ahci_sb600_softreset,
  344. };
  345. #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
  346. static const struct ata_port_info ahci_port_info[] = {
  347. /* board_ahci */
  348. {
  349. .flags = AHCI_FLAG_COMMON,
  350. .pio_mask = 0x1f, /* pio0-4 */
  351. .udma_mask = ATA_UDMA6,
  352. .port_ops = &ahci_ops,
  353. },
  354. /* board_ahci_vt8251 */
  355. {
  356. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
  357. .flags = AHCI_FLAG_COMMON,
  358. .pio_mask = 0x1f, /* pio0-4 */
  359. .udma_mask = ATA_UDMA6,
  360. .port_ops = &ahci_vt8251_ops,
  361. },
  362. /* board_ahci_ign_iferr */
  363. {
  364. AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
  365. .flags = AHCI_FLAG_COMMON,
  366. .pio_mask = 0x1f, /* pio0-4 */
  367. .udma_mask = ATA_UDMA6,
  368. .port_ops = &ahci_ops,
  369. },
  370. /* board_ahci_sb600 */
  371. {
  372. AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
  373. AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
  374. AHCI_HFLAG_SECT255),
  375. .flags = AHCI_FLAG_COMMON,
  376. .pio_mask = 0x1f, /* pio0-4 */
  377. .udma_mask = ATA_UDMA6,
  378. .port_ops = &ahci_sb600_ops,
  379. },
  380. /* board_ahci_mv */
  381. {
  382. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
  383. AHCI_HFLAG_MV_PATA),
  384. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  385. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
  386. .pio_mask = 0x1f, /* pio0-4 */
  387. .udma_mask = ATA_UDMA6,
  388. .port_ops = &ahci_ops,
  389. },
  390. /* board_ahci_sb700 */
  391. {
  392. AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
  393. .flags = AHCI_FLAG_COMMON,
  394. .pio_mask = 0x1f, /* pio0-4 */
  395. .udma_mask = ATA_UDMA6,
  396. .port_ops = &ahci_sb600_ops,
  397. },
  398. /* board_ahci_mcp65 */
  399. {
  400. AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
  401. .flags = AHCI_FLAG_COMMON,
  402. .pio_mask = 0x1f, /* pio0-4 */
  403. .udma_mask = ATA_UDMA6,
  404. .port_ops = &ahci_ops,
  405. },
  406. /* board_ahci_nopmp */
  407. {
  408. AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
  409. .flags = AHCI_FLAG_COMMON,
  410. .pio_mask = 0x1f, /* pio0-4 */
  411. .udma_mask = ATA_UDMA6,
  412. .port_ops = &ahci_ops,
  413. },
  414. };
  415. static const struct pci_device_id ahci_pci_tbl[] = {
  416. /* Intel */
  417. { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
  418. { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
  419. { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
  420. { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
  421. { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
  422. { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
  423. { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
  424. { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
  425. { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
  426. { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
  427. { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
  428. { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
  429. { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
  430. { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
  431. { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
  432. { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
  433. { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
  434. { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
  435. { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
  436. { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
  437. { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
  438. { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
  439. { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
  440. { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
  441. { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
  442. { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
  443. { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
  444. { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
  445. { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
  446. { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
  447. { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
  448. /* JMicron 360/1/3/5/6, match class to avoid IDE function */
  449. { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  450. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
  451. /* ATI */
  452. { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
  453. { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
  454. { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
  455. { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
  456. { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
  457. { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
  458. { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
  459. /* VIA */
  460. { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
  461. { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
  462. /* NVIDIA */
  463. { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
  464. { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
  465. { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
  466. { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
  467. { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
  468. { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
  469. { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
  470. { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
  471. { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
  472. { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
  473. { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
  474. { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
  475. { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
  476. { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
  477. { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
  478. { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
  479. { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
  480. { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
  481. { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
  482. { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
  483. { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
  484. { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
  485. { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
  486. { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
  487. { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
  488. { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
  489. { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
  490. { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
  491. { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
  492. { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
  493. { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
  494. { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
  495. { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
  496. { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
  497. { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
  498. { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
  499. { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
  500. { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
  501. { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
  502. { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
  503. { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
  504. { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
  505. { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
  506. { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
  507. { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
  508. { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
  509. { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
  510. { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
  511. { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
  512. { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
  513. { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
  514. { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
  515. { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
  516. { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
  517. { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
  518. { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
  519. { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
  520. { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
  521. { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
  522. { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
  523. { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
  524. { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
  525. { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
  526. { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
  527. { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
  528. { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
  529. { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
  530. { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
  531. /* SiS */
  532. { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */
  533. { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */
  534. { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */
  535. /* Marvell */
  536. { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
  537. { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
  538. /* Generic, PCI class code for AHCI */
  539. { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  540. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
  541. { } /* terminate list */
  542. };
  543. static struct pci_driver ahci_pci_driver = {
  544. .name = DRV_NAME,
  545. .id_table = ahci_pci_tbl,
  546. .probe = ahci_init_one,
  547. .remove = ata_pci_remove_one,
  548. #ifdef CONFIG_PM
  549. .suspend = ahci_pci_device_suspend,
  550. .resume = ahci_pci_device_resume,
  551. #endif
  552. };
  553. static int ahci_em_messages = 1;
  554. module_param(ahci_em_messages, int, 0444);
  555. /* add other LED protocol types when they become supported */
  556. MODULE_PARM_DESC(ahci_em_messages,
  557. "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
  558. static inline int ahci_nr_ports(u32 cap)
  559. {
  560. return (cap & 0x1f) + 1;
  561. }
  562. static inline void __iomem *__ahci_port_base(struct ata_host *host,
  563. unsigned int port_no)
  564. {
  565. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  566. return mmio + 0x100 + (port_no * 0x80);
  567. }
  568. static inline void __iomem *ahci_port_base(struct ata_port *ap)
  569. {
  570. return __ahci_port_base(ap->host, ap->port_no);
  571. }
  572. static void ahci_enable_ahci(void __iomem *mmio)
  573. {
  574. int i;
  575. u32 tmp;
  576. /* turn on AHCI_EN */
  577. tmp = readl(mmio + HOST_CTL);
  578. if (tmp & HOST_AHCI_EN)
  579. return;
  580. /* Some controllers need AHCI_EN to be written multiple times.
  581. * Try a few times before giving up.
  582. */
  583. for (i = 0; i < 5; i++) {
  584. tmp |= HOST_AHCI_EN;
  585. writel(tmp, mmio + HOST_CTL);
  586. tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
  587. if (tmp & HOST_AHCI_EN)
  588. return;
  589. msleep(10);
  590. }
  591. WARN_ON(1);
  592. }
  593. /**
  594. * ahci_save_initial_config - Save and fixup initial config values
  595. * @pdev: target PCI device
  596. * @hpriv: host private area to store config values
  597. *
  598. * Some registers containing configuration info might be setup by
  599. * BIOS and might be cleared on reset. This function saves the
  600. * initial values of those registers into @hpriv such that they
  601. * can be restored after controller reset.
  602. *
  603. * If inconsistent, config values are fixed up by this function.
  604. *
  605. * LOCKING:
  606. * None.
  607. */
  608. static void ahci_save_initial_config(struct pci_dev *pdev,
  609. struct ahci_host_priv *hpriv)
  610. {
  611. void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
  612. u32 cap, port_map;
  613. int i;
  614. int mv;
  615. /* make sure AHCI mode is enabled before accessing CAP */
  616. ahci_enable_ahci(mmio);
  617. /* Values prefixed with saved_ are written back to host after
  618. * reset. Values without are used for driver operation.
  619. */
  620. hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
  621. hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
  622. /* some chips have errata preventing 64bit use */
  623. if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
  624. dev_printk(KERN_INFO, &pdev->dev,
  625. "controller can't do 64bit DMA, forcing 32bit\n");
  626. cap &= ~HOST_CAP_64;
  627. }
  628. if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
  629. dev_printk(KERN_INFO, &pdev->dev,
  630. "controller can't do NCQ, turning off CAP_NCQ\n");
  631. cap &= ~HOST_CAP_NCQ;
  632. }
  633. if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
  634. dev_printk(KERN_INFO, &pdev->dev,
  635. "controller can do NCQ, turning on CAP_NCQ\n");
  636. cap |= HOST_CAP_NCQ;
  637. }
  638. if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
  639. dev_printk(KERN_INFO, &pdev->dev,
  640. "controller can't do PMP, turning off CAP_PMP\n");
  641. cap &= ~HOST_CAP_PMP;
  642. }
  643. if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
  644. port_map != 1) {
  645. dev_printk(KERN_INFO, &pdev->dev,
  646. "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
  647. port_map, 1);
  648. port_map = 1;
  649. }
  650. /*
  651. * Temporary Marvell 6145 hack: PATA port presence
  652. * is asserted through the standard AHCI port
  653. * presence register, as bit 4 (counting from 0)
  654. */
  655. if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
  656. if (pdev->device == 0x6121)
  657. mv = 0x3;
  658. else
  659. mv = 0xf;
  660. dev_printk(KERN_ERR, &pdev->dev,
  661. "MV_AHCI HACK: port_map %x -> %x\n",
  662. port_map,
  663. port_map & mv);
  664. port_map &= mv;
  665. }
  666. /* cross check port_map and cap.n_ports */
  667. if (port_map) {
  668. int map_ports = 0;
  669. for (i = 0; i < AHCI_MAX_PORTS; i++)
  670. if (port_map & (1 << i))
  671. map_ports++;
  672. /* If PI has more ports than n_ports, whine, clear
  673. * port_map and let it be generated from n_ports.
  674. */
  675. if (map_ports > ahci_nr_ports(cap)) {
  676. dev_printk(KERN_WARNING, &pdev->dev,
  677. "implemented port map (0x%x) contains more "
  678. "ports than nr_ports (%u), using nr_ports\n",
  679. port_map, ahci_nr_ports(cap));
  680. port_map = 0;
  681. }
  682. }
  683. /* fabricate port_map from cap.nr_ports */
  684. if (!port_map) {
  685. port_map = (1 << ahci_nr_ports(cap)) - 1;
  686. dev_printk(KERN_WARNING, &pdev->dev,
  687. "forcing PORTS_IMPL to 0x%x\n", port_map);
  688. /* write the fixed up value to the PI register */
  689. hpriv->saved_port_map = port_map;
  690. }
  691. /* record values to use during operation */
  692. hpriv->cap = cap;
  693. hpriv->port_map = port_map;
  694. }
  695. /**
  696. * ahci_restore_initial_config - Restore initial config
  697. * @host: target ATA host
  698. *
  699. * Restore initial config stored by ahci_save_initial_config().
  700. *
  701. * LOCKING:
  702. * None.
  703. */
  704. static void ahci_restore_initial_config(struct ata_host *host)
  705. {
  706. struct ahci_host_priv *hpriv = host->private_data;
  707. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  708. writel(hpriv->saved_cap, mmio + HOST_CAP);
  709. writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
  710. (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
  711. }
  712. static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
  713. {
  714. static const int offset[] = {
  715. [SCR_STATUS] = PORT_SCR_STAT,
  716. [SCR_CONTROL] = PORT_SCR_CTL,
  717. [SCR_ERROR] = PORT_SCR_ERR,
  718. [SCR_ACTIVE] = PORT_SCR_ACT,
  719. [SCR_NOTIFICATION] = PORT_SCR_NTF,
  720. };
  721. struct ahci_host_priv *hpriv = ap->host->private_data;
  722. if (sc_reg < ARRAY_SIZE(offset) &&
  723. (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
  724. return offset[sc_reg];
  725. return 0;
  726. }
  727. static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
  728. {
  729. void __iomem *port_mmio = ahci_port_base(ap);
  730. int offset = ahci_scr_offset(ap, sc_reg);
  731. if (offset) {
  732. *val = readl(port_mmio + offset);
  733. return 0;
  734. }
  735. return -EINVAL;
  736. }
  737. static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
  738. {
  739. void __iomem *port_mmio = ahci_port_base(ap);
  740. int offset = ahci_scr_offset(ap, sc_reg);
  741. if (offset) {
  742. writel(val, port_mmio + offset);
  743. return 0;
  744. }
  745. return -EINVAL;
  746. }
  747. static void ahci_start_engine(struct ata_port *ap)
  748. {
  749. void __iomem *port_mmio = ahci_port_base(ap);
  750. u32 tmp;
  751. /* start DMA */
  752. tmp = readl(port_mmio + PORT_CMD);
  753. tmp |= PORT_CMD_START;
  754. writel(tmp, port_mmio + PORT_CMD);
  755. readl(port_mmio + PORT_CMD); /* flush */
  756. }
  757. static int ahci_stop_engine(struct ata_port *ap)
  758. {
  759. void __iomem *port_mmio = ahci_port_base(ap);
  760. u32 tmp;
  761. tmp = readl(port_mmio + PORT_CMD);
  762. /* check if the HBA is idle */
  763. if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
  764. return 0;
  765. /* setting HBA to idle */
  766. tmp &= ~PORT_CMD_START;
  767. writel(tmp, port_mmio + PORT_CMD);
  768. /* wait for engine to stop. This could be as long as 500 msec */
  769. tmp = ata_wait_register(port_mmio + PORT_CMD,
  770. PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
  771. if (tmp & PORT_CMD_LIST_ON)
  772. return -EIO;
  773. return 0;
  774. }
  775. static void ahci_start_fis_rx(struct ata_port *ap)
  776. {
  777. void __iomem *port_mmio = ahci_port_base(ap);
  778. struct ahci_host_priv *hpriv = ap->host->private_data;
  779. struct ahci_port_priv *pp = ap->private_data;
  780. u32 tmp;
  781. /* set FIS registers */
  782. if (hpriv->cap & HOST_CAP_64)
  783. writel((pp->cmd_slot_dma >> 16) >> 16,
  784. port_mmio + PORT_LST_ADDR_HI);
  785. writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
  786. if (hpriv->cap & HOST_CAP_64)
  787. writel((pp->rx_fis_dma >> 16) >> 16,
  788. port_mmio + PORT_FIS_ADDR_HI);
  789. writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
  790. /* enable FIS reception */
  791. tmp = readl(port_mmio + PORT_CMD);
  792. tmp |= PORT_CMD_FIS_RX;
  793. writel(tmp, port_mmio + PORT_CMD);
  794. /* flush */
  795. readl(port_mmio + PORT_CMD);
  796. }
  797. static int ahci_stop_fis_rx(struct ata_port *ap)
  798. {
  799. void __iomem *port_mmio = ahci_port_base(ap);
  800. u32 tmp;
  801. /* disable FIS reception */
  802. tmp = readl(port_mmio + PORT_CMD);
  803. tmp &= ~PORT_CMD_FIS_RX;
  804. writel(tmp, port_mmio + PORT_CMD);
  805. /* wait for completion, spec says 500ms, give it 1000 */
  806. tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
  807. PORT_CMD_FIS_ON, 10, 1000);
  808. if (tmp & PORT_CMD_FIS_ON)
  809. return -EBUSY;
  810. return 0;
  811. }
  812. static void ahci_power_up(struct ata_port *ap)
  813. {
  814. struct ahci_host_priv *hpriv = ap->host->private_data;
  815. void __iomem *port_mmio = ahci_port_base(ap);
  816. u32 cmd;
  817. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  818. /* spin up device */
  819. if (hpriv->cap & HOST_CAP_SSS) {
  820. cmd |= PORT_CMD_SPIN_UP;
  821. writel(cmd, port_mmio + PORT_CMD);
  822. }
  823. /* wake up link */
  824. writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
  825. }
  826. static void ahci_disable_alpm(struct ata_port *ap)
  827. {
  828. struct ahci_host_priv *hpriv = ap->host->private_data;
  829. void __iomem *port_mmio = ahci_port_base(ap);
  830. u32 cmd;
  831. struct ahci_port_priv *pp = ap->private_data;
  832. /* IPM bits should be disabled by libata-core */
  833. /* get the existing command bits */
  834. cmd = readl(port_mmio + PORT_CMD);
  835. /* disable ALPM and ASP */
  836. cmd &= ~PORT_CMD_ASP;
  837. cmd &= ~PORT_CMD_ALPE;
  838. /* force the interface back to active */
  839. cmd |= PORT_CMD_ICC_ACTIVE;
  840. /* write out new cmd value */
  841. writel(cmd, port_mmio + PORT_CMD);
  842. cmd = readl(port_mmio + PORT_CMD);
  843. /* wait 10ms to be sure we've come out of any low power state */
  844. msleep(10);
  845. /* clear out any PhyRdy stuff from interrupt status */
  846. writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
  847. /* go ahead and clean out PhyRdy Change from Serror too */
  848. ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
  849. /*
  850. * Clear flag to indicate that we should ignore all PhyRdy
  851. * state changes
  852. */
  853. hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
  854. /*
  855. * Enable interrupts on Phy Ready.
  856. */
  857. pp->intr_mask |= PORT_IRQ_PHYRDY;
  858. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  859. /*
  860. * don't change the link pm policy - we can be called
  861. * just to turn of link pm temporarily
  862. */
  863. }
  864. static int ahci_enable_alpm(struct ata_port *ap,
  865. enum link_pm policy)
  866. {
  867. struct ahci_host_priv *hpriv = ap->host->private_data;
  868. void __iomem *port_mmio = ahci_port_base(ap);
  869. u32 cmd;
  870. struct ahci_port_priv *pp = ap->private_data;
  871. u32 asp;
  872. /* Make sure the host is capable of link power management */
  873. if (!(hpriv->cap & HOST_CAP_ALPM))
  874. return -EINVAL;
  875. switch (policy) {
  876. case MAX_PERFORMANCE:
  877. case NOT_AVAILABLE:
  878. /*
  879. * if we came here with NOT_AVAILABLE,
  880. * it just means this is the first time we
  881. * have tried to enable - default to max performance,
  882. * and let the user go to lower power modes on request.
  883. */
  884. ahci_disable_alpm(ap);
  885. return 0;
  886. case MIN_POWER:
  887. /* configure HBA to enter SLUMBER */
  888. asp = PORT_CMD_ASP;
  889. break;
  890. case MEDIUM_POWER:
  891. /* configure HBA to enter PARTIAL */
  892. asp = 0;
  893. break;
  894. default:
  895. return -EINVAL;
  896. }
  897. /*
  898. * Disable interrupts on Phy Ready. This keeps us from
  899. * getting woken up due to spurious phy ready interrupts
  900. * TBD - Hot plug should be done via polling now, is
  901. * that even supported?
  902. */
  903. pp->intr_mask &= ~PORT_IRQ_PHYRDY;
  904. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  905. /*
  906. * Set a flag to indicate that we should ignore all PhyRdy
  907. * state changes since these can happen now whenever we
  908. * change link state
  909. */
  910. hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
  911. /* get the existing command bits */
  912. cmd = readl(port_mmio + PORT_CMD);
  913. /*
  914. * Set ASP based on Policy
  915. */
  916. cmd |= asp;
  917. /*
  918. * Setting this bit will instruct the HBA to aggressively
  919. * enter a lower power link state when it's appropriate and
  920. * based on the value set above for ASP
  921. */
  922. cmd |= PORT_CMD_ALPE;
  923. /* write out new cmd value */
  924. writel(cmd, port_mmio + PORT_CMD);
  925. cmd = readl(port_mmio + PORT_CMD);
  926. /* IPM bits should be set by libata-core */
  927. return 0;
  928. }
  929. #ifdef CONFIG_PM
  930. static void ahci_power_down(struct ata_port *ap)
  931. {
  932. struct ahci_host_priv *hpriv = ap->host->private_data;
  933. void __iomem *port_mmio = ahci_port_base(ap);
  934. u32 cmd, scontrol;
  935. if (!(hpriv->cap & HOST_CAP_SSS))
  936. return;
  937. /* put device into listen mode, first set PxSCTL.DET to 0 */
  938. scontrol = readl(port_mmio + PORT_SCR_CTL);
  939. scontrol &= ~0xf;
  940. writel(scontrol, port_mmio + PORT_SCR_CTL);
  941. /* then set PxCMD.SUD to 0 */
  942. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  943. cmd &= ~PORT_CMD_SPIN_UP;
  944. writel(cmd, port_mmio + PORT_CMD);
  945. }
  946. #endif
  947. static void ahci_start_port(struct ata_port *ap)
  948. {
  949. struct ahci_port_priv *pp = ap->private_data;
  950. struct ata_link *link;
  951. struct ahci_em_priv *emp;
  952. /* enable FIS reception */
  953. ahci_start_fis_rx(ap);
  954. /* enable DMA */
  955. ahci_start_engine(ap);
  956. /* turn on LEDs */
  957. if (ap->flags & ATA_FLAG_EM) {
  958. ata_port_for_each_link(link, ap) {
  959. emp = &pp->em_priv[link->pmp];
  960. ahci_transmit_led_message(ap, emp->led_state, 4);
  961. }
  962. }
  963. if (ap->flags & ATA_FLAG_SW_ACTIVITY)
  964. ata_port_for_each_link(link, ap)
  965. ahci_init_sw_activity(link);
  966. }
  967. static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
  968. {
  969. int rc;
  970. /* disable DMA */
  971. rc = ahci_stop_engine(ap);
  972. if (rc) {
  973. *emsg = "failed to stop engine";
  974. return rc;
  975. }
  976. /* disable FIS reception */
  977. rc = ahci_stop_fis_rx(ap);
  978. if (rc) {
  979. *emsg = "failed stop FIS RX";
  980. return rc;
  981. }
  982. return 0;
  983. }
  984. static int ahci_reset_controller(struct ata_host *host)
  985. {
  986. struct pci_dev *pdev = to_pci_dev(host->dev);
  987. struct ahci_host_priv *hpriv = host->private_data;
  988. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  989. u32 tmp;
  990. /* we must be in AHCI mode, before using anything
  991. * AHCI-specific, such as HOST_RESET.
  992. */
  993. ahci_enable_ahci(mmio);
  994. /* global controller reset */
  995. if (!ahci_skip_host_reset) {
  996. tmp = readl(mmio + HOST_CTL);
  997. if ((tmp & HOST_RESET) == 0) {
  998. writel(tmp | HOST_RESET, mmio + HOST_CTL);
  999. readl(mmio + HOST_CTL); /* flush */
  1000. }
  1001. /*
  1002. * to perform host reset, OS should set HOST_RESET
  1003. * and poll until this bit is read to be "0".
  1004. * reset must complete within 1 second, or
  1005. * the hardware should be considered fried.
  1006. */
  1007. tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
  1008. HOST_RESET, 10, 1000);
  1009. if (tmp & HOST_RESET) {
  1010. dev_printk(KERN_ERR, host->dev,
  1011. "controller reset failed (0x%x)\n", tmp);
  1012. return -EIO;
  1013. }
  1014. /* turn on AHCI mode */
  1015. ahci_enable_ahci(mmio);
  1016. /* Some registers might be cleared on reset. Restore
  1017. * initial values.
  1018. */
  1019. ahci_restore_initial_config(host);
  1020. } else
  1021. dev_printk(KERN_INFO, host->dev,
  1022. "skipping global host reset\n");
  1023. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  1024. u16 tmp16;
  1025. /* configure PCS */
  1026. pci_read_config_word(pdev, 0x92, &tmp16);
  1027. if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
  1028. tmp16 |= hpriv->port_map;
  1029. pci_write_config_word(pdev, 0x92, tmp16);
  1030. }
  1031. }
  1032. return 0;
  1033. }
  1034. static void ahci_sw_activity(struct ata_link *link)
  1035. {
  1036. struct ata_port *ap = link->ap;
  1037. struct ahci_port_priv *pp = ap->private_data;
  1038. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  1039. if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
  1040. return;
  1041. emp->activity++;
  1042. if (!timer_pending(&emp->timer))
  1043. mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
  1044. }
  1045. static void ahci_sw_activity_blink(unsigned long arg)
  1046. {
  1047. struct ata_link *link = (struct ata_link *)arg;
  1048. struct ata_port *ap = link->ap;
  1049. struct ahci_port_priv *pp = ap->private_data;
  1050. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  1051. unsigned long led_message = emp->led_state;
  1052. u32 activity_led_state;
  1053. led_message &= 0xffff0000;
  1054. led_message |= ap->port_no | (link->pmp << 8);
  1055. /* check to see if we've had activity. If so,
  1056. * toggle state of LED and reset timer. If not,
  1057. * turn LED to desired idle state.
  1058. */
  1059. if (emp->saved_activity != emp->activity) {
  1060. emp->saved_activity = emp->activity;
  1061. /* get the current LED state */
  1062. activity_led_state = led_message & 0x00010000;
  1063. if (activity_led_state)
  1064. activity_led_state = 0;
  1065. else
  1066. activity_led_state = 1;
  1067. /* clear old state */
  1068. led_message &= 0xfff8ffff;
  1069. /* toggle state */
  1070. led_message |= (activity_led_state << 16);
  1071. mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
  1072. } else {
  1073. /* switch to idle */
  1074. led_message &= 0xfff8ffff;
  1075. if (emp->blink_policy == BLINK_OFF)
  1076. led_message |= (1 << 16);
  1077. }
  1078. ahci_transmit_led_message(ap, led_message, 4);
  1079. }
  1080. static void ahci_init_sw_activity(struct ata_link *link)
  1081. {
  1082. struct ata_port *ap = link->ap;
  1083. struct ahci_port_priv *pp = ap->private_data;
  1084. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  1085. /* init activity stats, setup timer */
  1086. emp->saved_activity = emp->activity = 0;
  1087. setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
  1088. /* check our blink policy and set flag for link if it's enabled */
  1089. if (emp->blink_policy)
  1090. link->flags |= ATA_LFLAG_SW_ACTIVITY;
  1091. }
  1092. static int ahci_reset_em(struct ata_host *host)
  1093. {
  1094. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  1095. u32 em_ctl;
  1096. em_ctl = readl(mmio + HOST_EM_CTL);
  1097. if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
  1098. return -EINVAL;
  1099. writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
  1100. return 0;
  1101. }
  1102. static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
  1103. ssize_t size)
  1104. {
  1105. struct ahci_host_priv *hpriv = ap->host->private_data;
  1106. struct ahci_port_priv *pp = ap->private_data;
  1107. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1108. u32 em_ctl;
  1109. u32 message[] = {0, 0};
  1110. unsigned int flags;
  1111. int pmp;
  1112. struct ahci_em_priv *emp;
  1113. /* get the slot number from the message */
  1114. pmp = (state & 0x0000ff00) >> 8;
  1115. if (pmp < MAX_SLOTS)
  1116. emp = &pp->em_priv[pmp];
  1117. else
  1118. return -EINVAL;
  1119. spin_lock_irqsave(ap->lock, flags);
  1120. /*
  1121. * if we are still busy transmitting a previous message,
  1122. * do not allow
  1123. */
  1124. em_ctl = readl(mmio + HOST_EM_CTL);
  1125. if (em_ctl & EM_CTL_TM) {
  1126. spin_unlock_irqrestore(ap->lock, flags);
  1127. return -EINVAL;
  1128. }
  1129. /*
  1130. * create message header - this is all zero except for
  1131. * the message size, which is 4 bytes.
  1132. */
  1133. message[0] |= (4 << 8);
  1134. /* ignore 0:4 of byte zero, fill in port info yourself */
  1135. message[1] = ((state & 0xfffffff0) | ap->port_no);
  1136. /* write message to EM_LOC */
  1137. writel(message[0], mmio + hpriv->em_loc);
  1138. writel(message[1], mmio + hpriv->em_loc+4);
  1139. /* save off new led state for port/slot */
  1140. emp->led_state = message[1];
  1141. /*
  1142. * tell hardware to transmit the message
  1143. */
  1144. writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
  1145. spin_unlock_irqrestore(ap->lock, flags);
  1146. return size;
  1147. }
  1148. static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
  1149. {
  1150. struct ahci_port_priv *pp = ap->private_data;
  1151. struct ata_link *link;
  1152. struct ahci_em_priv *emp;
  1153. int rc = 0;
  1154. ata_port_for_each_link(link, ap) {
  1155. emp = &pp->em_priv[link->pmp];
  1156. rc += sprintf(buf, "%lx\n", emp->led_state);
  1157. }
  1158. return rc;
  1159. }
  1160. static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
  1161. size_t size)
  1162. {
  1163. int state;
  1164. int pmp;
  1165. struct ahci_port_priv *pp = ap->private_data;
  1166. struct ahci_em_priv *emp;
  1167. state = simple_strtoul(buf, NULL, 0);
  1168. /* get the slot number from the message */
  1169. pmp = (state & 0x0000ff00) >> 8;
  1170. if (pmp < MAX_SLOTS)
  1171. emp = &pp->em_priv[pmp];
  1172. else
  1173. return -EINVAL;
  1174. /* mask off the activity bits if we are in sw_activity
  1175. * mode, user should turn off sw_activity before setting
  1176. * activity led through em_message
  1177. */
  1178. if (emp->blink_policy)
  1179. state &= 0xfff8ffff;
  1180. return ahci_transmit_led_message(ap, state, size);
  1181. }
  1182. static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
  1183. {
  1184. struct ata_link *link = dev->link;
  1185. struct ata_port *ap = link->ap;
  1186. struct ahci_port_priv *pp = ap->private_data;
  1187. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  1188. u32 port_led_state = emp->led_state;
  1189. /* save the desired Activity LED behavior */
  1190. if (val == OFF) {
  1191. /* clear LFLAG */
  1192. link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
  1193. /* set the LED to OFF */
  1194. port_led_state &= 0xfff80000;
  1195. port_led_state |= (ap->port_no | (link->pmp << 8));
  1196. ahci_transmit_led_message(ap, port_led_state, 4);
  1197. } else {
  1198. link->flags |= ATA_LFLAG_SW_ACTIVITY;
  1199. if (val == BLINK_OFF) {
  1200. /* set LED to ON for idle */
  1201. port_led_state &= 0xfff80000;
  1202. port_led_state |= (ap->port_no | (link->pmp << 8));
  1203. port_led_state |= 0x00010000; /* check this */
  1204. ahci_transmit_led_message(ap, port_led_state, 4);
  1205. }
  1206. }
  1207. emp->blink_policy = val;
  1208. return 0;
  1209. }
  1210. static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
  1211. {
  1212. struct ata_link *link = dev->link;
  1213. struct ata_port *ap = link->ap;
  1214. struct ahci_port_priv *pp = ap->private_data;
  1215. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  1216. /* display the saved value of activity behavior for this
  1217. * disk.
  1218. */
  1219. return sprintf(buf, "%d\n", emp->blink_policy);
  1220. }
  1221. static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
  1222. int port_no, void __iomem *mmio,
  1223. void __iomem *port_mmio)
  1224. {
  1225. const char *emsg = NULL;
  1226. int rc;
  1227. u32 tmp;
  1228. /* make sure port is not active */
  1229. rc = ahci_deinit_port(ap, &emsg);
  1230. if (rc)
  1231. dev_printk(KERN_WARNING, &pdev->dev,
  1232. "%s (%d)\n", emsg, rc);
  1233. /* clear SError */
  1234. tmp = readl(port_mmio + PORT_SCR_ERR);
  1235. VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
  1236. writel(tmp, port_mmio + PORT_SCR_ERR);
  1237. /* clear port IRQ */
  1238. tmp = readl(port_mmio + PORT_IRQ_STAT);
  1239. VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
  1240. if (tmp)
  1241. writel(tmp, port_mmio + PORT_IRQ_STAT);
  1242. writel(1 << port_no, mmio + HOST_IRQ_STAT);
  1243. }
  1244. static void ahci_init_controller(struct ata_host *host)
  1245. {
  1246. struct ahci_host_priv *hpriv = host->private_data;
  1247. struct pci_dev *pdev = to_pci_dev(host->dev);
  1248. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  1249. int i;
  1250. void __iomem *port_mmio;
  1251. u32 tmp;
  1252. int mv;
  1253. if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
  1254. if (pdev->device == 0x6121)
  1255. mv = 2;
  1256. else
  1257. mv = 4;
  1258. port_mmio = __ahci_port_base(host, mv);
  1259. writel(0, port_mmio + PORT_IRQ_MASK);
  1260. /* clear port IRQ */
  1261. tmp = readl(port_mmio + PORT_IRQ_STAT);
  1262. VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
  1263. if (tmp)
  1264. writel(tmp, port_mmio + PORT_IRQ_STAT);
  1265. }
  1266. for (i = 0; i < host->n_ports; i++) {
  1267. struct ata_port *ap = host->ports[i];
  1268. port_mmio = ahci_port_base(ap);
  1269. if (ata_port_is_dummy(ap))
  1270. continue;
  1271. ahci_port_init(pdev, ap, i, mmio, port_mmio);
  1272. }
  1273. tmp = readl(mmio + HOST_CTL);
  1274. VPRINTK("HOST_CTL 0x%x\n", tmp);
  1275. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  1276. tmp = readl(mmio + HOST_CTL);
  1277. VPRINTK("HOST_CTL 0x%x\n", tmp);
  1278. }
  1279. static void ahci_dev_config(struct ata_device *dev)
  1280. {
  1281. struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
  1282. if (hpriv->flags & AHCI_HFLAG_SECT255) {
  1283. dev->max_sectors = 255;
  1284. ata_dev_printk(dev, KERN_INFO,
  1285. "SB600 AHCI: limiting to 255 sectors per cmd\n");
  1286. }
  1287. }
  1288. static unsigned int ahci_dev_classify(struct ata_port *ap)
  1289. {
  1290. void __iomem *port_mmio = ahci_port_base(ap);
  1291. struct ata_taskfile tf;
  1292. u32 tmp;
  1293. tmp = readl(port_mmio + PORT_SIG);
  1294. tf.lbah = (tmp >> 24) & 0xff;
  1295. tf.lbam = (tmp >> 16) & 0xff;
  1296. tf.lbal = (tmp >> 8) & 0xff;
  1297. tf.nsect = (tmp) & 0xff;
  1298. return ata_dev_classify(&tf);
  1299. }
  1300. static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
  1301. u32 opts)
  1302. {
  1303. dma_addr_t cmd_tbl_dma;
  1304. cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
  1305. pp->cmd_slot[tag].opts = cpu_to_le32(opts);
  1306. pp->cmd_slot[tag].status = 0;
  1307. pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
  1308. pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
  1309. }
  1310. static int ahci_kick_engine(struct ata_port *ap, int force_restart)
  1311. {
  1312. void __iomem *port_mmio = ahci_port_base(ap);
  1313. struct ahci_host_priv *hpriv = ap->host->private_data;
  1314. u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
  1315. u32 tmp;
  1316. int busy, rc;
  1317. /* do we need to kick the port? */
  1318. busy = status & (ATA_BUSY | ATA_DRQ);
  1319. if (!busy && !force_restart)
  1320. return 0;
  1321. /* stop engine */
  1322. rc = ahci_stop_engine(ap);
  1323. if (rc)
  1324. goto out_restart;
  1325. /* need to do CLO? */
  1326. if (!busy) {
  1327. rc = 0;
  1328. goto out_restart;
  1329. }
  1330. if (!(hpriv->cap & HOST_CAP_CLO)) {
  1331. rc = -EOPNOTSUPP;
  1332. goto out_restart;
  1333. }
  1334. /* perform CLO */
  1335. tmp = readl(port_mmio + PORT_CMD);
  1336. tmp |= PORT_CMD_CLO;
  1337. writel(tmp, port_mmio + PORT_CMD);
  1338. rc = 0;
  1339. tmp = ata_wait_register(port_mmio + PORT_CMD,
  1340. PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
  1341. if (tmp & PORT_CMD_CLO)
  1342. rc = -EIO;
  1343. /* restart engine */
  1344. out_restart:
  1345. ahci_start_engine(ap);
  1346. return rc;
  1347. }
  1348. static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
  1349. struct ata_taskfile *tf, int is_cmd, u16 flags,
  1350. unsigned long timeout_msec)
  1351. {
  1352. const u32 cmd_fis_len = 5; /* five dwords */
  1353. struct ahci_port_priv *pp = ap->private_data;
  1354. void __iomem *port_mmio = ahci_port_base(ap);
  1355. u8 *fis = pp->cmd_tbl;
  1356. u32 tmp;
  1357. /* prep the command */
  1358. ata_tf_to_fis(tf, pmp, is_cmd, fis);
  1359. ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
  1360. /* issue & wait */
  1361. writel(1, port_mmio + PORT_CMD_ISSUE);
  1362. if (timeout_msec) {
  1363. tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
  1364. 1, timeout_msec);
  1365. if (tmp & 0x1) {
  1366. ahci_kick_engine(ap, 1);
  1367. return -EBUSY;
  1368. }
  1369. } else
  1370. readl(port_mmio + PORT_CMD_ISSUE); /* flush */
  1371. return 0;
  1372. }
  1373. static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
  1374. int pmp, unsigned long deadline,
  1375. int (*check_ready)(struct ata_link *link))
  1376. {
  1377. struct ata_port *ap = link->ap;
  1378. const char *reason = NULL;
  1379. unsigned long now, msecs;
  1380. struct ata_taskfile tf;
  1381. int rc;
  1382. DPRINTK("ENTER\n");
  1383. /* prepare for SRST (AHCI-1.1 10.4.1) */
  1384. rc = ahci_kick_engine(ap, 1);
  1385. if (rc && rc != -EOPNOTSUPP)
  1386. ata_link_printk(link, KERN_WARNING,
  1387. "failed to reset engine (errno=%d)\n", rc);
  1388. ata_tf_init(link->device, &tf);
  1389. /* issue the first D2H Register FIS */
  1390. msecs = 0;
  1391. now = jiffies;
  1392. if (time_after(now, deadline))
  1393. msecs = jiffies_to_msecs(deadline - now);
  1394. tf.ctl |= ATA_SRST;
  1395. if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
  1396. AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
  1397. rc = -EIO;
  1398. reason = "1st FIS failed";
  1399. goto fail;
  1400. }
  1401. /* spec says at least 5us, but be generous and sleep for 1ms */
  1402. msleep(1);
  1403. /* issue the second D2H Register FIS */
  1404. tf.ctl &= ~ATA_SRST;
  1405. ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
  1406. /* wait for link to become ready */
  1407. rc = ata_wait_after_reset(link, deadline, check_ready);
  1408. /* link occupied, -ENODEV too is an error */
  1409. if (rc) {
  1410. reason = "device not ready";
  1411. goto fail;
  1412. }
  1413. *class = ahci_dev_classify(ap);
  1414. DPRINTK("EXIT, class=%u\n", *class);
  1415. return 0;
  1416. fail:
  1417. ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
  1418. return rc;
  1419. }
  1420. static int ahci_check_ready(struct ata_link *link)
  1421. {
  1422. void __iomem *port_mmio = ahci_port_base(link->ap);
  1423. u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
  1424. return ata_check_ready(status);
  1425. }
  1426. static int ahci_softreset(struct ata_link *link, unsigned int *class,
  1427. unsigned long deadline)
  1428. {
  1429. int pmp = sata_srst_pmp(link);
  1430. DPRINTK("ENTER\n");
  1431. return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
  1432. }
  1433. static int ahci_sb600_check_ready(struct ata_link *link)
  1434. {
  1435. void __iomem *port_mmio = ahci_port_base(link->ap);
  1436. u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
  1437. u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
  1438. /*
  1439. * There is no need to check TFDATA if BAD PMP is found due to HW bug,
  1440. * which can save timeout delay.
  1441. */
  1442. if (irq_status & PORT_IRQ_BAD_PMP)
  1443. return -EIO;
  1444. return ata_check_ready(status);
  1445. }
  1446. static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
  1447. unsigned long deadline)
  1448. {
  1449. struct ata_port *ap = link->ap;
  1450. void __iomem *port_mmio = ahci_port_base(ap);
  1451. int pmp = sata_srst_pmp(link);
  1452. int rc;
  1453. u32 irq_sts;
  1454. DPRINTK("ENTER\n");
  1455. rc = ahci_do_softreset(link, class, pmp, deadline,
  1456. ahci_sb600_check_ready);
  1457. /*
  1458. * Soft reset fails on some ATI chips with IPMS set when PMP
  1459. * is enabled but SATA HDD/ODD is connected to SATA port,
  1460. * do soft reset again to port 0.
  1461. */
  1462. if (rc == -EIO) {
  1463. irq_sts = readl(port_mmio + PORT_IRQ_STAT);
  1464. if (irq_sts & PORT_IRQ_BAD_PMP) {
  1465. ata_link_printk(link, KERN_WARNING,
  1466. "failed due to HW bug, retry pmp=0\n");
  1467. rc = ahci_do_softreset(link, class, 0, deadline,
  1468. ahci_check_ready);
  1469. }
  1470. }
  1471. return rc;
  1472. }
  1473. static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  1474. unsigned long deadline)
  1475. {
  1476. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  1477. struct ata_port *ap = link->ap;
  1478. struct ahci_port_priv *pp = ap->private_data;
  1479. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  1480. struct ata_taskfile tf;
  1481. bool online;
  1482. int rc;
  1483. DPRINTK("ENTER\n");
  1484. ahci_stop_engine(ap);
  1485. /* clear D2H reception area to properly wait for D2H FIS */
  1486. ata_tf_init(link->device, &tf);
  1487. tf.command = 0x80;
  1488. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  1489. rc = sata_link_hardreset(link, timing, deadline, &online,
  1490. ahci_check_ready);
  1491. ahci_start_engine(ap);
  1492. if (online)
  1493. *class = ahci_dev_classify(ap);
  1494. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  1495. return rc;
  1496. }
  1497. static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  1498. unsigned long deadline)
  1499. {
  1500. struct ata_port *ap = link->ap;
  1501. bool online;
  1502. int rc;
  1503. DPRINTK("ENTER\n");
  1504. ahci_stop_engine(ap);
  1505. rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
  1506. deadline, &online, NULL);
  1507. ahci_start_engine(ap);
  1508. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  1509. /* vt8251 doesn't clear BSY on signature FIS reception,
  1510. * request follow-up softreset.
  1511. */
  1512. return online ? -EAGAIN : rc;
  1513. }
  1514. static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  1515. unsigned long deadline)
  1516. {
  1517. struct ata_port *ap = link->ap;
  1518. struct ahci_port_priv *pp = ap->private_data;
  1519. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  1520. struct ata_taskfile tf;
  1521. bool online;
  1522. int rc;
  1523. ahci_stop_engine(ap);
  1524. /* clear D2H reception area to properly wait for D2H FIS */
  1525. ata_tf_init(link->device, &tf);
  1526. tf.command = 0x80;
  1527. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  1528. rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
  1529. deadline, &online, NULL);
  1530. ahci_start_engine(ap);
  1531. /* The pseudo configuration device on SIMG4726 attached to
  1532. * ASUS P5W-DH Deluxe doesn't send signature FIS after
  1533. * hardreset if no device is attached to the first downstream
  1534. * port && the pseudo device locks up on SRST w/ PMP==0. To
  1535. * work around this, wait for !BSY only briefly. If BSY isn't
  1536. * cleared, perform CLO and proceed to IDENTIFY (achieved by
  1537. * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
  1538. *
  1539. * Wait for two seconds. Devices attached to downstream port
  1540. * which can't process the following IDENTIFY after this will
  1541. * have to be reset again. For most cases, this should
  1542. * suffice while making probing snappish enough.
  1543. */
  1544. if (online) {
  1545. rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
  1546. ahci_check_ready);
  1547. if (rc)
  1548. ahci_kick_engine(ap, 0);
  1549. }
  1550. return rc;
  1551. }
  1552. static void ahci_postreset(struct ata_link *link, unsigned int *class)
  1553. {
  1554. struct ata_port *ap = link->ap;
  1555. void __iomem *port_mmio = ahci_port_base(ap);
  1556. u32 new_tmp, tmp;
  1557. ata_std_postreset(link, class);
  1558. /* Make sure port's ATAPI bit is set appropriately */
  1559. new_tmp = tmp = readl(port_mmio + PORT_CMD);
  1560. if (*class == ATA_DEV_ATAPI)
  1561. new_tmp |= PORT_CMD_ATAPI;
  1562. else
  1563. new_tmp &= ~PORT_CMD_ATAPI;
  1564. if (new_tmp != tmp) {
  1565. writel(new_tmp, port_mmio + PORT_CMD);
  1566. readl(port_mmio + PORT_CMD); /* flush */
  1567. }
  1568. }
  1569. static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
  1570. {
  1571. struct scatterlist *sg;
  1572. struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
  1573. unsigned int si;
  1574. VPRINTK("ENTER\n");
  1575. /*
  1576. * Next, the S/G list.
  1577. */
  1578. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1579. dma_addr_t addr = sg_dma_address(sg);
  1580. u32 sg_len = sg_dma_len(sg);
  1581. ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
  1582. ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1583. ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
  1584. }
  1585. return si;
  1586. }
  1587. static void ahci_qc_prep(struct ata_queued_cmd *qc)
  1588. {
  1589. struct ata_port *ap = qc->ap;
  1590. struct ahci_port_priv *pp = ap->private_data;
  1591. int is_atapi = ata_is_atapi(qc->tf.protocol);
  1592. void *cmd_tbl;
  1593. u32 opts;
  1594. const u32 cmd_fis_len = 5; /* five dwords */
  1595. unsigned int n_elem;
  1596. /*
  1597. * Fill in command table information. First, the header,
  1598. * a SATA Register - Host to Device command FIS.
  1599. */
  1600. cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
  1601. ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
  1602. if (is_atapi) {
  1603. memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
  1604. memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
  1605. }
  1606. n_elem = 0;
  1607. if (qc->flags & ATA_QCFLAG_DMAMAP)
  1608. n_elem = ahci_fill_sg(qc, cmd_tbl);
  1609. /*
  1610. * Fill in command slot information.
  1611. */
  1612. opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
  1613. if (qc->tf.flags & ATA_TFLAG_WRITE)
  1614. opts |= AHCI_CMD_WRITE;
  1615. if (is_atapi)
  1616. opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
  1617. ahci_fill_cmd_slot(pp, qc->tag, opts);
  1618. }
  1619. static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
  1620. {
  1621. struct ahci_host_priv *hpriv = ap->host->private_data;
  1622. struct ahci_port_priv *pp = ap->private_data;
  1623. struct ata_eh_info *host_ehi = &ap->link.eh_info;
  1624. struct ata_link *link = NULL;
  1625. struct ata_queued_cmd *active_qc;
  1626. struct ata_eh_info *active_ehi;
  1627. u32 serror;
  1628. /* determine active link */
  1629. ata_port_for_each_link(link, ap)
  1630. if (ata_link_active(link))
  1631. break;
  1632. if (!link)
  1633. link = &ap->link;
  1634. active_qc = ata_qc_from_tag(ap, link->active_tag);
  1635. active_ehi = &link->eh_info;
  1636. /* record irq stat */
  1637. ata_ehi_clear_desc(host_ehi);
  1638. ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
  1639. /* AHCI needs SError cleared; otherwise, it might lock up */
  1640. ahci_scr_read(ap, SCR_ERROR, &serror);
  1641. ahci_scr_write(ap, SCR_ERROR, serror);
  1642. host_ehi->serror |= serror;
  1643. /* some controllers set IRQ_IF_ERR on device errors, ignore it */
  1644. if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
  1645. irq_stat &= ~PORT_IRQ_IF_ERR;
  1646. if (irq_stat & PORT_IRQ_TF_ERR) {
  1647. /* If qc is active, charge it; otherwise, the active
  1648. * link. There's no active qc on NCQ errors. It will
  1649. * be determined by EH by reading log page 10h.
  1650. */
  1651. if (active_qc)
  1652. active_qc->err_mask |= AC_ERR_DEV;
  1653. else
  1654. active_ehi->err_mask |= AC_ERR_DEV;
  1655. if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
  1656. host_ehi->serror &= ~SERR_INTERNAL;
  1657. }
  1658. if (irq_stat & PORT_IRQ_UNK_FIS) {
  1659. u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
  1660. active_ehi->err_mask |= AC_ERR_HSM;
  1661. active_ehi->action |= ATA_EH_RESET;
  1662. ata_ehi_push_desc(active_ehi,
  1663. "unknown FIS %08x %08x %08x %08x" ,
  1664. unk[0], unk[1], unk[2], unk[3]);
  1665. }
  1666. if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
  1667. active_ehi->err_mask |= AC_ERR_HSM;
  1668. active_ehi->action |= ATA_EH_RESET;
  1669. ata_ehi_push_desc(active_ehi, "incorrect PMP");
  1670. }
  1671. if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
  1672. host_ehi->err_mask |= AC_ERR_HOST_BUS;
  1673. host_ehi->action |= ATA_EH_RESET;
  1674. ata_ehi_push_desc(host_ehi, "host bus error");
  1675. }
  1676. if (irq_stat & PORT_IRQ_IF_ERR) {
  1677. host_ehi->err_mask |= AC_ERR_ATA_BUS;
  1678. host_ehi->action |= ATA_EH_RESET;
  1679. ata_ehi_push_desc(host_ehi, "interface fatal error");
  1680. }
  1681. if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
  1682. ata_ehi_hotplugged(host_ehi);
  1683. ata_ehi_push_desc(host_ehi, "%s",
  1684. irq_stat & PORT_IRQ_CONNECT ?
  1685. "connection status changed" : "PHY RDY changed");
  1686. }
  1687. /* okay, let's hand over to EH */
  1688. if (irq_stat & PORT_IRQ_FREEZE)
  1689. ata_port_freeze(ap);
  1690. else
  1691. ata_port_abort(ap);
  1692. }
  1693. static void ahci_port_intr(struct ata_port *ap)
  1694. {
  1695. void __iomem *port_mmio = ahci_port_base(ap);
  1696. struct ata_eh_info *ehi = &ap->link.eh_info;
  1697. struct ahci_port_priv *pp = ap->private_data;
  1698. struct ahci_host_priv *hpriv = ap->host->private_data;
  1699. int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
  1700. u32 status, qc_active;
  1701. int rc;
  1702. status = readl(port_mmio + PORT_IRQ_STAT);
  1703. writel(status, port_mmio + PORT_IRQ_STAT);
  1704. /* ignore BAD_PMP while resetting */
  1705. if (unlikely(resetting))
  1706. status &= ~PORT_IRQ_BAD_PMP;
  1707. /* If we are getting PhyRdy, this is
  1708. * just a power state change, we should
  1709. * clear out this, plus the PhyRdy/Comm
  1710. * Wake bits from Serror
  1711. */
  1712. if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
  1713. (status & PORT_IRQ_PHYRDY)) {
  1714. status &= ~PORT_IRQ_PHYRDY;
  1715. ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
  1716. }
  1717. if (unlikely(status & PORT_IRQ_ERROR)) {
  1718. ahci_error_intr(ap, status);
  1719. return;
  1720. }
  1721. if (status & PORT_IRQ_SDB_FIS) {
  1722. /* If SNotification is available, leave notification
  1723. * handling to sata_async_notification(). If not,
  1724. * emulate it by snooping SDB FIS RX area.
  1725. *
  1726. * Snooping FIS RX area is probably cheaper than
  1727. * poking SNotification but some constrollers which
  1728. * implement SNotification, ICH9 for example, don't
  1729. * store AN SDB FIS into receive area.
  1730. */
  1731. if (hpriv->cap & HOST_CAP_SNTF)
  1732. sata_async_notification(ap);
  1733. else {
  1734. /* If the 'N' bit in word 0 of the FIS is set,
  1735. * we just received asynchronous notification.
  1736. * Tell libata about it.
  1737. */
  1738. const __le32 *f = pp->rx_fis + RX_FIS_SDB;
  1739. u32 f0 = le32_to_cpu(f[0]);
  1740. if (f0 & (1 << 15))
  1741. sata_async_notification(ap);
  1742. }
  1743. }
  1744. /* pp->active_link is valid iff any command is in flight */
  1745. if (ap->qc_active && pp->active_link->sactive)
  1746. qc_active = readl(port_mmio + PORT_SCR_ACT);
  1747. else
  1748. qc_active = readl(port_mmio + PORT_CMD_ISSUE);
  1749. rc = ata_qc_complete_multiple(ap, qc_active);
  1750. /* while resetting, invalid completions are expected */
  1751. if (unlikely(rc < 0 && !resetting)) {
  1752. ehi->err_mask |= AC_ERR_HSM;
  1753. ehi->action |= ATA_EH_RESET;
  1754. ata_port_freeze(ap);
  1755. }
  1756. }
  1757. static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
  1758. {
  1759. struct ata_host *host = dev_instance;
  1760. struct ahci_host_priv *hpriv;
  1761. unsigned int i, handled = 0;
  1762. void __iomem *mmio;
  1763. u32 irq_stat, irq_masked;
  1764. VPRINTK("ENTER\n");
  1765. hpriv = host->private_data;
  1766. mmio = host->iomap[AHCI_PCI_BAR];
  1767. /* sigh. 0xffffffff is a valid return from h/w */
  1768. irq_stat = readl(mmio + HOST_IRQ_STAT);
  1769. if (!irq_stat)
  1770. return IRQ_NONE;
  1771. irq_masked = irq_stat & hpriv->port_map;
  1772. spin_lock(&host->lock);
  1773. for (i = 0; i < host->n_ports; i++) {
  1774. struct ata_port *ap;
  1775. if (!(irq_masked & (1 << i)))
  1776. continue;
  1777. ap = host->ports[i];
  1778. if (ap) {
  1779. ahci_port_intr(ap);
  1780. VPRINTK("port %u\n", i);
  1781. } else {
  1782. VPRINTK("port %u (no irq)\n", i);
  1783. if (ata_ratelimit())
  1784. dev_printk(KERN_WARNING, host->dev,
  1785. "interrupt on disabled port %u\n", i);
  1786. }
  1787. handled = 1;
  1788. }
  1789. /* HOST_IRQ_STAT behaves as level triggered latch meaning that
  1790. * it should be cleared after all the port events are cleared;
  1791. * otherwise, it will raise a spurious interrupt after each
  1792. * valid one. Please read section 10.6.2 of ahci 1.1 for more
  1793. * information.
  1794. *
  1795. * Also, use the unmasked value to clear interrupt as spurious
  1796. * pending event on a dummy port might cause screaming IRQ.
  1797. */
  1798. writel(irq_stat, mmio + HOST_IRQ_STAT);
  1799. spin_unlock(&host->lock);
  1800. VPRINTK("EXIT\n");
  1801. return IRQ_RETVAL(handled);
  1802. }
  1803. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
  1804. {
  1805. struct ata_port *ap = qc->ap;
  1806. void __iomem *port_mmio = ahci_port_base(ap);
  1807. struct ahci_port_priv *pp = ap->private_data;
  1808. /* Keep track of the currently active link. It will be used
  1809. * in completion path to determine whether NCQ phase is in
  1810. * progress.
  1811. */
  1812. pp->active_link = qc->dev->link;
  1813. if (qc->tf.protocol == ATA_PROT_NCQ)
  1814. writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
  1815. writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
  1816. ahci_sw_activity(qc->dev->link);
  1817. return 0;
  1818. }
  1819. static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
  1820. {
  1821. struct ahci_port_priv *pp = qc->ap->private_data;
  1822. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  1823. ata_tf_from_fis(d2h_fis, &qc->result_tf);
  1824. return true;
  1825. }
  1826. static void ahci_freeze(struct ata_port *ap)
  1827. {
  1828. void __iomem *port_mmio = ahci_port_base(ap);
  1829. /* turn IRQ off */
  1830. writel(0, port_mmio + PORT_IRQ_MASK);
  1831. }
  1832. static void ahci_thaw(struct ata_port *ap)
  1833. {
  1834. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1835. void __iomem *port_mmio = ahci_port_base(ap);
  1836. u32 tmp;
  1837. struct ahci_port_priv *pp = ap->private_data;
  1838. /* clear IRQ */
  1839. tmp = readl(port_mmio + PORT_IRQ_STAT);
  1840. writel(tmp, port_mmio + PORT_IRQ_STAT);
  1841. writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
  1842. /* turn IRQ back on */
  1843. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1844. }
  1845. static void ahci_error_handler(struct ata_port *ap)
  1846. {
  1847. if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
  1848. /* restart engine */
  1849. ahci_stop_engine(ap);
  1850. ahci_start_engine(ap);
  1851. }
  1852. sata_pmp_error_handler(ap);
  1853. }
  1854. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
  1855. {
  1856. struct ata_port *ap = qc->ap;
  1857. /* make DMA engine forget about the failed command */
  1858. if (qc->flags & ATA_QCFLAG_FAILED)
  1859. ahci_kick_engine(ap, 1);
  1860. }
  1861. static void ahci_pmp_attach(struct ata_port *ap)
  1862. {
  1863. void __iomem *port_mmio = ahci_port_base(ap);
  1864. struct ahci_port_priv *pp = ap->private_data;
  1865. u32 cmd;
  1866. cmd = readl(port_mmio + PORT_CMD);
  1867. cmd |= PORT_CMD_PMP;
  1868. writel(cmd, port_mmio + PORT_CMD);
  1869. pp->intr_mask |= PORT_IRQ_BAD_PMP;
  1870. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1871. }
  1872. static void ahci_pmp_detach(struct ata_port *ap)
  1873. {
  1874. void __iomem *port_mmio = ahci_port_base(ap);
  1875. struct ahci_port_priv *pp = ap->private_data;
  1876. u32 cmd;
  1877. cmd = readl(port_mmio + PORT_CMD);
  1878. cmd &= ~PORT_CMD_PMP;
  1879. writel(cmd, port_mmio + PORT_CMD);
  1880. pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
  1881. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1882. }
  1883. static int ahci_port_resume(struct ata_port *ap)
  1884. {
  1885. ahci_power_up(ap);
  1886. ahci_start_port(ap);
  1887. if (sata_pmp_attached(ap))
  1888. ahci_pmp_attach(ap);
  1889. else
  1890. ahci_pmp_detach(ap);
  1891. return 0;
  1892. }
  1893. #ifdef CONFIG_PM
  1894. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
  1895. {
  1896. const char *emsg = NULL;
  1897. int rc;
  1898. rc = ahci_deinit_port(ap, &emsg);
  1899. if (rc == 0)
  1900. ahci_power_down(ap);
  1901. else {
  1902. ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
  1903. ahci_start_port(ap);
  1904. }
  1905. return rc;
  1906. }
  1907. static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
  1908. {
  1909. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  1910. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  1911. u32 ctl;
  1912. if (mesg.event & PM_EVENT_SLEEP) {
  1913. /* AHCI spec rev1.1 section 8.3.3:
  1914. * Software must disable interrupts prior to requesting a
  1915. * transition of the HBA to D3 state.
  1916. */
  1917. ctl = readl(mmio + HOST_CTL);
  1918. ctl &= ~HOST_IRQ_EN;
  1919. writel(ctl, mmio + HOST_CTL);
  1920. readl(mmio + HOST_CTL); /* flush */
  1921. }
  1922. return ata_pci_device_suspend(pdev, mesg);
  1923. }
  1924. static int ahci_pci_device_resume(struct pci_dev *pdev)
  1925. {
  1926. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  1927. int rc;
  1928. rc = ata_pci_device_do_resume(pdev);
  1929. if (rc)
  1930. return rc;
  1931. if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
  1932. rc = ahci_reset_controller(host);
  1933. if (rc)
  1934. return rc;
  1935. ahci_init_controller(host);
  1936. }
  1937. ata_host_resume(host);
  1938. return 0;
  1939. }
  1940. #endif
  1941. static int ahci_port_start(struct ata_port *ap)
  1942. {
  1943. struct device *dev = ap->host->dev;
  1944. struct ahci_port_priv *pp;
  1945. void *mem;
  1946. dma_addr_t mem_dma;
  1947. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1948. if (!pp)
  1949. return -ENOMEM;
  1950. mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
  1951. GFP_KERNEL);
  1952. if (!mem)
  1953. return -ENOMEM;
  1954. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  1955. /*
  1956. * First item in chunk of DMA memory: 32-slot command table,
  1957. * 32 bytes each in size
  1958. */
  1959. pp->cmd_slot = mem;
  1960. pp->cmd_slot_dma = mem_dma;
  1961. mem += AHCI_CMD_SLOT_SZ;
  1962. mem_dma += AHCI_CMD_SLOT_SZ;
  1963. /*
  1964. * Second item: Received-FIS area
  1965. */
  1966. pp->rx_fis = mem;
  1967. pp->rx_fis_dma = mem_dma;
  1968. mem += AHCI_RX_FIS_SZ;
  1969. mem_dma += AHCI_RX_FIS_SZ;
  1970. /*
  1971. * Third item: data area for storing a single command
  1972. * and its scatter-gather table
  1973. */
  1974. pp->cmd_tbl = mem;
  1975. pp->cmd_tbl_dma = mem_dma;
  1976. /*
  1977. * Save off initial list of interrupts to be enabled.
  1978. * This could be changed later
  1979. */
  1980. pp->intr_mask = DEF_PORT_IRQ;
  1981. ap->private_data = pp;
  1982. /* engage engines, captain */
  1983. return ahci_port_resume(ap);
  1984. }
  1985. static void ahci_port_stop(struct ata_port *ap)
  1986. {
  1987. const char *emsg = NULL;
  1988. int rc;
  1989. /* de-initialize port */
  1990. rc = ahci_deinit_port(ap, &emsg);
  1991. if (rc)
  1992. ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
  1993. }
  1994. static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
  1995. {
  1996. int rc;
  1997. if (using_dac &&
  1998. !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  1999. rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  2000. if (rc) {
  2001. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  2002. if (rc) {
  2003. dev_printk(KERN_ERR, &pdev->dev,
  2004. "64-bit DMA enable failed\n");
  2005. return rc;
  2006. }
  2007. }
  2008. } else {
  2009. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2010. if (rc) {
  2011. dev_printk(KERN_ERR, &pdev->dev,
  2012. "32-bit DMA enable failed\n");
  2013. return rc;
  2014. }
  2015. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  2016. if (rc) {
  2017. dev_printk(KERN_ERR, &pdev->dev,
  2018. "32-bit consistent DMA enable failed\n");
  2019. return rc;
  2020. }
  2021. }
  2022. return 0;
  2023. }
  2024. static void ahci_print_info(struct ata_host *host)
  2025. {
  2026. struct ahci_host_priv *hpriv = host->private_data;
  2027. struct pci_dev *pdev = to_pci_dev(host->dev);
  2028. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  2029. u32 vers, cap, impl, speed;
  2030. const char *speed_s;
  2031. u16 cc;
  2032. const char *scc_s;
  2033. vers = readl(mmio + HOST_VERSION);
  2034. cap = hpriv->cap;
  2035. impl = hpriv->port_map;
  2036. speed = (cap >> 20) & 0xf;
  2037. if (speed == 1)
  2038. speed_s = "1.5";
  2039. else if (speed == 2)
  2040. speed_s = "3";
  2041. else
  2042. speed_s = "?";
  2043. pci_read_config_word(pdev, 0x0a, &cc);
  2044. if (cc == PCI_CLASS_STORAGE_IDE)
  2045. scc_s = "IDE";
  2046. else if (cc == PCI_CLASS_STORAGE_SATA)
  2047. scc_s = "SATA";
  2048. else if (cc == PCI_CLASS_STORAGE_RAID)
  2049. scc_s = "RAID";
  2050. else
  2051. scc_s = "unknown";
  2052. dev_printk(KERN_INFO, &pdev->dev,
  2053. "AHCI %02x%02x.%02x%02x "
  2054. "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
  2055. ,
  2056. (vers >> 24) & 0xff,
  2057. (vers >> 16) & 0xff,
  2058. (vers >> 8) & 0xff,
  2059. vers & 0xff,
  2060. ((cap >> 8) & 0x1f) + 1,
  2061. (cap & 0x1f) + 1,
  2062. speed_s,
  2063. impl,
  2064. scc_s);
  2065. dev_printk(KERN_INFO, &pdev->dev,
  2066. "flags: "
  2067. "%s%s%s%s%s%s%s"
  2068. "%s%s%s%s%s%s%s"
  2069. "%s\n"
  2070. ,
  2071. cap & (1 << 31) ? "64bit " : "",
  2072. cap & (1 << 30) ? "ncq " : "",
  2073. cap & (1 << 29) ? "sntf " : "",
  2074. cap & (1 << 28) ? "ilck " : "",
  2075. cap & (1 << 27) ? "stag " : "",
  2076. cap & (1 << 26) ? "pm " : "",
  2077. cap & (1 << 25) ? "led " : "",
  2078. cap & (1 << 24) ? "clo " : "",
  2079. cap & (1 << 19) ? "nz " : "",
  2080. cap & (1 << 18) ? "only " : "",
  2081. cap & (1 << 17) ? "pmp " : "",
  2082. cap & (1 << 15) ? "pio " : "",
  2083. cap & (1 << 14) ? "slum " : "",
  2084. cap & (1 << 13) ? "part " : "",
  2085. cap & (1 << 6) ? "ems ": ""
  2086. );
  2087. }
  2088. /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
  2089. * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
  2090. * support PMP and the 4726 either directly exports the device
  2091. * attached to the first downstream port or acts as a hardware storage
  2092. * controller and emulate a single ATA device (can be RAID 0/1 or some
  2093. * other configuration).
  2094. *
  2095. * When there's no device attached to the first downstream port of the
  2096. * 4726, "Config Disk" appears, which is a pseudo ATA device to
  2097. * configure the 4726. However, ATA emulation of the device is very
  2098. * lame. It doesn't send signature D2H Reg FIS after the initial
  2099. * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
  2100. *
  2101. * The following function works around the problem by always using
  2102. * hardreset on the port and not depending on receiving signature FIS
  2103. * afterward. If signature FIS isn't received soon, ATA class is
  2104. * assumed without follow-up softreset.
  2105. */
  2106. static void ahci_p5wdh_workaround(struct ata_host *host)
  2107. {
  2108. static struct dmi_system_id sysids[] = {
  2109. {
  2110. .ident = "P5W DH Deluxe",
  2111. .matches = {
  2112. DMI_MATCH(DMI_SYS_VENDOR,
  2113. "ASUSTEK COMPUTER INC"),
  2114. DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
  2115. },
  2116. },
  2117. { }
  2118. };
  2119. struct pci_dev *pdev = to_pci_dev(host->dev);
  2120. if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
  2121. dmi_check_system(sysids)) {
  2122. struct ata_port *ap = host->ports[1];
  2123. dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
  2124. "Deluxe on-board SIMG4726 workaround\n");
  2125. ap->ops = &ahci_p5wdh_ops;
  2126. ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
  2127. }
  2128. }
  2129. static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  2130. {
  2131. static int printed_version;
  2132. unsigned int board_id = ent->driver_data;
  2133. struct ata_port_info pi = ahci_port_info[board_id];
  2134. const struct ata_port_info *ppi[] = { &pi, NULL };
  2135. struct device *dev = &pdev->dev;
  2136. struct ahci_host_priv *hpriv;
  2137. struct ata_host *host;
  2138. int n_ports, i, rc;
  2139. VPRINTK("ENTER\n");
  2140. WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
  2141. if (!printed_version++)
  2142. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  2143. /* acquire resources */
  2144. rc = pcim_enable_device(pdev);
  2145. if (rc)
  2146. return rc;
  2147. /* AHCI controllers often implement SFF compatible interface.
  2148. * Grab all PCI BARs just in case.
  2149. */
  2150. rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
  2151. if (rc == -EBUSY)
  2152. pcim_pin_device(pdev);
  2153. if (rc)
  2154. return rc;
  2155. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  2156. (pdev->device == 0x2652 || pdev->device == 0x2653)) {
  2157. u8 map;
  2158. /* ICH6s share the same PCI ID for both piix and ahci
  2159. * modes. Enabling ahci mode while MAP indicates
  2160. * combined mode is a bad idea. Yield to ata_piix.
  2161. */
  2162. pci_read_config_byte(pdev, ICH_MAP, &map);
  2163. if (map & 0x3) {
  2164. dev_printk(KERN_INFO, &pdev->dev, "controller is in "
  2165. "combined mode, can't enable AHCI mode\n");
  2166. return -ENODEV;
  2167. }
  2168. }
  2169. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  2170. if (!hpriv)
  2171. return -ENOMEM;
  2172. hpriv->flags |= (unsigned long)pi.private_data;
  2173. /* MCP65 revision A1 and A2 can't do MSI */
  2174. if (board_id == board_ahci_mcp65 &&
  2175. (pdev->revision == 0xa1 || pdev->revision == 0xa2))
  2176. hpriv->flags |= AHCI_HFLAG_NO_MSI;
  2177. if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
  2178. pci_intx(pdev, 1);
  2179. /* save initial config */
  2180. ahci_save_initial_config(pdev, hpriv);
  2181. /* prepare host */
  2182. if (hpriv->cap & HOST_CAP_NCQ)
  2183. pi.flags |= ATA_FLAG_NCQ;
  2184. if (hpriv->cap & HOST_CAP_PMP)
  2185. pi.flags |= ATA_FLAG_PMP;
  2186. if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
  2187. u8 messages;
  2188. void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
  2189. u32 em_loc = readl(mmio + HOST_EM_LOC);
  2190. u32 em_ctl = readl(mmio + HOST_EM_CTL);
  2191. messages = (em_ctl & 0x000f0000) >> 16;
  2192. /* we only support LED message type right now */
  2193. if ((messages & 0x01) && (ahci_em_messages == 1)) {
  2194. /* store em_loc */
  2195. hpriv->em_loc = ((em_loc >> 16) * 4);
  2196. pi.flags |= ATA_FLAG_EM;
  2197. if (!(em_ctl & EM_CTL_ALHD))
  2198. pi.flags |= ATA_FLAG_SW_ACTIVITY;
  2199. }
  2200. }
  2201. /* CAP.NP sometimes indicate the index of the last enabled
  2202. * port, at other times, that of the last possible port, so
  2203. * determining the maximum port number requires looking at
  2204. * both CAP.NP and port_map.
  2205. */
  2206. n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
  2207. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  2208. if (!host)
  2209. return -ENOMEM;
  2210. host->iomap = pcim_iomap_table(pdev);
  2211. host->private_data = hpriv;
  2212. if (pi.flags & ATA_FLAG_EM)
  2213. ahci_reset_em(host);
  2214. for (i = 0; i < host->n_ports; i++) {
  2215. struct ata_port *ap = host->ports[i];
  2216. ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
  2217. ata_port_pbar_desc(ap, AHCI_PCI_BAR,
  2218. 0x100 + ap->port_no * 0x80, "port");
  2219. /* set initial link pm policy */
  2220. ap->pm_policy = NOT_AVAILABLE;
  2221. /* set enclosure management message type */
  2222. if (ap->flags & ATA_FLAG_EM)
  2223. ap->em_message_type = ahci_em_messages;
  2224. /* disabled/not-implemented port */
  2225. if (!(hpriv->port_map & (1 << i)))
  2226. ap->ops = &ata_dummy_port_ops;
  2227. }
  2228. /* apply workaround for ASUS P5W DH Deluxe mainboard */
  2229. ahci_p5wdh_workaround(host);
  2230. /* initialize adapter */
  2231. rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
  2232. if (rc)
  2233. return rc;
  2234. rc = ahci_reset_controller(host);
  2235. if (rc)
  2236. return rc;
  2237. ahci_init_controller(host);
  2238. ahci_print_info(host);
  2239. pci_set_master(pdev);
  2240. return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
  2241. &ahci_sht);
  2242. }
  2243. static int __init ahci_init(void)
  2244. {
  2245. return pci_register_driver(&ahci_pci_driver);
  2246. }
  2247. static void __exit ahci_exit(void)
  2248. {
  2249. pci_unregister_driver(&ahci_pci_driver);
  2250. }
  2251. MODULE_AUTHOR("Jeff Garzik");
  2252. MODULE_DESCRIPTION("AHCI SATA low-level driver");
  2253. MODULE_LICENSE("GPL");
  2254. MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
  2255. MODULE_VERSION(DRV_VERSION);
  2256. module_init(ahci_init);
  2257. module_exit(ahci_exit);