tlb_uv.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792
  1. /*
  2. * SGI UltraViolet TLB flush routines.
  3. *
  4. * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
  5. *
  6. * This code is released under the GNU General Public License version 2 or
  7. * later.
  8. */
  9. #include <linux/mc146818rtc.h>
  10. #include <linux/proc_fs.h>
  11. #include <linux/kernel.h>
  12. #include <asm/mmu_context.h>
  13. #include <asm/uv/uv_mmrs.h>
  14. #include <asm/uv/uv_hub.h>
  15. #include <asm/uv/uv_bau.h>
  16. #include <asm/genapic.h>
  17. #include <asm/idle.h>
  18. #include <asm/tsc.h>
  19. #include <mach_apic.h>
  20. static struct bau_control **uv_bau_table_bases __read_mostly;
  21. static int uv_bau_retry_limit __read_mostly;
  22. /* position of pnode (which is nasid>>1): */
  23. static int uv_nshift __read_mostly;
  24. static unsigned long uv_mmask __read_mostly;
  25. static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
  26. static DEFINE_PER_CPU(struct bau_control, bau_control);
  27. /*
  28. * Free a software acknowledge hardware resource by clearing its Pending
  29. * bit. This will return a reply to the sender.
  30. * If the message has timed out, a reply has already been sent by the
  31. * hardware but the resource has not been released. In that case our
  32. * clear of the Timeout bit (as well) will free the resource. No reply will
  33. * be sent (the hardware will only do one reply per message).
  34. */
  35. static void uv_reply_to_message(int resource,
  36. struct bau_payload_queue_entry *msg,
  37. struct bau_msg_status *msp)
  38. {
  39. unsigned long dw;
  40. dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
  41. msg->replied_to = 1;
  42. msg->sw_ack_vector = 0;
  43. if (msp)
  44. msp->seen_by.bits = 0;
  45. uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
  46. }
  47. /*
  48. * Do all the things a cpu should do for a TLB shootdown message.
  49. * Other cpu's may come here at the same time for this message.
  50. */
  51. static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
  52. int msg_slot, int sw_ack_slot)
  53. {
  54. unsigned long this_cpu_mask;
  55. struct bau_msg_status *msp;
  56. int cpu;
  57. msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
  58. cpu = uv_blade_processor_id();
  59. msg->number_of_cpus =
  60. uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
  61. this_cpu_mask = 1UL << cpu;
  62. if (msp->seen_by.bits & this_cpu_mask)
  63. return;
  64. atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
  65. if (msg->replied_to == 1)
  66. return;
  67. if (msg->address == TLB_FLUSH_ALL) {
  68. local_flush_tlb();
  69. __get_cpu_var(ptcstats).alltlb++;
  70. } else {
  71. __flush_tlb_one(msg->address);
  72. __get_cpu_var(ptcstats).onetlb++;
  73. }
  74. __get_cpu_var(ptcstats).requestee++;
  75. atomic_inc_short(&msg->acknowledge_count);
  76. if (msg->number_of_cpus == msg->acknowledge_count)
  77. uv_reply_to_message(sw_ack_slot, msg, msp);
  78. }
  79. /*
  80. * Examine the payload queue on one distribution node to see
  81. * which messages have not been seen, and which cpu(s) have not seen them.
  82. *
  83. * Returns the number of cpu's that have not responded.
  84. */
  85. static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
  86. {
  87. struct bau_payload_queue_entry *msg;
  88. struct bau_msg_status *msp;
  89. int count = 0;
  90. int i;
  91. int j;
  92. for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
  93. msg++, i++) {
  94. if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
  95. msp = bau_tablesp->msg_statuses + i;
  96. printk(KERN_DEBUG
  97. "blade %d: address:%#lx %d of %d, not cpu(s): ",
  98. i, msg->address, msg->acknowledge_count,
  99. msg->number_of_cpus);
  100. for (j = 0; j < msg->number_of_cpus; j++) {
  101. if (!((1L << j) & msp->seen_by.bits)) {
  102. count++;
  103. printk("%d ", j);
  104. }
  105. }
  106. printk("\n");
  107. }
  108. }
  109. return count;
  110. }
  111. /*
  112. * Examine the payload queue on all the distribution nodes to see
  113. * which messages have not been seen, and which cpu(s) have not seen them.
  114. *
  115. * Returns the number of cpu's that have not responded.
  116. */
  117. static int uv_examine_destinations(struct bau_target_nodemask *distribution)
  118. {
  119. int sender;
  120. int i;
  121. int count = 0;
  122. sender = smp_processor_id();
  123. for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) {
  124. if (!bau_node_isset(i, distribution))
  125. continue;
  126. count += uv_examine_destination(uv_bau_table_bases[i], sender);
  127. }
  128. return count;
  129. }
  130. /*
  131. * wait for completion of a broadcast message
  132. *
  133. * return COMPLETE, RETRY or GIVEUP
  134. */
  135. static int uv_wait_completion(struct bau_desc *bau_desc,
  136. unsigned long mmr_offset, int right_shift)
  137. {
  138. int exams = 0;
  139. long destination_timeouts = 0;
  140. long source_timeouts = 0;
  141. unsigned long descriptor_status;
  142. while ((descriptor_status = (((unsigned long)
  143. uv_read_local_mmr(mmr_offset) >>
  144. right_shift) & UV_ACT_STATUS_MASK)) !=
  145. DESC_STATUS_IDLE) {
  146. if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
  147. source_timeouts++;
  148. if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
  149. source_timeouts = 0;
  150. __get_cpu_var(ptcstats).s_retry++;
  151. return FLUSH_RETRY;
  152. }
  153. /*
  154. * spin here looking for progress at the destinations
  155. */
  156. if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
  157. destination_timeouts++;
  158. if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
  159. /*
  160. * returns number of cpus not responding
  161. */
  162. if (uv_examine_destinations
  163. (&bau_desc->distribution) == 0) {
  164. __get_cpu_var(ptcstats).d_retry++;
  165. return FLUSH_RETRY;
  166. }
  167. exams++;
  168. if (exams >= uv_bau_retry_limit) {
  169. printk(KERN_DEBUG
  170. "uv_flush_tlb_others");
  171. printk("giving up on cpu %d\n",
  172. smp_processor_id());
  173. return FLUSH_GIVEUP;
  174. }
  175. /*
  176. * delays can hang the simulator
  177. udelay(1000);
  178. */
  179. destination_timeouts = 0;
  180. }
  181. }
  182. }
  183. return FLUSH_COMPLETE;
  184. }
  185. /**
  186. * uv_flush_send_and_wait
  187. *
  188. * Send a broadcast and wait for a broadcast message to complete.
  189. *
  190. * The cpumaskp mask contains the cpus the broadcast was sent to.
  191. *
  192. * Returns 1 if all remote flushing was done. The mask is zeroed.
  193. * Returns 0 if some remote flushing remains to be done. The mask is left
  194. * unchanged.
  195. */
  196. int uv_flush_send_and_wait(int cpu, int this_blade, struct bau_desc *bau_desc,
  197. cpumask_t *cpumaskp)
  198. {
  199. int completion_status = 0;
  200. int right_shift;
  201. int tries = 0;
  202. int blade;
  203. int bit;
  204. unsigned long mmr_offset;
  205. unsigned long index;
  206. cycles_t time1;
  207. cycles_t time2;
  208. if (cpu < UV_CPUS_PER_ACT_STATUS) {
  209. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
  210. right_shift = cpu * UV_ACT_STATUS_SIZE;
  211. } else {
  212. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
  213. right_shift =
  214. ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
  215. }
  216. time1 = get_cycles();
  217. do {
  218. tries++;
  219. index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
  220. cpu;
  221. uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
  222. completion_status = uv_wait_completion(bau_desc, mmr_offset,
  223. right_shift);
  224. } while (completion_status == FLUSH_RETRY);
  225. time2 = get_cycles();
  226. __get_cpu_var(ptcstats).sflush += (time2 - time1);
  227. if (tries > 1)
  228. __get_cpu_var(ptcstats).retriesok++;
  229. if (completion_status == FLUSH_GIVEUP) {
  230. /*
  231. * Cause the caller to do an IPI-style TLB shootdown on
  232. * the cpu's, all of which are still in the mask.
  233. */
  234. __get_cpu_var(ptcstats).ptc_i++;
  235. return 0;
  236. }
  237. /*
  238. * Success, so clear the remote cpu's from the mask so we don't
  239. * use the IPI method of shootdown on them.
  240. */
  241. for_each_cpu_mask(bit, *cpumaskp) {
  242. blade = uv_cpu_to_blade_id(bit);
  243. if (blade == this_blade)
  244. continue;
  245. cpu_clear(bit, *cpumaskp);
  246. }
  247. if (!cpus_empty(*cpumaskp))
  248. return 0;
  249. return 1;
  250. }
  251. /**
  252. * uv_flush_tlb_others - globally purge translation cache of a virtual
  253. * address or all TLB's
  254. * @cpumaskp: mask of all cpu's in which the address is to be removed
  255. * @mm: mm_struct containing virtual address range
  256. * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
  257. *
  258. * This is the entry point for initiating any UV global TLB shootdown.
  259. *
  260. * Purges the translation caches of all specified processors of the given
  261. * virtual address, or purges all TLB's on specified processors.
  262. *
  263. * The caller has derived the cpumaskp from the mm_struct and has subtracted
  264. * the local cpu from the mask. This function is called only if there
  265. * are bits set in the mask. (e.g. flush_tlb_page())
  266. *
  267. * The cpumaskp is converted into a nodemask of the nodes containing
  268. * the cpus.
  269. *
  270. * Returns 1 if all remote flushing was done.
  271. * Returns 0 if some remote flushing remains to be done.
  272. */
  273. int uv_flush_tlb_others(cpumask_t *cpumaskp, struct mm_struct *mm,
  274. unsigned long va)
  275. {
  276. int i;
  277. int bit;
  278. int blade;
  279. int cpu;
  280. int this_blade;
  281. int locals = 0;
  282. struct bau_desc *bau_desc;
  283. cpu = uv_blade_processor_id();
  284. this_blade = uv_numa_blade_id();
  285. bau_desc = __get_cpu_var(bau_control).descriptor_base;
  286. bau_desc += UV_ITEMS_PER_DESCRIPTOR * cpu;
  287. bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
  288. i = 0;
  289. for_each_cpu_mask(bit, *cpumaskp) {
  290. blade = uv_cpu_to_blade_id(bit);
  291. BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
  292. if (blade == this_blade) {
  293. locals++;
  294. continue;
  295. }
  296. bau_node_set(blade, &bau_desc->distribution);
  297. i++;
  298. }
  299. if (i == 0) {
  300. /*
  301. * no off_node flushing; return status for local node
  302. */
  303. if (locals)
  304. return 0;
  305. else
  306. return 1;
  307. }
  308. __get_cpu_var(ptcstats).requestor++;
  309. __get_cpu_var(ptcstats).ntargeted += i;
  310. bau_desc->payload.address = va;
  311. bau_desc->payload.sending_cpu = smp_processor_id();
  312. return uv_flush_send_and_wait(cpu, this_blade, bau_desc, cpumaskp);
  313. }
  314. /*
  315. * The BAU message interrupt comes here. (registered by set_intr_gate)
  316. * See entry_64.S
  317. *
  318. * We received a broadcast assist message.
  319. *
  320. * Interrupts may have been disabled; this interrupt could represent
  321. * the receipt of several messages.
  322. *
  323. * All cores/threads on this node get this interrupt.
  324. * The last one to see it does the s/w ack.
  325. * (the resource will not be freed until noninterruptable cpus see this
  326. * interrupt; hardware will timeout the s/w ack and reply ERROR)
  327. */
  328. void uv_bau_message_interrupt(struct pt_regs *regs)
  329. {
  330. struct bau_payload_queue_entry *va_queue_first;
  331. struct bau_payload_queue_entry *va_queue_last;
  332. struct bau_payload_queue_entry *msg;
  333. struct pt_regs *old_regs = set_irq_regs(regs);
  334. cycles_t time1;
  335. cycles_t time2;
  336. int msg_slot;
  337. int sw_ack_slot;
  338. int fw;
  339. int count = 0;
  340. unsigned long local_pnode;
  341. ack_APIC_irq();
  342. exit_idle();
  343. irq_enter();
  344. time1 = get_cycles();
  345. local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
  346. va_queue_first = __get_cpu_var(bau_control).va_queue_first;
  347. va_queue_last = __get_cpu_var(bau_control).va_queue_last;
  348. msg = __get_cpu_var(bau_control).bau_msg_head;
  349. while (msg->sw_ack_vector) {
  350. count++;
  351. fw = msg->sw_ack_vector;
  352. msg_slot = msg - va_queue_first;
  353. sw_ack_slot = ffs(fw) - 1;
  354. uv_bau_process_message(msg, msg_slot, sw_ack_slot);
  355. msg++;
  356. if (msg > va_queue_last)
  357. msg = va_queue_first;
  358. __get_cpu_var(bau_control).bau_msg_head = msg;
  359. }
  360. if (!count)
  361. __get_cpu_var(ptcstats).nomsg++;
  362. else if (count > 1)
  363. __get_cpu_var(ptcstats).multmsg++;
  364. time2 = get_cycles();
  365. __get_cpu_var(ptcstats).dflush += (time2 - time1);
  366. irq_exit();
  367. set_irq_regs(old_regs);
  368. }
  369. static void uv_enable_timeouts(void)
  370. {
  371. int i;
  372. int blade;
  373. int last_blade;
  374. int pnode;
  375. int cur_cpu = 0;
  376. unsigned long apicid;
  377. last_blade = -1;
  378. for_each_online_node(i) {
  379. blade = uv_node_to_blade_id(i);
  380. if (blade == last_blade)
  381. continue;
  382. last_blade = blade;
  383. apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
  384. pnode = uv_blade_to_pnode(blade);
  385. cur_cpu += uv_blade_nr_possible_cpus(i);
  386. }
  387. }
  388. static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
  389. {
  390. if (*offset < num_possible_cpus())
  391. return offset;
  392. return NULL;
  393. }
  394. static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
  395. {
  396. (*offset)++;
  397. if (*offset < num_possible_cpus())
  398. return offset;
  399. return NULL;
  400. }
  401. static void uv_ptc_seq_stop(struct seq_file *file, void *data)
  402. {
  403. }
  404. /*
  405. * Display the statistics thru /proc
  406. * data points to the cpu number
  407. */
  408. static int uv_ptc_seq_show(struct seq_file *file, void *data)
  409. {
  410. struct ptc_stats *stat;
  411. int cpu;
  412. cpu = *(loff_t *)data;
  413. if (!cpu) {
  414. seq_printf(file,
  415. "# cpu requestor requestee one all sretry dretry ptc_i ");
  416. seq_printf(file,
  417. "sw_ack sflush dflush sok dnomsg dmult starget\n");
  418. }
  419. if (cpu < num_possible_cpus() && cpu_online(cpu)) {
  420. stat = &per_cpu(ptcstats, cpu);
  421. seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
  422. cpu, stat->requestor,
  423. stat->requestee, stat->onetlb, stat->alltlb,
  424. stat->s_retry, stat->d_retry, stat->ptc_i);
  425. seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
  426. uv_read_global_mmr64(uv_blade_to_pnode
  427. (uv_cpu_to_blade_id(cpu)),
  428. UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
  429. stat->sflush, stat->dflush,
  430. stat->retriesok, stat->nomsg,
  431. stat->multmsg, stat->ntargeted);
  432. }
  433. return 0;
  434. }
  435. /*
  436. * 0: display meaning of the statistics
  437. * >0: retry limit
  438. */
  439. static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
  440. size_t count, loff_t *data)
  441. {
  442. long newmode;
  443. char optstr[64];
  444. if (count == 0 || count > sizeof(optstr))
  445. return -EINVAL;
  446. if (copy_from_user(optstr, user, count))
  447. return -EFAULT;
  448. optstr[count - 1] = '\0';
  449. if (strict_strtoul(optstr, 10, &newmode) < 0) {
  450. printk(KERN_DEBUG "%s is invalid\n", optstr);
  451. return -EINVAL;
  452. }
  453. if (newmode == 0) {
  454. printk(KERN_DEBUG "# cpu: cpu number\n");
  455. printk(KERN_DEBUG
  456. "requestor: times this cpu was the flush requestor\n");
  457. printk(KERN_DEBUG
  458. "requestee: times this cpu was requested to flush its TLBs\n");
  459. printk(KERN_DEBUG
  460. "one: times requested to flush a single address\n");
  461. printk(KERN_DEBUG
  462. "all: times requested to flush all TLB's\n");
  463. printk(KERN_DEBUG
  464. "sretry: number of retries of source-side timeouts\n");
  465. printk(KERN_DEBUG
  466. "dretry: number of retries of destination-side timeouts\n");
  467. printk(KERN_DEBUG
  468. "ptc_i: times UV fell through to IPI-style flushes\n");
  469. printk(KERN_DEBUG
  470. "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
  471. printk(KERN_DEBUG
  472. "sflush_us: cycles spent in uv_flush_tlb_others()\n");
  473. printk(KERN_DEBUG
  474. "dflush_us: cycles spent in handling flush requests\n");
  475. printk(KERN_DEBUG "sok: successes on retry\n");
  476. printk(KERN_DEBUG "dnomsg: interrupts with no message\n");
  477. printk(KERN_DEBUG
  478. "dmult: interrupts with multiple messages\n");
  479. printk(KERN_DEBUG "starget: nodes targeted\n");
  480. } else {
  481. uv_bau_retry_limit = newmode;
  482. printk(KERN_DEBUG "timeout retry limit:%d\n",
  483. uv_bau_retry_limit);
  484. }
  485. return count;
  486. }
  487. static const struct seq_operations uv_ptc_seq_ops = {
  488. .start = uv_ptc_seq_start,
  489. .next = uv_ptc_seq_next,
  490. .stop = uv_ptc_seq_stop,
  491. .show = uv_ptc_seq_show
  492. };
  493. static int uv_ptc_proc_open(struct inode *inode, struct file *file)
  494. {
  495. return seq_open(file, &uv_ptc_seq_ops);
  496. }
  497. static const struct file_operations proc_uv_ptc_operations = {
  498. .open = uv_ptc_proc_open,
  499. .read = seq_read,
  500. .write = uv_ptc_proc_write,
  501. .llseek = seq_lseek,
  502. .release = seq_release,
  503. };
  504. static int __init uv_ptc_init(void)
  505. {
  506. struct proc_dir_entry *proc_uv_ptc;
  507. if (!is_uv_system())
  508. return 0;
  509. if (!proc_mkdir("sgi_uv", NULL))
  510. return -EINVAL;
  511. proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
  512. if (!proc_uv_ptc) {
  513. printk(KERN_ERR "unable to create %s proc entry\n",
  514. UV_PTC_BASENAME);
  515. remove_proc_entry("sgi_uv", NULL);
  516. return -EINVAL;
  517. }
  518. proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
  519. return 0;
  520. }
  521. /*
  522. * begin the initialization of the per-blade control structures
  523. */
  524. static struct bau_control * __init uv_table_bases_init(int blade, int node)
  525. {
  526. int i;
  527. int *ip;
  528. struct bau_msg_status *msp;
  529. struct bau_control *bau_tabp;
  530. bau_tabp =
  531. kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
  532. BUG_ON(!bau_tabp);
  533. bau_tabp->msg_statuses =
  534. kmalloc_node(sizeof(struct bau_msg_status) *
  535. DEST_Q_SIZE, GFP_KERNEL, node);
  536. BUG_ON(!bau_tabp->msg_statuses);
  537. for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
  538. bau_cpubits_clear(&msp->seen_by, (int)
  539. uv_blade_nr_possible_cpus(blade));
  540. bau_tabp->watching =
  541. kmalloc_node(sizeof(int) * DEST_NUM_RESOURCES, GFP_KERNEL, node);
  542. BUG_ON(!bau_tabp->watching);
  543. for (i = 0, ip = bau_tabp->watching; i < DEST_Q_SIZE; i++, ip++)
  544. *ip = 0;
  545. uv_bau_table_bases[blade] = bau_tabp;
  546. return bau_tabp;
  547. }
  548. /*
  549. * finish the initialization of the per-blade control structures
  550. */
  551. static void __init
  552. uv_table_bases_finish(int blade, int node, int cur_cpu,
  553. struct bau_control *bau_tablesp,
  554. struct bau_desc *adp)
  555. {
  556. struct bau_control *bcp;
  557. int i;
  558. for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
  559. bcp = (struct bau_control *)&per_cpu(bau_control, i);
  560. bcp->bau_msg_head = bau_tablesp->va_queue_first;
  561. bcp->va_queue_first = bau_tablesp->va_queue_first;
  562. bcp->va_queue_last = bau_tablesp->va_queue_last;
  563. bcp->watching = bau_tablesp->watching;
  564. bcp->msg_statuses = bau_tablesp->msg_statuses;
  565. bcp->descriptor_base = adp;
  566. }
  567. }
  568. /*
  569. * initialize the sending side's sending buffers
  570. */
  571. static struct bau_desc * __init
  572. uv_activation_descriptor_init(int node, int pnode)
  573. {
  574. int i;
  575. unsigned long pa;
  576. unsigned long m;
  577. unsigned long n;
  578. unsigned long mmr_image;
  579. struct bau_desc *adp;
  580. struct bau_desc *ad2;
  581. adp = (struct bau_desc *)
  582. kmalloc_node(16384, GFP_KERNEL, node);
  583. BUG_ON(!adp);
  584. pa = __pa((unsigned long)adp);
  585. n = pa >> uv_nshift;
  586. m = pa & uv_mmask;
  587. mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
  588. if (mmr_image) {
  589. uv_write_global_mmr64(pnode, (unsigned long)
  590. UVH_LB_BAU_SB_DESCRIPTOR_BASE,
  591. (n << UV_DESC_BASE_PNODE_SHIFT | m));
  592. }
  593. for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
  594. memset(ad2, 0, sizeof(struct bau_desc));
  595. ad2->header.sw_ack_flag = 1;
  596. ad2->header.base_dest_nodeid =
  597. uv_blade_to_pnode(uv_cpu_to_blade_id(0));
  598. ad2->header.command = UV_NET_ENDPOINT_INTD;
  599. ad2->header.int_both = 1;
  600. /*
  601. * all others need to be set to zero:
  602. * fairness chaining multilevel count replied_to
  603. */
  604. }
  605. return adp;
  606. }
  607. /*
  608. * initialize the destination side's receiving buffers
  609. */
  610. static struct bau_payload_queue_entry * __init
  611. uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
  612. {
  613. struct bau_payload_queue_entry *pqp;
  614. char *cp;
  615. pqp = (struct bau_payload_queue_entry *) kmalloc_node(
  616. (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
  617. GFP_KERNEL, node);
  618. BUG_ON(!pqp);
  619. cp = (char *)pqp + 31;
  620. pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
  621. bau_tablesp->va_queue_first = pqp;
  622. uv_write_global_mmr64(pnode,
  623. UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
  624. ((unsigned long)pnode <<
  625. UV_PAYLOADQ_PNODE_SHIFT) |
  626. uv_physnodeaddr(pqp));
  627. uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
  628. uv_physnodeaddr(pqp));
  629. bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
  630. uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
  631. (unsigned long)
  632. uv_physnodeaddr(bau_tablesp->va_queue_last));
  633. memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
  634. return pqp;
  635. }
  636. /*
  637. * Initialization of each UV blade's structures
  638. */
  639. static int __init uv_init_blade(int blade, int node, int cur_cpu)
  640. {
  641. int pnode;
  642. unsigned long pa;
  643. unsigned long apicid;
  644. struct bau_desc *adp;
  645. struct bau_payload_queue_entry *pqp;
  646. struct bau_control *bau_tablesp;
  647. bau_tablesp = uv_table_bases_init(blade, node);
  648. pnode = uv_blade_to_pnode(blade);
  649. adp = uv_activation_descriptor_init(node, pnode);
  650. pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
  651. uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
  652. /*
  653. * the below initialization can't be in firmware because the
  654. * messaging IRQ will be determined by the OS
  655. */
  656. apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
  657. pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
  658. if ((pa & 0xff) != UV_BAU_MESSAGE) {
  659. uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
  660. ((apicid << 32) | UV_BAU_MESSAGE));
  661. }
  662. return 0;
  663. }
  664. /*
  665. * Initialization of BAU-related structures
  666. */
  667. static int __init uv_bau_init(void)
  668. {
  669. int blade;
  670. int node;
  671. int nblades;
  672. int last_blade;
  673. int cur_cpu = 0;
  674. if (!is_uv_system())
  675. return 0;
  676. uv_bau_retry_limit = 1;
  677. uv_nshift = uv_hub_info->n_val;
  678. uv_mmask = (1UL << uv_hub_info->n_val) - 1;
  679. nblades = 0;
  680. last_blade = -1;
  681. for_each_online_node(node) {
  682. blade = uv_node_to_blade_id(node);
  683. if (blade == last_blade)
  684. continue;
  685. last_blade = blade;
  686. nblades++;
  687. }
  688. uv_bau_table_bases = (struct bau_control **)
  689. kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
  690. BUG_ON(!uv_bau_table_bases);
  691. last_blade = -1;
  692. for_each_online_node(node) {
  693. blade = uv_node_to_blade_id(node);
  694. if (blade == last_blade)
  695. continue;
  696. last_blade = blade;
  697. uv_init_blade(blade, node, cur_cpu);
  698. cur_cpu += uv_blade_nr_possible_cpus(blade);
  699. }
  700. set_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
  701. uv_enable_timeouts();
  702. return 0;
  703. }
  704. __initcall(uv_bau_init);
  705. __initcall(uv_ptc_init);