setup-sh7723.c 9.6 KB

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  1. /*
  2. * SH7723 Setup
  3. *
  4. * Copyright (C) 2008 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/serial.h>
  13. #include <linux/mm.h>
  14. #include <linux/serial_sci.h>
  15. #include <asm/mmzone.h>
  16. static struct plat_sci_port sci_platform_data[] = {
  17. {
  18. .mapbase = 0xffe00000,
  19. .flags = UPF_BOOT_AUTOCONF,
  20. .type = PORT_SCIF,
  21. .irqs = { 80, 80, 80, 80 },
  22. },{
  23. .mapbase = 0xffe10000,
  24. .flags = UPF_BOOT_AUTOCONF,
  25. .type = PORT_SCIF,
  26. .irqs = { 81, 81, 81, 81 },
  27. },{
  28. .mapbase = 0xffe20000,
  29. .flags = UPF_BOOT_AUTOCONF,
  30. .type = PORT_SCIF,
  31. .irqs = { 82, 82, 82, 82 },
  32. },{
  33. .mapbase = 0xa4e30000,
  34. .flags = UPF_BOOT_AUTOCONF,
  35. .type = PORT_SCI,
  36. .irqs = { 56, 56, 56, 56 },
  37. },{
  38. .mapbase = 0xa4e40000,
  39. .flags = UPF_BOOT_AUTOCONF,
  40. .type = PORT_SCI,
  41. .irqs = { 88, 88, 88, 88 },
  42. },{
  43. .mapbase = 0xa4e50000,
  44. .flags = UPF_BOOT_AUTOCONF,
  45. .type = PORT_SCI,
  46. .irqs = { 109, 109, 109, 109 },
  47. }, {
  48. .flags = 0,
  49. }
  50. };
  51. static struct platform_device sci_device = {
  52. .name = "sh-sci",
  53. .id = -1,
  54. .dev = {
  55. .platform_data = sci_platform_data,
  56. },
  57. };
  58. static struct resource rtc_resources[] = {
  59. [0] = {
  60. .start = 0xa465fec0,
  61. .end = 0xa465fec0 + 0x58 - 1,
  62. .flags = IORESOURCE_IO,
  63. },
  64. [1] = {
  65. /* Period IRQ */
  66. .start = 69,
  67. .flags = IORESOURCE_IRQ,
  68. },
  69. [2] = {
  70. /* Carry IRQ */
  71. .start = 70,
  72. .flags = IORESOURCE_IRQ,
  73. },
  74. [3] = {
  75. /* Alarm IRQ */
  76. .start = 68,
  77. .flags = IORESOURCE_IRQ,
  78. },
  79. };
  80. static struct platform_device rtc_device = {
  81. .name = "sh-rtc",
  82. .id = -1,
  83. .num_resources = ARRAY_SIZE(rtc_resources),
  84. .resource = rtc_resources,
  85. };
  86. static struct resource sh7723_usb_host_resources[] = {
  87. [0] = {
  88. .name = "r8a66597_hcd",
  89. .start = 0xa4d80000,
  90. .end = 0xa4d800ff,
  91. .flags = IORESOURCE_MEM,
  92. },
  93. [1] = {
  94. .start = 65,
  95. .end = 65,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. };
  99. static struct platform_device sh7723_usb_host_device = {
  100. .name = "r8a66597_hcd",
  101. .id = 0,
  102. .dev = {
  103. .dma_mask = NULL, /* not use dma */
  104. .coherent_dma_mask = 0xffffffff,
  105. },
  106. .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
  107. .resource = sh7723_usb_host_resources,
  108. };
  109. static struct platform_device *sh7723_devices[] __initdata = {
  110. &sci_device,
  111. &rtc_device,
  112. &sh7723_usb_host_device,
  113. };
  114. static int __init sh7723_devices_setup(void)
  115. {
  116. return platform_add_devices(sh7723_devices,
  117. ARRAY_SIZE(sh7723_devices));
  118. }
  119. __initcall(sh7723_devices_setup);
  120. enum {
  121. UNUSED=0,
  122. /* interrupt sources */
  123. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  124. HUDI,
  125. DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
  126. _2DG_TRI,_2DG_INI,_2DG_CEI,
  127. DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
  128. VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
  129. SCIFA_SCIFA0,
  130. VPU_VPUI,
  131. TPU_TPUI,
  132. ADC_ADI,
  133. USB_USI0,
  134. RTC_ATI,RTC_PRI,RTC_CUI,
  135. DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
  136. DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
  137. KEYSC_KEYI,
  138. SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
  139. MSIOF_MSIOFI0,MSIOF_MSIOFI1,
  140. SCIFA_SCIFA1,
  141. FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
  142. I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
  143. SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
  144. CMT_CMTI,
  145. TSIF_TSIFI,
  146. SIU_SIUI,
  147. SCIFA_SCIFA2,
  148. TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
  149. IRDA_IRDAI,
  150. ATAPI_ATAPII,
  151. SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
  152. VEU2H1_VEU2HI,
  153. LCDC_LCDCI,
  154. TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
  155. /* interrupt groups */
  156. DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
  157. SDHI1, RTC, DMAC1B, SDHI0,
  158. };
  159. static struct intc_vect vectors[] __initdata = {
  160. INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
  161. INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
  162. INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
  163. INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
  164. INTC_VECT(DMAC1A_DEI0,0x700),
  165. INTC_VECT(DMAC1A_DEI1,0x720),
  166. INTC_VECT(DMAC1A_DEI2,0x740),
  167. INTC_VECT(DMAC1A_DEI3,0x760),
  168. INTC_VECT(_2DG_TRI, 0x780),
  169. INTC_VECT(_2DG_INI, 0x7A0),
  170. INTC_VECT(_2DG_CEI, 0x7C0),
  171. INTC_VECT(DMAC0A_DEI0,0x800),
  172. INTC_VECT(DMAC0A_DEI1,0x820),
  173. INTC_VECT(DMAC0A_DEI2,0x840),
  174. INTC_VECT(DMAC0A_DEI3,0x860),
  175. INTC_VECT(VIO_CEUI,0x880),
  176. INTC_VECT(VIO_BEUI,0x8A0),
  177. INTC_VECT(VIO_VEU2HI,0x8C0),
  178. INTC_VECT(VIO_VOUI,0x8E0),
  179. INTC_VECT(SCIFA_SCIFA0,0x900),
  180. INTC_VECT(VPU_VPUI,0x980),
  181. INTC_VECT(TPU_TPUI,0x9A0),
  182. INTC_VECT(ADC_ADI,0x9E0),
  183. INTC_VECT(USB_USI0,0xA20),
  184. INTC_VECT(RTC_ATI,0xA80),
  185. INTC_VECT(RTC_PRI,0xAA0),
  186. INTC_VECT(RTC_CUI,0xAC0),
  187. INTC_VECT(DMAC1B_DEI4,0xB00),
  188. INTC_VECT(DMAC1B_DEI5,0xB20),
  189. INTC_VECT(DMAC1B_DADERR,0xB40),
  190. INTC_VECT(DMAC0B_DEI4,0xB80),
  191. INTC_VECT(DMAC0B_DEI5,0xBA0),
  192. INTC_VECT(DMAC0B_DADERR,0xBC0),
  193. INTC_VECT(KEYSC_KEYI,0xBE0),
  194. INTC_VECT(SCIF_SCIF0,0xC00),
  195. INTC_VECT(SCIF_SCIF1,0xC20),
  196. INTC_VECT(SCIF_SCIF2,0xC40),
  197. INTC_VECT(MSIOF_MSIOFI0,0xC80),
  198. INTC_VECT(MSIOF_MSIOFI1,0xCA0),
  199. INTC_VECT(SCIFA_SCIFA1,0xD00),
  200. INTC_VECT(FLCTL_FLSTEI,0xD80),
  201. INTC_VECT(FLCTL_FLTENDI,0xDA0),
  202. INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
  203. INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
  204. INTC_VECT(I2C_ALI,0xE00),
  205. INTC_VECT(I2C_TACKI,0xE20),
  206. INTC_VECT(I2C_WAITI,0xE40),
  207. INTC_VECT(I2C_DTEI,0xE60),
  208. INTC_VECT(SDHI0_SDHII0,0xE80),
  209. INTC_VECT(SDHI0_SDHII1,0xEA0),
  210. INTC_VECT(SDHI0_SDHII2,0xEC0),
  211. INTC_VECT(CMT_CMTI,0xF00),
  212. INTC_VECT(TSIF_TSIFI,0xF20),
  213. INTC_VECT(SIU_SIUI,0xF80),
  214. INTC_VECT(SCIFA_SCIFA2,0xFA0),
  215. INTC_VECT(TMU0_TUNI0,0x400),
  216. INTC_VECT(TMU0_TUNI1,0x420),
  217. INTC_VECT(TMU0_TUNI2,0x440),
  218. INTC_VECT(IRDA_IRDAI,0x480),
  219. INTC_VECT(ATAPI_ATAPII,0x4A0),
  220. INTC_VECT(SDHI1_SDHII0,0x4E0),
  221. INTC_VECT(SDHI1_SDHII1,0x500),
  222. INTC_VECT(SDHI1_SDHII2,0x520),
  223. INTC_VECT(VEU2H1_VEU2HI,0x560),
  224. INTC_VECT(LCDC_LCDCI,0x580),
  225. INTC_VECT(TMU1_TUNI0,0x920),
  226. INTC_VECT(TMU1_TUNI1,0x940),
  227. INTC_VECT(TMU1_TUNI2,0x960),
  228. };
  229. static struct intc_group groups[] __initdata = {
  230. INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
  231. INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
  232. INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
  233. INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
  234. INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
  235. INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
  236. INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
  237. INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
  238. INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
  239. INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
  240. INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
  241. };
  242. static struct intc_mask_reg mask_registers[] __initdata = {
  243. { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
  244. { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
  245. { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
  246. { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
  247. { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
  248. { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
  249. { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
  250. { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
  251. { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
  252. { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
  253. { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
  254. { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
  255. { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
  256. { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
  257. { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
  258. { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
  259. FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
  260. { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
  261. { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
  262. { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
  263. { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
  264. { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
  265. { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
  266. { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
  267. { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
  268. { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
  269. { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
  270. { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
  271. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  272. };
  273. static struct intc_prio_reg prio_registers[] __initdata = {
  274. { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
  275. { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
  276. { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
  277. { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
  278. { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
  279. { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
  280. { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
  281. { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
  282. { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
  283. { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
  284. { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
  285. { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
  286. { 0xa4140010, 0, 32, 4, /* INTPRI00 */
  287. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  288. };
  289. static struct intc_sense_reg sense_registers[] __initdata = {
  290. { 0xa414001c, 16, 2, /* ICR1 */
  291. { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  292. };
  293. static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
  294. mask_registers, prio_registers, sense_registers);
  295. void __init plat_irq_setup(void)
  296. {
  297. register_intc_controller(&intc_desc);
  298. }